A Corporate Dedication to - Computer History Museum

A Corporate Dedication to Quality and Reliability

National Semiconductor is an industry leader in the manufacture of high quality, high reliability integrated circuits. We have been the leading prop'onent of driving down IC defects and extending product lifetimes. From raw material through product design, manufacturing and shipping, our quality and reliability is second to none.

We are proud of our success ... it sets a standard for others to achieve. Yet, our quest for perfection is ongoing so that you, our customer, can continue to rely on National Semiconductor Corporation to produce high quality products for your systems.

Charles E. Sporck President,Chief Executive Officer National Semiconductor Corporation

· I .' ,( l

Wir f(ihlen uns zu Qualitat und Zuverlassigkeit verpflichtet

National Semiconductor Corporation 1st fUhrend bei der Harstellung von integrierten Schaltungen hoher QualiUit und hoher Zuverlassigkeit. National Semiconductor war schon immer Vorreiter, wenn es galt, die Zahl von IC Ausfallen zu verringern und die Lebensdauern von Produkten zu verbessern. Vom ,Rohmaterial Uber Entwurf und Herstellung bis zur Auslieferung, die QualiUit und die Zuverlassigkeit per Produkte von National Semiconductor sind unUbertroffen.

Wir sind stolz auf unseren Erfolg, der Standards setzt, die fUr andere erstrebenswert sind. Auch ihre AnsprUche steigen standig, Sieals unser Kunde konnen sich auch weiterhin auf National Semiconductor verlassen.

La Qualite et La Fiabilite: Une Vocation Commune Chez National Semiconductor Corporation

National Semiconductor Corporation c'est I'un des· leaders industriels qui fabrique des circuits intE~gres d'une tres ,grande qualite et d'une fiabilite exceptionnelle. National a ete Ie premier a vQuloir faire chuter Ie nombre de circuits in~ tegres defectueux et a augmenter la duree de vie des produits. Oepuis les matieres premieres, en passant par la conception du produit sa fabrication et son expedition, partout la qualite et la

. fiabilite chez National sont sans equivalents.

Nous sommes fiers de notre succes et Ie standard ainsi detini devrait devenir I'objectif a atteindre par les autres societes. Et nous continuons a vouloir faire progresser notre recherche de la perfection; II en resulte que vous, qui etes notre client, pouvez toujours faire confiance a National Semiconductor Corporation, en produisant des systemes d'une tres grande qualite standard. .

Un Impegno Societario di Qualitae Affidabilita

National Semiconductor Corporation e un'industria al vertice nella costruzione di circuiti integrati di alta qualita ed affidabilita. National e stata iI principale promotore per I'abbattimento della difettosita dei circuiti integrati e per I'allungamento della vita dei prodotti. Oal materiale grezzo attraverso tuUe Ie fasi di progettazione, costruzione e spedizione, la qualita e affidabllita National non e second a a nessuno.

Noi siamo orgogliosi del nostro successo che fissaper gli altri un traguardo da raggiungere. II nostro desiderio di perfezione e d'altra parte iilimitato e pertanto tu, nostro cliente, puoi continuare ad affidarti a National Semiconductor Corporation per la produzione dei tuoi sistemi con elevati livelli di qualita.

/,) ; I. /'y~_" ~ ~~,~" .'

Charles E. Sporck President, Chief Executive Officer National Semiconductor Corporation

2

MOS MEMORY DATABOOK

Standard Terminology

MOS Memory Cross Reference Guide

Dynamic RAMs

NMOS Static RAMs

CMOS Static RAMs

EPROMs

EEPROMs

Military/Aerospace

Reliability

Physical Dimensions

3

TRADEMARKS

Following is the most current list of National Corporation's trademarks and registered trademarks.

Abuseable™ Macrobus™ QUAD3000™ AnadigTM MacrocomponentTM RATTM ANS-R-TRANTM Maxi-ROM® RTX-16™ Auto-Chern Deflasher™ Meatv-Chek™ SCRIPT v-Chek™ BI-FETTM Microbus™ data bus (adjective) Shelf-ChekTM BI-LiNETM MICRO-DACTM SERIESI800™ BIPLANTM IltalkerTM SPIRETM BLC/BLXTM Microtalker™ Starlink™ CIMTM MICROWIRETM STARPLEXTM CIMBUSTM MICROWIRE PLUSTM STARPLEX UTM Clockv-Chek™ MOLETM SuperChipTM COPSTM microcontrollers MSTTM SYS16™ DATACHECKER® Nitride PIUS™ TAPE-PAKTM DENSPAKTM Nitride Plus Oxide™ TDSTM DIBTM NMLTM The National Anthem® Digitalker® NSC800™ Timev-Chek™ DISCERNTM NS16000™ TrapezoidaFM DNRTM NSX-16™ TRI-CODETM DPVMTM NSCX-16™ TRI-POLYTM E-Z-LlNKTM NURAMTM TRI-SAFETM GENIXTM OXISSTM TRI-STATE® HEX 3000™ Perfect Watch ™ XMOSTM ISETM Pharmav-Chek™ XPUTM INFOCHEXTM PLANTM Z STARTM IntegrallSETM Polycraft™ 883B/RETSTM IntelisplayTM POSitalker™ 883S/RETSTM ISEI16™

Z80® is a registered trademark of Zilog Corporation.

LIFE SUPPORT POLICY

NATIONAL:S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

National Semiconductor Corporation 2900 Semiconductor Drive Santa Clara, California 95051 Tel.: (408) 721·5000 TWX: (910) 339·9240 National does not aSsume any responsibility for use of any circuitry described; no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry.

4

MOS MEMORY DATABOOK

INTRODUCTION

National Semiconductor Corporation's MOS Memory Databook is a comprehensive collection of information on advanced, high-density memory products covering the spectrum of this mainstream semiconductor component category.

Virtually every electronic system being designed today requires some level of storage capacity. National is committed to designing and supplying high-performance memory products ranging from state-of-the-art dynamic RAMs to programmable non-volatile EPROMs and EEPROMs which are currently finding increasing usage in a wide range of microprocessor-based systems.

National Semiconductor has an array of advanced technology processes to apply to memory design and development. These range from our high-density triple-poly process used in the most advanced RAMs, to our small-geometry, silicongate, oxide-isolated microCMOS technology which is now being applied to high-performance memory devices for the first time.

National is committed to technical excellence in design, manufacturing, reliability and service to our customers through the continuing development of new devices. If you don't find the memory products you need in this book, please contact your local National Semiconductor sales office or distributor.

National is also committed to providing the most complete, up-to-date information available on its entire product line, and has accomplished this with its master databook program. This program, of which the MOS Memory Databook is a part, provides one master databook for each product family with periodic supplements designed to keep you abreast of all new and revised information. We are confident that this program will serve your information needs well in the quickly changing world of technology.

5

DATABOOK MEMOIRES MOS

INTRODUCTION

Le Databook Memoires MOS edite par National Semiconductor Corporation est un recueil detaille et complet d'informations portant sur les circuits memoires de pointe a haute densite, couvrant tout Ie spectre· de cette importante categorie de composants semiconducteurs.

Pratiquement tout systeme electronique conc;:u aujourd'hui necessite quelquepart un moyen de memorisation. National s'est engage a concevoir et a produire des produits memoires tres performants qui vont depuis les RAMs dynamiques nec plus ultra jusqu'aux EPROMs et EEPROMs programmables non volatiles, qui sont actuellement de plus en plus utilisees dans une vaste gam me de systemes a microprocesseurs.

National Semiconductor dispose d'un ensemble de technologies de pointe pour concevoir et developper ses memoires. Cet ensemble va de notre technologies haute densite triplepoly utilitsee dans la plupart des RAMs de pointe, a notre technologie microCMOS, a isolation d'oxyde, porte au silicium et petite gedmetrie maintenant mise en oeuvre dans les circuits memoires a hautes performances, ou la premiere fois.

National s'est engage a fournir une qualite technique irreprochable a ses clients, en ce qui concerne la conception, la fabrication, la fiabilite et Ie service, et ceci tout au long au developpement des nos nouveaux circuits. Si vous ne trouvez pas dans cet ouvrage Ie produit memoire dont vous avez besoin, veuillez contacter s'il vous plait votre ingenieur commercial National Semiconductor ou votre distributeur Ie plus proche.

National s'est aussi engage a fournir I'information la plus complete et la plus a ·jour qui soit; sur toute sa gam me de produits. C'est ce que National vient de faire avec la sortie de son nouveau programme de Databook. Ce programme, dont ce Databook Memoires MOS fait partie, comprend un Databook pour chaque famille de produits ainsi que des mises a jour periodiques destinees a vous informer de toutes les nouveautes ou revisions. Nous sommes certains que ce programme vous apportera toutes les informations dont vous avez besoin dans ce monde technologique qui change aussi rapidement.

MEMORY DATABOOK

II catalogo "Memorie MOS" della National Semiconductor e una raccolta di informazioni sui prodotti pill avanzati ed ad alta dens ita in uno dei seitori pill importanti dei componenti elettronici.

Teoricamente, ogni sistema elettronico, progettato oggi richiede una certa capac ita di memorizzazione la National e impesanta nel progrettare e produrre memorie ad elevate prestazioni: dalle memorie "RAM" dinamiche aile memorie non volatili programmabili quali "EPROM" ed ancora a quelle programmabili e, cancellabili elettroicamente "EEPROM" che stanno suscitan do un crescente interesse per applicazioni con i microprocessori.

La National Semiconductor possiede un gran numero di processi tecnologici utilizzabili nella fabbricazione di dispositivi di memoria. Fra i processi pili interessanti e da notare quello "Triple-poly" ad alta densita per Ie pill avanzate memorie "RAM" di namiche ed iI processo micro-CMOS con geometrie ridottissime. Silicone-gate con isolamento ad ossido. Utilizzato dalla National per la prima volta nella fabbricazione di memorie ad elevate prestazioni.

La National Semiconductor, grazie allo sviluppo continuo di nuovi prodotti si e indirizzata verso la ricerca di altre tecnologie di progetto. Tecniche di fabbricazione specializzate ad alta affidabilita. Tutto per offrire il migliore servizio ai clienti. Se non trovate in questo catalogo iI prodotto che vi interessa, non esitate a contattare gli uffici vendite della National Semiconductor od iI vostro Distributore.

La National e impegnata a fornire Ie informazioni pill complete e pill aggiornate oirca tutti i suoi prodotti; per cio sta implementando un programma detto "MASTER DATABOOK PROGRAM". Con questo programma, di oui j(

manuale della Memorie MOS fa parte, viene fornito un volume principale (Master Databook) per ciacuna famiglia di prodotto oltre a supplementi periodici che contengono tutte Ie informazioni pill recenti riguardo ai prodotti. Noi crediamo che con questo programma saremo in grado id darvi tutte Ie informazione necessarie 'aggiornando Ie stesse con la stessa rapidita con cui evolve iI mondo tecnologico.

6

MOS-Speicher-Datenbuch

EINLEITUNG

Das· MOS-Speicher-Datenbuch von National Semiconductor ist eine umfangreiche Sammlung von Informationen uber fortschrittliche Speicherprodukte hoher Scheltunge-

I dichte. Es wird gesamte Spektrum dieser wichtigen Halbleiter-Bauelemente-Kategorie abgedeckt.

Praktisch jedes System, des heute entwickelt wird, beotigt eine gewisse Speicherkepazitat. National Semiconductor entwickelt und fertigt Hochleistungs-Speicherbauelemente. Des Typenspektrum reicht vom modernen dynamischen RAM bis zu programmierbaren nichtfluchtigen EPROMs und EEPROMs, die derzeit immer mehr Anwendungen in einem weiten Spektrum von Microprozessorsystemen finden.

National Semiconductor verfugt uber ein weites Spektrum I an Herstellungsverfahren modernster Art, die bei der

Entwicklung und Fertigung von Speichern angewendet werden. Diesen reichen vom Triple-Poly-ProzeB hoher Dichte, der bei den meisten modernen RAMs verwendet wird, bis zur oxidisolierten Silizium-Gate-microCMOS-Technologie mit ihren kleinen Geometrien, die derzeit erstmals bei Hochleistungs-Speicherbauelementen Verwendung findet.

National Semiconductor Whit sich zu' hochster technischer Perfektion bei Entwicklung, Herstellung, Zuverlassigkeit und Kunden-Service verpflichtet. Dies kommt in der kontinuierlichen Entwicklung immer neuer Bauelemente zum Ausdruk. Sollten Sie das von Ihnen benotigte Bauelemente nicht in diesem Datenbuch finden, fragen Sie doch bitte den fur Sie zustandigen National-Semiconductor-Distributor oder das nachste Verkaufsburo.

National Semiconductor mochte Ihnen die vollstandigsten und aktuellsten Informationen uber aile Produkte zuganglich machen. DaWr wurde das neue DatenbuchProgramm zusammengestellt. Diesen Programm, zu dem auch das MOS-Speicher-Oatenbuch gehort, besteht aus jeweils einem Haupt-Datenbuch ("Master Databook") fUr eine Produktfamilie, das mit periodisch erscheinenden Erganzungsbanden aktualisiert wird. Damit steht Ihnen die jeweils neueste Produktinformation zur Verfugung. Wir glauben, daB wir auf diese Weise Ihrem Informationsbedurfnis ubr die sich schnell a'1dernde Technologie am besten gerecht werden.

Table of Contents

Quality & Reliability .......................... .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .• 1

Edge Index by Product Family ......................................................................• 3

Trademarks . ',' ............. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Alphanumeric Index ............................................................................... 9

Section 1-Standard Terminology Proposed Standard Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·3

Section 2-MOS Memory Cross Reference Guide Industry Package Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·3

MOS Memory Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2·4

MOS Memory Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • 2·5

Section 3-Dynamic RAMs NMC3764 65,536 x 1·Bit Dynamic RAM .................................................... , .... . . . ... 3·3

NMC41257 262,144 x 1-Bit Dynamic RAM ............................................................. 3·10

Section 4-NMOS Static RAMs MM2114/MM2114L Family 4096-Bit (1024 x 4) Static RAMs .............................. , . . . . . . . . . . . . . . . . 4·3

NMC2147H 4096 x 1 Static RAM ................ , ..... , ................. , ....................... " . . 4·7

NMC2148H 1024x4StaticRAM ...................... : .............................................. 4·11

Section 5-CMOS Static RAMs NMC6164/6164L 8192x8-BitStatic RAM.............................................................. 5-3

Section 6-EPROMs MM2716 16,384-Bit (2048 x 8) UV Erasable PROM ....................... " ................... , .. . .. . . . . . 6-3

MM2758 8,192-Bit (1024x 8) UV Erasable PROM ............................................. , .......... 6·10

NMC27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . ... 6-16

NMC27C32 32,768-Bit (4096 x 8) UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·23

NMC27C256 262,144·Bit (32k x 8) UV Erasable CMOS PROM .............................................. 6·30

Section 7-EEPROMs NMC9306/COP494 256·Bit Serial Electrically Erasable Programmable Memory. . . • . . . . . . . . . . . . . .. . . .. . . . . . . . . 7·3

NMC9306E/COP394 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

NMC9346/COP495 1024·Bit Serial Electrically Erasable Programmable Memory (5V Only) . . . . . . . .. . . . . . . . . . . . .. 7·13

NMC9346E/COP395 1024·Bit Serial Electrically Erasable Programmable Memory(5V Only) ..................... 7·18

NMC2816 16k (2k x 8) Electrically Erasable PROM ...................................... .' . . . . . . . . . . . . . .. 7·23

NMC2816M 16k(2kx 8) Electrically Erasable PROM .................. , ..... , '" . ...... . ..... . ..•. .... .. 7·29

N MC9716 16k (2k x 8) Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. 7·35

NMC9716M 16k(2kx 8) Electrically Erasable PROM ............ '" ... , .. . . .... ... .... . . ..... . . ... . ... .. 7·42

NMC9817 16,384·Bit (2k x 8) E2PROM ...... , . .. . .. .. .. .. . .. . .. . .. . .. . . . . . .. .. .. . .. . .. .. .. .. . .. . . .. . .. 749

NMC98C64A 65,536·Bit (8k x 8) E2PROM . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·54

AB·5 Threshold Bit Mapping in EEPROMs (NMC2816) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·57

AB·15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs. . . . . . . . . . . . . . . . . . . . .. 7·59

7

Table of Contents (Continued)

Section 7-EEPROMs (Continued)

AN-328 EEPROM Application Note, Vpp Generation on Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-61

AN-338 Designing with the NMC9306ICOP494, a Versatile, Simple to Use E2PROM . .. . .. . . . . . . .. . . . . . . . . .. . .. 7·67

AN-342 Designing with the NMC9817, a 2nd Generation E2PROM ........................................... 7-74

Section 8-Military/Aerospace Detailed Electrical Test and Burn-in Information ................ ' .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8B3B/RETS ™ Products ..................... ' ....... ' ........................ ' ... '. . . . . . . . . . . . . . . . . . . . .. 8-4

Section 9-Reliability Introduction to the Reliability Military/Aerospace Programs .... : . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3

The A+ Reliability Enhancement Program ............................................................. 9-12

MST™ Program The System Environment Approach to Memory Component Testing. . . . . . . . . . . . . . . . . . . . . . . . .. 9-14

Section 10-Physical Dimensions .................................................... 10-1

8

Alphanumeric Index

AN·328 EEPROM Application Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·61

AN·338 Designing with the NMC9306/COP494 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·67

AN·342 Designing with the NMC9817 . . . .. . . . . . . . . . . . . . .. .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . .. 7·74

Application Brief 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·57

Application Brief 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·59

COP394 Serial Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7·8

COP395 Serial Electrically Erasable PROM ........................................................... , 7·18

COP494 Serial Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7·3

COP495 Serial Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 7·13

MM2114 Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4·3

MM2114LStatic RAM................. .................................. ........................... 4·3

MM2716 UV Erasable PROM. . . . . . . . . . . . . . . .. . . . . ... . . . . .. . . . .. . . . . . . . . . . .. .. . . . . .... . .. .... . .. . . . . . . 6·3

MM2758 UV Erasable PROM ........................................................................ 6·10

NMC2147H Static RAM ........................................ '. . . . . . . . . . .. . . . . .. . . . .. . . .. .. . . . . . .. 4·7

NMC2148H Static RAM ............................................................................ 4·11

NMC281616K Electrically Erasable PROM ............................................................. 7·23

NMC2816M 16K Electrically Erasable PROM .............................................. , ............ 7·29

N MC3764 Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3·3

N MC6164 Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5·3

NMC6164L Static RAM. .. .. . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ... ... . . . .. . . . .... . .. . . . . . . . .. 5·3

N MC9306 Serial Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7·3

NMC9306E Serial Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . .. . .. . ... . . . .. . . . 7·8

N MC9346 Serial Electrically Erasable PROM (5V Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·13

NMC9346E Serial Electrically Erasable PROM (5V Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 7·18

NMC971616K Electrically Erasable PROM ............................................................. 7·35

NMC9716M 16K Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 7·42

NMC9817 Electrically Erasable PROM ................................................................ 7·49

NMC41257 Dynamic RAM. . . . . . . . . . . . . .. . . . .. . . . . . . . . . .. . . . .. . . .. . . . .. . . . .. . . . . . ... . ... . .. . . ... . . .. 3·10

N MC27C16 UV Erasable CMOS PROM .............................................. .-. . .. . . .. .. . . .. ... 6·16

N MC27C32 UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·23

N MC27C256 UV Erasable CMOS PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·30

N MC98C64A Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·54

9

Section'1



Section Contents

Proposed Standard Terminology .................................... '.' .................................. 1-3

Proposed Standard Terminology

This databook includes a new set of symbols. This new format is a proposed industry standard for semIconductor memories. It is intended to clarify the symbols, abbreviations and definitions, and to make all memory data sheets consistent.

DC ELECTRICAL PARAMETER ABBREVIATIONS

All abbreviations use upper case letters with no subscripts. The initial symbol is one of these four characters:

V (Voltage) I (Current) P (Power) C (CapaCitance)

The second letter specifies Input (I) or Output (0), and the third letter indicates the High (H), Low (L) or Off (Z) state of the pin during measurements. Examples:

VIL - Input Low Voltage 10Z - Output Leakage Current

AC ELECTRICAL PARAMETER ABBREVIATIONS

All timing abbreviations use upper case characters with no subscripts. The initial character is always T and is fol· lowed by four or more descriptors. These characters specify two signal points arranged in a "from·to" se· quence that define a timing interval. The two or more descriptors for each signal point specify the signal name and signal transitions. The format using four descriptors is:

T X X X X

Sigoal oam. '<om ohl," l,toNal i, d.fI," ttl J Transition direction for first Signal

Signal name to which interval is defined

Transition direction for second signal

Signal definitions:

A = Address 0= Data In Q = Data Out W = Write Enable E = Chip Enable S = Chip Select G = Output Enable

Transition definitions:

H = Transition to High L = Transition to Low V = Transition to Valid X = Transition to Invalid or Don't Care Z = Transition to Off (High Impedance)

1·3

Example:

CHIP SELECT

S

DATA OUT --+-;,;,;,;,;,;,,;,;;;,--~---(

o

Chip Select access time, teo, the time from Chip Select low to Data Out valid, and the time from Chip Select low to Data Out active, tex, are shown.

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view; e.g., the address set·up time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view; e.g., the access time is shown as a maximum since the device never provides data later than that time.

WAVEFORMS

Symbol

~

IfIIM

Input Output

MUST BE WILL BE VALID VALID

CHANGE WILL CHANGE FROM H TO L FROM H TO L

CHANGE WILL CHANGE FROM L TO H FROM L TO H

DON'T CARE: CHANGI NG: ANY CHANGE STATE UNKNOWN

PERMITTED

N/A HIGH IMPEDANCE

Section 2

MOS .Memory Cross Reference Guide fI

MOS Memory Cross Reference Guide

Section Contents

Industry Package Cross Reference .......•.............................................................. 2-3

MOS Memory Cross Reference Guide ................................ : .......................•........... 2-4

MOS Memory Selection Guide .......................................................................... 2-5

2-2

MOS Memory Cross Reference and Selection Guide

National Semiconductor offers the widest range of MOS Memory circuits of any manufacturer, both domestic and foreign, with quality and reliability being our primary goal.

Industry Package Cross Reference Package Type Molded DIP CERDIP Flat Pack

National N J F

AMD P 0 F

GI R e

Fujitsu M Z

Xicor P 0

Hitachi P e

Intel P 0 F

Mostek N J F

Motorola P 0

NEe e 0

TI N J u OKI RS AS F

'Synertek P D F

Toshiba P e

2-3

MOS Memory Cross Reference Guide AMD Xlcor Fujitsu GI Hitachi Intel Mostek Motorola NEC OKI Synertek TI

AM9114 MBM8114 HM472114 M2114 MCM2114 ,..P02114 MSM2114 SY2114 TMS2114 en AM9128 MB8128 HM6116P MK4802 MCM2016 ,..P04016 MSM2128 SY2128 TMS4016 u ~ AM9147 MBM2147 HM4847 02147H MK2147H MCM2147 ,..P02147 SY2147 TMS2147 ... AM9148 MBM2148 HM2148 2148H MCM2148 SY2148 en

HM6264 2186

en MBM8264 HM4864 2164 MK4164 MCM6665 ,..P04164 MSM3764 TMS4164 u MB81257 HM50257 MK4556 MCM6256 ,..P041257 MSM41257 TMS41257 i c( z >-Q . AM2716 MBM2716 HN462716 2716 MCM2716 ,..P02716 MSM2716 SY2716 TMS2716 :& 0 a: AM2732 MBM27C32 HN462732 2732A ,..P02732 MSM2732 Q. w 2758 MSM2758 TMS2758 . HN48016 02816 :& HN48016 02816 0 4X2444 ER59256 a: Q.

ER5911 w w X2816A 28l7A 4(See Q 52B13)

~

Toshiba NATIONAL

TMM314 1MM2114 TMM2016 1NMC2116 TMM315 *1NMC2147H

1NMC2148H TC5564 3NMC6164

TMM4164 NMC3764 TMM41257 3NMC41257

TMM323 *MM2716 *NMC27C16

TMM2732 *NMC27C32 MM2758

NMC2S16 NMC9716 NMC9306

2NMC9348 3NMC9S17

Pins Type Organization

lS NMOS lk x4 24 NMOS 2kxS 18 NMOS 4kx 1 lS NMOS lk x 4 2S CMOS SkxS

16 NMOS 64kx1 16 NMOS 256k x 1

24 NMOS 2kx8 24 CMOS 2kxS 24 CMOS 2kxS 24 NMOS 1k x S

24 NMOS 2kxS 24 NMOS 2kxS 8 NMOS 256·blt S NMOS 1k·blt

2S NMOS 2kxS

• A + available 1. Low power available 2. Sole source 3. Future product 4. Not pin compatible Note: 41257= Nibble Mode

256 = Page Mode

MOS Memory Selection Guide Access

Temperature Access

Temperature Part Number Organization Time Part Number Organization Time (ns)

(OC) (ns)

(0C)

NMC6164-10 8kx8 100 o to + 70 NMC2816-25 2kx 8 250 o to + 70 NMC6164-12 8kx8 120 o to + 70 NMC2816-35 2kx8 350 o to + 70 NMC6164-15 8kx8 150 o to + 70 NMC2816-45 2kx8 450 o to + 70 NMC6164-20 8kx8 200 o to + 70 NMC2816M-25 2kx8 250 -55to + 125 MM2114 1kx4 450 o to + 70 NMC2816M-35 2kx8 350 - 55 to + 125 MM2114-2 1kx4 200 o to + 70 NMC2816M-45 2kx 8 450 -55to + 125 MM2114-3 1kx4 300 o to + 70 NMC3764-15 64kx 1 150 o to + 70 MM2114-15 1kx4 150 o to + 70 NMC3764-20 64kx 1 200 o to + 70 MM2114-25 1kx 4 250 o to + 70

NMC2147H 4kx 1 70 o to + 70 NMC41257-12 256 x 1 120 o to + 70 NMC41257-15 256x 1 150 o to + 70

NMC2147H-1 4kx 1 35 o to + 70 NMC41257-20 256x 1 200 o to + 70 NMC2147H-2 4kx 1 45 o to + 70 NMC2147H-3 4kx 1 55 o to + 70 NMC9817-20 2kx8 200 o to + 70

NMC2148H 1kx 4 ·70 o to + 70 NMC9817-25 2kx8 250 o to + 70

NMC2148H-2 1kx4 45 o to + 70 NMC9817-35 2kx 8 350 o to + 70

NMC2148H·3 1kx4 55 o to + 70 NMC9346 64 x 16-bit Serial o to + 70

MM2716 2kx8 450 o to + 70 Access

MM2716-1 2kx8 350 o to + 70 NMC9306 16 x 16·bit (N/A o to + 70 MM2716E 2kx8 450 -40 to +85 Serial

NMC27C16-35 2kx8 350 o to + 70 Access)

NMC9306E 16 x 16-bit (N/A - 40 to + 85 NMC27C16-45 2kx8 450 o to + 70 Serial NMC27C16E-45 2kx8 450 -40 to + 85 Access)

*NMC27C16HQ-45 2kx8 450 o to + 70

NMC27C32·35 4kx8 350 o to + 70 NMC9716-25 2kx8 250 o to + 70 NMC9716-35 2kx8 350 o to + 70

NMC27C32·45 4kx8 450 o to + 70 NMC9716-45 2kx8 450 o to + 70 NMC27C32E-45 4kx8 450 - 40 to + 70

*NMC27C32H-45 4kx8 450 o to + 70 NMC9716M-25 2kx8 250 -55to + 125

MM2758Q lkx8 450 : 0 to + 70 NMC9716M-35 2kx8 350 -55to + 125 NMC9716M-45 2kx8 450 -55to+125

'H= 10 ms max programming

2-5

Section 3

Dynamic RAMs II

Dynamic RAMs

Section Contents

NMC3764 65,536 x 1-Bit Dynamic RAM . ................................................................. 3-3

N,MC41257. 262,144 x 1-Bit Dynamic RAM . .................. " ........................................... 3-10

3-2

~National ~ Semiconductor

NMC3764 65,536 x 1·Bit Dynamic RAM

General Description The NMC3764 is a 65,536 by 1-bit dynamic RAM. It is fabricated with National's XMOSTM N-channel process and uses double polysilicon gate technology. This provides high density and improved reliability. The chip is passivated with a silicone coating for alpha particle immunity. '

The NMC3764 operates with a single 5V power supply with ± 10% tolerance. All inputs and outputs are TTL compatible.

Multiplexed address inputs with separate row and column strobes allow the NMC3764 to be packaged in a standard 16-pin DIP.

The NMC3764 must be refreshed every 2 ms. This is accomplished by performing any routine which cycles the row address strobe (RAS) active during each of the 128 different row addresses defined by row address inputs AO-A6 (the additional addresses provided by row address input A7 are not necessary for refreshing.) Any read, write, RAS-only refresh or hidden refresh cycle refreshes all cells at the selected row address. The RASonly refresh mode permits RAS to be cycled while the column address strobe (CAS) is held high, i.e., inactive.

Block And Connection Diagrams AD -Al

A2 -

Vee

~ SV

Vss

~ GNO

Conversely the buried refresh mode allows the memory to be refreshed by cycling RAS while CAS is held low, i.e., active, thus maintaining valid data on the output.

Features • MSpM screen available * • High performance: 120, 150,200 ns access times • Single power supply: 5V ± 10% • On chip substrate bias generator • Low power: 248 mW (max) active • Read, Write and Read-Modify-Write cycles • Common 1/0 capability using Early Write cycle

• Page Mode operation • G~ted CAS-noncritical timing • RAS-only Refresh and Buried Refresh capability

• 128 cycle, 2 ms refresh • TTL compatible: all inputs and outputs

• TRI·STATE~output

• Industry standard 16-pin configuration

DI

A3- ~-----------------.----------------~ A4-

AS -A6 -A7-

Pin Names

RAS CAS WE

Ao-A7 01 DO Vee Vss

·See the MST™ Program.

ROW CLOCKS

COLUMN CLOCKS

WRITE CLOCKS

Function

Row Address Strobe Column Address Strobe Write Enable Address Inputs Data Input Data Output Power (+5V) Ground

3-3

MEMORY ARRAY

TUDI5493-1

DO

Dual-In-Llne Package

NC • DI 2

WE 3

m 4

,At!

Az

Al

Vee

TL ')15493·2 TOP VIEW

Order Number NMC3764N NS Package Number N16F

Absolute Maximum Ratings (Note 1)

Operating Temperature Range Storage Temperature

O°Cto + 70°C - 65°C to + 150°C

1W

Voltage on Any Pin Relative to VSS

Power Dissipation Lead Temperature (Soldering, 10 seconds) Short Circuit Output Current

Recommended DC Operating Conditions Symbol Parameter Min

TA Ambient Temperature 0

VCC Supply Voltages (Notes 2, 3) 4.5

Vss 0

VIH Input High Voltage, All Inputs (Note 2) 2.4

VIL Input Low Voltage, All Inputs (Note 2) -1.0

DC Electrical Characteristics (at recommended operating conditions)

Symbol Parameter Min

ICCt Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC MIN, DO = High Impedance) (Note 4)

ICC2 Standby Current Power Supply Standby Current (RAS = VIH, DO = High Impedance)

ICC3 Refresh Current Average Power Supply Current, Refresh Mode (RAS Cycling: tRC = tRC MIN, DO = High Impedance) (Note 4)

ICC4 Page Mode Current Average Power Supply Current, Page Mode (RAS = VIL, CAS Cycling: tpc = tpc MIN, DO = High Impedance) (Note 4)

III Input Leakage Input Leakage Current, Any Input -10 (OV < VIN < Vce, All Other Pins Not Under Test = OV)

ILO Output Leakage Output Leakage Current -10 (DO is Disabled, OV < VOUT < Vce>

Output Levels VOH Output High Voltage (loUT = - 5 mA) 2.4

VOL Output Low Voltage (lOUT = 4.2 mA) 0

Capacitance Symbol Parameter Max

CI Input Capacitance, AO-A7, 01 (Note 5) 5

Cc Input Capacitance, RAS, CAS, WE (Note 5) 10

Co Output Capacitance, DO (Note 5) 7

-1.0Vto + 7V 300°C 50mA

Max Units

70 °C

5.5 V 0 V

6.5 V

0.8 V

Max Units

45 mA

5 mA

35 mA

42 mA

10 p,A

10 p,A

Vcc V 0.4 V

Units

pF

pF

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Recommended DC Operating Conditions" provides conditions for actual device operation.

Note 2: All voltages referenced to Vss.

Note 3: When applying voltages to the device, Vcc should never be 1.0V more negative'than Vss.

Note 4: Iccl • Icc3 and Icc4 depend on cycle rate. Note 5: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = ATItN. Capacitance is guaranteed by periodic testing.

3-4

AC Electrical Characteristics (at recommended operating conditions) (Notes 6, 7, 8)

Symbol Parameter

READ, WRITE CYCLES

tRAC Access Time from RAS (Notes 12, 13) 120 150

tCAC Access Time from CAS (Notes 12, 14) 80 100

tRP RAS Precharge Time 90 100 120

tRAS RAS Pulse Width 120 10k 150 10k 200

tCAS CAS Pulse Width 80 10k 100 10k 135

tRC Random Read or Write Cycle Time 240 270 330

tRCD RAS to CAS Delay Time (Note 9) 30 40 30 50 35

tCRP CAS to RAS Precharge Time 0 0 0

tRSH RAS Hold Time 80 100 135

tCSH CAS Hold Time 120 150 200

tASR Row Address Set-Up Time 0 0 0

tRAH Row Address Hold Time 20 20 25

tASC Column Address Set-Up Time 0 0 0

tCAH Column Address Hold Time 40 45 55

tAR Column Address Hold Time Referenced to RAS 80 95 120

tRCS Read Command Set-Up Time 0 0 0

tRCH Read Command Hold Time (Note 11) 0 0 0

tOFF Output Buffer Turn-Off Delay (Note 15) 0 35 0 40 0

twp Write Command Pulse Width 40 45 55

twcs WE to CAS Set-Up Time (Note 16) -10 -10 -10

tWCH Write Command Hold Time 40 45 55

tWCR Write Command Hold Time Referenced to RAS 80 95 120

tRwL Write Command to RAS Lead Time 40 45 55

tCWL Write Command to CAS Lead Time 40 45 55

tDS Data-In Set-Up Time 0 0 0

tDH Data-In Hold Time 40 45 55

tDHR Data-In Hold Time Referenced to RAS 80 95 120

tT Transition Time (Rise and Fall) 3 35 3 35 3

tRRH Read Command Hold Time Referenced to RAS 20 20 25

tREF Refresh Period 2 2

READ-MODIFY-WRITE CYCLES

tRWD RAS to WE Delay 90 110 145

tCWD CAS to WE Delay (Note 16) 50 60 80

tRWC Read-Write-Cycle Time 240 270 330

PAGE MODE CYCLES

CAS Precharge Time (Note 10)

Page Mode Cycle Time

Note 6: An initial pause of 100 p'S is required after power-up, followed by any 8 RAS cycles, before proper device operation is achieved. Note 7: Transition times are assumed to be 5 ns. Note 8: Timing reference points are V1H (min) and V1L (max). _

Units

200 ns

135 ns

ns

10k ns

10k ns

ns

65 ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

50 ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

50 ns

ns

2 ms

ns

ns

ns

ns

ns

Note 9: If tRCD (min) < tRCD < tRCD (max) the access time is tRAe (RAS limited timing). If the tRCD exceeds tRCD (max) the access time is tRCD plus tCAG (CAS limited timing). I

Note 10: tcp is necessary for RAS/CAS cycles preceded by a CAS only cycle or page mode cycle. Note 11: tRcH is referenced to the first rising edge of RAS or CAS .. Note 12: Load = 2 TTL loads and 100 pF. Note 13: Assumes tRCD < tRCD (~ (RAS limited timing). Note 14: Assumes tRCD > tRCD (CAS limited timing). Note 15: t()"" max defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Note 16: The placement of the negative going edge of WE with respect to the negative edge of ~ determines the type of write cycle. If twcs is greater than twcs (min) (negative edge of M before the negative edge of CAS) the memory is in an early write cycle and data out is TRI·STATE. If tcwD is greater than tCWD (min), the memory is in a read-write or read-modify-write cycle and data out is the original contents of the selected cell. If WE goes low between these two times, the cycle is a write cycle and data out is indeterminate.

3-5

Switching Time Waveforms

ADDRESSES VIL

Read Cycle Timing

COLUMN ADORESS

. L I-tRCH-!

tRRH-l

WE V'H=.!f/////////////.,..-g.--C:=:==-l~. VIL -'1//////////////1

1------tCAC-----t

It--,1---------tRAC---------I !oFF

DOUT VOH-" __________ ~ OPEN VALID DATA

VOL-

TUO/5493-3

Write Cycle Timing (Early Write)

'n~

"'[\ )1 .)\ VIH- "n ..

VIL- \. nr

I 'n~u 'un" I nr

VIH- "'1\ \ ]V if VIL- -'~

I tRAH tASC- rtCAH + I-- I-

ADDRESSES WJA. , ROW l .1J7l77A.. t«" COLUMN l fjjl/; v'" !III//i/~ ADDRESS ADDRESS IL -(ff1f1U ~ 'j WIf/U" ~ '"

I tCWL ·1 I !--tWCH--+ .... ~!J

f/, • -,n -Wd VIL

IRWL ·1 ~.-- tWCR

D" ::~:~ "u.::' ~_I"' ____ ~---..j DOUT VOH

VOL- OPEN

3-6

I TUD/549:K

Switching Time Waveforms (Continued)

Read-WritelRead-Modify-Write Cycle

~------------------------------IRWC--------------------------------------~

~--------------------------------IRAS------------------------~ I,-_____ ~I

1------+----.,----------- IRSH -----------------1 t--IIRP ---I

ADDRESSES VIH Vil

WE VIHVll-

~-----------4----~------+-------ICSH--------~------------~

-------

Dour VOH-___ -t-_____ -1 VOl- OPEN

RAS Only Refresh Timing

IOFF

TUD15493-5

1------------------------IRC-------------------------l

t----------IRAS----------.j

ADDRESSES

.-

_ ~ASR VIH-

Vll- """'''''''''''''''''''''''''''''''''''''''''''''' _____ _

VOH-Dour VOL - ------------1 OPEN

TUD15493-6

Note: CAS: VIH, WE and DIN: Don'l care.

3·7


Hidden Refresh

t-------READ CyCLE-------i------RAS ONLY CYCLE-----t

CAS ~:~= --I+--.... ~

OOUT VOH- ----OPEH-----t'l VOl-

ADDRESSES VIHVIL-

DOUT VOH- OPEN-----~ VOL-

~ V,,-==~." VIL-~ "~"""","~jI"fJI

VALID DATA

Page Mode Read Cycle

3·8

TUD/5493-7

TUD/5493-8


Page Mode Write Cycle

3·9


PRELIMINARY

NMC41257 262, 144 x 1-Bit Dynamic RAM

General Description The NMC41257 is a 262,144 words by 1-bit new generation dynamic RAM. It is fabricated with National's proprietary N-channel triple-polysilicon technology which combines high performance and high density with improved reliability and excellent alpha radiation tolerance.

The NMC41257 is designed to operate with a single + 5V power supply with ± 10% tolerance. The use of a single transistor memory cell and advanced dynamic circuitry enable it to achieve high speeds with low power consumption.

Multiplexed address inputs with separate row and column strobes allow the NMC41257 to be packaged in a standard 16-pin DIP. It is available in both plastic and cerdip packages.

The NMC41257 must be refreshed every 4 ms. This is accomplished by performing any cycle which brings the row address strobe (RAS) active at each of the 256 row addresses. Thus any read, write, RAS-only refresh or hidden refresh cycle refreshes all cells at the selected row address. The RAS-only refresh mode permits the RAS to be cycled while the column address strobe (CAS) is held high, i.e., inactive. In this mode, addresses AO-A7 select the roW that is refreshed. In addition, a CAS before RAS automatic refresh is provided. When RAS goes low after CAS has

been low (by tCSA), the internal refresh counter is activated to generate the addresses to be refreshed. In this mode all address inputs are ignored by the device. A nibble mode is also provided allowing the serial access of 4 bits of data at a very high data rate. Nibble mode address is controlled by the addresses supplied to pin 1 (AS - Rowand Column).

Features • High performance: 100, 120, 150 ns access time

• Single power supply: 5V. ± 10% • Low power: 22 mW (max) standby

412 mW (max) active

• Wide RAS to CAS delay windows • Read, Write and Read-Modify-Write cycles

• Common I/O capability using Early Write cycle

• RAS-only Refresh and Hidden Refresh capability

• Automatic CAS before RAS refresh mode

• 256 cycle, 4 ms refresh • TTL compatible: all inputs and output

• Industry standard 16-pin configuration

• TRI-STATE® output

• Fast nibble mode on either read or write cycles - 20 ns access (41257-10) - 40 ns cycle (41257-10)

• MSTTM screen available*

Block Diagram NMC41257 Vss

! ROW

TIMING

AUTO REF. ROW ADD COUNTER BUFFER

Ao ... A7 • See the MST program.

64K ARRAY

512 SENSE AMP

2 OF 256 COL

DECODER

64K ARRAY

64K ARRAY

3-10

~S (CE)

512 . SENSE

AMP

2 OF 256 COL

DECODER

64K ARRAY

1---"". 1 OF 128 ROW

DECODER

~DO ~(Q)

DI BUFFER

WRITE TIMING

DI (D)

TUDI7S1()'1

Connection Diagram Dual-In-Line Package

As ..! '-' t1t Vss Pin Names

DI~

we.2 t!L CAS

~DO

RAS (RE) Row Address Strobe CAS (CE) Column Address Strobe WE (W) Write Enable

RAS .,j t1!- Ae Ao-As Address Inputs

Ao .J ~A3 o I (D) Data Input DO (Q) Data Output

A2.l ~A4 Vcc Power (5V)

A12 ~A5 Vss Ground

Vee ...! .LA7

TOP VIEW TU01751()'2

NS Package Number N16A

Absolute Maximum Ratings (Note 1) Device

Operating Temperature Range Storage Temperature

OOC to + 70°C -65°C to + 150°C

1 Watt -1.0V to + 7V

tRAC (ns, Max)

tCAC (ns, Max) Power Dissipation -

tRC (ns, Min) Voltage on Any Pin Relative to Vss Lead Temperature (Soldering, 10 seconds) ICCl (rnA, Max) -

Icc2 (mA, Max)

Recommended DC Operating Conditions Symbol Parameter Min

Ambient Temperature o VCC Supply Voltages (Notes 2 and 3) 4.5

Vss Supply Voltages (Notes 2 and 3) o Input High Voltage, All Inputs (Note 2) 2.4

Input Low Voltage, All Inputs (Note 2) -1.0

DC Electrical Characteristics (at recommended operating conditions)

Symbol

leCl

leC2

leC3

loz

VOH VOL

Parameter

Operating Current Average Power Supply OperatiJlg Current (Note 4) (RAS, CAS Cycling, tRC = tRC MIN)

Standby Current Power Supply Standby Current (RAS = CAS = VIH, DO = High Impedance)

Refresh Current (RAS only) Average Power Supply Current, Refresh Mode (Note 4) (RAS Cycling, CAS = VIH, tRC = tRC MIN)

Refresh Current (automatic CAS before RAS) Average Power Supply Current, Refresh Mode (Note 4) CAS = VIL, RAS Cycling, tRC = tRe MIN)

Input Leakage Input Leakage Current, Any Input (OV < VIN < Vee, All Other Pins not Under Test=OV)

Output Leakage Output Leakage Current (Do is Disabled, OV < VOUT < Vee>

Output Levels Output High Voltage (lOUT = -5 mA) Output Low Voltage (lOUT = 4.2 mA)

3-11

NMC 41257-10

100

50

200

75

4

Max

70

5.5

o VCC+1.0

Min

-10

-10

2.4 o

0.8

NMC 41257-12

120

60

230

75

4

Max

75

4

50

50

10

10

Vee 0.4

NMC 41257-15

150

75

280

7~

4

Units

V

V

V

V

Units

mA

mA

mA

mA

p.A

p.A

V V

AC Testing Conditions 2. Input Levels

I Vil (Max)

I O.BV

I 1. Data Out Load VIH (Min) 2.4V

DEVICE DATA 220n ... < VREF=1.311V 3. Output Levels UNDER DUT.l. .... TEST

I VOL

I 0.4V

I IOl = 4.2 rnA

I J'OO" VOH 2.4V IOl = -5.0 rnA

TUDI751().3

4. Transition times are measured between O.BV (\Ill Max) and 2.4V (VIH Min). Rise and fall times are 5 ns.

Capacitance Symbol Parameter Max Units

CI Input Capacitance, AO-AB, 01 (Note 5) 5 pF

CC Input Capacitance,. RAS, CAS, WE (Note 5) 10 pF

CO Output Capacitance, DO (Note 5) 7 pF

AC Electrical Characte~istlcs (at recommended operating conditions) (Notes 2, 6, 7, and B)

Symbol NMC41257-10 NMC41257-12 NMC41257-15

Parameter Units Min Max Min Max Min Max

READ, WRITE CYCLES

tRAC Access Time from RAS (Notes 11, 12) 100 120 150 ns

tCAC Access Time from CAS (Notes 11, 13) 50 60 75 ns

tRP RAS Precharge Time 90 100 120 ns

tRAS RAS Pulse Width 100 10k 120 10k 150 10k ns

tCAS CAS Pulse Width 50 60 75 ns

tRC Random Read or Write Cycle Time 200 230 280 ns

tRCO RAS to CAS Delay Time (Note 9) 20 50 25 60 25 75 ns

tCRP CAS to RAS Precharge Time 10 10 10 ns

tRSH RAS Hold Time 50 60 75 ns I

tCSH CAS Hold Time 100 120 150 ns

tASR Row Address Set-Up Time 0 0 0 ns

tRAH Row Address Hold Time 15 20 20 ns

tASC Column Address Set-Up Time 0 0 0 ns

tCAH Column Address Hold Time 25 30 30 ns

tAR Column Address Hold Time Referenced to RAS 75 90 105 ns

tRCS Read Command Set-Up Time 0 0 0 ns

tRCH Read Command Hold Time (Note 10) 0 0 0 ns

tOFF Output Buffer Turn-Off Delay (Note 14) 20 25 25 ns

twp Write Command Pulse Width 20 25 30 ns

twcs WE to CAS Set-Up Time (Note 15) 0 0 0 ns

tWCH Write Command Hold Time 20 25 30 ns

tWCR Write Command Hold Time Referenced to RAS 95 100 120 ns

tRWl Write Command to RAS Lead Time 40 45 45 ns

tcWl Write Command to CAS Lead Time 40 45 45 ns

tos Data-In Set-Up Time 0 0 0 ns

3-12

AC Electrical Characteristics (Continued)

NMC41257-10 NMC41257-12 NMC41257-15 Symbol Parameter

Min Max Min Max Min Max Units

tOH Data-In Hold Time 20 25 30 ns

tOHR Data-In Hold Time Referenced to RAS 85 100 120 ns

tT Transition Time (Rise and Fall) (Note 7) 3 50 3 50 3 50 ns

tREF Refresh Period 4 4 4 ms

READ-MODIFY-WRITE CYCLES

tRWO RAS to WE Delay 100 120 150 ns

tcwo CAS to WE Delay (Note 15) 50 60 75 ns

tRWC Read-Write-Cycle Time 245 280 330 ns

tRRW RMW Cycle RAS Pulse Width 145 10k 170 10k 205 10k ns

tCRW RMW Cycle CAS Pulse Width 95 110 130 ns

REFRESH CYCLE

tCSR Column Address Strobe Setup Time for Auto Refresh 10 10 10 ns

tCHR Column Address Strobe Hold Time for Auto Refresh 30 30 30 ns

tRPC Precharge to CAS Active Time 0 0 0 ns

NIBBLE MODE CYCLE

tNC Nibble Mode Cycle Time 40 50 60 ns

tNAC Nibble Mode Access Time 20 25 30 ns

tNAS Nibble Mode Setup Time 20 25 30 ns

tNP Nibble Mode Precharge Time 10 15 20 ns

tNRSH Nibble Mode RAS Hold Time 20 25 30 ns

tNCWD Nibble Mode CAS to WRITE Delay 20 25 30 ns

tNCRW Nibble Mode RMW CAS Pulse Width 45 55 !~:.: .. ~; 65 ns

tNCWL Nibble Mode WRITE to CAS Lead Time 20 25 ·~t·~~ ~;" 30 ns

AUTO REFRESH COUNTER TEST MODE

tATC Refresh Counter Test Cycle Time (Note 16) 360 410 500

tTRAS Refresh Counter Test RAS Pulse and Width (Note 16) 260 10k 300 10k 360 10k

tCPT Refresh Counter Test CAS Precharge Time (Note 16) 50 60 70

Note1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the device should be operated at these limits. The table of "Recommended DC Operating Conditions" provides conditions for actual device operation. _

Note 2: All voltages referenced to Vss.

Note 3: When applying voltages to the device. Vcc should never be 1.0V more negative than Vss.

Note 4: Icc,. Icca. and Icc4 depend on cycle rate measured with output open.

Note 5: Capacitance measured with 800nton Meter or effective capacitance calculated from the equation C = I AUAV with the recommended DC operating conditions applied to the device. Capacitance is guaranteed by periodic testing.

Note 6: Any 8 cycles that perform refresh must be applied following either p'ower on or periods of no row address strobe activity exceeding 4 ms.

Note 7: Transition times are assumed to be 5 ns.

Note 8: Timing reference points are V1H (min) and V1L (max).

Note 9: If tRCO (min) < tACO < tACO (max) the access time is tRAe (row timing limited). If the tACO exceeds tACO (max) the access time is tACO plus tCAe (column timing limited). If - 10 ns < tACO < tACO (min) the cycle is indeterminate.

Note 10: tACH is referenced to the first rising edge of RAS or CAs. Note 11: See AC Testing Conditions for output load.

Note 12: Assumes tACO < tACO (max) (row limited timing),

Note 13: AsslJmes tACO > tACO (max) (column limited timing).

Note 14: tOFF max defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.

Note 15: The placement of the negative gOing edge of WE with respect to the negative edge of CAS determines the type of write cycle. If twcs is great,er than 0 ns (negative edge of WE before the negative edge of CAS) the memory is in an early write cycle and data out is TAl-STATE. If tcwD is greater than tCWD (min) the memory is in a r-;ad-write or read-modify·write cycle and data out is the original contents of the selected cell. If WE goes low between these two tim'es the cycle is a write cycle and data out is indeterminate.

Note 16: Read·modify·write cycle only.

3-13

tIl) N ,... ~ o :E z

Switching Time Waveforms

VIH-ADDRESS

Vll-

WE VIH-

Vll-

VOH-DO (0)

VOl-

RAS VIH-

Vll-

CAS VIH-

Vll-

ADDRESS VIH-

Vll-

WE VIH-

Vll-

01 (D) VIH-

Vll-

DO (0) VOH-

VOl-

Read Cycle Timing

i+-----------tRc-------------+I

~---------tRAS--------___i

i+----tcAc---+l

1--------tRAc-------~

---------HIGH Z----------cI

Early Write Cycle

HIGH Z

3-14

- tOFF

VALID DATA

TUOI7S10-4

TU017S10-5


ADDRESS

01 (D)

DO (0)

RAS

ADDRESS

RAS

CAS

DO (0)

Read-Modify-Write or Late Write Cycle

t+-------------tAWC---------------i

f4---------tAAw-----------l

f4-----tAwo-----..t

f4----tAco----..t

1----tAP----l

t+--+----tcAw----~·1

r-----------------VIH----~~-----~ VIL-

VOH-

VOL-

VIH-

Vll-

VIH-

Vll-

VIH-

Vll-

VOH-

tAWL-:----.-i I--+----tcwl---'--..j

...,..,iitos

tOH--\

HIGH Z

< VALID DATA

RAS Only Refresh Cycle (Data-in and Write are Don't Care)

tAC

tAAS

Automatic (CAS Before RAS) Refresh Cycle

tAC

tAP- I tAAS

}f- :1~r-

-tAPC tCSR-- I- tCHR

) TliD/7510-6

TUDn510·7

-,~r-

VOL- ----------------------------------HIGHZ----------------------------------TUD/7510·8

3·15


Hidden Refresh Cycle

I+-------IRC-------.j

RAS VIH-

VIL- READ CYCLE

I-----IRAS----~

CAS VIH-

VIL-

VIH_ ADDRESS

VIL-

WE VIH-

VIL-

VOH-DO (0)

VOL--------HIGH Z

ICAC~If'--~-----------~ ______ _ _ VALID

DATA

TUD1751D-9

Nibble Mode Read Cycle*

f----------------IRAS-----------------~

I------ICSH ------1

RAS VIH-

VIL-

CAS VIH-

VIL-

ADDRESS VIH-

VIL-

WE VIH-

VIL-

DO (0) VOH- -----------00(] VOL- ~ ___ ...... ,-

·Pin 1 at row time and column time determine the starting address of the nibble cycle. TUD1751D-l0

3-16


Nibble Mode Write Cycle (Early Write)

VIH-CAS

Vll-

VIH-ADDRESS

VIL-

VIH-WE

VIL-

VIH-01 (D)

Vll-

DO (0) VOH~

VOl-HIGH Z

TUD17510-11

Nibble Mode Read-Modify-Write

VIH-RAS

VIL-

VIH-CAS

VIL-

VIH-ADDRESS

VIL-

VIH-WE

VIL-

VIH-01 (D)

VIL-

DO (0) VOH-

HIGH Z VALID

VOL- DATA

TUD17510-12

3-17


Auto Refresh Counter Test Cycle

~-----------------------tmc------------------------~ ~-----------------tAAS----------------~

ADDRESSES

WE (READ)

VIH-DO (Q) ------------------------------~--41

WE (WRITE)

DI (D) .-ltos

tOH::! ~:~ II!~V-A-lI-D-DA-:r-A-~~

Functional Description Device Initialization: The 256K dynamic RAM requires a single + 5V supply. After power up an initial 100 microsecond pause is required to allow an internal substrate pump to establish the correct substrate bias. After this pause a minimum of 8 cycles of Row Address Strobe (RAS) clock must be given to the part to allow the internal dynamic circuitry to reach proper levels. Upon completion of the initialization sequence the part will be ready to operate in accordance with these specifications.

Address Inputs: Eighteen binary address inputs are required to address anyone of 262,144 bits in this DRAM. These addresses are multiplexed and strobed into the part in two groups of 9 addresses by the negative going edge of the Row Address Strobe (RAS) and Column Address Strobe (CAS) clocks. The delay interval between these two clocks (tReD) describes the minimum time at which the column addresses may follow the row addresses for good device performance and the maximum time at which the column addresses may follow the row addresses before the Access Time (tRAd will begin to increase beyond the specification.

Reading Data: A read cycle begins by presenting a valid row address to the address inputs and bringing the RAS input from V1H to V1L. This causes the row addresses to be latched into the part. This is followed by presenting a valid column address to the address inputs and bringing the CAS input from V1H to VI~which time the column addresses are latched in. If the CAS input transition is made before the tRCD maximum time then valid data will appear on data out

3·18

TuonSlO·13

in time to meet the tRAC specification. If the CAS input transition is made after the tRCD maximum time data out will be valid in time to meet the tCAC speCification. The external CAS signal may become active as soon as the row address hold time (tRAH) specification has been met and defines the tRCD minimum specification. The time difference between tRCD minimum and tRCD maximum can be used to absorb skew delays in switching the address bus from row to column addresses and in generating the CAS clock.

Once the clocks have become active, th~ust stay active for the minimum (tRAS) period for the RAS clock and the minimum (tCAS) period for the CAS clock. The RAS clock must stay inactive for the minimum (tRP) time. The former is for the completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle.

Data out is not latched and is valid as long as the CAS clock is active; the output will switch to the TRI-STATE mode when the CAS clock goes inactive. To perform a read cycle, the write (WE) input must be held at the V1H level from the time the CAS clock makes its active transition (tRCS) to the time when it transitions into the inactive (tRCH) mode. .

Writing Data: The write cycle is similar to the read cycle except the Write Enable (WE) clock must be at VIL during the time CAS is active. If the WE transition is done before the minimum twcs time, the cycle will be an early write cycle (data out remains in TRI-STATE). If WE makes a transition after tCWD minimum time, the cycle will be a read-modify-

Functional Description (Continued)

write cycle. If WE makes a transition between twcs and tcwD time, then the type of cycle is indeterminate.

Data is supplied to the data in input and is latched in with Write Enable (WE) in the same manner as the addresses are with RAS and CAS provided the WE transition is made after the CAS transition. If the WE transition is made before the CAS transition, then the data is latched by the CAS transition.

The Read-Modify-Write Cycle: This type of cycle allows the user to both read and write a single bit in memory during the same cycle.

For the read-modify-write cycle a normal read cycle is initiated with the write (WE) clock at the V1H level until after the tCWD time has elapsed. At this time the write (WE) clock is asserted. The data in is set up and held with respect to the active edge of the write clock. The cycle described assumes a zero modify time between read and write.

Refreshing the DRAM: The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the bits need to be refreshed at least once every 4 ms. This is accomplished by sequentially cycling through the 256 row address locations every 4 ms. These row addresses are controlled by address inputs AO through A7. A normal read or write operation to the RAM will serve to refresh all the bits (1024) associated with that particular row decoded.

For RAS-Only Refresh type cycle the memory component is in standby. In this refresh method, the user must perform a RAS-only cycle on all 256 row addresses e~ 4 ms. The row addresses (AO-A7) are latched with the RAS clock, and the associated internal row locations are refreshed. As the heading implies, the CAS clock is not required and should be inactive or at a VIH level to conserve power.

3-19

For a CAS before RAS refresh (auto refresh) type cycle RAS falls after CAS has been low by tCSR' This activates the internal refresh counter which generates the address to be refreshed. Externally applied addresses are ignored during the automatic refresh cycle. If the output buffer was off \ before the automatic refresh cycle, the output will stay in the high impedance state. If the output was enabled by CAS in the previous cycle, the data out will be maintained during the automatic refresh cycle as long as CAS is held active (hidden refresh).

The Nibble Mode Cycle: Nibble Mode Operation allows faster successive data operation on 4 bits. The first bit is accessed in the usual manner with read data coming out at tCAC time. By keeping RAS low, CAS can be cycled up and then down, to read or write the next three bits at a high data rate (tNAd. Rowand column addresses need only be supplied for the first access of the cycle. From then on, the failing edge of CAS will activate the next bit. After four bits have been accessed, the next bit will be the same as the first bit accessed (wrap-around method).

~[O,O]~[O,1]"'[1,O]"'[1,1]~

Pin one (AS) determines the starting point of the circular 4-bit nibble. Row AS and Column AS provide the two binary bits needed to select one of four bits. From then on, successive bits come out in a binary fashion; 00 ... 01--.10~11 with AS row being the least significant address.

A nibble cycle can be a read, write, or late write cycle. Any combinations of reads and writes or late writes will be allowed. In addition, the circular wrap-around will continue for as long as RAS is kept low.

Section 4

NMOS Static RAMs

NMOS Static RAMs

Section Contents

MM2114, MM2114L Family 4096-Bit(1024x 4) Static RAMs...... ... . ....... ... . ... .... . . . .. . . . . . . .. . .. ... .. 4-3

NMC2147H 4096 x 1 Static RAM ............................................ -........................... 4-7

NMC2148H 1024x4Static RAM .............................. ,.,_ ..... ' .................................. 4-11

NMC21,16 2048 x 8 Static RAM ......................................... ; .............................. 4-15

4-2

~National ~ Semiconductor MM2114/MM2114L Family 4096-Bit (1024 x 4) Static RAMs

Maximum MM2114· MM2114· MM2114· MM2114· Access/Current 15L 2L 25L 3L

Access (TAVQV -ns) 150 200 250 300

Active Current (ICC-mA) 70 70 70 70

General Description The MM2114 family of 1024·word by 4·bit static random access memories is fabricated using N-channel sllicongate technology. All internal circuits are fully static and therefore require no clocks or refreshing for operation. The data Is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.

The separate chip select input (CS) allows easy memory expansion by OR-tying individual devices to a data bus.

Block Diagram *

A3

A4

A5

A6

Al 11

AS 16

1/01 14 (0011

1/02 13 (ODZ)

1/03 12 (003)

1/04 11 (004)

WE 10 (W)

* Symbols in parentheses are proposed industry standard.

ROW SelECT

4-3

MM2114· MM2114· MM2114· MM2114· MM2114· MM2114 L 15 2 25 3

450 150 200 250 300 450

70 100 100 100 100 100

Features • All inputs and outputs directly TTL compatible • Static operation-no clocks or refreshing required • Low power-225 mW typical ' • High speed-down to 150 ns access time • TRI·STATE~ output for bus interface • Common Data In and Data Out pins • Single 5V supply • Standard 18-pln dual·in·line package • Available with MIL-STD-883 class B screening

MEMORY ARRAY 64 ROWS

64 COLUMNS

CO LUMN liD CIRCUITS

..-!!-oVCC

TL/D/5258-1

Write Cycle AC Electrical Characteristics (Note 3) TA = O°C to + 70°C, Vee = 5V ± 5%

Symbol MM2114·15 MM2114-2 MM2114·25 MM2114-3 MM2114

Parameter MM2114·15L MM2114·2L MM2114·25L MM2114·3L MM2114-L Units Alternate Standard Min Max Min Max Min Max Min Max Min Max

twe TAVAV Write Cycle Time 150 200 250 300 450 ns

twp TWLWH Write Pulse Width 90 100 125 150 200 ns

tWA TWHAX Write Recovery Time 0 0 0 0 0 ns

tow TDVWH Data Set·Up Time 90 100 125 150 200 ns

tOH TWHDX Data Hold Time 0 0 0 0 0 ns

twz TWLOZ Write Enable to Output 0 40 0 40 0 60 0 80 0 100 ns TRI·STATE (Note 5)

tow TWHOX Output Active from End of 80 80 90 100 120 ns Write (WE) (Note 5) ..

*Symbols in parentheses are proposed Industry standard.

Write Cycle Waveforms· (Note 4)

Write Cycle 1 (Write Enable Limited) twe

(TAVAV)

ADDRESS~~ -;f--

eHIPSELECT~ I~ ~ '~(T~~~X)-

(~~~H) ~ ~, .. 7'--·

tow tDH

~ nDVWH) I (TWHDX)

DATA IN *-I ~z l-taWHQX) I (TWLUZI

HIGH ,n .. ,r<

.,:,,~~ DATA OUT . UNDEFINED-r --vxx

TUD/5258·2

Write Cycle 2 (Chip Select Limited)

twe nAVAVI

ADDRESS ~~ ~~ -tew

(TSLWH)

-C'iiiiiS'ETICf -'~ 1'-

twp twR ,"'L"", (TWHAXI

WIITfITNi("8"[E ~ ~<- '}~~~ tow tOH

i nDVWH) .1 (TWHDX)

DATA IN * I I

(T~t~X)-II h~~tZ)1 -{:OATI -x HIGH IMPEDANCE

DATA OUT ..¥.

TUD/5258-3

4-4 .

Read Cycle AC Electrical Characteristics TA = O°C to + 70°C, Vcc = 5V ± 5%

Symbol MM2114·15 MM2114·2 MM2114·25 MM2114·3 MM2114

Parameter MM2114·15L MM2114·2L MM2114·25L MM2114·3L MM2114·L Alternate Standard Min Max Min Max Min Max Min Max Min

tRc TAVAV Read Cycle Time (WE = VIH) 150 200 250 300 450

tAA TAVQV Address Access Time 150 200 250 300

tACS TSLQV Chip Select Access Time 70 70 90 100

tlZ TSLQX Chip Select to Output Active 20 20 20 20 20 (Note 5)

tHZ TSHQZ Chip Deselect to Output 0 40 0 40 0 60 0 80 0 TRI·STATE (Note 5)

tOH TAXQX Output Hold from Address 15 10 10 10 10 Change

Read Cycle Waveforms *

ADDRESS

DATA OUT

Read Cycle 1 (Continuous Selection CS = V1Lo WE = V1H )

IAA (TAVQV)

IRC I (TAVAV) .1

DATA VALID PREVIOUS DATA VALID ]( '------' _

IDH .----1 (TAXQX) I

Read Cycle 2 (Chip Select Switched, WE = V1H)

TUD/525B-4

f-----(T~-~V)=====:'~----

ADDRESS -------..... ~

-------..... ----IAA---

.1. lACS

CHIP SELECT \. (TSLQV)--

(T~~lix)-I l- 4(T~~liz) DATA _______________ ~7~~~·.-·· .. ~~~------------~~1~------~

OUT HIGH IMPEDANCE -\, .:~ .Y. HIGH IMPEDANCE

TUD/5258·5

Note 3: A write occurs during the coincidence low of Cs and WE.

Max

450

120

100

Note 4: The output remains TRI·STATE if the Cs and WE go high simultaneously. WE or CS or both must be high during the address transitions. Note 5: Measured:l: 50 mV from steady state voltage. This parameter is sampled and not 100% tested.

DC Electrical CharacteristicsTA=o°Cto +70·C, Vcc=5V ±5%

MM2114, MM2114·15, MM2114·L, MM2114·15L,

Symbol Parameter Conditions MM2114·2, MM2114·25, MM2114·2L, MM2114·25L,

Units MM2114·3 MM2114·3L

Min Max Min Max

III Input Load Current V1N = OV to 5.25V -10 10 -10 10 Jl.A (All Input Pins)

ILO Output Leakage Current CS = V1H, VOUT = O.4V to 4V -10 10 -10 10 Jl.A

V1l Input Low Voltage -0.5 0.8 -0.5 0.8 V

V1H Input High Voltage 2.0 Vcc 2.0 Vce V

VOL Output Low Voltage 10l = 2.1 rnA 0.4 0.4 V

VOH Output High Voltage 10H= -1.0 rnA 2.4 . 2.4 V

Icc Power Supply Current V1N =5.25V, TA=O·C 100 70 rnA Outputs Open

* The symbols in parentheses are proposed industry standard.

4·5

s: s: N

Units ..... ..... ,1::1.. ""'-

ns s: ns s: ns N ..... ns .....

,1::1..

ns r-

ns

Logic Symbol*

- AD

- Al

- A2

- A3

- A4

- AS

- A6

- A7

- A8

- A9

Pin Names·

AO-A9

WE(W) CS(S)

1/01 t-(Oal)

1/02 (Oa2) I-

1/03 ~ (Oa3)

cs 1/04 I-(s) : (Oa4)

Y Y TUD/5258-6

Address Inputs

Write Enable

Chip Select

1101-1104 (001-004) Data Input/Output

Absolute Maximum Ratings Voltage at Any Pin -0.5Vto + 7V

Storage Temperature -65°Cto -150°C

Power Dissipation 1W

Lead Temperature (Soldering, 10 seconds) 300°C

CapacitanceTA =25°C, f=l MHz (Note 1)

Connection Diagram *

Dual·ln·L1ne Package

In;--- 18 A6 - I-Vcc

AS 2 17 I-A7

A42 ~A8

A3..! 15 ~A9

5 14 1/01 AO- ~(Oal)

6 13 1/02 Al- 1-(002)

A2.!. ~1/03 (Oa3)

CS(S)..! ~1/04 (Oa4)

Vss ..! 10 _ I-WE (W)

TOP VIEW TUD/5258-7

Order Number MM2114N·15L, MM2114N·15, MM2114N·2L, MM2114N·2, MM2114N·3L,

MM2114N·3, MM2114N·L or MM2114N NS Package Number N18A

Operating Conditions Min Max

Supply Voltage CY cd 4.75 5.25

Ambient Temperature (T ~ 0 +70

MM2114, MM2114-15, MM2114-L, MM2114-15L,

Units

V

°C

Symbol Parameter Conditions MM2114-2, MM2114-25, MM2114-2L, MM2114-25L,

Units

C,N Input Capacitance All Inputs V,N = OV

COUT Output Capacitance Vo = OV (Note 2)

Note 1: This parameter Is guaranteed by periodic testing.

Note 2: COUT Is max 10 pF for(J) package.

AC Test Conditions Input Pulse Levels

Input Rise and Fall Times Input Timing Level

·Symbols in parentheses are proposed industry standard.

OVto3V

:510 ns

1.5V

Min

4-6

MM2114-3 Max

5

5

Output Load and Timing Levels

MM2114-3L' Min Max

5 pF

5 pF

0.8V @ 2.1 rnA + 100 pF 2.0V@ -1.0mA+100pF

~National ~ Semiconductor NMC2147H 4096 x 1 Static RAM

Max Access/Current NMC2147H·l NMC2147H·2 NMC2147H·3 NMC2147H·3L NMC2147H

Access (TAVQV - ns) 35 45 55 55 70

Active Current (ICC - rnA) 180 180 180 125 160

Standby Current (ISB - rnA) 30 30 30 20 20

General Description Features The NMC2147H is a 4096-word by 1-bit static random access memory fabricated using N-channel silicon-gate technology. All internal circuits are fully static and therefore require no clocks or refreshing for operation. The data is read out nondestructively and has the same polarity as the input data.

• All inputs and outputs directly TTL compatible • Static operation-no clocks or refreshing required

The separate chip select input automatically switches the part to its low power standby mode when it goes high.

The output is held in a high impedance state during write to simplify common 1/0 applications.

Block Diagram*

• Automatic power-down • High speed-down to 35 ns access time • TRI-STATE® output for bus interface

• Separate Data In and Data Out pins • Single 5V supply • Standard 18-pin dual-in-line package • Available in MIL-STD-883 class B screening

Logic Symbol *

AD ..,!.!..o vcc

+!.oVSS

Al

A2 MEMORY ARRAY

64 ROWS 64 COLUMNS

AJ

A4

A5

COLUMN 110 CIRCUITS DOUT (Q)

Pin Names·

AD-All WE(W) CS(S) DIN(D)

DOUT(Q)

VCC

VSS

Address Inputs

Write Enable

Chip Select

Data In

Data Out

Power (5V)

Ground

COLUMN SELECT

A9

* The symbols In parentheses are proposed Industry standard.

Al Tl1D/5257·1

Order Number NMC2147HJ-1, NMC2147HJ-2, NMC2147HJ-3

or NMC2147HJ-3L NS Package Number J18A

Order Number NMC2147HN-1, NMC2147HN-2, NMC2147HN-3

or NMC2147HN-3L NS Package Number N18A

4-7

Al

A2

A3

A5

A6

A7

AS

A9

AID

All DIN (0)

cs (5)

f

DIN (D)

DOUT (a)

WE (W)

Tl1D/5257·3

Connection Diagram* Dual-In-Llne Package

18 AD vec

AI

A2

AJ

A4

A5

VSS 10 CS IS)

TOP VIEW TL/D/525/.2

.,.

Absolute Maximum Ratings Truth Table * Voltage on Any Pin Relative to VSS -3.5Vto +7V CS WE DIN DoUr Storage Temperature Range -65°Cto +150°C (S) (W) (0) (a) Mode Power

Power Dissipation 1.2W H x x Hi·Z Not Selected Standby

DC Output Current 20mA L L H' Hi·Z Write 1 Active

L L L Hi·Z Write 0 Active Bias Temperature Range -65°Cto +135°C L H X DOUT Read Active Lead Temperature(Soldering, 10 seconds) 300°C

DC Electrical Chanicteristics TA = O°C ~o 70°C, VCC = 5V ± 10% (Notes 1 and 2)

NMC2147H·1

Symbol . ' Parameter Conditions NMC2147H·3L NMC2147H·2 NMC2147H

Units NMC2147H·3

Min Max Min Max Min Max

IILlI Input Load Current VIN = OV to 5.5V, VCC = Max 10 10 ' 10 p.A (All Input Pins)

IILOI Output Leakage CS = VIH, VOUT = GND to 4.5V, 50 50 50 p.A Current VCC=Max

VIL Input Low Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 V

VIH Input High Voltage 2.0 6.0 2.0 6.0 2.0 6.0 V

VOL Output Low Voltage IOL=8.0mA 0.4 0.4 . 0.4 V

VOH 'Output High Voltage IOH= -4.0 rnA 2.4 2.4 2.4 V

ICC Power Supply VIN = 5.5V, TA = O°C, 125 180 160 rnA Current Output Open

ISB Standby Current VCC= Min to Max, CS=VIH 20 30 20 rnA

IPO Peak Power·On VCC = VSS to VCC Min, 30 40 30 rnA Current CS = Lower of VCC or VIH Min

Capacitance TA = 25°C, f = 1 MHz (Note 3)

Symbol Parameter Conditions Min Max Units

CIN Address/Control Capacitance VIN=OV 5 pF

COUT Output Capacitance VOUT=OV 6 pF

Note 1: The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.

Note 2: These circuits require 500 P.s time delay after vee reaches the specified minimum limit to ensure proper orientation after power·on. This allows the internally generated substrate bias to reach its functional level. '

Note 3: This parameter is guaranteed by periodic testing.

DOUT sv

AC Test Conditions ) )

~ GNDto3.0V Input Test Levels ,:SUIn

Input Rise and Fall Times 5ns

Input Timing Reference Level 1.5V

Output Timing Reference Level (H·1) 1.5V ~ 30pF 300n '-~ (INCLUDING

Output Timing Reference Levels 0.8V and 2.0V T SCOPE AND

(H·2, H·3, H·3L) FIXTURE)

Output Load See Figure 1 ~ TUD15257·4

FIGURE 1. Output Load

·Symbols in parentheses are proposed industry standard.

,4·8

Read Cycle AC Electrical Characteristics TA = b'c t~ 70'C, VCC = 5V ~~,~ (Note 1)

.' .:.."r·~;.··

Symbol NMC2147H·1 NMC2147H·2 NMcti~7~.3

NMC2147H Parameter NMCi !ijH;3L Units

Alternate Standard Min Max Min Max Min"~ .. Max Min Max

tRC TAVAV Read Cycle Time 35 45 55..' ,. .4;~ 70 ns ,

tAA TAVQV Address Access Time 35 45 .55 70 ns .'

tACS TSLQV Chip Select Access Time 35 45 55 70 ns (Note 4)

tLZ TSLQX Chip Select to Output Active 5 5 10 10 ns (Note 5)

tHZ TSHQZ Chip Deselect to Output 0 30 0 30 0 30 0 30 ns TRI·STATE (Note 5)

tOH TAXQX Output Hold from Address 5 5 5 5 ns Change

tpu TSLIH Chip Select to Power-Up 0 0 0 0 ns

tpo TSHIL Chip Deselect to Power-Down 20 20 20 30 ns


~. :

Read Cycle 1 (Continuous Selection CS = VIL, WE = VIH)

tRC (TAVAV)

ADDRESS ~'(. * --tAA 1

(TAVQV)

DATA OUT PREVIOUS DATA VALID -f::':': .:.: ··:.·.Jt DATA VALID

tDH _I i--(TAXQX)-

TLID/~257·5

Read Cycle 2 (Chip Select Switched, WE = VI H) (Note 4)

tRC (TAVAV)

CHIPSElECT ~ j[-. -.1{

tACS J - f--(~~~QZ) (TSlQV) I '--:- (TStt~X) .1

DATA OUT Ir//,

DATA VALID ~["

HIGH IMPEDANCE r0://///.?",dk. "1F- HIGH IMPEDANCE

I t" tpD - ",'Ol11 vcc ICC _______ _< (TSLlH)

50% SUPPLY 50% CURRENT ISS

TLlD/5257-6

".

Note 4: Address must be valid coincident with or prior to the chip select transition from highto low. Note 5:. Measured ± 50 mV from steady state voltage. This parameter is sampled and not 100% tested.

* The symbols in parentheses are proposed Industry standard.

4·9

Write Cycle AC Electrical Characteristics TA = DoC to 70De, vee = 5V ± 10% (Note 1)

Symbol NMC2147H-1 NMC2147H-2 NMC2147H-3

NMC2147H Parameter NMC2147H-3L Units

Altemate Standard Min Max Min Max Min Max Min Max

twe TAVAV Write Cycle Time 35 45 55 70 ns

tew TSLWH Chip Select to End of Write 35 45 45 55 ns

tAW TAVWH Address Valid to End of Write 35 45 45 55 ns

tAS TAVSL Address Set-Up Time 0 0 0 0 ns TAVWL

twp TWLWH Write Pulse Width 20 25 25 40 ns

tWR TWHAX Write Recovery Time 0 0 10 15 ns

tDW TDVWH Data Set-Up Time 20 25 25 30 ns

tDH TWHDX Data Hold Time 10 10 10 10 ns

twz TWLOZ Write Enable to Output 0 20 0 25 0 25 o· 35 ns TRI-STATE (Note 5)

tow TWHOX Output Active from End 0 0 0 0 ns of Write (Note 5)

Write Cycle Waveforms· (Note 6) Write Cycle 1 (Write Enable Limited)

'We (TAVAVI

ADDRESS j - J

lew

~ (TSLWHI

eHJrnIm~ (h ~ lAW -~I!.

lAS ".AVWH' 'WP

" .. n,,,., ITAVWLI ITWlWH,

WIIlTfmm .~ } ..

lOW IDH (TDVWHI (TWHDXI

DATA IN ) (

~ 'WZ cl .-=iIOW (TWlQZI (TWHGXI

DATA OUT " H'GH IMPEDANCE /I

I I

Write Cycle 2 (Chip Select L,lmlted) TUO/525H

'We {TAVAV, -ADDRESS ~ !-

,.

lew

(T~ ~-(TSlWH)

fHIrnIm l-lAW

(TAVWHI

1-(TW~1I ITW~:II'-WJUTrlflQ[! ~ J_

r f----,- (T~~HI I _IDH IIWHUII/

DATA IN ){ X 1- 'WZ

(TWlQZ)

nATA ,,"ncc,"cn HIGH IMPEDANCE DATA OUT .. TL/0/5257-8

Note 8: The output remains TRI-STATE If the CS and WE go high simultaneously. WE or CS or both must be high during the address transitions to prevent an erroneous write.

* The symbols In parentheses are proposed industry standard.

4·10

~National D Semiconductor NMC2148H 1024 x 4 Static RAM

Max Access/Current NMC2148H·2 NMC2148H·3

Access (TAVOV - ns) 45 55

Active Current (iCC - rnA) 180 180

Standby Current (iS9 - rnA) 30 30

NMC2148H

70

180

30

General Description Features

NMC2148H·3L NMC2148H·L

55 70

125 125

20 20

The NMC2148H is a 1024·word by 4·bit static random access memory fabricated using N-channel silicon·gate technology. All internal circuits are fully static and therefore require no clocks or refreshingfor operation. The data is read out nondestructively and has the same polarity as the input data.

• All inputs and outputs directly TTL compatible ~ Static operation-no clocks or refreshing required

The separate chip select input automatically switches the part to its low power standby mode when it goes high. Common input/output pins are provided.

Block Diagram·

A60-:-----I

• Automatic power-down • High speed-down to 45 ns access time • TRI-STATE'" output for bus interface

• Common data 110 pins • Single + 5V supply • Standard 18-pin dual-in-line package

A5O----~ ~VCC Logic Symbol·

A4o-----4

15 A9O-----4

16 A8~----4

17 Alo-----4

1/04 11 (004)

1/03 12 (003) o-~H-+--I

(O'~~~ o-'3-+H-+--I

(O'~~ o-'4.-t-H-+--I

ROW SElECT 1 OF 64

INPUT DATA

CONTROL

MEMORY ARRAY 64 ROWS

64 COLUMNS

..-.!oVSS

m(w)O----r--4--~~~--------------------------~

Pin Names~

AO·A9

WE(W) CS(S)

Address Inputs

Write Enable

Chip Select

1/01-1/04 (001-0Q4) Data Input/Output

VCC Power (5V)

VSS Ground

TUO/7404-1

Order Number NMC2148HJ-L, NMC2148HJ-3L, NMC2148HJ,

NMC2148HJ-2 or NMC2148HJ-3 NS Package Number J18A

Order Number NMC2148HN-L, NMC2148HN-3L, NMC2148HN,

NMC2148HN-2 or NMC2148HN-3 NS Package Number N18A

* Symbols in parentheses are proposed industry standard.

4-11

AD

1101 (DOl)

TUD17404-2

Connection Diagram·

Dual-ln-L1ne Package

TOP VIEW TUD17404-3

Absolute Maximum Ratings Truth Table Voltage at Any Pin with Respect to VSS -3.5Vto + 7V CS WE 110 Mode Power Storage Temperature - 65°C to + 150°C H x Hi·Z Standby Standby Temperature with Bias -10°C to + 85°C L L H Write 1 Active

DC Output Current 20mA L L L Write 0 Active

Power Dissipation 1.2W L H DOUT Read Active


DC Electrical Characteristics TA = O°C to + 70°C, VCC = 5V ± 10% (Notes 1 and 2)

NMC2148H·L NMC2148H

Symbol Parameter Conditions NMC2148H·3L NMC2148H·2

Units NMC2148H·3

Min Max Min Max

IILlI Input Load Current VIN = OV to 5.5V, 10 10 /LA (All Input Pins) VCC=Max

IILOI Output Leakage Current CS = VIH, VOUT = GND to 4.5V, 50 50 /LA VCC=Max

VIL Input Low Voltage -2.5 0.8 -2.5 0.8 V

VIH Input High Voltage 2.1 6.0 . 2.1 6.0 V

VOL Output Low Voltage IOL=8.0 mA 0.4 0.4 V

VOH Output High Voltage 10H= -4.0mA 2.4 2.4 V

ICC Power Supply Current VIN = 5.5V, TA = O°C, 125 180 mA Output Open

ISB Standby Current VCC = Min to Max, CS = VIH ?O 30 mA

IPO Peak Power·On Current VCC = VSS to VCC Min, 30 40 mA CS = Lower of VCC or VIH Min

IIOSI Output Short Circuit Current VOUT = GND to VCC 250 250 mA

Capacitance TA = 25°C, f = 1.0 MHz (Note 3)

Symbol Pa~ameter Conditions Min Max Units

CIN Address/Control Capacitance VIN=OV 5 pF

CliO Input/Output Capacitance VIIO=OV 7 pF

Note 1: The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.

Note 2: These circuits require 500,.,s time delay after vee reaches the specified minimum limit to ensure proper operation after power·on. This allows the in· ternally generated substrate bias to reach its functional level.

Note 3: This parameter is guaranteed by periodic testing.

DOUT 5V ) )

AC Test Conditions ..

~ 480n

Input Test Levels GNDto3.0V .

Input Riseand Fall Times 5ns 4~

. 30 pF Input Timing Reference Level 1.5V 2550: q IINCLUOING SCOPE

Output Timing Reference Levels 0.8V and 2.0V • AND FIXTURE)

Output Load See Figure 1 ":" TUD/7404-4

FIGURE 1. Output Load

4·12

Read Cycle AC Electrical Characteristics TA = O°C to + 70°C, VCC = 5V ± 10% (Note 1)

Symbol NMC2148H-2 NMC2148H-3 NMC2148H

Parameter NMC2148H-3L NMC2148H-L Units

Alternate Standard Min Max Min Max Min Max

tRc TAVAV Read Cycle Time 45 55 70 ns

tAA TAVQV Address Access Time 45 55 70 ns

tACS1 TSLQV1 Chip Select Access Time (Notes 4 and 5) 45 55 70 ns

tACS2 TSLQV2 Chip Select Access Time (Notes 4 and 6) 55 65 80 ns

tLZ TSLQX Chip Select to Output Active (Note 7) 20 20 20 ns

I tHZ TSHQZ Chip Deselect to Output TRI-STATE (Note 7) 0 20 0 20 0 20 ns

tOH TAXQX Output Hold from Address Change 5 5 5 ns

tpu TSLIH Chip Select to Power-Up 0 0 0 ns

tpD TSHIL Chip Deselect to Power-Down 30 30 30 ns


Read Cycle 1 (Continuous Selection CS = VIL, WE = VIH)

IRC (TAVAV)

ADDRESS ~? * tAA I (TAVQV) ~ I

DATA OUT PREVIOUS DATA VALID !k:\/>\:\:::\::::::)t DATA VAllO

" 10H _I -(TAXQX)---

TUOn404-5

Read Cycle 2 (Chip Select Switched, WE = VIH) (Note 4)

tRC (TAVAV)

CHIP SELECT ~r- -,~ tACS I - --(~~az) (TSLQV) I ILZ

DATA OUT (TSLQX) .Y;X DATA VALID

... HIGH IMPEDANCE l~xYY'Y'VV'I-lr- ..., HIGH IMPEDANCE

I ~., 'PO ~ vec

SUPPLY

ICC ________ (TSLlH) - (TSHIL) ---

50% CURRENT ISS

50%

TUOn404-6

Note 4: Addresses must be valid coincident with or prior to the chip select transition from high to low. Note 5: Chip deselected lon"ger than 55 ns. Note 6: Chip deselected less than 55 ns. Note 7: Measured :to 50 mV from steady state voltage. This parameter Is sampled and not 100% tested.

*The symbols in parentheses are proposed industry standard.

4·13

:J: ~ Write Cycle AC Electrical Characteristics TA = O°C to + 70°C, VCC = 5V ± 10% (Note 1)

..... C'I o :IE z

Symbol NMC2148H·2 NMC2148H·3 NMC2148H

. Parameter NMC2148H·3L NMC2148H·L Alternate Standard Min ·Max Min Max Min Max

twe TAVAV Write Cycle Time 45 55 70

tew TSLWH Chip Select to End of Write 40 50 65

tAW TAVWH Address Valid to End of Write 40 50 65

tAS TAVSL Address Set·Up Time 0 0 0 TAVWL

twp TWLWH Write Pulse Width 35 40 50

tWR TWHAX Write Aecovery Time 5 ·5 5

tow TDVWH· Data Set·Up Time. 20 20 25

tOH TWHDX Data Hold Time 0 0 0

twz TWLQZ Write Enable to Output TAI·STATE (Note 7) 0 15 0 20 0 25

tow TWHQX Output Active from End of Write (Note 7) 0 0 0

Write Cycle Waveforms * (Note 8)

Write Cycle 1 (Write Enable Limited)

DATA IN

DATADUT

TUDI7404-7 Write Cycle 2 (Chip Select Limited)

DATA IN

DATADUT DATA UNDEFINED

------------------------------~ TUDI7404-8

Not.8: The output remains TRI-5TATE If the CS and WE go high simultaneously. WE orCS or both must be high during the address transitions to prevent an erroneous write.

*Symbols In parentheses are proposed industry standard.

4·14

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Section 5

CMOS Static RAMs

CMOS Static RAMs

Section 5-CMOS Static RAMs

NMC6164/6164L 8192x 8-Bit Static RAM ................................................................. 5-3

5-2

~National· ~ Semiconductor

PRELIMINARY .......J.~--.....IJ:=~"-'" ......

microCMOS

NMC6164/6164L 8192 x 8·Bit Static RAM General Description The NMC6164/6164L is a 8192-word by 8-bit, new-generation static RAM. It is fabricated with National's proprietary microCMOS double·polysilicon technology which combines high performance and high density with low power consumption and excellent reliability.

The NMC6164/6164L operates with a single 5V power supply with ± 10% tolerance. Additional battery back-up operation is available (L version) for data retention down to 2V, with low standby current.

Packaging is in standard 28-pin DIP and is available in both plastic and CERDIP.

In addition to the inputs and outputs being TTL compatible, the outputs are also CMOS compatible, in that capacitive loads are driven to Vcc or Vss.

Block and Connection Diagrams

Features • Single power supply: 5V ± 10%

• Fast access time 100 ns/120 ns/150 ns max

• Equal access and cycle times • Completely static RAM: no clock or timing strobe

required .

• Low standby power and low power operation Standby: 10/!W, typical Operation: 15 mW/MHz, typical

• Battery back-up operation available (L version) with data retention supply voltage: 2V-5.5V

• Common data input and output, TRI-STATE~ output

• TTL compatible: all inputs and outputs

• CMOS compatible: outputs drive capacitive loads to Vcc or Vss

• Standard 28-pin package configuration

Dual·ln·Line Package

A12 --0 Vee NC 28 Vee

e.

A4

A3

AD

CHIP SELECT

ROW DECODE

CS2 CSl WE TIE READIWRITE

Truth Table Mode WE CS1

Not Selected . H

(Power Down) . . Output Disabled H L

Read H L

Write L L

CS2 . L

H

H

H

MEMORY ARRAY 128x512

--0 Vss

OE

· · H

L

·

COLUMN SELECT

I/O

Hi-Z

Hi-Z

Hi-Z

Dour

DIN

TLfO/5287·'

Current

ISB,lsBl

ISB,lsBl

Icc,lcCl

Icc,lcCl

Icc,lcCl • Don'l care (H or L) H = Logic HIGH Level L = Logic LOW Level

5-3

A12 27 WE

A7 26 CS2

A6 25 A8

A5 24 A9

A4 23 All

A3 22 DE

A2 21 Al0

A1 ffi

AD II0a

1/01 1/07

1/02 1/0&

1/03 1/05

Vss 15 1/04

TOP VIEW TLf0/5287-2

Order Number NMC6164J (NMC6164LJ) NS Package Number J28A

Order Number NMC6164N (NMC6164LN) NS Package Number N28B

Absolute Maximum Ratings Recommended DC Operating Conditions

Min Max Units

Voltage on Any Pin Relative to Vss -0.5Vto-7V Vcc Supply Voltage 4.5 5.5 V Storage Temperature, T STG - 55~C to + 125°C Vss Supply Voltage 0 0 V Temperature Under Bias, T BIAS -10°C to + 85°C VIH, Input High Voltage· Power Dissipation, Po 1~OW (Logic 1) Current Through Any Pin 100 rnA TIL 2.2 . 6.0 V

CMOS· Vcc- 0.2 Vcc+ 0.2 V

VII:., Input Low Voltage (Logic 0)

TIL -0.3 0.8 'V CMOS -0.2 0.2 :V

T OPR, Operating Temp 0 70 °C (

DC Electrical Characteristics at. recommended ~perating conditions


III Input Leakage Current VIN = Vss to Vcc "':'2 2 p.A

ILo Output Leakage Current CS1.= VIH or CS2= VIL or OE= VIH -2 2 p.A VIIO = Vss to Vcc

All Inputs at TTL Levels Icc Active Quiescent Current, TTL CS1 = VIL, TTL or CS2= YIH, TTL 25 ,rnA

1110 =0 rnA

Std. All Inputs at CMOS Levels 2 rnA Icc I--- Active Quiescent Current, CMOS CS1 = VIL, CMOS and CS2 = VIH, CMOS

L 1110=0 rnA 100 p.A

Average Operating Current, TTL Duty Cycle = 100% 60 rnA All Inputs at TTL Levels .

ICCl Duty Cycle = 100% Average Operating Current, CMOS All Inputs at CMOS Levels

40 rnA

Std. CS1 = VIH, TTL or CS2 = VIL, ~TL 4 rnA ISB I--- Standby Power Supply Current

L 1110 =0 rnA 2 rnA

Std. Standby Power Supply c'urrent CS1 = VIH, CMOS or CS2= VIL' CMOS

2 rnA ISBl I---

L 100 p.A

Output Low Voltage, TTL IOL=2.1 rnA 0.4 V VOL

Output Low Voltage, CMOS 10L= ± 10 p.A -0.2 0.2 V

Output High Voltage, TTL 10H= -1.0 rnA 2.4 V VOH

Output High Voltage, CMOS 10H= ±10p.A. Vc·c"':' 0.2 Vcc+ 0.2 V

Capacitance Symbol Parameter Conditions Max Units

CIN Input Capacitance VIN = OV (Note 5) 6 pF

CliO . Input/Output Capacitance VI/O = OV (Note 5) 8 pF

5·4

AC Electrical Characteristics (Note 1) (Standard and L Versions)

NMC6164/6164L

Symbol Parameter -10* -12* -15* Units

Min Max Min Max Min Max

READ CYCLE (Note 4)

tAC Read Cycle Time 100 120 150 ns

tAA Address Access Time 100 120 150 ns

tCOl Chip Selection (CS1) to Output Valid 100 120 150 ns

tC02 Chip Selection (CS2) to Output Valid 100 120 150 ns

tOE Output Enable (OE) to Output Valid 50 60 70 ns

tLll Chip Selection (CS1) to Output Active 10 10 15 ns

tLl2 Chip Selection (CS2) to Output Active 10 10 15 ns

tOll Output Enable (OE) to Output Active 5 5 5 ns

tHZl Chip Deselection (CS1) to Output in Hi-Z (Notes 2 and 3) 0 35 0 40 0 50 ns

tHZ2 Chip Deselection (CS2) to Output in Hi-Z (Notes 2 and 3) 0 35 0 40 0 50 ns

tOHZ Output Disable (OE) to Output in HI-Z (Notes 2 and 3) 0 35 0 40 0 50 ns

tOHA Output Hold from Address Change 10 10 15 ns

WRITE CYCLE

twc Write Cycle Time 100 120 150 ns

tCWl Chip Selection (CS1) to End of Write (Note 10) 80 85 100 ns

tCW2 Chip Selection (CS2) to End of Write 80 85 100 ns

tAS Address Set-Up Time (Note 7) 0 0 0 ns

tAW Address Valid to End of Write 80 85 100 ns

twp Write Pulse Width (Note 6) 60 70 90 ns

tWAl Write Recovery Time from CS1 (Note 8) 0 5 10 ns

tWA2 Write Recovery Time from CS2 (Note 8) 0 5 10 ns

tWHZ Beginning of Write to Output in Hi-Z (Note 9) 0 35 0 40 0 50 ns

tow Data Valid to Write Time Overlap 35 40 50 ns

tOH Data Hold from End of Write 0 0 0 ns

tOHZ Output Disable (OE) to Output in Hi-Z 0 35 0 40 0 50 ns

tow Output Active from End of Write 5 5 10 \

ns "Applies to Standard and L Versions. Note 1: AC test conditions TA = O·C to + 70·C, Vee = 5V ± 10%. Note 2: tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are determined as:

High to TAI·STATE measured as VOH (OC)- 0.1V Low to TAI·STATE measured as VOL (DC) + 0.1V

Note 3: At any given temperature and voltage condition, tHZ MAX is less than tLZ MIN' both for a given device and from device to device. Note 4: WE is high for read cycle. Note 5: TA = 25·C, f = 1.0 MHz. This parameter is sampled and not 100% tested. Note 6: A write occurs during the overlap (twp) of a low CS1 and a high CS2 and a low WE. Note 7: tAS is measured from the address changes to the beginning of the write. Note 8: tWA is measured from the earliest of CS1 or WE going high or CS2 going low to the end of the write cycle. Note 9: If CSl is low and CS2 is high during this period, 1/0 pins are in the output state. At this time, the data input signals of opposite phase to the outputs must not be applied. Note 10: If the CS1 low transition occurs simultaneously with the WE low transition or after the We transition, the outputs will remain in a Hi-Z state. Note ~ ~2 controls the address buffers, WE buffer, CSl buffer, DIN buffer and Of buffer. When CS2 controls the data retention mode, VIN level (address, ~,CS1, OE) can be in the high impedance state. When CSl controls the data retention mode, CS2 must be at VIH , CMOS. All other input levels (address, WE, I/O) can be in the high impedance state.

AC Test Conditions: ACTest Load

5V ±10% 1.6V Input pulse levels VIH =3.0V, VIL=O.OV I ~ Input rise and fall times 5 ns

vee ~: 390n All input and output timing reference levels 1.5V

NMC6164! liOn 6164L (INCLUDING

VSS - .... 100pF JIG' PROBE

* T CAPACITANCE) TUD/5287·3

5-5

...J

~ ,.. CD o :E z ...... ~ ,.. CD o :E z

Timing Waveforms Write Cycle 1 (OE Clocked)

ADDRESS

~--------------------~~~~~~

DOUT

DIN-------------------~

TUDf5287-4

Write Cycle 2 (OE Low Fixed)

M----~--------_w~~~

DOUT

--+I-oO---IOH~

DIN ---------------------~ TUDf5287·5

5-6

Timing Waveforms (Continued)

Read Cycle

ADDRESS

CS2

DaUI -----------------f><

Low Vee Data Retention (L Version)


VDR1 Vcc for Data Retention CS1 > V1H• CMOS 2.0 V CS2 > V1H• CMOS

VDR2 Vcc for Data Retention CS2<V1L• CMOS 2.0 V

ICCDR1 Data Retention Current (Note 11) Vcc=2V 40 p.A CS1 > V1H• CMOS CS2>V1H• CMOS

ICCDR2 Data Retention Current (Note 11) Vcc=2V 40 p.A CS2 < V1L• CMOS

tCDR Chip Deselect to Data Retention Time See Retention Waveform 0 ns

tR Operation Recovery Time See Retention Waveform tRC ns

Low Vee Data Retention Waveforms

No.1 (CS1 Controlled)

vee~DR -.-_-_-_-_-_-_-_-_-_-_-_-_DA_TA_R_ET_E_NT_ID_N_M_OD_E~~~~~~~~~~~-~-'= _____ _

~~ ---------------------~ CS1 ffi =VIH. CMOS OV----------------------------------------

TUD/5287·7

No.2 (CS2 Controlled)

- leDR II.'-------DATA RETENTION MODE-------!-I IR __

V~ J 1 4.5V -------I~'" J.oI"'"

CS2" ./ 2.2V " V O.2V " CS2=VIL, CMOS ./ DV----------~~==============================~-----------

TUD/5287-8

5·7

z 35: (') 0) ..... 0) ~ --z 35: (') 0) ..... 0) ~ r-

Section 6

EPROMs

EPROMs

;.;~.;~t.\ 'j

Section Contents

MM2716 16,384·Blt (2048 x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·3

MM2758 8,192·Blt (1024 x 8) UV Erasable PROM .......................................................... 6-10

NMC27C16 16,384·Bit (2048 x 8) UV Erasable CMOS PROM ..... '" ......................................... 6·16

NMC27C32' 32,768·Bit (4096 x 8) UV Erasable CMOS PROM ................... : ............................. 6·23

N MC27C256 262,144-Bit 8) UV Erasable CMOS PROM ................................................ 6-30 .

-".'" ,

6-2

~Nationai D Semiconductor MM2716 16,384-Bit (2048 x 8) UV Erasable PROM

Parameter/Order Number

Access Time (ns)

Vee Power Supply

General Description

MM2716 MM2716·1 MM2716E

450 350 450

5V ±50.10 5V ± 10% 5V ±5%

Features • Access time down to 350 ns

• Low power consumption Active power: 525 mW max

The MM2716 Is a high speed 16k UV erasable and electrically reprogrammable EPROM, ideally suited for applications where fast turnaround and pattern experimentation are important requirements. Standby power: 132 mW max (75% savings)

• Single 5V power supply The MM2716 is packaged in a 24-pln dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written Into the device by following the programming procedure.

• Extended temperature range available (MM2716E), - 40·C to + 85·C, 450 ns ± 5% power supply

• Pin compatible to National's higher density EPROMs

• Static-no clocks required This EPROM is fabricated with the reliable, high volume, time proven, N-channel MOS silicon gate technology.

• TTL compatible inputs/outputs

• TRI-STATE@ output

Block and Connection Diagrams Vee 0--+ GND 0--+ V", 0--+

Pin Names

AO-A14 Addresses CE Chip Enable

OE Output Enable

0 0-07 Outputs

PGM Program

NC No Connect

27C256 27C128 27C64 27C32 27256 27128 276( 2732

V", Vpp Vpp

A12 A12 A12

A7 A7 A7 A7

A6 A6 A6 A6

A5 AS AS A5

A4 A4 A4 A4

A3 A3 A3 A3

A2 A2 A2 A2

Al Al Al Al

AD AD AD AD

00 00 00 00

01 01 01 01

02 02 02 02

GNO GNO GHO GNO

A7

A6

AS

A4

A3

A2

Al

AO

00

01

02

GND

AD-AID ADDRESS

INPUTS

Dual-In-Line Package

MM2716 TDP VIEW

10

11

12

A8

A9

v",

W

AID

u: D7

Oe

05

O.

03

NS Package Number J24A-Q

OUTPUT ENABLE CHIP ENABLE

ANO PROG LOGIC

y DECDDER

X DECODER

27C32 27C64 27C128 2732 2764 27128

Vee Vee

PGM PllM

Vee HC A13

A8 A8 A8

A9 A9 A9

All A11 All

oE/v", liE liE

Al0 Al0 Al0

CE CE CE

07 07 07

Oe Oe Oe

05 05 05

O. O. O.

03 03 03

27C2S6 27256

Vee

A14

A13

A8

. A9

A11

liE

AID

CE

07

Oe

05

O.

03

OATA OUTPUTS 00-07

Note: National's socket compatible EPROM pin configurations are sh~wn In the blocks adjacent to the MM2716 pins.

6-3

Absolute Maximum Ratings (Note 1) Operating Conditions (Note 9)

Temperature Range Temperature Under Bias

Storage Temperature

All Input or Output Voltages with Respect to Ground

MM2716, MM2716-1

MM2716E

O°Cto + 70°C

-40°Cto +85°C

Vpp Supply Voltage with Respect to Ground During Program

Power Dissipation

+ 6.5V to - 0.3V

+ 26.5V to - 0.3V 1.5W


READ OPERATION

DC and Operating Characteristics

Vee Power Supply (Notes 2 and 3) MM2716, MM2716E

MM2716-1

V pp Power Supply (Note 3)

Symbol Parameter Conditions Min Typ (Note 4) Max

III Input Load Current VIN=VceorGND

ILO Output Leakage Current Vour= Vcc or GND, C'E=VIH

ICCl Vec Current (Standby) CE:=V1H

ICC2 (Note 3) Vcc Current (Active) 0'E=CE=V1b I/O=OmA

V1L Input Low Voltage

VIH. Input High Voltage

VOL Output Low Voltage IOL=2.1 mA

VOH Output High Voltage IOH= -400p.A

AC Characteristics

Symbol . Parameter

tACC Address to Output Delay

tCE CE to Output Delay

tOE Output Enable to Output Delay

tOF Output Enable High to Output Float

tOH (Note 5) Output..!:!old from Addresses, CE or OE, Whichever Occurred First

Capacitance (Note 5) (T A = + 25°C, f = 1 MHz)

Symbol Parameter Conditions Typ

C 1N Input Capacitance V1N=OV 4

C OUT Output Capacitance VOUT=OV 8

AC Test Conditions Output Load

Input Rise and Fall Times Input Pulse Levels

1 TTL Gate and C L = 100 pF s20ns

0.8Vt02.2V

Timing Measurement Reference Level Inputs Outputs

1Vand2V O.8V and 2V

Conditions

CE=0E=V1L

OE=VIL

CE=V1L

CE=V1L

CE=0E=V1L

Max Units

6 pF

12 pF

6-4

10

10

10 25

57 100

-0.1 0.8

2.0 Vcc +1

0.45

2.4

MM2716E MM2716·1 MM2716

Min Max Min Max

450 350

450 350

120 120

0 100 0 100

0 0

5V±5%

5V±10%

Vee

Units

p.A

p.A

mA

mA

V

V

V

V

Units

ns

ns

ns

ns

ns

_. AC Waveforms (Note 2)

ADDRESSES

HI-Z OUTPUT

ADDRESSES VALID

I----ICE---~

HI-Z

TLlD/5183·3

Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress rating only and functional operation of the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: VCC must be applied slmultane.ously or before Vpp and removed simultaneously or after Vpp.

Note 3: Vpp may be connected to VCC except during programming. ICC2",the sum of the ICC active and Ipp read currents. Note 4: Typical values are for TA = + 2SoC and nominal supply voltages.

Note 5: This parameter Is only sampled and Is not 100% tested.

Note 6: 5E may be delayed up to tACC - tOE after the failing edge of CE without impact on tACC'

Nole 7: The t OF compare level Is determined as follows: High to TRI-STATE. the measured VOH (OC)-0.10V_ Low to TRI·STATE. the measured VOL (DC) + 0.10V

Note 6: TRI-STATE may be attained using OE or CE. Note 9: The power switching characteristics of EPROMs require careful device decoupling. It Is recommended that a 0.1 p.F ceramic capacitor be used on every device between VCC and GNO.

6-5

PROGRAMMING CHARACTERISTICS (Note 1)

DC Programming Characteristics(Notes2and3)(TA= +25°C±5°C, Vee=5V±5%, Vpp=25V±1V)

Symbol Parameter Conditions Min Typ Max Units

III Input Current (for Any Input) VIN=Vee orGND (10 p.A

Ipp Vpp Supply Current During CE/PGM~VIH 30 mA Programming Pulse

lee Vee Supply Current 100 mA

V1L Input Low Level - -0.1 0.8 V

VIH Input High Level 2.0 Vee+ 1 V

AC Programming Characteristics (Notes 2 and 3) (T A = + 25°C ± 5°C, Vee = 5V ± 5%, Vpp = 25V ± 1V)


tAS Address Set·Up Time 2 P.s

tOES OE Set·Up Time 2 P.s

tos Data Set·Up Time 2 P.s

tAH Address Hold Time 2 P.s

tOEH OE Hold Time 2 p's

tOH Data Hold Time 2 p's

tOF Output Enable to Output Float Delay CE/PGM=VIL 0 160 ns

tOE Output Enable to Output Delay CE/PGM=V1L 160 ns

tpw· Program Pulse Width 45 50 55 ms

tpRT Program Pulse Rise Time 5 ns

tPFT Program Pulse Fall Time 5 ns

AC Test Conditions Vee 5V±5% Vpp 25V ± 1V Input Rise and Fall Times :s;20ns Input Pulse Levels 0.8Vt02.2V Timing Measurement Reference Level

Inputs 1Vand2V Outputs 0.8Vand2V

6·6

Programming Waveforms (Note 3) (Vpp = 25V ± 1V, Vee = 5V ± 5%)

PROGRAM PROGRAM ..... --- ----+1----- VERIFY -----.!

~-----ADDRESS

DATA

CE/PGM

tDF (0.16 MAX)

DATA IN STABLE ADD N+m

TLlDI5183,4

Note: All times shown In parentheses are minimum times and are in ~s unless otherwise specified.

Note 1: National's standard product warranty applies only to devices programmed So specifications described herein.

Note 2: Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The MM2716 must not be Inserted into or removed from a board with Vpp. at 25V ± 1 V to prevent damage to the device.

Note 3: The maximum allowable voltage which may be applied to the Vpp pin during programming is 26V. eare must be taken when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification. A 0.1 ~F capacitor is required across Vpp, Vee to GND to suppress spurious voltage tran· s'ients which may damage the device.

6·7

Functional Description DEVICE OPERATION

The five modes of operation of the MM2716 are listed in Table Lit should be noted that all inputs forthe five modes are at TTL levels. The power supplies required are a 5V Vee and a Vpp. The Vpp power supply must be at 25V during the three programming modes, and must be at 5V in the other two modes.

Read Mode'

The MM2716 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (0 E) is the output control and should be used to gate data to the output pins, independent'of device selection. Assuming that addresses are stable, address access time (tACe) is equal to the delay from CE to output (tCB' Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE.

Standby Mode

The MM2716 has a standby mode which reduces the active power dissipation by 75%, from 525 mW to 132 mW. The MM2716 Is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are In a high impedance state, independent of the OE Input.

Output OR-Tying

Because MM2716s are usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for:

a) the lowest possible memory power diSSipation, and

b) complete assurance that output bus contention will not occur.

To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus_ This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.

Programming

CAUTION: Exceeding 26.5V on pin 21 (V pp) will damage the MM2716.

Initially, and after each erasure, all bits of the MM2716 are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed, both "1 s" and "Os" can be presented in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure.

Tlie MM2716 is in the programming mode when the Vpp power supply is at 25V and OE is at VIH. It is required that a 0.1 /LF capacitor be placed across Vpp, Vee to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. .

When the address and data are stable, a 50 ms, active high, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. You can program any location at any time~either individually, sequentially, or at random. The program pulse has a maximumwidthof55ms.The MM2716 must not be programmed with a DC Signal applied to the CE/PGM input.

Programming of multiple MM2716s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled MM2716s may be connected together when they are programmed with the same data. A high level TTL pulse applied to the CE/PGM input programs the paralleled MM2716s.

Program Inhibit

Programming multiple MM2716s in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs (including OE) of the parallel MM2716s may be common.A TTL level program pu Ise applied to an MM2716's CE/PGM input with Vpp at 25V will program that MM2716. A low level CE/PGM input Inhibits the other MM2716 from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with Vpp at 25V. Except during programming and program verify, Vpp must be at Vcc.

TABLE I. Mode Selection

~ CE/PGM OE Vpp Vce Outputs

Mode (18) (20) (21) (24) (9-11,13-17)

Read VIL VIL Vcc 5 DOUT Standby VIH Don't Care Vee 5 Hi-Z Program Pulsed VIL to VIH VIH 25 5 DIN Program Verify VIL VIL 25 5 DOUT Program Inhibit VIL VIH 25 5 Hi-Z

6-8


ERASURE CHARACTERISTICS

The erasure characteristics of the MM2716 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A).lt should be noted that sunlight and certain types of fluorescent lamps have wavelengths In the 3000A-4000A range. Data shows that constant exposure to room-level fluorescent lighting could erase the typical MM2716 in approximately 3 years, while It would take approximately 1 week to cause erasure when exposed to direct sunlight. If the MM2716 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the MM2716 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

The recommended erasure procedure .for'the MM2716 is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (I.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2• The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a 12,000 /!W/cm2 power rating. The MM2716 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.

6-9

An erasure system should be calibrated periodically; The distance from lamp to unit should be maintained at one Inch. The erasure time Increas'es as the square oLthe distance. (If distance Is doubled the erasure time Increases by a factor of 4.) Lamps lose Intensity as they age. When a lamp Is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure Is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when Incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful decoupllng of the devices. The supply current, Icc, has three segments that are of Interest to the system designer-the standby current level, the active current level, and the'translent current peaks th'at are produced on the falling and rising edges of chip enable. The magnitude of these transient current peaks Is dependent on the output capacitance loading of the device. The associated transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1 p.F ceramic capacitor be used on every device between Vcc and GND. This should be a high frequency capacitor of low Inherent inductance. In addition, a 4.7 /!F bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The bulk capacitor should be located near where the power supply Is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effects of the PC board traces.

co ~ ~ National . ~ ~ Semiconductor ::E MM2758 8,192-Bit (1024 x 8) UV Erasable PROM

G~~eral Description The MM2758isa high speed 8k UV erasable and electrically reprogrammable EPROM, ideally suited for applications where fast turnaround and pattern 'experimentation are important requirements.

Features • Access time-450 ns • Low power consumption

Active power: 525 mW max Standby power: 132 mW max (75% savings)

• Single 5V power supply The MM2758 is packaged in a 24-piri dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device by following the programming procedure;

• Pin compatible to National's higher density EPROMs • Static-no clocks required 0

• TIL compatible inputs/outputs

This EPROM is fabricated With the reliable, high volume, time proven, N-channel MOS silicon gate technology.

• TRI-STATE(!) output

Block and Connection Diagrams Vee 0--+ GND <>--+ Vpp 0--+

Pin Names

AO-A14 Addresses CE Chip Enable OE Output Enable

0 0-07 Outputs

PGM Program NC No Connect

*AR Select Reference Input Level

27C256 27C128 27C64 27C32 27C16 27256 27128 2764 2732 2716

Vpp Vpp Vpp

A12 A12 A12

A7 A7 A7 A7 A7

A6 A6 A6 A6 A6

A5 A5 A5 A5 A5

A4 A4 A4 A4 A4

A3 A3 A3 A3 A3

A2 A2 A2 A2 A2

A1 A1 A1 A1 A1

AD AD AD AD AD

00 00 00 00 00

01 01 01 01 01

02 02 02 02 02

GND GND GND GND GND

A7

A6

AS

A4

A3

A2

A1

AD

00

01

02

GND

Ao-Ag ADDRESS

INPUTS

Dual·ln·Llne Package

21

MM2758 TOP VIEW

12 13

Vee

A8

A9

Vpp

DE

An·

CE

07

06

05

D.

03


AND PROG LOGIC

y DECODER

x DECODER

27C16 2716

Vee

A8

A9

Vpp

27C32 2732

Vee

A8

A9

A11

DE DE/Vpp

A10 A10

CE CE

07 07

06 06

05 05

04 04

03 03

27C64 2764

Vee

PGM

NC

A8

A9

A11

DE

A1D

CE

07

06

05

04

03

DATA OUTPUTS , . 00-07

OUTPUT BUFFERS

Y GATING

8192-BIT CELL MATRIX

27C12B 27C256 27128 27256

Vee Vee

PGM A14

A13 A13

A8 A8

A9 A9

A11 A11

De OE

A10 A10

CE CE

07 07

06 06

05 05

D. D.

03 03

Note: National's socket compatible EPROM pin configurations are shown In the blocks adjacent to the MM2758 pins.

* For MM2758A, AR = VIL for all operating modes. Order Number MM2758Q·A or MM2758Q·B

NS Package Number J24A·Q • For MM2758B, AR = VIH for all operating modes.

6-10 .

Tl1D/5475·1

TlIOf5475·2


Temperature Under Bias

Storage Temperature

All Input or Output Voltages with Respect to Ground

Vpp Supply Voltage with Respect to Ground During Program

Power Dissipation

-10°Cto +80°C

- 65°C to + 125°C

. + 6.5V to - 0.3V

+ 26.5V to - 0.3V 1.5W


READ OPERATION


Temperature Range

Vee Power Supply (Notes 2 and 3) Vpp Power Supply (Note 3)

Symbol Parameter Conditions Min Typ (Note 4)

III Input Load Current V'N = Vee or GND

ILO Output Leakage Current VOUT= Vee or GND, CE = V'H

leel Vcc Current (Standby) C'1:=V'H

I eC2 (Note 3) Vee Current (Active) OE=CE=V'L, 1/0=0 rnA

V'L Input Low Voltage

V'H Input High Voltage

VOL Output Low Voltage IOL=2.1 rnA

VOH Output High Voltage IOH= -400JlA

AC Characteristics

Symbol Parameter

tAec Address to Output Delay

tCE CE to Output Delay

tOE Output Enable to Output Delay

tOF Output Enable High to Output Float

tOH (Note 5) Output Hold from Addresses, CE or OE, Whichever Occurred First

Capacitance (Note 5) (TA = + 25°C, f = 1 MHz)


C'N Input Capacitance V'N=OV 4

COUT Output Capacitance VOUT=OV 8

AC Test Conditions Output Load Input Rise and Fall Times

Input Pulse Levels

1 TILGateandC L = 100pF s20ns

0.8Vt02.2V

Timing Measurement Reference Level Inputs 1Vand2V

0.8Vand2V Outputs

Max

6

12

6·11

Conditions

CE=OE=V'L

OE=V'L

CE=V'L

CE=V'L

CE=OE=V'L

Units

pF

pF

10

57

-0.1

2.0

2.4

Min Max

. 450

450

120

0 100

0

Max

10

10

25

100

0.8

Vcc+ 1

0:45

0°C-70°C

5V±5%

Vee

Units

JlA

JlA

rnA

rnA

V V

V

V

Units

. ns

ns

ns

ns

ns

AC Waveforms (Note 2)

ADDRESSES

OUTPUT

ADDRESSES VALID

Hi-Z

TL/D/5415-3

Note1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and func· tional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.

Note 3: Vpp may be connected to VCC except during programming.ICC2,sthe sum of the ICC active and Ipp read currents.

Note 4: Typical values are for TA = + 2SoC and nominal supply Voltages.

Note 5: This parameter Is only sampled and is not 100% tested.

- Note 8: OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC.

Note 7: The tDF compare level is determined as follows: High to TRI·STATE, the measured VOH (DC)-0.10V Low to TRI-STATE, the measured VOL (DC) + 0.10V

Note 8: TRI-STATE may be attained using OE or CE. Note 9: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that a 0.11'F ceramic capacitor be used on every device between Vec and GND.

Programming Waveforms (Note 3) (Vpp = 25V ± lV, VCC = 5V ± 5%)

ADDRESS

DATA

CE/PGM

tDF (0.16 MAX)

DATA IN STABLE ADDN+m

TL/D/541S ..

Note: All times shown In parentheses are minimum times and are In I'S unless otherwise specified.

Note1: National's standard product warranty applies only to devices programmed to specifications described herein.

Note 2: VCC must be applied simultaneously or before Vpp and removed simultaneously or afterVpp. The MM2758 must not be inserted Intopr removed from a board with Vpp at 25V ± 1V to prevent damage to the device. '

Note 3: The maximum allowable voltage which may be applied to the Vpp pin during programming is 26V. Care must be taken when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification. A 0.11'F capacitor is required across Vpp, VCC to GND to suppress spurious voltage transients which may damage the device.

6-12


DC Programming Characteristics (Notes 2 and 3) (TA = + 2SoC ± SoC, Vee = SV ± S%, Vpp = 2SV ± 1V)


III Input Current (for Any Input) VIN = Vee or GND 10 Jl.A

Ipp Vpp Supply Current During CE/PGM=VIH 30 mA Programming Pulse

Icc Vee Supply Current 100 mA

V1L Input Low Level -0.1 0.8 V

V1H Input High Level 2.0 Vcc+ 1 V

AC Programming Characteristics (Notes 2 and 3) (TA = + 2Soc ± SoC, Vee = SV ± 5%, Vpp = 25V ± 1V)


tAS Address Set-Up Time 2 Jl.s

tOES OE Set-Up Time 2 Jl.S

tos Data Set-Up Time 2 Jl.S

tAH Address Hold Time 2 Jl.S

tOEH OE Hold Time 2 Jl.S

tOH Data Hold Time 2 Jl.S

tOF Output Enable to Output Float Delay CE/PGM=VIL 0 160 ns

tOE Output Enable to Output Delay CE/PGM=V1L 160 ns

tpw Program Pulse Width 45 50 SS ms

tpRT Program Pulse Rise Time 5 ns

tPFT Program Pulse Fall Time S ns

AC Test Conditions Vce SV±S%

Vpp 2SV± 1V Input Rise and Fall Times :5 20 ns

Input Pulse Levels 0.8Vto2.2V

Timing Measurement Reference Level Inputs 1Vand2V Outputs 0.8Vand2V

6-13

Functional Description !

DEVICE OPERATION

The five modes of otJeratlon of the MM2758 are listed in Table Lit should be noted that all inputs forthe five modes are at TTL levels. The power supplies required area5VVee and a Vpp. The Vpp power supply must be at 25V during the three programming modes, and must be at 5V in the other two modes.

Read Mode

The MM2758 has two control functions, both of which must be logically active in order to obtain data at the out· puts. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACe) is equal to the delay from CE to output (te8' Data is available at the outputs tOE after the falling edge of OE, assuming that ~ has been low and addresses have been stable for at least tAee-toE'

Standby Mode

The MM2758 has a standby mode which reduces the ac· tive power dissipation by 75%, from 525 mW to 132 mW. The MM2758 Is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output OR·Tylng

Because MM2758s are usually used in larger memory ar· rays, National has provided a 2·line control function that accommodates this use of multiple memory connections. The 2·line control function allows for:

a) the lowest possible memory power dissipation, and


To most efficiently use these two control lines, it is recom· mended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data Is desired from a particular memory device.

Programming

CAUTION: Exceeding 26.5Von pin 21 (Vpp) will damage the MM2758.

Initially, and after each erasure, all bits of the MM2758 are in the "1" state. Data is introduced by selectively program· ming "Os" into the desired bit locations. Although only "Os" will be programmed, both "1s" and "Os" can be presented In the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure.

The MM2758 is in the programming mode when the Vpp power supply is at 25V and OE is at VIH.lt is required that a 0.1 #LF capacitor be placed across Vpp, Vee to ground to suppress spurious voltage transients which may damage the device. The data to be programmed Is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

When the address and data are stable, a 50 ms, active high, TTL program pulse is applied to the CE/PGM input. A pro· gram pulse must be applied at each address location to be programmed. You can program any location at any timeeither individually, sequentially, or at random. The program pulse has a maximum width of 55 ms. The MM2758 must not be programmed with a DC signal applied to the CE/PGM input.

Programming of multiple MM2758s in parallel with the same data can be easily accomplished due to the simplic· ity of the programming requirements. Like inputs of the paralleled MM2758s may be connected together when they are programmed with the same data. A high level TTL pulse applied to the CE/PGM input programs the paral· leled MM2758s.

Program Inhibit

Programming multiple MM2758s in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs (including OE) of the parallel MM2758s may be . common. A TTL level program pulse applied to an MM2758's CE/PGM input with Vpp at 25V will program that MM2758. A low level CE/PGM input inhibits the other MM2758 from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with Vpp at 25V. Except during programming and program verify, Vpp must be at Vee ..


~ CE/PGM . OE Vpp Vee Outputs Mode (18) (20) (21) (24) (9-11,13-17)

Read VIL VIL Vec 5 DOUT Standby VIH Don't Care Vce 5 Hi·Z Program Pulsed VIL to VIH VIH 25 5 DIN Program Verify VIL VIL 25 5 DOUT Program Inhibit VIL VIH 25 5 Hi·Z

6·14



The erasure characteristics of the MM2758 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A ).It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A -4000A range. Data shows that constant exposure to room-level fluorescent lighting could erase the typical MM2758 in approximately 3 years, while It would take approximately 1 week to cause erasure when exposed to direct sunlight. If the MM2758Is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the MM2758 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

The recommended erasure procedure for the MM2758 is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2• The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a 12,000 p.W/cm2 power rating. The MM2758 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.

Note: The MM2758 may take up to 60 minutes for complete erasure to occur.

An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one

6-15

Inch. The erasure time Increases as the square of the distance. (If distance Is doubled the erasure time increases by a factor of 4.) Lamps lose Intensity as they age. When a lamp Is changed, the distance has changed or the lamp has aged, the system should be checked to make certain fuil erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when Incomplete erasure was the problem.


The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, Ice, has three segments that are of interest to the system designer-the standby current level, the active current level, and the transient current peaks that are produced on the falling and rising edges of chip enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated transient voltage peaks ean be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1 p.F ceramic capacitor be used on every device between Vee and GND. This should be a high frequency capacitor of low inherent inductance. In addition, a 4.7 p.F bulk electrolytic capacitor should be used between Vee and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the Inductive effects of the PC board traces.

CD

(3 ~National ~ ~ Semiconductor, microCMOS

~ NMC27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM z Parameter/Order Number

Access Time (ns)

Vee Power Supply

General Description The NMC27C16 is a high speed 16k UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.

The NMC27C16 is packaged ina 24-pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device by following the programming procedure.

This EPROM Is fabricated with the reliable, high volume, time proven, microCMOS silicon gate technology.


Pin Names


0 0-07 Outputs PGM Program NC No Connect

27C256 27C128 27C64 27C32 27256 27128 2764 2732

Vpp Vpp Vpp

NMC27C16·35 NMC27C16·45

NMC27CI6H-45

350 450

5V±5% 5V±5%

Features • Access time: 350 ns, 450 ns • Low CMOS power consumption

Active power: 26.25 mW max Standby power: 0.53 mW max (98% savings)

• Performance compatible to NSC800™ CMOS microprocessor .

• Single 5V power supply • Extended temperature range available

(NMC27C16E-45), - 40°C to + 85°C, 450 ns ± 5% power supply

• 10 ms programming available (NMC27C16H-45), an 80% time savings

• Pin compatible to MM2716 and National's higher density EPROMs

• Static-no clocks required • TTL compatible inputs/outputs • TRI-STATE@ output

Vee e>---. GND 0---+ Vpp e>---.

AD-AID ADDRESS

INPUTS

OUTPUT ENA8LE CHIP ENABLE

AND PRDG LOGIC

y DECODER

X DECODER

27C32 27C64 27C128 2732 2764 27128

Vee Vee

27C256 27256

Vee

A12 A12 A12 Dual-ln·Line Package Pli'M PGM A14

A7 A7 A7 A7 A7 24 Vee Vee NC A13 A13

A6 A6 A6 A6 A6 23 A8 A8 A8 A8 A8

A5 A5 A5 A5 A5 22 A9 A9 A9 A9 A9

A4 A4 A4 A4 A4 21 Vpp All All All All

A3 A3 A3 A3 A3 2D M" DE/Vpp DE DE DE

A2 A2 A2 A2 A2 NMC27C16 19 AID AID A1D A1D AID TOP VIEW

Al Al Al Al Al 18 CE CE CE CE C"E

AD AD AD AD AD 17 07 07 07 07 07

00 00 00 00 00 16 06 06 06 06 06

01 01 01 01 01 lD 15 05 05 05 05 05

02 02 02 02 02 11 14 D4 04 Dc D. 04

GNO GND GNO GNO GNO 12 13 03 03 03 03 03

NS Package Number J24A·Q Note: National's socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C16 pins.

6·16


Temperature Under Bias -10°C to + 80°C Temperature Range Storage Temperature -65°Cto + 125°C NMC27C16-35, NMC27C16-45,

All Input Voltages with Respect NMC27C16H-45 O°Cto + 70°C

to Ground + 6.5V to - 0.3V NMC27C16E-45 - 40°C to + 85°C

All Output Voltages with Respect Vee Power Su pply (Notes 2 and 3) 5V±5% to Ground Vee + 0.3V to GND - 0.3V Vpp Power Supply(Note3) Vee

Vpp Supply Voltage with Respect to Ground During Programming + 26.5V to - 0.3V

Power Dissipation 1.0W Lead Temperature (Soldering, 10 seconds) 300°C

READ OPERATION


Symbol Parameter Conditions Min Typ(Note 4) Max Units

III Input Load Current VIN = Vee or GND 10 p.A

ILo Output Leakage Current VOUT = Vee or GND, CE = VIH 10 p.A

lee1 (Note 3) Vee Current (Active) OE=CE=VIL 2 10 mA TIL Inputs Inputs = VIH or VIL, f = 1 MHz,

1I0=OmA

lee2 (Note 3) Vee Current (Active) OE=CE=VIL, 1 5 mA . CMOS Inputs Inputs = Vee or GND

f= 1 MHz, 1/0=0 mA

leesB1 Vee Current (Standby) CE=V1H 0.1 1 mA TIL Inputs

leesB2 Vee Current (Standby) CE=Vee 0.Q1 0.1 mA CMOS Inputs

VIL Input Low Voltage -0.1 0.8 V

V1H Input High Voltage 2.0 Vee+ 1 V

VOl1 Output Low Voltage IOL=2.1 mA 0.45 V

VOH1 Output High Voltage 10H= -400p.A 2.4 V

VOL2 Output Low Voltage 10L=OJLA 0.1 V

VOH2 Output High Voltage 10H=OJLA Vee- 0.1 V

AC Characteristics NMC27C16E-45

Symbol Parameter Conditions NMC27C16·35 NMC27C16·45

Units N MC27C16H·45

Min Max Min Max

tAec Address to Output Delay CE= OE=V1L 350 450 ns

tCE CE to Output Delay OE=VIL 350 450 ns

tOE Output Enable to C'E= VIL 120 120 ns Output Delay

tOF Output Enable High to CE=VIL 0 100 0 100 ns Output Float

tOH (Note 5) Output Hold.l!om _ CE=OE=VIL 0 0 ns Addresses, CE or OE, Whichever Occurred First

6-17

z s:: o I\) ~ o ...... en

CD (3 Capacitance (Note 5) (TA = + 25°C, f=1 MHz)

" C'I o :E z


CIN Input Capacitance VIN=OV 4

C OUT Output Capacitance VOUT=OV 8


Input Rise and Fall Times

Input Pulse Levels

1 TTLGateandCL= 100pF

:s;20ns

O.8Vto2.2V

Timing Measurement Reference Level

Inputs

Outputs

AC Waveforms (Note 2)

ADDRESSES

OUTPUT

1Vand2V

O.8Vand2V

Max Units

6 pF

12 pF

ADDRESSES VALID

Hi·Z

TlID/5275·3

Note1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and func· tlonal operation of the device at these or any other conditions above those Indicated In the operational sections of this specification Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: VCC must be applied simultaneously or before VPF! and removed simultaneously or after Vpp.

Note 3: Vpp may be connected to VCC except during programming. ICC1 sthe sum of the ICC active and Ipp read currents. Note 4: Typical values are for TA = + 25"C and nominal supply voltages.

Note 5: This parameter Is only sampled and Is not 100% tested.

Note 6: OE may be delayed up to tACC - tOE after the failing edge of CE without Impact on tACC. Note 7: The tOF compare level Is determined as follows:

High to TRI·STATE, the measured VOH1 (~C) - O.10V Low to TRI·STATE, the measured VOU (DC) + O.10V

Note 8: TRI·STATE may be attained using 5E or CE. Note 9: The power switching characteristics of EPROMs1'equlre careful device decoupling. It is recommended that a O.1I'F ceramic capacitor be used on every device between VCC and GNO. '

Note 10: The NMC27C16 requires one address transition after Initial power·up to reset the outputs.

Note 11: The outputs must be restricted to V CC + O.3V to avoid latch·up and device damage.

6·18


DC Programming Characteristics (Notes 2 and 3) (TA= +25°C±5°C, Vee=5V±5%, Vpp =25V± 1V)


III Input Current (for Any Input) VIN = Vee or GND .,

10 I'A

Ipp Vpp Supply Current During CE/PGM=V1H 30 rnA Programming Pulse

Icc Vee Supply Current 10 rnA

V1L Input Low Level -0.1 0.8 V

V1H Input High Level 2.0 Vee + 1 V

AC Programming Characteristics (Notes 2 and 3) (TA= +25°C±5°C, Vee=5V±5%, Vpp =25V± 1V)

NMC27C16 Devices NMC27C16H·45 Symbol Parameter Conditions Units

Min Typ Max Min Typ Max

tAS Address Set-Up Time 2 2 I'S

tOEs OE Set-Up Time 2 2 /LS

tos Data Set·Up Time 2 2 /LS

tAH Address Hold Time 2 2 /LS

tOEH OE Hold Time 2 2 /LS

tOH Data Hold Time 2 2 /LS

tOF Output Enable to Output Float Delay CE/PGM =VIL 0 160 0 160 ns

tOE Output Enable to Output Delay CE/PGM =V1L 160 160 ns

tpw Program Pulse Width 45 50 55 9 10 11 ms

tpRT Program Pulse Rise Time 5 5 ns

tPFT Program Pulse Fall Time 5 5 ns

AC Test Conditions Vee 5V±S% Vpp 25V±1V Input Rise and Fall Times s20ns Input Pulse Levels O.8Vto2.2V

Timing Measurement Reference Level Inputs 1V and 2V Outputs 0.8Vand2V

6·19

z 3: o N ~ o .... 0)

co ,... o ....... C'I o :IE z

Programming Waveforms (Note 3) (Vpp=25V± 1V, Vcc=5V±5%)

ADDRESS

DATA

eE/PGM

!of (0.16 MAX)

__ -._---~~:~~M ___ ~ ~----

DATA IN STABLE ADDN+m

TL1D/5275-4

Note: All times shown In parentheses are minimum and In "s unless otherwise specified.

Note 1: National's standard product warranty applies only to devices programmed to specifications described herein.

Not.2: VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The NMC27C16 must not be Inserted Into or removed from a board with Vpp at 25V:t 1V to prevent damage to the device.

Not.3: The maximum allowable voltage which may be applied to the Vpp pin during programming Is 26V. Care must betaken when switching the Vpp supply to prevent overshoot exceeding this 26V maximum speCification. A 0.1 "F capacitor Is required across Vpp, VCC to GND to suppress spurious voltage tran· sients which may damage the device.

6·20,

Functional Description

DEVICE OPERATION

The five modes of operation of the NMC27C16 are listed in Table I. It should be noted that all inputs for the five modes are at TTL levels. The power supplies required area5VVcc and a Vpp. The Vpp power supply must be at 25V during the three programming modes, and must be at 5V in the other two modes.

I Read Mode

The NMC27C16 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tAee) is equal to the delay from CE to output (tccl. Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tAcc-tOE' The NMC27C16 requires one address transition after initial power-up to reset the outputs.

Standby Mode

The NMC27C16 has a standby mode which reduces the active power dissipation by 98%, from 26.25 mW to 0.53 mW. The NMC27C16 is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output OR-Tying

Because NMC27C16s are usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for:

a) the lowest possible memory power dissipation, and


To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while Ol: (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that ali deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.

Programming

CAUTION: Exceeding 26.5Von pin 21 (Vpp) will damage the NMC27C16.

Initially, and after each erasure, all bits of the NMC27C16 are in the "1" state. Data is introduced by selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed, both "1s" and "Os" can be presented in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure.

The NMC27C16is in the programming mode when the Vpp power supply is at 25V and OE is at VIH.lt is required that a 0.1 IlF capacitor be placed across Vpp, Vee to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

When the addres~ and data are stable, a 50 ms (10 ms for the NMC27C16H-45), active high, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. You can program any location at any time-either individually, sequentially, or at random. The program pulse has a maximum width of 55 ms (11 ms for the NMC27C16H-45). The NMC27C16 must not be programmed with a DC signal applied to the CElPGM input.

Programming multiple NMC27C16s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled NMC27C16s may be connected together when they are programmed with the same data. A high level TTL pulse applied to the CE/PGM input programs the paralleled NMC27C16s.


~ CE/PGM OE Vpp Vee Outputs

Mode (18) (20) (21) (24) (9-11,13-17)

Read VIL VIL Vec 5 DOUT Standby VIH Don't Care Vec 5 Hi-Z

Program Pulsed VIL to VIH VIH 25 5 DIN Program Verify VIL VIL 25 5 DOUT Program Inhibit VIL VIH 25 5 Hi-Z

6-21

z s: o N ~ o ..&.

CD

CD ,... o " N o :E z


Program Inhibit

Programming multiple NMC27C16s in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs (including OE) of the parallel NMC27C16s may be common. A TTL level program pulse applied to an NMC27C16's CE/PGM input with Vpp at 25V will program that NMC27C16. A low level CE/PGM input inhibits the other NMC27C16 from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with Vpp at 25V. Except during programming and program verify, Vpp must be at Vce.


The erasure characteristics of the NMC27C16 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 A -4000A range. Data shows that constant exposure to room-level fluorescent lighting could erase the typical NMC27C16 in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the NMC27C16 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the NMC27C16 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

The recommended erasure procedure for the NMC27C16 is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2• The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a 12,000 p.W/cm2 power rating. The NMC27C16 should

6-22

be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.

An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch.· The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.


The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designer-the standby current level, the active current level, and the transient current peaks that are produced on the falling and rising edges of chip enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1 p.F ceramic capacitor be used on every device between Vee and GND. This should be a high frequency capacitor of low inherent inductance. In addition, a 4.7 p.F bulk electrolytic capacitor should be used between Vee and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effects of the PC board traces.

~National ~ Semiconductor microCMOS

NMC27C32 32,768-Bit (4096 x 8) UV Erasable CMOS PROM Paramet,,(Order Number

Access Time (ns)

Vee Power Supply

General Description The NMC27C32 is a high speed 32k UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. The NMC27C32 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device by following the programming procedure.

This EPROM is fabricated with the reliable, high volume, time proven, microCMOS silicon gate technology.


Pin Names


°0-0 7 Outputs PGM Program NC No Connect

nC2S6 27C128 27C64 27C16 27256 27128 2764 2716

Vpp Vpp Vpp

NMC21C32·35 NMC21C32-4S

NMC21C32H·45

350 450

5V:t5% 5V:t5%

Features • Access time: 350 ns, 450 ns • Low CMOS power consumption

Active power: 26.25 mW max Standby power: 0.53 mW max (98% savings)

• Performance compatible to NSC800™ CMOS microprocessor

• Single 5V power supply • Extended temperature range available

(NMC27C32E-45), - 40°C to + 85°C, 450 ns ± 5% power supply

• 10 ms programming available (NMC27C32H·45), an 80% time savings

• Pin compatible to NMC2732 and National's higher density EPROMs

• Static - no clocks required • TTL compatible inputs/outputs • Two-line control • TRI-~TATE@output

Vee 0---. GNO 0---. Vpp 0---.

AO-A11 AODRESS

INPUTS

OUTPUT ENABLE AND CHIP ENABLE

LOGIC

y DECODER

X DECODER

27C16 27C64 27C128 27C256 2716 2764 27128 27256

Vee Vee Vee

1.12 1.12 1.12 Dual-In-Line Package P"GM P"GM 1.14

1.7 1.7 1.7 1.7 1.7 24 Vee Vee NC 1.13 1.13

A6 1.6 A6 1.6 1.6 23 1.8 1.8 A8 A8 A8

1.5 1.5 A5 A5 1.5 1.9 A9 A9 1.9 1.9

1.4 1.4 A4 1.4 1.4 All vpp All All All

A3 A3 A3 1.3 1.3 DE/Vpp DE DE DE DE

1.2 A2 1.2 A2 1.2 AID AID AID 1.10 AID NMC21CJ2

Al Al Al Al Al TOPVIEW ' 18 cr CE CE fl fl

AD AD AO AD 1.0 17 0, 0, 0, 0, 0,

00 Do 00 00 00 16 0, 0, 0, 0, 0,

0, 01 01 01 0, 10 IS 05 05 05 05 05

0, 0, 0, 0, 0, 11 14 O. O. O. O. O.

GND GND GND GNO GNO 12 13 0, 0, 0, 0, 0,

NS Package Number J24A·Q Note: National's socket compatible EPROM pin configurations are shown In the blocks adjacent to the NMC27C32 pins.

6-23


Temperature Under Bias -10°Cto + 80°C Temperature Range Storage Temperature -65°Cto + 125°C NMC27C32-35, NMC27C32-45,

All Input Voltages with NMC27C32H-45 O°Cto + 70°C

Respect to Ground + 6.5V to - 0.3V NMC27C32E-45 - 40°Cto + 85°C

All Output Voltages with Vee Power Supply 5V±5%

Respect to Ground Vee+ 0.3VtoGND-0.3V Vpp Supply Voltage with 'Respect

to Ground During Programming + 26.5V to - 0.3V

Power Dissipation 1.0W


READ OPERATION


Symbol Parameter Conditions Min Typ (Note 2) Max Units

III Input Load Current V1H = Vee or GND 10 p.A

ILO Output Leakage Current VOUT = Vee or GND, CE = V1H 10 p.A

lee1 Vee Current (Active) OE=CE=V1L 2 10 rnA TTL Inputs Inputs = V1H or V1L, f = 1 MHz

I/O=OmA

lee2 Vee Current (Active) OE=CE=VIL 1 5 rnA CMOS Inputs Inputs = Vee or GND, f = 1 MHz

I/O=OmA

lecsB1 Vec Current (Standby) CE=V1H 0.1 1 rnA TTL Inputs

lecsB2 Vee Current (Standby) CE=Vec 0.01 0.1 rnA CMOS Inputs

V1L Input Low Voltage -0.1 0.8 V

V1H Input High Voltage "- 2.0 Vee +1 V

VOL1 Output Low Voltage IOL=2.1 rnA 0.45 V

VOH1 Output High Voltage 10H= -400p.A 2.4 V

VOL2 Output Low Voltage 10L=0p.A 0.1 V

VOH2 Output High Voltage IOH=O p.A Vec- 0.1 V

AC Characteristics

NMC27C32E·45

Symbol Parameter Conditions NMC27C32·35 NMC27C32·45

Units NMC27C32H·45

Min Max Min Max

tAce Address to Output Delay CE=OE=V1L 350 450 ns

teE CE to Output Delay OE=VIL 350 450 ns

tOE OE to CE=V1L 150 150 ns Output Delay

tOF OE High to CE= V1L 0 130 0 130 ns Output Float

tOH (Note 3) Output Hold from CE=OE=V1L 0 0 ns Addresses,' CE or OE, Whichever Occurred First

6·24

Capacitance (Note 3) (TA = + 25°C, f = 1 MHz)


CIN1 Input Capacitance VIN=OV 4 Except OEIVpp

CIN2 OEIVpp Input VIN=OV Capacitance

COUT Output Capacitance VOUT=OV 8

AC Test Conditions Output Load 11TLGateandCL= 100pF

Input Rise and Fall Times

Input Pulse Levels

Timing Measurement Reference Level Inputs Outputs

AC Waveforms

ADDRESSES

OUTPUT HI·Z

:s 20 ns

0.45Vto2.4V

1V~nd2V 0.8Vand2V

Max

6

20

12

ADDRESSES VALID

Units

pF

pF

pF

Hi·Z

TLlD/5274-J

Nola 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Nola 2: Typical values are for TA = + 2SoC and nominal supply voltages.

Nola 3: This parameter is only sampled and is not 100% tested.

Nola 4: BE may be delayed up to tACC-tOE after the falling edge of CE without impacting tACC'

Nota 5: The tOF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (~C) - 0.10V Low to TRI-STATE, the measured VOL1 (~C) + 0.10V

Nota 6: TRI-STATE may be attained using BE or CEo

Nota 7: The power switching characteristics of EPROMs require carefui device decoupling. It is recommended that a 0.1 ",F ceramic capacitor be used on every device between VCC and GND.

Nota 8: The outputs must be restricted to VCC + 0.3V to avoid latch·up and device damage.

6·25

PROGRAMMING (Note 1)

DC Programming Characteristics (Notes 2 and 3) (TA= +25°C±5°C, Vee=5V±5%, Vpp =25V± 1V)


III Input Current (All Inputs) VIN = Vee or GND 10 /LA

VOL Qutput Low Voltage During Verify IOL=2.1JmA 0.45 V

VOH Output High Voltage During Verify IOH = -400 /LA 2.4 V

lee Vee Supply Current 2 10 rnA

VIL I Input Low Level (All Inp!Jts) -0.1 0.8 V

VIH Input High Level (All Inputs Except OE/Vpp) 2.0 Vee+ 1 V

Ipp Vpp Supply Current CE = VIL, OE = Vpp 30 rnA

AC Programming Characteristics(TA= +25°C±5°C, Vee=5V±5%, Vpp=25V± 1V)

Symbol Parameter Conditions NMC27C32 Devices INI\IIC27C32H·45

Units Min Typ Max Min Typ Max

tAS Address Set·Up Time 2 2 P.s

tOES OE Set·Up Time 2 2 P.s

tos Data Set·Up Time 2 2 P.s

tAH Address Hold Time 0 p P.s

tOEH OE Hold Time 2 2 P.s

tOH Data Hold Time 2 2 P.s

tOF Chip Enable to Output Float Delay 0 130 0 130 ns

tov Data Valid from CE CE = VIL, OE = VIL 1 1 P.s

tpw CE Pulse Width During Programming 45 50 55 9 10 11 ms

tpRT OE Pulse Rise Time During Programming 50 50 ns

tVR Vpp Recovery Time 2 2 P.s

AC Test Conditions Vce 5V±5% ,

Vpp 25V±1V

Input Rise and Fall Times :520 ns

Input Pulse Levels 0.45Vto2.4V Timing Measurement Reference Level

Inputs 1Vand2V Outputs 0.8V and 2V

6-26

Programming Waveforms (Note 3)

I_------PROGRAM------.-I---P~~~I~~M--

AODRESSES ADDRESS N

DATA----{I

OE/Vpp

CE

Vpp -----~---+----+---"'"

VIH -------'"'-'

VIL --------' .... -.-'

Note: All times shown in parentheses are minimum and In P.s unless otherwise specified. The Input timing reference level Is 1V for a VIL and 2V for a VIH.

Nole 1: National's standard product warranty applies only to devices programmed to specifications described herein.

TlID/5214-4

Nole 2: VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The NMC27C32 must not be inserted into or removed from a board with Vpp at 25V:t 1 V to prevent damage to the device.

Nole 3: The maximum allowable voltage which may be applied to the Vpp pin during programming Is 26V. Care must be taken when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification. A 0.1 p.F capacitor Is required across Vpp, VCC to GND to suppress spurious voltage transients which may damage the device.

6-27

z 3: o I\) ~ o w I\)

Functional Description DEVICE OPERATION

The five modes of operation of the NMC27C32 are listed in Table I. A single 5V power supply is required in the read mode. All inputs are TTL levels except for OElVpp during programming. In the program mode the OElVpp input is pulsed from a TTL level to 25V.

Read Mode

The NMC27C32 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent.of deviceselection. Assuming that addresses are stable, address access time (tACe) is equal to the delay from CE to output (tcE>. Data is available at the outputs after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tAcc-tOE.

Standby Mode

The NMC27C32 has a standby mode which reduces the active power dissipation by 98%, from 26.25 mW to 0.53 mW. The NMC27C32 is placed in the standby mode by applying a TIL high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output OR·Tying

Because EPROMS are usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connection. The 2-line control function allows for:

a) the lowest possible memory power disSipation, and


To most efficiently use these two control I ines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.

Programming

CAUTION: Exceeding 26.5Von pin 20 (Vpp) will damage the NMC27C32.

Initially, and after each erasure, all bits of the NMC27C32 are in the "1" state. Data is introduced by selectively programming "as" into the desired bit locations. Although only "as" will be programmed, both "1s" and "as" can be presented in the data word. The only way to change a "a" to a "1" is by ultraviolet light erasure.

The NMC27C32 is in the programming mode when the OElVpp input is at 25V.lt is required that aO.1 ~F capacitor be placed across OElVpp, Vcc, and ground to suppress spurious voltage transients which may damage the de-· vice. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

When the address and data are stable, a 50 ms (10 ms for the NMC27C32H-45),active low, TTL program pulse is applied to the CE input. A program pulse must be applied at each address location to be programmed. You can program any location at any time-either individually, sequentially, or at random. The program pulse has a maximum width of 55 ms (11 ms for the NMC27C32H-45). The NMC27C32 must not be programmed with a DC signal applied to the CE input.

Programming of multiple NMC27C32s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled NMC27C32s may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE input programs the paralleled NMC27C32s.

Program Inhibit

Programming multiple NMC27C32s in parallel with different data is also easily accomplished. Except for CE, all !'ike inputs (including OE) of the parallel NMC27C32s may be common. ~ TTL level pr~ram pulse applied to an NMC27C32's CE input with OElVpp at 25V will program that NMC27C32. A high level CE input inhibits the other NMC27C32s from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify is accomplished with OElVpp and CE at VIL. Data should be verified tov after the falling edge of CE.


~ CE OE/Vpp Vee Outputs Mode (18) (20) (24) (9-11,13-17)

Read VIL VIL 5 DouT Standby VIH Don't Care 5 Hi-Z Program VIL Vpp 5 DIN Program Verify VIL VIL 5 Dour Program Inhibit VIH Vpp 5 Hi-Z

6-28



The erasure characteristics of the NMC27C32 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A -4000A range. Data shows that constant exposure to room-level fluorescent lighting could erase the typical NMC27C32 in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the NMC27C32 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the NMC27C32 window to prevent unintentional erasure. Covering the window will also prevent temporary fUnctional failure due to the generation of photo currents.

The recommended erasure procedure for the NMC27C32 is exposure ,to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 21 minutes using an ultraviolet lamp with a 12,000 /lW/cm 2 power rating. The NMC27C32 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.

An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age.

6-29

When a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure Is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.


The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, Icc. has three segments that are of interest to the system designer-the standby current level. the active current level. and the transient current peaks that are produced on the falling and rising edges of chip enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that a 0.1JlF ceramic capacitor be used on every device between Vee and GND. This should be a high frequency capacitor of low inherent inductance. In addition, a 4.7 JlF bulk electrolytic capacitor should be used between Vee and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the

. voltage droop caused by the inductive effects of the PC board traces.

CD II) N () l"'"N ()

:E z

~National . ~ Semiconductor

PRELIMINARY

microCMOS

NMC27C256 262,144-Bit (32K x 8) UV Erasable CMOS PROM

General Description The NMC27C256 is a high-speed 256k UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements.

The NMC27C256 is packaged in a 28-pin dual in-line package with transparent lid. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device by following the programming procedure.

This EPROM is fabricated with the reliable, high volume, time proven, microCMOS silicon gate technology.

Block Diagram

Features • Access time down to 200 ns, microCMOS technology

• Low CMOS power consumption • Compatible to high-speed (8 MHz) microprocessors,

zero wait state

• Performance compatible to NSC800™ CMOS microprocessor

• Single 5V power supply

• Fast and reliable programming • Static - no clocks required

• TTL compatible inputs/outputs

• CMOS compatible inputs/outputs

• Two-line control • TRI-STATE® output

DATA OUTPUTS 00-07 Vee 0---+

GND 0---+

Pin Names

AO-A14 Addresses

CE Chip Enable

OE Output Enable

0 0-07 Outputs

PGM Program

NC No Connect AD-A14

ADDRESS INPUTS

6-30

OUTPUT BUFFERS

Y GATING

262,144·BIT CEll MATRIX

TUD17512·1


X CE OE Vpp Vee Outputs (11-13,

Mode (20) (22) (1) (28) 15-19)

Read VIL VIL Vee Vee Dour

Output Disable VIL VIH Vee Vee High Z

Standby VIH X Vee Vee High Z

Verify VIH VIL Vpp Vee Dour

Program Inhibit VIH VIH Vpp Vee High Z

Note: X can be V1H or V1L•

Connection Diagram

27C32 27C16 27C16 27C32 2732 2716 2716 2732

Vpp 2B Vee

A12 A14

A7 A7 A7 A13 Vee Vee

A6 A6 A6 AB AB AB

AS AS AS A9 A9 A9

A4 A4 A4 All Vpp A11

DE DENpp A3 A3 A3 NMC27C256 DE TOP VIEW

A2 A2 A2 21 A1D A1D A1D

A1 A1 A1 20 CE CE CE

AD AD AD 19 07 07 07

00 00 00 11 1B 06 06 06

01 01 01 12 17 Os 05 05

02 02 02 13 16 04 04 04

03 03 GND GND GND 14 15 03 TuonS12·2

Note: National's socket compatible EPROM pin configurations are shown In the blocks adjacent to the NMe27e256 pins.

NS Package Number J24A·Q

6·31

Section 7

EEPROMs

EEPROMs

Section Contents

NMC9306/COP494 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

NMC9306E/COP394 256-Bit Serial Electrically Erasable Programmable Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

NMC9346/COP495 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) . . . . . . . . . . . . . . . . . . . . . . .. 7-13

NMC9346E/COP395 1024-Bit Serial Electrically Erasable Programmable Memory (5V Only) . . . . . . . . . . . . . . . . . . . . . .. 7-18

NMC2816 16k (2k x 8) Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-23

NMC2816M 16k (2k x 8) Electrically Erasable PROM ............. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·29

NMC9716 16k (2k x 8) Electrically Etasable PROM ................ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-35

NMC9716M 16k (2kx 8) Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-42

NMC9817 16,384-Bit (2kx 8) E2PROM ................................................................... 7·49

NMC98C64A 65,536-Bit(8kx 8) E2PROM ................................................................ 7-54

AB-5 Threshold Bit Mapping in EEPROMs(NMC2816) ...................................................... 7·57

AB-15 Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . .. 7-59

AN·328 EEPROM Application Note, Vpp Generation on Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-61

AN-338 Designing with the NMC9306/COP494, a Versatile; Simple to Use E2PROM .................. , . . . . . . . . . .. 7-67

AN-342 Designing with the NMC9817, a 2nd Generation E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-74

7-2

~National U Semiconductor NMC9306/COP494 256·Bit Serial Electrically Erasable Programmable Memory General Description The NMC9306/COP494 is a 256-bit non-volatile sequential access memory fabricated using advanced floating gate N-channel E2PROM technology. It is a peripheral memory designed for data storage and/or timing and is accessed via the simple MICROWIRE™ serial interface. The device contains 256 bits of read/write memory divided into 16 regIsters of 16 bits each. Each register can be serially read or written by a COP400 series controller. Written information Is stored in a floating gate cell with at least 10 years data retention and can be updated by an erase-write cycle. The NMC9306/COP494 has been designed to meet applications requiring up to 1 X 104 erase/write cycles per register. A power down mode reduces power consumption by 70 percent.


vpp ~VCC

Features • Low cost • Single supply operation (5V ± 10%)

• TTL compatible • 16 x 16 serial read/write memory

• MICROWIRE compatible serial I/O • Compatible with COP400 processors

• Low standby power • Non-volatile erase and write • Reliable floating gate technology

GENERATOR ~ Dual·ln·Llne Packago

Ivpp

+ r-+

~ E2PROM

DECODER 256 BITS

r+ 1/16 (16x16)

fa $6

ADDRESS LATCHES

R/WAMPS

4 $6

DATA r-+ REGISTER

(17 BITS) ClK

I

4 INSTRUCTION REGISTER ClK

r-+ (9 BITS)

J: "'"""'-

INSTRUCTION DECODE,

CONTROL AND

CS CLOCK GENERATORS

SK ~

FIGURE 1

+-

.,L... ."" DO

.,1.

--

TUDf502 9·1

7-3

CS vee

SK NC

01 NC

DO GNO

TOP VIEW TUDf5029·2

FIGURE2

Order Number NMC9306N NS Package Number NOSE

Pin Names

CS Chip Select SK Serial Data Clock 01 Serial Data Input DO Serial Data Output VCC Power Supply GNO Ground

~

~. a.. o o co o ~ en o :E z

Absolute Maximum Ratings Voltage Relative to GNO Ambient Operating Temperature

NMC9306ICOP494 Ambient Storage Temperature

+6Vto -0.3V

with Data Retention - 65°C to + 125°C Lead Temperature (Soldering, 10 seconds) 300°C

Note: Stresses above those listed under "Absolute Maxi· mum Ratings" may cause permanent damage to the de· vice. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating con· ditions for extended periods may affect device reliability.

Electrical Characteristics O°C ::5 TA ::5 70°C, VCC = 5V ± 10% unless otherwise specified

Parameter Conditions Min Typ Max

Operating Voltage (VCC) 4.5 5.5

Operating Current (ICC1) VCC = 5.5V, CS = 1 10

Standby Current (lCC2) VCC = 5.5V, CS = 0 3

Input Voltage Levels VIL -0.1 0.8 VIH 2.0 VCC+1

Output Voltage Levels VOL IOL=2.1 rnA 0.4 VOH 10H= -400p.A 2.4

Input Leakage Current VIN=5.5V 10

Output Leakage Current VbUT = 5.5V, CS = 0 10

SK Frequency 0 250

SK Duty Cycle 25 75

Input Set·Up and Hold Times CS tcss 0.2

tCSH 0

01 tolS 0.4 tOIH 0.4

Output Delay CL= 100 pF DO tp01 VOL = 0.8V, VOH = 2.0V 2

tpoo VIL = 0.45V, VIH = 2.40V 2

EraselWrite Pulse Width (tE/W) ~O 30

Note: tE/W measured to rising edge of SK or CS, whichever occurs last.

I nstruction Set Instruction S8 OpCode Address Data Comments

READ 1 10xx A3A2A1AO Read register A~A2A1AO

WRITE 1 01xx A3A2A1AO 015-00 Write register A~A2A1AO ERASE 1 11xx A3A2A1AO Erase register A3A2A1AO

EWEN 1 0011 xxxx Eraselwrite enable

EWOS 1 0000 xxxx Eraselwrite discible

ERAL 1 0010 xxx x Erase all registers

WRAL 1 0001 xxxx 015-00 Write all registers NMC93061COP494 has 7 instructions as shown. Nole that MSa of any given Instruction is a "1" and is viewed as a start bit in the interface sequence. The next 8 bits carry the op code and the 4·bit address for 1 of 16, 16·bit registers. X Is a don't care state.

FIGURE 3

7-4

Units

V

rnA

rnA

V V

V V

p.A

p.A

kHz

0/0

JLs JLs

JLs JLS

JLS JLs

ms

Functional Description The NMC9306/COP494 is a small peripheral memory Intended for use with COPS ™ controllers and other nonvolatile memory applications. Its organization is sixteen registers and each register Is sixteen bits wide. The Input and output pins are controlled by separate serial formats. Six 9-bit instructions can be executed. The instruction format has a logical '1' as a start bit, four bits as an op code, and four bits of address. SK clock cycle is necessary after CS equals logical "1" before the instruction can be loaded. The on-chip programming·voltage generator allows the user to use a single power supply (VCC). Only during the read mode is the serial output (DO) pin valid. During all other modes the DO pin is In TRI-STATE@, eliminating bus contention.

READ

The read instruction is the only instruction which outputs serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the 16-bit data output string. The output data changes during the high states of the system clock.

ERASE/WRITE ENABLE AND DISABLE

Programming must be preceded once by a programming enable (EWEN) instruction. Programming remains enabled until a programming disable (EWDS) instruction is executed. The programming disable instruction is provided to protect against accidental data disturb. Execution of a READ instruction is independent of both EWEN and EWDS instructions.

Timing Diagrams

SK

DI

cs

DO

*Thls is the minimum SK period

ERASE

Like most E2PROMS, the register must first be erased (all bits set to 1 s) before the register can be written (certain bits set to Os). After an ERASE instruction is Input, CS is dropped low. This falling edge of CS determines the start of programming. The register at the address specified In the instruction is then set entirely to 1s. When the erase/write programming time (t E/W) constraint has been satisfied, CS is brought up for at least one SK period. A new instruction may then be input, or a low-power standby state may be achieved by dropping CS low.

WRITE

The WRITE instruction is followed by 16 bits of data which are written Into the specified address. This register must have been previously erased. Like any programming mode, erase/write time is determined by the low state of CS following the instruction. The on-chip high voltage section only generates high voltage during these programming modes, which prevents spurious programming during other modes. When CS rises to VIH, the programming cycle ends. All programming modes should be ended with CS high for one SK period, or followed by another instruction.

CHIP ERASE

Entire chip erasing is provided for ease of programming. Erasing the chip means that all registers in t,he memory array have each bit set to a 1. Each register is then ready for a WRITE instruction.

CHIP WRITE

All registers must be erased before a chip write operation. The chip write cycle is identical to the write cycle, except for the different op code. All registers are simultaneously written with the data pattern specified in the instruction.

TUD/5029-3

FIGURE 4. Synchronous Data Timing

7-5

z 3: o CO W o 2! o o ." ~ CO ~

" 6>

N MC9306/COP494

SK UL.rUlSl CS / \'------

READ

01 ----1 1 \ 0 0 C€)()CM"\ II-I _______________ _

DO ~ TUD/5029-4

SK l.IUU 1...fLf1 WRITE < CS .I ~EI!=:I

DI ~)CM:\ I 1 cx:::::x: TUD/5029-5

SK 1...fLf1 ' ERASE < CS / ~E/W* - i

01 / 1 1 ',-_0 __ _ TUD/5029-6

* IE/W measured 10 rising edge of SK or CS, whichever occurs last. FIGURE 5. Instruction Timing

=! ~. :l

CO c iii"

CO .... $»

3 en o o ~ :::J C co ..e,

-..,J

.!.J

SK

::t 3 s·

CQ c Di"

(C

"'" Q)

3 EWEN EWDS

(ERASE/WRITE ENABLE/DISABLE)

CS/ - --- \""'"' __________ _ en ()

DI

SK

___ '" 0 I \ ENABLE = 11 DISABLE=OO

ERAL J / '\-IE~W* i (ERASE ALL) 1 cs '----

01 ~ 0 0 r-;-\""'"' ________________ oooIl-____ oI

*IE/W measured to rising edge of SK or CS, whichever occurs last.

FIGURE 5. Instruction Timing (Continued)

TUD/S029-7

TUD/S029-8

o ~ :::J C CD

S

1'61'd 00/90£60 W N

~ 0) ('I) a.. o o --.. w co o ('I) 0)

o :E z

~National D Semiconductor NMC9306E/COP394 256·Bit Serial Electrically Erasable Programmable Memory General Description The NMC9306E/COP494E is a 256-bit non-volatile sequential access memory fabricated using advanced floating gate N-channel E2PROM technology_ It is a peripheral memory designed for data storage and/or timing and is accessed via the simple MICROWIRE™ serial interface. The device contains 256 bits of read/write memory divided into .16 registers of 16 bits each. Each register can be serially read or written by a COP400 series controller. Written infor-, mation is stored in a floating gate cell with at least 10 years data retention and can be updated by an erasewrite cycle. The NMC9306E/COP494E has been designed to meet applications requiring up to 1 X 104 erase/write cycles per register. A power down mode reduces power consumption by 70 percent.


VPP I+-VCC

GENERATOR -.

VPP

I r--t

~ E2PROM

DECODER 256 BITS .. 1116 (16x 16)

fa $6

ADDRESS R/WAMPS

~ LATCHES

A

$6 4

DATA

Features • Low cost • Single supply operation (5V ± 10%)

• TTL compatible • 16 x 16 serial read/write memory • MICROWIRE compatible serial I/O • Compatible with COP400 processors

• Low standby power • Non-volatile erase and write

• Reliable floating gate technology


CS VCC

SK NC

DI NC

DO GND

TOP VIEW TUD/S1S9·2

FIGURE 2

DO Order Number NMC9306NE NS Package Number N08E

--. REGISTER (17 BITS) CLK ,..L- a...

I

........ INSTRUCTION REGISTER CLK --. (9 BITS)

J: -

INSTRUCTION DECODE,

CONTROL AND

CS CLOCK GENERATORS

SK

FIGURE 1

~

~

~

TUD/S1 S9-1

7-8

Pin Names

CS Chip Select SK Serial Data Clock' 01 Serial Data Input DO Serial Data Output VCC Power Supply GND Ground

Absolute Maximum Ratings Voltage Relative to G N 0 + 6Vto -0.3V Note: Stresses above those listed under "Absolute Maxl-Ambient Operating Temperature mum Ratings" may cause permanent damage to the de-

NMC9306E/COP494E -40°Cto +85°C vice. This Is a stress rating only and functional operation

Ambient Storage Temperature of the device at these or any other conditions above those

with Data Retention - 65°C to + 125°C indicated in the operational sections of this specification

Lead Temperature (Soldering, 10 seconds) 300°C is not implied. Exposure to absolute maximum rating con-ditions for extended periods may affect device reliability.

Electrical Characteristics -40°C :s TA :s + 85°C, VCC = 5V ± 10% unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage (VCC) 4.5 5.5 V

Operating Current (ICC1) VCC = 5.5V, CS = 1 10 mA

Standby Current (ICC2) VCC = 5.5V, CS = 0 3 mA

Input Voltage Levels VIL -0.1 0.8 V VIH 2.0 VCC+1 V

Output Voltage Levels VOL IOL=2.1 mA 0.4 V VOH 10H = - 400 p.A 2.4 V

Input Leakage Current VIN=5.5V 10 p.A

Output Leakage Current VOUT = 5.5V, CS = 0 10 p.A

SK Frequency 0 250 kHz

SK Duty Cycle 25 75 %

Input Set-Up and Hold Times CS tcss 0.2 P.s

tCSH 0 p's

01 tOIS 0.4 p's tOIH 0.4 p's

Output Delay CL= 100 pF DO tp0 1 VOL = 0.8V, VOH = 2.0V 2 p's

tpoo VIL = 0.45V, VIH = 2.40V 2 p's

EraselWrlte Pulse Width (tE/W) 10 30 ms

Note: tEJW measured to rising edge of SK or CS, whichever occurs last.

Instruction Set Instruction S8 OpCode Address Data Comments

. READ 1 10xx A3A2A1AO Read register A3A2~1AO

WRITE 1 01xx A3A2A1AO 015-00 Write register A3A2A1AO

ERASE 1 11xx A3A2A1AO Erase registerA3A2A1AO

EWEN 1 0011 xxxx Erase/write enable

EWOS 1 0000 xxxx Eraselwrlte disable

ERAL 1 0010 xxxx Erase all registers

WRAL 1 0001 xxxx 015-00 Write all registers NMC9306E1COP494E has 7 Instructions as shown. Note that MSB of any given Instruction Is a "1" and Is viewed as a start bit In the Interface sequence. The next 8 bits carry the op code and the 4·blt address for 1 of 16, 16-blt registers. X Is a don't care state.

FIGURE 3

7-9

z 3: o CO

~ 0)

m o o "'0 w CO ..c-.

¢

~ D.. o 0: --w co o ~ en o :e z

Functional Description The NMC9306E/COP494E is a small peripheral memory intended for use with COPS ™ controllers and other nonvolatile memory applications. Its organization is sixteen registers and each register is sixteen bits wide. The input . and output pins are controlled by separate serial formats. Six 9-bit instructions can be executed. The instruction format has a logical '1' as a start bit, four bits as an op code, and four bits of address. SK clock cycle is necessary after CS equals logical "1 " before the instruction can be loaded: The on-chip programming-voltage generator allows the user to use a single power supply (VCC). Only during the read mode is the serial output (DO) pin valid. During all other modes the DO pin is in TRI-STATE~l, eliminating bus contention.

READ

The read instruction is the only instruction which outputs serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the memory register into a 16-bit serial-out shift register. A dummy bit (logical '0') precedes the 16-bit data output string. The output data changes during the high states of the system clock.


Programming must be preceded once by a programming enable (EWEN) instruction. Programming remains enabled until a programming disable (EWDS) instruction is executed. The programming disable instruction is provided to protect against accidental data disturb. Execution of a READ instruction is independent of both EWEN and EWDS instructions.

Timing Diagrams

ERASE

Like most E2PROMS, the register must first be erased (all bits set to 1s) before the register can be written (certain bits set to Os). After an ERASE instruction is input, CS is dropped low. This falling edge of CS determines the start of programming. The register at the address specified in the instruction is then set entirely to 1s. When the erase/write programming time (tE/W) constraint has been satisfied, CS is brought up for at least one SK period. A . new instruction may then be input, or a low-power standby state may be achieved by dropping CS low.

WRITE

The WRITE instruction is followed by 16 bits of data which are written into the specified address. This register must have been previously erased. Like any programmi ng mode, erase/write time is determined by the low state of CS following the instruction. The on-chip high voltage section only generates high voltage during these programming modes, which prevents spurious programming during other modes. When CS rises to VIH, the programming cycle ends. All programming modes should be ended with CS high for one SK period, or followed by another instruction.

CHIP ERASE

Entire chip erasing is provided for ease of programming. Erasing the chip means that all registers in the memory array have each bit set to a 1. Each register is then ready for a WRITE instruction.

CHIP WRITE

. All registers must be erased before a chip write operation. The chip write cycle is identical to the write cycle, except for the different op code. All registers are simUltaneously written with the data pattern specified in the instruction.

~-------4~*------~

SK

01

CS

DO

TU0/5159-3

*Thls Is the minimum SK period

FIGURE 4. Synchronous Data Timing

7-10

SK ~

cs /- - ----\ ....... _-------

READ

01 ---1 1 \ 0 0 ~ JC€\ I ~J ______________ _

DO ~ TLJD/S1S!l-4

SK uu-liUU1 ~ I WRITE 1 cs J I I I ~tu:::::::l

01 ~)G"\ I 1 c::x::::x: TUD/S1S9-S

SK .UU1 ERASE < cs / ~~r:::::::f

01 /,'-__ _

TUD/S1S~

*tE/W measured to rising edge of SK or es, whichever occurs last.

FIGURE 5. Instruction Timing

-I 3" :l ce c iii" ce m 3 U)

o o ;:!. :;-c: ro B

17SEdOO/390ESOIN N

:::. N

SK

NMC9306E/COP394

-t 3" :r ea c iii" ea ;; 3 EWEN

EWDS (ERASE/WRITE

ENABLE/ DISABlE)

cs/_· .-\.~: __________ _ en ~

ERAL (ERASE ALL)

m ;--;-\0 0/ \

SK

ENABLE = 11 DISABLE=OO

CS / 'c:=:.E:=J 01 ~ 0 0 ~~_O ____________________________ ~~ ______ ~

* tE/W measured to rising edge of SK or CS, whichever occurs last.

FIGURE 5. Instruction Timing (Continued)

Tl.ID/515~7

TlIDI5159-8

a :J

~C:

(I)

.s


NMC9346/COP4951024·Bit Serial Electrically Erasable Programmable Memory (5V Only)

General Description The NMC9346/COP495 is a 1024-bit non-volatile, se~uential E2PROM, fabricated using advanced N-channel EPROM technology. It is an external memory with the 1024 bits of read/write memory divided into 64 registers of 16 bits each. Each register can be serially read or written by a COP400 controller, or a standard microprocessor. Written Information is stored in a floating gate cell until updated by an erase and write cycle. The NMC9346/COP495 has been designed for applications requiring up to 104 erase/write cycles per register. A power-down mode is provided by CS to reduce power consumption by 75 percent.


Serial E2PROM Vec-GNO-

DI-I-f.-I--I----f.--......

CS~-----------------~

SK-------------------~

INSTRUCTION DECODE.

CONTROL. AND CLOCK GENERATOR

Features • Low cost • Single supply read/write/erase operations !5V ± 10%)

• TTL compatible • 64 x 16 serial read/write memory • MICROWIRE™ compatible serial I/O

• Simple interfacing • Low standby power • Non·volatlle erase and write • Reliable floating gate technology

• Self-timed programming cycle

• Device status signal during programming


CS Vee

SK NC

DI NC

DO GND

TOP VIEW

Order Number NMC9346N NS Package Number NOSE

00 Pin Names

CS Chip Select SK Serial Data Clock

01 Serial Data Input

DO Serial Data Output

Vee Power Supply GND Ground

NC Not Connected

7-13

z 3: o CO c,.) ~ S!! o o "'tJ ~ CO (II

Absolute Maximum Ratings (Note 1)

Voltage Relative to GNO +6Vto -0.3V Ambient Operating Temperature O°Cto + 70°C Ambient Storage Temperature -65°Cto + 125°C Lead Temperature (Soldering, 10 seconds) 300°C

DC and AC Electrical Characteristics O°C:5 TA:5 70°C, Vee = 5V ± 10% unless specified


Vee Operating Voltage 4.5 5.5 V

lect Operating Current Vee = 5.5V, CS= 1, SK= 1 12 mA

Erase/Write Operating Current Vcc =5.5V 12 mA

lee2 Standby Current Vee = 5.5V, CS = 0 3 mA

Input Voltage Levels VIL -0.1 0.8 V VIH 2.0 Vcc + 1 V

Output Voltage Levels

VOL IOL=2.1 mA 0.4 V VOH IOH= -400Jl.A 2.4 V

III Input Leakage Current VIN =5.5V 10 Jl.A

ILo Output Leakage Current VouT =5:5V, CS=O 10 Jl.A


SK Outy Cycle 25 75 %

Inputs

tcss CS 0.2 Jl.S

tCSH 0 Jl.S

tOIS 01 0.4 Jl.s tOIH 0.4 Jl.S

Output CL= 100 pF

tpd1 00 VOL = 0.8V, VOH = 2.0V 2 Jl.S

tpdO VIL = 0.45V, VIH = 2.40V 2 Jl.S

tE/W Self-Timed Program 10 ms Cycle

tcs Min CS Low Time 1 Jl.S

tsv Rising Edge of CS to CL=100pF 1 Jl.S

Status Valid

tOH , ttH Falling Edge of CS 0.4 Jl.S

to 00 TRI-STATE®

Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those Indicated In the operational sections of the specification is not implied. Exposure to abo solute maximum rating conditions for extended periods may affect device reliability.

Instruction Set for NMC9346/COP495

Instruction SB OpCode Address Data Comments

REAO 1 10 A5A4A3A2A1AO Read register A5A4A3A2A1AO

WRITE 1 01 A5A4A3A2A1AO 015-00 Write register A5A4A3A2A1AO

ERASE 1 11 A5A4A3A2A1AO Erase register A5A4A3A2A1AO

EWEN 1 00 11xxxx Erase/write enable

EWOS 1 00 OOxxxx Erase/write disable

ERAL 1 00 10xxxx Erase all registers I

WRAL 1 00 01xxxx 015-00 Write all registers i

NMC9346/COP495 has 7 instructions as shown. Note that the MSB of any given instruction Is a "1" and is viewed as a start bit in the interface sequence. The next 8 bits carry the op code a~d the 6·bit address for 1 of 64, 16·bit registers.

\

7-14

Functional Description The NMC9346/COP495 is a small peripheral memory in· tended for use with COPSTM controllers and other non· volatile memory applications. Its organization is sixty·four registers and each register is sixteen bits wide. The Input and output pins are controlled by separate serial formats. Six g.blt instructions can be executed. The instruction for· mat has a logical '1' as a start bit, two bits as an op code, and six bits of address. The programming cycle is self· timed, with the data out (DO) pin indicating the ready/busy status of the chip. The on·chip programming voltage gen· erator allows the user to use a single power supply (V cd. It only generates high voltage during the programming modes (write, erase, chip erase, chip write) to prevent spurious programming during other modes. The DO pin is valid as data out during the read mode, and if initiated, as a ready/busy status indicator during a programming cy· cle. During all other modes the DO pin is in TRI·STATE, eliminating bus contention.

READ

The read instruction is the only instruction which outputs serial data on the DO pin. After a read instruction is reo ceived, the instruction and address are decoded, followed by data transfer from the memory register into a 16·bit serial·out shift register. A dummy bit (logical '0') precedes the 16-bit data output string. The output data changes duro ing the high states of the system clock.


When Vee is applied to the part it powers up in the pro· gramming disable (EWDS) state, programming must be preceded by a programming enable (EWEN) instruction. Programming remains enabled until a programming dis· able (EWDS) instruction is executed or Vee is removed from the part. The programming disable instruction is pro· vided to protect against accidental data disturb. Execu· tion of a read instruction Is Independent of both EWEN and EWDS instrUctions.

ERASE

Like most E2PROMs, the register must first be erased (all bits set to logical '1') before the register can be written

(certain bits set to logical '0'). After an erase instruction is input, CS is dropped low. This falling edge of CS deter· mines the start of the self·timed programming cycle. If CS is brought high subsequently (after observing the tes specification), the DO pin will indicate the ready/busy status of the chip. The DO pin will go low if the chip is still programming. The DO pin will go high when all bits of the register at the address specified in the instruction have been set to a logical '1'. The part is now ready for the next instruction sequence.

WRITE

The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data (DO) is put on the data in (01) pin CS must be brought low before the next rising edge of the SK clock. This falling edge of CS initiates the self·timed programming cycle. Like all programming modes, DO indicates the ready/busy status of the chip if CS is brought high after a minimum of 1 p's (tes). DO = logical 'a' indicates that programming is still in progress. DO = logical '1 ' indicates that the register at the address specified in the instruction has been writ· ten with the data pattern specified in the instruction and the part is ready for another instruction. The register to be written into must have been previously erased.

CHIP ERASE

Entire chip erasing is provided for ease of programming. Erasi~g the chip means that all registers in the memory ar· ray have each bit set to a logical '1'. Each register is then ready for a write instruction. The chip erase cycle is iden· tical to the erase cycle except for the different op code.

CHIP WRITE

All registers must be erased before a chip write operation. The chip write cycle is identical to the write cycle except for the different op code. All registers are simultaneously written with the data pattern specified in the instruction.

Note1: es must be brought low for a minimum of 1 P.s (tes) between con· secutlve instruction cycles. Note 2: During a programming mode (write, erase, chip erase, chip write), SK clock Is only needed while the actual Instruction, i.e., start bit, op code, address and data, Is being input. It can remain deactivated during the self·timed programming cycle and status check.

Timing Diagrams Synchronous Data Timing

!-4p.S*---j SK VIH ---n .---

'Vll • - I '-__ _

01

CS

VOH ----_ 00

VOL ____ --.J~ ___ ...J TL/D/5497·3

*Thls Is the minimum SK period.

7·15 .

-~ en

READ

WRITE

EWEN EWOS

N MC9346/COP495

Instruction Timing

SK 1..fUlJLJL.JlilSl~

CS /

01 ~ ________________ ! .. ______________ ~.-+ ________________ __

DO TRI-STATE'" ~ TLlD/5497-4

SK 1SUUUULfU1I1JL..fl.J CS / CHECK STATUS

01 ~

DO

tsv

BUSY TRI-STATE \~

I. te/W .1

SK

STANDBY

tlH

TRI-STATE

TLlD/5497·5

cs / ----- \~ ________ _ STANDBY

01 ---"" 0 I X __.&, ENABLE=ll

OISABLE=DO TLlD/5497-6

-I 3" S" ca c iii" ca ; 3 en o o 3-:;-c: CD ..9:

ERASE

~ ERAL ....,

WRAL

Instruction Timing

SK 1...n.I.1..Il..nn.rLf1..f1 cs I

Dl ~ ~~--~--~I~.--~!I~----------~---------

DO TRI·STATE

TUOf5497·7

SK nJl...f1Sl1lJL CS/

01 ~ 0 0 ~~_O~~~~~~~~~~~~~i~~ __ ~ __ ~~ ______ ~ ____ __

00 TRI·STATE • =\.....:--'1 I+--te/W

SK I I I I I I lrULrU1Sl1lJL cs / + -I- CHECK STATUS

DO TRI·STATE • =\.....:~

I' te/W '1 TUOf5497·9

~ 3" 5" ce c iii" ce Ql 3 en '0 o ~ 5' c: (I)

.9:

I S617dOO/917£601N N

Il) 0) ~ c.. o o -.. w CD ~ ~ 0)

o :E z


NMC9346E/COP3951024-Bit Serial Electrically Erasable Programmable Memory (5V Only)

General Description The NMC9346E/COP395 is a 1024-bit non-volatile, sequential E2PROM, fabricated· using advanced N-channel E2PROM technology_ It is an external memory with the 1024 bits of read/write memory divided into 64 registers of 16 bits each. Each register can be serially read or written by a COP400 controller, or a standard microprocessor. Written information is stored in a floating gate cell until updated by an erase and write cycle. The NMC9346E/COP395 has been designed for applications requiring up to 104 erase/write cycles per register. A power-down mode is provided by CS to -reduce power consumption by 75 percent.

Block and Connection Diagrams Serial E2PROM

Vcc-GND-

01-1-+-+-+----+-----.

CS-;---------~

SK-------------------~

INSTRUCTION DECODE.

CONTROL. AND CLOCK GENERATOR

Features • Low cost • Single supply read/write~erase operations (5V ± 10%)

• TTL compatible • 64 x 16 serial read/write memory

• MICROWIRE™ compatible serial 110 • Simple interfacing

• Low standby power • Non-volatile erase and write

• ReJl~ble flo~ting gate technology

• SelHimed programming cycle

• Device status signal during programming

DO

TLlDI5582·1

Dual·ln-Line Package

CS

SK

01

DO

Order Number NMC9346NE NS Package Number NOSE

Pin Names

CS Chip Select

SK Serial Data Clock

01 DO

Vee GND

NC

Serial Data Input

Serial Data Output

Power Supply

Ground

Not Connected

7-18

Absolute Maximum Ratings (Note 1) \

Voltage RelativetoGND I

+6Vto -0.3V Ambient Storage Temperature Ambient Operating Temperature with Data Retention - 65°C to + 125°C

NMC9346E/COP395 - 40'C to + 85'C Lead Temperature (Soldering, 10 seconds) 3QO"C

DC and AC Electrical Characteristics - 40'C - TA:s 85"C, Vee = SV ± 10% unless specified


Vee Operating Voltage 4.S S.S V

leel Operating Current Vce =5.5V, CS=1, SK= 1 12 mA

PIE Operating Current Vce=S.SV 12 mA

ICC2 Standby Current Vce=S.SV, CS =0 3 mA

Input Voltage Levels VIL -0.1 0.8 V VIH 2.0 Vec +1 V

Output Voltage Levels VOL IOL=2.1 mA 0.4 V VOH 10H= -400p.A 2.4 V

III Input Leakage Current VIN =S.5V 10 p.A

ILO Output Leakage Current VouT=5.5V, CS =0 10 p.A


SK Duty Cycle 25 75 %

Inputs

tess CS 0.2 P.s tesH 0 p's tOIS 01 0.4 P.s tOIH 0.4 p's

Output CL= 100 pF tpd1 DO VOL = 0.8V, VOH = 2.0V 2 p's tpdO VIL = 0.45V, VIH = 2.40V 2 p's

tE/W Self·Timed Program 10 ms Cycle

tes Min CS Low Time 1 ",s

tsv Rising Edge of CS to CL = 100 pF 1 p's Status Valid

tOH. t1H Falling Edge of CS 0.4 ",s to DO TRI·STATE~

Note 1: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional opera· tion of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Instruction Set for NMC9346E/COP395

Instruction SB OpCode Address Data Comments

READ 1 10 A5A4A3A2A1AO Read register A5A4A3A2A1AO

WRITE 1 01 ASA4A3A2A1AO 015-00 Write register A5A4A3A2A1AO

ERASE 1 11 A5A4A3A2A1AO Erase register A5A4A3A2A1AO

EWEN 1 00 11xxxx Erase/write enable

EWDS 1 00 ooxxxx Erase/write disable

ERAL 1 00 10xxxx Erase all registers NMC9346E1COP395 has 6 instructions as shown. Note that the MSB of any given instruction Is a "1" and Is viewed as a start bit In the Interface sequence. The next 8 bits carry the op code and the 6-blt address for 1 of 64, l6-blt registers.

7-19

z 3: o CD

~ en m ....... o o " f8 en

It) 0) C") D.. o o ....... w co ~ 0)

o :E z

Functional Description The NMC9346E/COP395 is a small peripheral memory In-

.,tended for,use with COPSTM controllers and,other nonvolatile memory applications.lts.organizat,ion is sixty-four registers and each register is sixteen bits wide. The input and output pins are controlled by separate serial formats. Six 9·bit instructions can be executed. The instruction format has a logicai '1' as a start bit, two bits as an op code, and six bits of address. The programming cycle is selftimed, with the data out (DO) pin indicating the ready/busy status of the chip. The on-chip programming voltage generator allows the user to use a single power supply (V cd. It only generates high voltage during the programming modes (write, erase, chip erase) to prevent spurious programming during other modes. The DO pin is valid as data out during the read mode, and if initiated, as a ready/busy' status Indicator during a programming cycle. During all other modes the DO pin is in TRI-STATE, eliminating bus contention.

READ

The read instruction is the only instruction which outputs serial data on the DO pin. After a read instruction is received, the instruction and address are decoded, followed by data transfer, from the memory register into a 16-bit serJal-out shift register. A dummy bit (logical '0') precedes the 16-bit data output string. The output data changes during the'high states of the system clock.


When Vce is applied to the part'it powers up in the programming disable (EWDS) state, programming must be preceded by a programming enable (EWEN) instruction. Programming remains enabled until a programming disable (EWDS) instruction is executed or Vee is removed from the part. The programming disable instruction is provided to protect against accidental data disturb. Execution of a read instruction is independent of both EWEN 'and EWDS instructions.

ERASE

Like most E2PROMs, the register must first be erased (all bits set to logical '1') before the register can be written (certain bits set to logical '0'). After an erase instruction Is input, CS is dropped low. This failing edge of CS determines the start of the self-timed programming cycle. If CS is brought high subsequently (after observing the tes specification)" the DO pin will indicate the ready/busy status of the chip. The DO pin will go low if the chip is still

-programming. The DO pin will go high when all bits of the register at the address specified in' the instruction have been set to a logical '1' . The part is now ready for the next instruction sequence. '

WRITE

The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data' (DO) is put on the data in (01) pin CS must be brought low before the next rising edge of the SK ciock. This falling edge of CS initiates the self-timed programming cycle. Like all programming modes, DO indicates the ready/busy status of the chip if CS is brought high after a minimum of 1 P.s (tes). DO = logical '0' indicates that programming is still in progress. DO = logical '1 ' indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. The register to be written into must have been previously erased.

CHIP ERASE

Entire chip erasing is provided for ease of programming. Erasing the chip means that all registers in the memory array have each bit set to a logical '1'. Each register is then ready fora write instruction. The chip erase cycle is identical to the erase cycle except for the different op code.

Note1: es must be brought low for a minimum of 1"s (tesl between con· secutive InstrUction cycles.

Note 2: During a programming mode (write, erase, chip erase), SK clock is only needed while the actual instruction, i.e., start bit, op code, address and data, is being Input. It can remain deactivated during the self·tlmed programming cycle and status check.

Timing Diagrams Synchronous Data TIming

SK

DI

VrL

cs VrL

DO VOL ____ ...:.., ____ ..1

*Thls Is the minimum SK period.

7-20

'" ~

READ

WRITE

Instruction Timing

SK u-u-u-u-tJU1Iln...n...rLr CS /

DI ~ ~~--------------.. ----------------~II~I--------------------

TlID/5582-4

SK u-u-tJ1rLfUUU-UU-U-CS / CHECK STATUS

DI ~

DD TRI-STATE "\---'1

SK

STANDBY

'lH

TRI-STATE

TL/D/5582·5

EWEN J cs / EWDS 1 \, STANDBY

DI~O I X X1_~, ENABLE=11

DISABLE =00 TUD/5582-6

-I 3" S" ce c iii" ce Dl 3 o o o a 5-c: CD S

II S6EdOO/39tJE60IN N

ERASE

.....a

~

ERAL

N MC9346E/COP395

Instruction Timing

SK lIU1JLJLIl.JI...fUl. CS / CHECK STATUS STANDBY

DI ~ ~~~~----~I~.--~!~I----------"---------

DO TRI-STATE

SK

cs /

hH TRI-STATE

TLlDf5582·7

n.n..r1..fUlIl

DI -f7\ 0 D f7\.~_O~_",""""""""""""""''''''''''~~''''''''''~,,"A.I!~ -+--+--.f.~----+---DO

TRI-STATE

-t 3" S" ce c iii" ce D; 3 en o o a 3' c: CD .e,

~National ~ Semiconductor NMC281616k (2k x 8) Electrically Erasable PROM

Max Access/Current NMC2816·25 NMC2816·35 NMC2816-45

Max Access Time (ns) 250

Max Active Current (mA) 110

Max Standby Current (mA) 50

General Description The NMC2B16 is a 16,3B4-bit electrically erasable and programmable read-only memory (E2PROM) fabricated using National's high speed, low power, N-channel double silicon gate technology. The electrical erase/write capability of the NMC2B16 makes it ideal fora wide variety of applications requiring in-system, non-volatile erase and write.

The device operates from a 5V power supply in the read mode and, with its very fast read access speed, is compatible with high performance microprocessors.

350

110

50

Features • 204B x 8 organization

• Fuliy static • Reliable floating gate technology

• Very fast access time 250 ns max (NMC2816-25) 350 ns max (NMC2816-35) 450 ns max (NMC2B16-45)

• Single byte erase/write capability

• 10 ms byte erase/write time • Chip erase time of 10 ms

450

110

50

The NMC2B16 is deselected when pin 18 is high and is automatically placed in the standby mode. This mode provides a 52% reduction in power with no increase in access time. The NMC2B16 also has an output enable control to eliminate bus contention in a system environment.

• Conforms to JEDEC byte-wide family standard

• Microprocessor compatible architecture

• LQw power dissipation

The NMC2B16 can be easily erased and reprogrammed in a byte-by-byte mode and the entire memory array erased in a chip erase mode. Byte erase mode is identical to byte write mode, with all data inputs at logic ones (TTL high).

610 mW max (active power ICC + IPP) 295 mW max (standby power ICC + IPP)


VCC~

GND 0---+ VPP~

AO-A1D ADDRESS

INPUTS

Pin Names


AND E/W LOGIC

y DECODER

X DECODER

AO-A10 CE OE

Addresses Chip Enable Output Enable

FIGURE 1

DATA INPUTSIOUTPUTS 10/00-17/07

INPUTI OUTPUT

BUFFERS

Y GATING

16,384-81T CELL MATRIX

Data Outputs Data Inputs Program Voltage

7·23

A7

A6

AS

A4

A3

A2

A1

AD

10/00

Dual·ln·Llne Package

NMC2816 E2PROM

TOP VIEW TLI017513-2

FIGURE 2

Order Number NMC2816J NS Package Number J24A

co ,.... co C'I o :E z

Absolute Maximum Ratings Operating Conditions Temperature Under Bias -10°C to + SO°C Temperature Range O°Cto + 70°C Storage Temperature -S5°Cto +125°C VCC Power Supply (Notes 2 and 3) 5V±5%

All Input or Output Voltages with +SVto -0.3V Respect to Ground

VPP Supply Voltage with Respect + 22.5V to - 0.3V to Ground During Program

Maximum Duration of VPP Supply at 22V 24Hrs During ElW Inhibit

Maximum Duration of VPP Supply at 22V 15ms During Write/Erase Programming (Note 2)


Note: Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is. not implied. Exposure to abo solute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics TA = O°C to 70°C, VCC = 5V ± 5% (Notes 2 and 3)

Symbol Parameter Conditions Min Typ

Max Units (Note 1)

READ OPERATION

III Input Leakage Current VIN =5.25V 10 p.A

ILO Output Leakage Current VOUT=5.25V 10 p.A I

ICC2 VCC Current (Active) ,OE=CE=VIL 50 110 rnA

ICC1 VCC Current (Standby) CE=VIH 10 50 rnA

IPP(R) VPP Current (Read) VPP = SV, CE = VIH or VIL 1 5 rnA·

VIL Input Low Voltage -0.1 O.S V

VIH Input High Voltage 2.0 VCC+1 V

VOL Output Low Voltage IOL=2.1 rnA 0.45 V

VOH Output High Voltage IOH= -400p.A 2.4 V

VPP Read Voltage 4 S V

WRITE OPERATION

VPP Write/Erase Voltage 20 21 22 V

IPP(W) VPP Current (Write/Erase) OE = VIH, CE = VIL, VPP = 22V S 15 rnA

VOE OE Voltage (Chip Erase) IOEs10 p.A 9 15 V

IPP(I) VPP Current (Inhibit) CE = VIH, VPP = 22V 2 5 rnA

IPP(C) VPP Current (Chip Erase) OE = VOE, CE = VIL, VPP = 22V 2 5 rnA



Max Units (Note 1)

CIN Input Capacitance VIN=OV 5 10 pF


CVCC VCC Capacitance OE=CE=VIH SOO pF

CVPP VPP Capacitance OE=CE=VIH SO pF

AC Test Conditions Output Load 1 TTLgateand CL= 100 pF Input Pulse Levels 0.45Vt02.4V Timing Measurement Reference Level

Input 1Vand2V Output 0.SVand2V

7-24

Read Mode AC Electrical Characteristics TA = O°C to 70°C, VCC = 5V ± 5% (Notes 2 and 3)

NMC2816·25 NMC2816·35 NMC2816·45 Symbol Parameter Conditions

Min Typ

Max Min Typ

Max Min Typ

Max Units

(Note 1) (Note 1) (Note 1)

tACC Address to Output CE=OE=VIL 250 350 450 ns Delay

tCE CE to Output Delay OE=VIL 250 350 450 ns

tOE Output Enable to CE=VIL 10 100 10 120 10 120 ns Output Delay

tOF Output Disable to CE=OE=VIL 0 80 0 80 0 100 ns Output Float (Note 9)

tOH Output Hold from CE=OE=VIL 0 0 0 ns Addresses, CE or OE Whichever Occurred First

Switching Time Waveforms (Note 6) Read

------- C ADDRESSES ~ ADDRESSES VALID

--------

CE !;-..,

I-tce-~ v---

-------:}: IOF (NOTE 81 (NOTE 9)

~ -------

OUTPUT VALID OUTPUT

---------lAcc-- TU017513-3

Write Mode AC Electrical Characteristics TA = O°C to 70°C, VCC = 5V ± 5% (Notes 2 and 3)


tAs Address Set·Up Time 150 ns

tAH Address Hold Time 50 ns

tcs CE to VPP Set·Up Time 150 ns

tos Data Set·Up Time OE=VIH 0 ns

tOH Data Hold Time OE=VIH 50 ns

twp Write Pulse Width (Note 4) 9 10 15 ms'

tWA Write Recovery Time 50 ns

tos Chip Clear Set·Up Time 0 ns

tOH Chip Clear Hold Time 0 ns

tPAC VPP RC Time Constant 450 600 750 p's

tPFT VPP Fall Time (Note 5) 100 p's

taos Byte EraselWrite Set·Up Time (Note 12) 0 ns

taoH Byte EraselWrite Hold Time (Note 12) 0 ns

tCH Chip Enable High Time 1 p's

Note 1: This parameter Is only sampled and not 100% tested. Note 2: To prevent spurious device erasure or write. VCC must be applied simultaneously or before 21V application of VPP. VPP cannot be driven to 21V without previously applying VCC. Note 3: vec must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage to the device it must not be Inserted into or removed from a board with power applied. Note 4: Adherence to twp specification is important to device reliability. Note 5: To allow immediate read verify capability. VPP can be driven low In less than 50 ns.

7·25

co ,... co N o :E z

Switching Time Waveforms (Note 6)

Byte Erase and Byte Write Programming Cycle (Notes 7 and 12)

CE Yll

YIH ADDRESS

Yll

YIH DATA IN

Yll

YIH iiI

Yll

ZOY-ZZY

YPP

4V-6V

VPP (4V-6V)

lPRe tpH (NOTE 10) (NOTE 5)-

I-----twp-----l

Chip Erase (Note 11)

VIH-------"I

tOH

Note 6: All times shown In parentheses are minimum times and are ns unless otherwise specified.

TUOn513-4

TLJOn513-5

Note 7: Prior to a data write, an erase operation must be performed. For byte erase, data In = VIH, and for chip erase, data in = don't care.

Note 6: ~ may be delayed up to 230 ns after falling edge of CEwithout impact on tCE for NMC2816-35.

Note 9: tDF Is specified from .DE or CE, whichever occurs first.

Note 10: The rising edge of VPP must follow an exponential waveform. That waveform's time constant is specified as tpRC'

Note 11: In the chip erase mode DIN = don't care.

Note 12: In byte erase or write mode, OE must be at VIH (logic 1 state).

Note 13: CE = VIH places the chip in a low power standby condition and must be applied for a minimum time of tCH before the start of any byte pro-gramming cycle. '

Device Operation The NMC2816 hassix modes of operation, listed in Table L All operational modes are designed to provide maximum microprocessor compatibility and system consistency. The device pinout is a part of the JEDEC approved bytewide non-volatile memory family, allowing appropriate and cost-effective density and functionality, upgrades.

All control inputs are TTL compatible with the exception of chip erase. The VPP voltage must be pulsed to 21V duro ing write and erase, and held at 5V during the other two modes_

7·26

TABLE I. Mode Selection Vee = 5V :!: 10%

~ CE ·OE vpp Inputsl

Mode (18) (20) (21) Outputs

Read VIL -VIL 4V t06V DOUr Standby VIH Don't Care 4V t06V Hi-Z Byte Erase VIL VIH 20V t022V DIN=VIH Byte Write VIL VIH 20V to 22V DIN Chip Erase VIL 9V to 15V 20V to 22V ,DIN= (Note 11) Don't Care E/W Inhibit VIH Don't Care 4V t022V Hi-Z

Device Operation (Continued)

READ MODE

Both CE and OE must be at logic low levels to obtain infor· mation from the device. Chip enable (CE) is the power con· trol pin and could be used for device selection. The output enable (OE) pin serves to gate internal data to the output pins. Assuming that the address inputs are stable, ad· dress access time (tACe) is equal to the delay from CE to output (t CE). Data is available at the outputs after a time delay of tOE, assuming that CE has been low and ad· dresses have been stable for at least tACC-tOE.

CHIP ERASE MODE

Should one wish to erase the entire NMC2816 array at once, the device offers a chip erase function. When the chip erase function is performed, all2k bytes are returned to a logic 1 (FF) state.

The NMC2816's chip erase function is engaged when the output enable (OE) pin is raised above 9V. When OE is greater than 9V and CE and VPP are in the normal write mode, the entire array is erased. This chip erase function takes approximately 10 ms. The data input pins are don't care during this time to allow for ease in chip erase. Figure 3 is an example for an OE control switch.

VPP PULSE

The shape of the VPP pulse is important in ensuring long term reliability and operating characteristics. VPP must

rise to 21V through an RC waveform (exponential). The tpRC specification has been designed to accommodate changes of RC due to temperature variations.

Figure 4 shows an example for a VPP switch design, useful where programming will occur over the specified temperature and operating voltage conditions.

WRITE MODE

The NMC2816 is erased and reprogrammed electrically rather than optically, as opposed to EPROMs which reo quire UV light. The device offers dramatic flexibility because both byte (single location) and chip erase are possible.

To write a particular location, that byte must be erased prior to a data write. Erasing is accomplished by applying logic 1 (TTL high) inputs to all 8 data input pins, lowering CE, and applying a 21V programming signal to VPP. The OE pin must be equal to VIH during byte erase and write operations. The programming pulse width must be a mini· mum of 9 ms, and a maximum of 15 ms. The rising edge of VPP must conform to the RC time constant specified pre· vious Iy. Once the loca ti on has been erased, the same oper· ation is. repeated for a data write. The input pins in this case reflect the byte that is to be stored. CE must go from VIH to VIL at the beginning of a byte erase/write cycle and must be held high for a minimum of tCH between E/W cycles.

>------4It----.() TO fiE PIN OF NMC2816

CHIP ERASE

24V 10k

FIGURE 3. OE Chip Erase Control

TUD17513-6

24V.--------~--~--------~----------------------~

VPP CONTROL (WRITE/iiii)

Note 1: 5k is 21V fine adjust.

Note 2: Resistors are 1/4W.

1N914

FIGURE 4. Operational Amplifier VPP Switch Design

7·27

5V

1N914

TO "'---4~"'" VPP PIN

OF NMC2816

TUD17513-7

CD ,... CO C'\I o :E z


A characteristic of all E2PRDMs is that the total number of erase/write cycles is not unlimited. The NMC2816· has been designed to meet applications requiring up to 1 X 104

erase/write cycles per byte. The erase/write cycling characteristic is completely byte independent. Adjacent bytes are not affected during erase/write cycling.

Because the device is designed to be written in system, all data sheet specifications (including write and erase operations) hold over the full operating temperature range (O°C ,to 70°C).

OUTPUT OR·TYING

Because NMC2816s are usually used in larger memoryar· rays, a 2-line control function is provided that accommo· dates thisuse of multiple memory connections. The 2-line control function allows low power dissipation (by dese· lecting unused devices), and the removal of bus conten· tion from the system environment.

7-28

To most effectively use these two control lines, it is recom· mended that cr (pin 18) be decoded from addresses as the primary device selection function. DE (pin 20) should be made a common connection to all devices in system, and connected to the RD line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.

STANDBY MODE

The NMC2816 has a standby mode which reduces active power dissipation by 52% from 610 mW to 295 mW (ICC + IPP). The NMC2816 is placed in the standby mode by applying a TTL high Signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the DE input.

~National ~ Semiconductor NMC2816M 16k (2k x 8) Electrically Erasable PROM

Max Access/Current NMC2816M·25 NMC2816M·35 NMC2816M·45


Max Active Current (rnA) 140

Max Standby Current (rnA) 60

General Description The NMC2816M is a 16,384-bit electrically erasable and programmable read-only memory (E2PROM) fabricated using National's high speed, low power, N-channel double silicon gate technology. The electrical erase/write capability of the NMC2816M makes it ideal for a wide variety of applications requiring in-system, non-volatile erase and write.


350

140

60

Features • 2048 x 8 organization

• Fully static • Reliable floating gate technology

• Very fast access time 250 ns max (NMC2816M-25) 350 ns max (NMC2816M-35) 450 ns max (NMC2816M-45)


• 10 ms byte erase/write time

• Chip erase time of 10 ms

450

140

60

The NMC2816M is deselected when pin 18 is high and is automatically placed in the standby mode. This mode provides a55% reduction in powerwith no increase in access time. The NMC2816M also has an output enable control to eliminate bus contention in a system environment.

• Conforms to J EDEC byte-wide family standard


• Low power dissipation

The NMC2816M can be easily erased and reprogrammed ina byte-by-byte mode and the entire memory array erased in a chip erase mode. Byte erase mode is identical to byte write mode, with all data inputs at logic ones (TTL high).


800 mW max (active power ICC + IPP) 360 mW max (standby power ICC + IPP)


DATA INPUTS/OUTPUTS A7

VCC~

GND 0--+ VPP~


AND E/W lOGIC

Y DECODER

-AO-Al0 ADDRESS

INPUTS X

DECODER

Pin Names

•

FIGURE 1

10/00-17/07

INPUT/ OUTPUT BUFFERS

Y GATING

16,384-BIT CEll MATRIX

A6

AS

A4

A3

A2

Al

AO

la/Do

NMC2B16M E2PROM

TOP VIEW

FIGURE 2

24 VCC

23 A8

22 A9

21 VPP

20 DE

19 Al0

17/07

Is/Os

TUD/5193-2

AO-A10

CE

OE

Addresses

Chip Enable

Output Enable

Data Outputs

Data Inputs

Program Voltage Order Number NMC2816MJ NS Package Number J24A

7-29

:E co ,... co N o :E z

Absolute Maximum Ratings Operating Conditions Temperature Under Bias - 6SoC to + 13SoC Temperature Range -SSOCto + 12SoC

Storage Temperature - 6SoC to + 12SoC VCC Power Supply (Notes 2 and 3) SV±10%

Alii nput or Output Voltages with +6Vto -0.3V Respect to Ground

VPP Supply Voltage with Respect + 22.SV to - 0.3V to Ground During Program

Maximum Duration of VPP Supply at 22V 24Hrs During E/W Inhibit

Maximum Duration of VPP Supply at 22V 1Sms During Write/Erase Programming (Note 2)


Note: Stresses above those listed under "Absolute Max,imum Ratings" may cause permanent'damage to the device. Thls,ls a stress rating only and functional operation of the device at these or any other conditions above those Indicated In the operational sections of this specification Is not implied. Exposure to abo solute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics TA = - SSOC to + 12SOC, VCC = SV ± 10% (Notes 2 and 3)

Symbol f!arameter Conditions Min Typ

Max Units (Note 1)

READ OPERATION

III Input Leakage Current VIN =S.SOV 10 Jl-A

ILO Output Leakage Current VOUT=S.SOV 10 Jl-A

ICC2 VCC Current (Active) OE=CE=VIL 6S 140 rnA

ICC1 VCC Current (Standby) CE=VIH 12 60 rnA

IPP(R) VPP Current (Read) VPP = 6V, CE = VIH or VIL 1 S rnA

VIL Input Low Voltage -0.1 O.B V


VOL Output Low Voltage IOL=2.1 rnA 0.45 V

VOH Output High Voltage IOH= -400Jl-A 2.4 V

VPP Read Voltage ' 4 6 V

WRITE OPERATION


IPP(W) VPP Current (Write/Erase) OE = VIH, CE = VIL, VPP = 22V 6 15 rnA

VOE OE Voltage (Chip Erase) IOE~10JLA 9 15 V

IPP(I) VPP Current (Inhibit) CE ~ VIH, VPP = 22V 2 5 rnA

IPP(C) VPP Current (Chip Erase) OE = VOE, CE = VIL, VPP = 22V 2 5 rnA

Capacitance TA ~ 2SOC, f = 1 MHz (Note 1)


Max Units (Note 1)



CVCC VCC Capacitance OE=CE=VIH 500 pF

CVPP VPP Capacitance OE=CE=VIH 50 pF

AC Test Conditions Output Load 1 TTLgateandCL=100pF I

Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level

Input 1Vand2V Output 0.BVand2V

7·30

Read Mode AC Electrical Characteristics TA = - 55·C to + 125·C, VCC = 5V ± 10% (Notes 2 and 3)

NMC2816M·25 NMC2816M·35 NMC2816M·45

,mbol Parameter Conditions Typ Max Min

Typ Max Min

Typ Max

Units Min

(Note 1) (Note 1) (Note 1)

tACC Address to Output CE=OE=VIL 250 350 450 ns

Delay


t6E Output Enable to CE=VIL 10 120 10 140 10 140 ns

Output Delay

tOF Output Disable to CE=OE=VIL 0 100 0 100 0 100 ns

Output Float (Note 9)

tOH Output Hold from CE=OE=VIL 0 0 0 ns

Addresses, CE or OE

Whichever Occurred

First

Switching Time Waveforms (Note 6) Read

VIH ~<-

-------~K ADDRESSES ADDRESSES VALID

VIL ----------tACC--

VIH

\ / CE VIL ------ ")

1·-lfE-VIH

iiE \ f VIL ------tOE)-i-- tt:' (NOTE 8) (NOTE 9)

VOH

~ -------

OUTPUT VALID OUTPUT

VOL -------[--tOH - TU015193-3

Write Mode AC Electrical Characteristics TA= -55·C to + 125·C, VCC=5V± 10% (Notes 2 and 3)


tAS Address Set-Up Time 150 ns


tcs CE to VPP Set-Up Time 150 ns

tos Data Set-Up Time OE=VIH 0 ns


twp Write Pulse Width (Note 4) 9 10 15 ms

tWR Write Recovery Time 50 ns

tos Chip Clear Set-Up Time 0 ns


tpRC VPP RC Time Constant 450 600 750 /lS

tpFT Vpp Fall Time (Note 5) 100 /lS

tsos Byte Erase/Write Set·Up Time (Note 12) 0 ns

tSOH Byte Erase/Write Hold Time (Note 12) 0 ns

tCH Chip Enable High Time 1 /lS

Not. 1: This parameter is only sampled and not 100% tested~ Not. 2: To prevent spurious device erasure or write, VCC must be applied simultaneously or before 21V application of VPP. VPP cannot be driven to 21V without previously applying VCC. Not.3: VCC must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage to the device it must not be. Inserted Into or removed from a board with power applied. Not.4: Adherence to twp speCification is important to device reliability. Not. 5: To allow immediate read verify capability, VPP can be driven low in less than 50 ns.

7·31

:E CD ,... CO N o :E z

Switching Time Waveforms (Note 6)

Byte Erase and Byte Write Programming Cycle (Notes 7 and 12)

VIH CE

VIL -(NO~:13)-~-ICS-

VIH ADDRESS

VIL )( -lAs-

VIH DATA IN

VIL )( -Ios-

VIH liE

VIL

J ; leos -(NOTE 12)-

20V-22V

YPP

- I_ IPRC !PH -(NOTE 10) (NOTES)-

V ~ 4V-6Y twp


IpRe -(NOTE 10) -tPFT (NOTE 5)

VIH------""\

CE VIL--------------~-_+~-------~_+~

20V-22V -------------------+-;------"" VPP

4V-6V ---------~

V~--------------~r_~--------------~

VIH -------""1

Note 6: All times shown in parentheses are minimum times and are ns unless otherwise specified.

-twR-f

-IAH-e -IOH-e -IBOH-L

-

TUD/519J.4

TUD/5193-5

Note 7: Prior 10 a data write, an erase operation musl be performed. For byte erase, data in = VIH, and for chip erase, data in = don't care.

Note 8: OE may be delayed up to 210 ns after falling edge of CE without impact on tCE for NMC2816M-35.

Note 9: tDF is specified from DE or CE, whichever occurs first.

Note 10: The rising edge of VPP must follow an exponential waveform. That waveform's.time constant is specified as tpRC.


Note 12: In byte erase or write mode, 5E must be at VIH (logic 1 state).

Note 13: CE = VIH places the chip in a low power standby condition and must be applied for a minimum time of tCH before the start of any byte programming cycle.

Device Operation The NMC2816M has six modes of operation, listed in Table I. All operational modes are designed to provide maximum microprocessor compatibility and system consistency. The

. device pinout is a part of the JEDEC approved bytewide non-volatile memory family, allowing appropriate and costeffective density and functionality upgrades.

All control inputs are TTL compatible with the exception of chip erase. The VPP voltage must be pulsed to 21V duro ing write and erase, and held at 5V during the other two modes.

7·32

TABLE I. Mode Selection Vcc= 5V ~ 10%

.~ CE OE vpp Inputsl Mode (18) (20) (21) Outputs

Read VIL VIL 4V t06V DOUr Standby VIH Don't Care 4V t06V Hi·Z Byte Erase VIL VIH 20V t022V DIN=VIH Byte Write VIL VIH 20V t022V DIN Chip Erase VIL 9V to 15V 20V t022V DIN= (Note 11) Don't Care ElW Inhibit VIH Don't Care 4V to 22V Hi·Z


READ MODE

Both CE and OE must be at logic low levels to obtain infor· matlon from the device. Chip enable (CE) is the power con· trol pin and could be used for device selection. The output enable (OE) pin serves to gate internal data to the output pins. Assuming that the address inputs are stable, ad· dress access time (tACe) is equal to the delay from CE to output (tCE)' Data is available at the outputs after a time delay of tOE, assuming that CE has been low and ad· dresses have been stabie for at least tACC-tOE'

CHIP ERASE MODE

Shouid one wish to erase the entire NMC2816Marray at once, the device offers a chip erase function. When the chip erase function is performed, all 2k bytes are returned to a logic 1 (FF) state. ..

The NMC2816M's chip erase function is engaged when the output enable (OE) pin is raised above 9V. When OE is greater than 9V and CE and VPP are in the normal write mode, the entire array is erased. This chip erase function takes approximately 10 ms. The data input pins are don't care during this time to allow for ease in chip erase. Figure 3 is an example for an OE control switch.

VPP PULSE

The shape of the VPP pulse is important in ensuring long term reliability and operating characteristics. VPP must

rise to 21V through an RC waveform (exponential). The tpRC specification has been designed to accornmodate changes of RC due to temperature variations.

Figure 4 shows an example for a VPP switch design, useful where programming will occur overthe specified temperature and operating voltage conditions.

WRITE MODE

The NMC2816M is erased and reprogrammed .electrically rather than optically, as opposed to EPROMs which reo quire UV light. The device offers dramatic flexibility because both byte (single location) and chip erase are possible.

To write a particular location, that byte must be erased prior to a data write. Erasing is accomplished by applying logic 1 (TTL high) inputs to all 8 data input pins, lowering CE, and applying a 21V programming signal to VPP. The OE pin must be equal to VIH during byte erase and write operations. The programming pulse width must be a mini· mum of 9 ms, and a maximum of 15 ms. The rising edge of VPP must conform to the RC time constant specified pre· viously. Once the location has been erased, the same oper· ation is repeated for a data write. The input pins in this case reflect the byte that is to be stored. CE must go from VIH to VIL at the peginning of a byte erase/write cycle and must be held high for a minimum of tCH between E/W cycles.

>----.... ---0 TO fiE PIN OF NMC2816M

CHIP ERASE

24Y 10k ...... YrJ\t-05Y

1.2k ... """'.,.".-<l24Y

1.2k

TLlD/5193-6


24Y~----------~--e-------~~-----------------~

1N4747A

YPP CONTROL (WRITE/iiii)

Note 1: 5k is 21V fine adjust.

Note 2: Resistors are 1/4W.

10k

3.9k

12k

0.05/LF

T 1N914

FIGURE 4. Operational Amplifier VPP Switch Design

7·33

5Y

1N914

TO ... --4 ........ VPP PIN

OF NMC2816M

TLlD/S193-7

:e CD ,... CO N o :e z


·A characteristic of all E2PROMs Is that the total number of erase/write cycles is not unlimited. The NMC2816M has been designed to meet applications requiring up to 1 x 10~. erase/write cycles per byte. The erase/write cycling characteristic is completely byte independent. Adjacent bytes are not affected during erase/write cycling.

Because the device is designed to be written in system, all data sheet specifications (including write and erase operations) hold over the full operating temperature range (- 55°C to + 125°C).

OUTPUT OR·TYING

Because NMC2816Ms are usually used In larger memory arrays, a 2·line control function is provided that accommodates this use of muitiple memory connections. The 2-line control function allows low power dissipation (by deselecting unused devices), and the removal of bus contention from the system environment.

7·34

To most effectively use these two control lines, it is recom· mended that CE (pin 18) be decoded from addresses as the primary device selection function. OE (pin 20) should be made a common connection to all devices in system, and connected to the RD line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. .

STANDBY MODE

The NMC2816M has a standby mode which reduces active power dissipation !ly 55% from 800 mW to 360 mW. The NMC2816M Is placed In the standby mode by applying a TTL high Signal to the CE input. When in the standby mode, the outputs are In a high impedance state, independent of the OE Input.

~National . ~ Semiconductor NMC971616k (2k x 8) Electrically Erasable PROM

Max Access/Current NMC9716·25


Max Active Current (mA) 110

Max Standby Current (mA) 50

General Description The NMC9716 is a 16,384-bit electrically erasable and pro· grammable read·only memory (E2PROM) fabricated using National's high speed, low power, N·channel double slli· con gate technology. The electrical erase/write capability of the NMC9716 makes It Ideal for a wide variety of appli· cations requiring In·system, non·volatile erase and write.

The NMC9716 is pin and functionally compatible with the NMC2816 E2PROM, with the added system feature of eras· lng/writing with a 5V TTL pulse on chip enable (CE), while the VPP is held at 21V. The erase/write cycle is very similar to the industry standard 2716 EPROM programming cycle.

The device operates from a 5V power supply in the read mode and, with its very fast read access speed, is com· patible with high performance microprocessors.

The NMC9716 is deselected when CE input is high and is automatically placed in the standby mode. This mode pro· vides a 52% reduction in power with no increase in access time. The NMC9716 also has an output enable control to eliminate bus contention in a system environment.


NMC9716·35 NMC9716-45

350 450

110 110

50 50

The NMC9716 can be easily erased and reprogrammed in a byte·by-byte mode and the entire memory array can be erased with a single programming pulse in the chip erase mode. Byte erase is identical to byte write, with all inputs at logic one (TTL high).

Features • Erase/write with a 5V TTL pulse or a 21 V pulse • Pin and functionally compatible with the NMC2816

• No rise time r~striction on erase/write pulse

• 2048 x 8 organization • Conforms to JEDEC byte·wlde family standard




• 10 ms chip erase mode

• Low power dissipation 610 mW max (active power ICC + IPP) 295 mW max (standby power ICC + IPP)

Dual·ln·Line Package

24 DATA INPUTS/OUTPUTS

A7 VCC

VCCO--. GND D---+ VPP D---+


AND E/W LOGIC

Y OECODER

AD-Al0 ADDRESS

INPUTS X

DECODER

Pin Names

AO-Al0 Addresses 0 0-07 CE Chip Enable 10-17 OE Output Enable VPP

10/00-h/07

ttt!!!!! INPUT/ OUTPUT BUFFERS

Y GATING

16,384·BIT CELL MATRIX

FIGURE 1

Data Outputs

Data Inputs Program Voltage

7·35

A6

A5

A4

A3

A2

Al

AD

10/00

NMC9716 e2PROM

TOP VIEW

FIGURE 2

Order Number NMC9716J NS Package Number J24A

TLlD/5196-2

z 3: o CO ~ ..... 0)

CD ,... r-... CD o :E z

Absolute Maximum Ratings Operating Conditions Temperature Under Bias -10°C to + 80°C Temperature Range O°Cto + 70°C Storage Temperature -65°Cto +125°C VCC Power Supply (Notes 2 and 3) 5V±5% All Input or Output Voltages with +6Vto -0.3V

Respect to Ground VPP Supply Voltage with Respect + 22.5V to - 0.3V

to Ground During Program Maximum Duration of VPP Supply at 22V 24Hrs

During ElW Inhibit Maximum DurationofVPPSupplyat22V 15ms

During Write/Erase Programming (Note 2)

Lead Temperature(Soldering, 10 seconds) 300°C

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress rating only and functional operation of the device at these or any other conditions above those Indicated In the operational sections of this specification Is not implied. Exposure to abo solute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics TA = O°C to 70°C, VCC = 5V ± 5% (Notes 2 and 3)


Max Units (Note 1)

READ OPERATION

III Input Leakage Current VIN=5.25V 10 p.A

ILO Output Leakage Current VOUT=5.25V 10 p.A

ICC2 VCC Current (Active) OE=CE= VIL 50 110 mA

ICC1 VCC Current (Standby) CE=VIH 10 50 mA

IPP(R) VPP Current (Read) ,VPP=6V, CE= VIH or VIL 1 5 mA



VOL Output Low Voltage IOL=2.1 mA 0.45 V

VOH Output High Voltage IOH = -400 p.A 2.4 V

VPP Read Voltage 4 6 V

WRITE OPERATION


IPP(W) VPP Current (Write/Erase) OE=VIH, CEsVIL, VPP=22V 6 15 mA

VOE OE Voltage (Chip Erase) IOEs10p.A 9 15 V

IPP(I) VPP Current (Inhibit) CE = VIH, VPP = 22V 2 5 mA

IPP(C) VPP Current (Chip Erase) OE = VOE, CE = VIL, VPP = 22V 2 5 mA



Max Units (Note 1)





AC Test Conditions Output Load 1 TTL gate and CL = 100 pF Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level

Input Wand2V Output 0.8Vand2V

7-36

Read Mode AC Electrical Characteristics TA = aoc to 7aoc, VCC = 5V ± 5% (Notes 2 and 3)

NMC9716-25 NMC9716·35 NMC9716·45

ymbol Parameter Conditions Typ Typ Typ Units Min (Note 1) Max Min (Note 1) Max Min (Note 1) Max

tAcc Address to Output CE=OE=VIL 250 350 450 ns Delay


tOE Output Enable to CE=VIL 10 100 10 120 10 120 ns Output Delay

tOF Output Disable to CE=OE=VIL a 80 0 80 0 100 ns Output Float (Note 9)

tOH Output Hold from CE=OE=VIL 0 0 0 ns Addresses, CE or OE Whichever Occurred First

Read Waveforms (Note 6)

VIH----

x~ -------

~K ADDRESSES VALID .... t- ...,~' --------

ADDRESSES

VIL-----tAcc-----

1-tc,- If ------ -1'-

VIH-----~

CE VIL-------

\ J( ------

tOEI~_ - tOF (NOTE 8) - c-(NOTE 9)

VIH-------~

VIL-------------------I .... --t-

VOH-------------------r.~ __

OUTPUT Jf@!j

-------~ VALID

~ OUTPUT m -------I-tOH - TUD/5196·3

VOL-------------------~~4-

Note 1: This parameter is only sampled and not 100% tested.

Note 2: To prevent spurious device erasure or write, VCC must be applied simultaneously or before 21V application of VPP. VPP cannot be driven to 21V without previously applying VCC.

Note 3: VCC must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage to the device it must not be inserted into or removed from a board with power applied.

Note 4: Adherence to twp specification is important to device reliability.

Note 5: To allow immediate read verify capability, VPP can be driven low in less than 50 ns.

Note 6: All limes shown in parentheses are minimum times and are ns unless otherwise specified.

Note 7: Prior to a data write, an erase operation must be performed. For a byte erase, data in = VIH, and for chip erase, data in = don't care.

Note 8: OE may be delayed up to 230 ns after falling edge of CE without impact on tCE for NMC9716·35.

Note 9: tOF is specified from OE or CE whichever occurs first.

Note 10: When programming with VPP, the rising edge of VPP can follow a linear or an exponential waveform. That waveform's rise time or time constant is specified as tpRC' There is no restriction on the rising edge of VPP if programming with CEo


Note 12: In byte erase or write mode, OE must be equal to VIH.

Note 13: More than one address location can be erase/written without pulsing VPP between every address.

Note 14: CE = VIH places the chip in a low power standby condition, and must be applied for a minimum timeoftCH before the start of any byte programming cycle.

7·37

Z s: 0 CO ....-.. ~

0)

CD ,... ...... 0')

o :IE z

Write Mode AC Electrical Characteristics TA = O°C to 70°C, vc6 = 5V ± 5% (Notes 2 and 3)




tcs CE Set-Up Time 150 ns

tpR VPP Set-Up Time 0 ns



twp Write Pulse Width (Note 4). 9 10 15 ms




tpRc VPP RC Time Constant (Note 10) 0 750 p's

t pFT VPP Fall Time (Note 5) 100 p's

taos Byte Erase/Write Set-Up Time (Note 12) 0 ns

taoH Byte Erase/Write Hold Time (Note 12) 0 ns

tCH Chip Enable High Time 1 p's

Recommended Erase/Write Waveforms

CE Pulsed (Notes 7, 12 and 13)

VIH

I~J< i: ><= ADDRESSES >1 VIL I

lAS Iwp

VIH I

-1-10 '-1

CE .~ / VIL ---ICH

I IpR

20V-22V

~ vpp 4V-6V

VIH L 'OS

- I-IOH~

: <I >-DATA IN

VIL r---IBOS

____ IBOH

'-VIH

/ II

DE VIL

TLJD/519&-4

Chip Erase Waveforms

CE Pulsed (Note 11)

Iwp

VIH

'" / U VIL

20V-22V r-- IPR

- ~IWR~

vpp 4V-6V

f los ! !

IOH

Q vilE 9V-15V

DE VIH

TLJD/5196-5

7-38

Chip Erase Waveforms (Continued)

- Byte Erase and Byte Write Programming Cycle, VPP Pulsed

VIH-----~

tpRC (NOTE 10) -tPFT

VIL -------11'--+--+-------+--+--.11

20V-22V ----------f--J------"""'" VPP

4V-6V ----------11 V~---------_4----------4--

VIH ----------'1

Alternate Erase/Write Waveforms (NMC2816 compatible) (Note 6)

VPP Pulsed (Note 11)

VIH CE

I

- (NO~; 14) -) ---=,~S~ .,

VIL

VIH

ADDRESS VIL

) -lAs-

VIH DATA IN

VIL ) -Ios-

VIH

DE VIL

20V-22V

VPP

)_ IBOS _ (NOlE 12)

- I_ \pRe (NOl~~~--(NDlEl0)

V 4V-6V

1 twp

TUD/519E>S

-twR-1

-IAH-C -tOH-L -IBOH-L

-~

TUDf519E>7

Device Operation TABLE I. Mode Selection Vcc = 5V :t 5%

The NMC9716 has six modes of operation, listed in Table I. A" operational modes are designed to provide maximum microprocessor compatibility and system consistency. The device pinout is a part of the JEDEC approved bytewide non-volatile memory family, allowing appropriate and cost-effective density and functionality upgrades.

All control inputs are TTL compatible with the exception of chip erase. The VPP voltage must be pulsed to 21V during write and erase, and held at 5V during the other two modes.

7-39

~ Mode

Read Standby

Byte Erase

Byte Write


E/W Inhibit

CE DE (18) (20)

VIL VIL

VIH Don't Care

VIL VIH

VIL VIH

VIL 9V to 15V

VIH Don't Care

vpp Inputs I (21) Outputs

4V to 6V DOUr 4V to 6V Hi-Z

20V to 22V DIN =VIH

20V to 22V DIN 20V to 22V DIN=

Don't Care

4V to 22V Hi-Z

z s: o CD ~ .. en


READ MODE

Both CE and OE must be at logic low levels to obtain information from the device. Chip enable (CE) is the power control pin and could be used for device selection. The output enable (OE) pin serves to gate internal data to the output pins. Assuming that the address inputs are stable, address access time (tACe) is equal to the delay from CE to output (teE). Data is available at the outputs after a time delay of tOE, assuming that CE has been low and addresses have been stable for at least tACC-tOE'

CHIP ERASE MODE

Should one wish to erase the entire NMC9716 array at once, the device offers a chip erase function. When the chip erase function is performed, all 2k bytes are returned to a logic 1 (FF) state.

The NMC9716's chip erase function is engaged when the output enable (OE) pin is raised above 9V. When OE is greater than 9V and CE and VPP are in the normal write mode, the entire array is erased. This chip erase function takes approximately 10 ms. The data input pins are don't care during this time to allow for ease in chip erase. Figure 3 is an example foran OE control switch.

VPP PULSE

If using VPP to write or erase, the shape of the VPP pulse can rise to 21V through an RC waveform (0 IIs-750 liS time constant), such as the NMC2816, or a linear ramp (0 IIs-750 liS). There is no restriction on the rising edge of VPP if using CE to write or erase.


WRITE MODE

The NMC9716 is erased and reprogrammed electrically rather than optically, as opposed to EPROMs which require UV light. The device offers dramatic flexibility because both byte (single location) and chip erase are possible.

To write a particular location, that byte must be erased prior to a data write. Erasing is accomplished by applying logic 1 (TTL high) inputs to all 8 data input pins, lowering CE, and applying a 21V programming Signal to VPP or raising VPP to 21 V and applying a TTL low pulse to CEo The OE pin must be equal to or below VIH during byte erase and write operations. The programming pulse width must be a minimum of 9 ms, and a maximum of 15 ms. Once the location has been erased, the same operation is repeated for a data write. The input pins in this case reflect the byte that is to be stored.

>------..... ---oTO DE PIN OF NMC9716

CHIP ERASE

24V 10k .... ~.,."..-05V

10k

1.2k .... ~.,."..-Q24V

1.2k

FIGURE 3_ OE Chip Erase Control

TUD15196-8

24V ~---....-04""--I TO VPP PIN

I----~t-. OF NMC9716

ERASE/WRITE (WRITE/ROI

R1 120

R2 470

TUD15196-9

FIGURE 4_ VPP Switch Design with Electronic Shutdown for CE Pulsed Erase/Write

7-40


A characteristic of all E2PAOMs I s that the total number of erase/write cycles is not unlimited. The NMC9716 has been designed to meet applications requiring up to 1 X 104

erase/write cycles per byte. The erase/write cycling characteristic is completely byte Independent. Adjacent bytes are not affected during erase/write cycling.

Because the device is designed to be written in-system, ali data sheet specifications (including write and erase operations) hold over the full operating temperature range (O·C to 70·C).

OUTPUT OR-TYING

Because NMC9716s are usualiy used in larger memory arrays, a 2-line control function is provided that accommodates this use of multiple memory connections. The 2-line control function aliows low power dissipation (by deselecting unused devices) and the removal of bus contention from the system environment.

7-41

To most effectively use these two control lines, It Is recommended that CE (pin 18) be decoded from addresses as the primary device selection function. OE (pin 20) should be made a common connection to ali devices In-system, and connected to the AD line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.

STANDBY MODE

The NMC9716 has a standby mode which reduces active power dissipation by 52% from 610 mW to 295· mW (ICC + IPP). The NMC9716 is placed in the standby mode by applying a TTL high signal to the CE input. When in the standby mode, the outputs are In a high Impedance state, independent of the OE input.

~ ~National 5 ~ Semiconductor ~ NMC9716M 16k (2k x 8) Electrically Erasable PROM z

Max Access/Current NMC9716M·25


Max Active Current (rnA) 140

Max Standby Current (rnA) 60

General Description The NMC9716M is a 16,384-bit electrically erasable and programmable read-only memory (E2PROM) fabricated using National's high speed, low power, N-channel double silicOn gate technology. The electrical erase/write capability of the NMC9716M makes it ideal for a wide variety of applications requiring in-system, non-volatile erase and write.

The NMC9716M is pin and functionally compatible with the NMC2816M E2PROM, with the added system feature of erasing/writing with a 5V TTL puls~ on chip enable (CE), while the VPP is held at 21V. The erase/write cycle is very similar to ttie industry standard 2716 EPROM programming cycle.


The NMC9716M is deselected when CEinput is high and is automatically placed in the standby mode. This mode provides a 55% reduction in power with no increase in access time. The N MC9716M also has an output enable control to eliminate bus contention in a system environment.


NMC9716M·35 NMC9716M·45

350 450

140 140

60 60

The NMC9716M can be easily erased and reprogrammed in a byte-by-byte mode and the entire memory array can be erased with a single programming pulse in the chip erase mode. Byte erase is identical to byte write, with all inputs at logic one (TTL high).

Features • Erase/write with a 5V TTL pulse or a 21V pulse

• Pin and functionally compatible with the NMC2816M

• No rise time restriction on erase/write pulse

• 2048 x 8 organization • Conforms to JEDEC byte-wide family standard




• 10 ms chip erase mode

• Low power dissipation 800 mW max (active power ICC + IPP) 360 mW max (standby power ICC + IPP)


O~TA INPUTS/OUTPUTS A7

VCCO--+

GND 0---+ VPP 0--+


AND E/W LOGIC

Y DECODER

AO-Al0 ADDRESS

INPUTS X

DECODER

Pin Names

AO-A10

CE

OE

Addresses 0 0-07 Chip Enable 10-17 Output Enable VPP

10/00-17/07

ttlllll! INPUT/ OUTPUT BUFFERS

Y GATING

l6.384-BIT CELL MATRIX

~--------------~ FIGURE 1

Data Outputs

Data Inputs Program Voltage

TLlD/5195-1

7-42

A6

AS

A4

AJ

A2

Al

AO

10/00

12/02

GNO

NMC97l6M . E2PROM

TOP VIEW

FIGURE 2

Order Number NMC9716MJ NS Package Number J24A

TLJD/5195-2

Absolute Maximum Ratings Operating Conditions Temperature Under Bias -65°Cto + 135°C Temperature Range ,-q5°Cto + 125°C

Storage Temperature -65°Cto +125°C VCC Power Supply (Notes 2 and 3) 5V ± 10%

All Input or Output Voltages with +6Vto -0.3V Respect to Ground

VPP Supply Voltage with Respect + 22.5V to - 0.3V to Ground During Program

Maximum Duration of VPP Supply at 22V 24Hrs During E/W Inhibit

Maximum Duration of VPP Supply at 22V 15ms During Write/Erase Programming (Note 2)


Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to thedevice. This Is a stress rating only and functional operation of the device at these or any other conditions above those Indicated In the operational sections 01 this specification is not implied. Exposure to ab-solute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics TA = - 55°C to + 125°C, VCC = 5V ± 10% (Notes 2 and 3)


Max Units (Note 1)

READ OPERATION

III Input Leakage Current VIN =5.50V 10 p.A

ILO Output Leakage Current VOUT=5.50V 10 p.A

ICC2 VCC Current (Active) OE=CE=VIL 65 140 mA

ICC1 VCC Current (Standby) CE=VIH 12 60 mA

IPP(R) VPP Current (Read) VPP = 6V, CE = VIH or VIL 1 5 mA



VOL Output Low Voltage IOL=2.1 mA 0.45 V

VOH Output High Voltage IOH= -400p.A 2.4 V

VPP Read Voltage 4 6 V

WRITE OPERATION


IPP(W) VPP Current (Write/Erase) OE=VIH, CE::5VIL, VPP=22V 6 15 mA

VOE OE Voltage (Chip Erase) IOE::510p.A 9 15 V

IPP(I) VPP Current (Inhibit) CE = VIH, VPP = 22V 2 5 mA

IPP(C) VPP Current (Chip Erase) OE = VOE, CE = VIL, VPP = 22V 2 5 mA



Max Units (Note 1)





AC Test Conditions Output Load 1 TTL gate and CL = 100 pF

Input Pulse Levels 0.45V to 2.4V

Timing Measurement Reference Level Input 1Vand2V Output 0.8Vand2V

7-43

~ Read Mode AC Electrical Characteristics TA = - 55°C to + 125°C, VCC = 5V ± 10% (Notes 2 and 3) ..tCD o :E z

NMC9716M-25 NMC9716M-35 NMC9716M-45 Symbol Parameter Conditions Typ Typ Typ

Min (Note 1) Max Min (Note 1) Max Min (Note 1) Max

tACC Address to Output CE=OE=VIL 250 350 450 Delay

tCE CE to Output Delay OE=VIL 250 350 450

tOE Output Enable to CE=VIL 10 120 10 140 10 140 Output Delay

tOF Output Disable to CE=OE=VIL 0 100 0 100 0 100 Output Float (Note 9)

tOH Output Hold from CE=OE=VIL 0 0 0 Addresses, CE or OE Whichever Occurred First

Read Waveforms (Note 6)

11---------------------~ ADDRESSES ADDRESSES VALID

~----------~,-----------------J

VIL-------J'o--------1- ----------------1

VIL----------I'----t----------------"'I tOF

I--I-(NOTE 9) VOH----------r.~--

OUTPUT -----+-~ VALID

OUTPUT VOL----------~~~-----------------~~·

Note 1: This parameter is only sampled and not 100% tested.

TUD/5195-3

Uni

m

n~

n~

nE

ns

Note 2: To prevent spurious device erasure or write, VCC must be applied simultaneously or before 21V application of VPP. VPP cannot be driven to 21V without previously applying VCC.

Note 3: VCC must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage to the device it must not be Inserted Into or removed from a board with power applied.

Note 4: Adherence to twp specification Is Important to device reliability.

Note 5: To allow immediate read verify capability, VPP can be driven low In less than 50 ns.

Note 6: All times shown In parentheses are minimum times and are ns unless otherwise specified.

Note 7: Prior to a data write, an erase operation must be performed. For a byte erase, data In = VIH, and for chip erase, data In = don't care.

Note 8: OE may be delayed up to 210 ns after failing edge of CE without impact on tCE for NMC9716M·35.

Note 9: tOF Is specified from OE or ~ whichever occurs first.

Note 10: When programming with VPP, the rising edge of VPP can follow a linear or an exponential waveform. That waveform's rise time or time constant Is specified as tpRC' There is no restriction on the rising edge of VPP If programming wlth~.


Note 12: In byte erase or write mode, OE must be equal to VIH.

Note13: More than one address location can be erase/written without pulsing VPP between every address.

Note14: CE = VIH places the chip In a low power standby condition, and must be applied for a minimum time oftCH before the start of any byte programming cycle.

7-44

Write Mode AC Electrical Characteristics TA = - 55°C to + 125°C, VCC = 5V ± 10% (Notes 2 and 3)




tcs CE Set-Up Time 150 ns

tpR VPP Set-Up Time 0 ns



twp Write Pulse Width (Note 4) 9 10 15 ms




tpRC VPP RC Time Constant (Note 10) 0 750 J!s

tPFT VPP Fall Time (Note 5) 100 J!s

tsos Byte Erase/Write Set-Up Time (Note 12) 0 ns

tSOH Byte EraselWrite Hold Time (Note 12) 0 ns

tCH Chip Enable High Time 1 J!S

Recommended Erase/Write 'Waveforms

I CE Pulsed (Notes 7, 12 and 13)

VIH

, .. ]< j: >C ADDRESSES >1 VIL I

lAS Iwp

VIH I

~-'''I CE '" / VIL -----ICH

I IPR

20V-22V

~ VPP

4V-6V

VIH ,IOS- I-IO~

: DATA IN <l >-VIL

r- IBOS-

IBOH

'-VIH

/ n

tiE VIL

I TLJD/5195-4

Chip Erase Waveforms

CE Pulsed (Note 11)

Iwp

VIH

'" / CE VIL

20V-22V r- IPR

-~lwR---1

VPP

4V-6V

j/ los

, 10H

Q VOE 9V-15V

tiE VIH

TLJD/5195-5

7-45

z s: O. CO ~ -&. 0)

s:

Chip Erase Waveforms (Continued)

VIH

CE Vil

20V-22V

VPP

4V-6V

VOE

fiE VIH

VPP Pulsed (Note 11)

tpRC (NOTE 10)

twp

-tPFT

tOH

Alternate Erase/Write Waveforms (NMC2816M compatible) (Note 6)

Byte Erase and Byte Write Programming Cycle, VPP Pulsed

CE VIL

VIH ADDRESS

VIL

VIH DATA IN

VIL

VIH DE

VIL IPRe (NOT~~i--(NDTE 10)

20V-22V

VPP

4V-6V

I-----twp----~

TU015195-6

TU015195-7

Device Operation TABLE I. Mode Selection Vee = 5V ± 10%

The NMC9716M has six modes of operation, listed in Table I. All operational modes are designed to provide maximum microprocessor compatibility and system consistency. The device pinout is a part of the JEDEC approved byte· wide non-volatile memory family, allowing appropriate and cost·effective density and functionality upgrades.

All control inputs are TTL compatible with the exception of chip erase. The VPP voltage must be pulsed to 21V during write and erase, and held at 5V during the other two modes. .

7-46

~ Mode

Read

Standby

Byte Erase

Byte Write


E/W Inhibit

CE . (18)

VIL

VIH VIL

VIL

VIL

VIH

OE vpp Inputs' (20) (21) Outputs

VIL 4V t06V DOUT

Don't Care 4Vt06V Hi·Z VIH 20V to 22V DIN=VIH VIH 20V to 22V DIN

9V to 15V 20V to 22V DIN= Don't Care

Don't Care 4V to 22V Hi-Z


READ MODE

Both CE and OE must be at logic low levels to obtain Information from the device. Chip enable (CE) is the power control pin and could be used for device selection. The output enable (OE) pin serves to gate internal data to the output pins. Assuming that the address inputs are stable, address access time (tACe) is equal to the delay from CE to output (teE). Data is available at the outputs after a time delay of tOE, assuming that CE has been low and addresses have been stable for at least tACC-tOE'

CHIP ERASE MODE

Should one wish to erase the entire NMC9716M array at once, the device offers a chip erase function. When the chip erase function Is performed, all 2k bytes are returned to a logic 1 (FF) state.

_ The NMC9716M's chip erase function is engaged when the output enable (OE) pin is raised above 9V. When OE is greater than 9V and CE and VPP are in the normal write mode, the entire array is erased. This chip erase function takes approximately 10 ms. The data input pins are don't care during this time to allow for ease in chip erase. Figure 3 is an example for an OE control switch.

VPP PULSE

If using VPP to write or erase, the shape of the VPP pulse can rise to 21V through an RC waveform (0 Its-750 itS time constant), such as the NMC2816M, or a linear ramp (0 Its-750 its). There Is no restriction on the rising edge of VPP if using CE to write or erase.


WRITE MODE

The NMC9716M is erased and reprogrammed electrically rather than optically, as opposed to EPROMs which require UV light. The device offers dramatic flexibility because both byte (single location) and chip erase are possible.

To write a particular location, that byte must be erased prior to a data write. Erasing is accomplished by applying logic 1 (TTL high) inputs to all 8 data input pins, lowering CE, and applying a 21 V programming signal to VPP or raising VPP to 21V and applying a TTL low pulse toCE. The OE pin must be equal to or below VIH during byte erase and write operations. The programming pulse width must be a minimum of 9 ms, and a maximum of 15 ms. Once the location has been erased, the same operation is repeated for a data write. The input pins in this case reflect the byte that is to be stored.

>------e_----<JTQ TIE PIN OF NMC9716M

CHIP ERASE

24V 10k

10k

_"",,..,..-o24V


TUO/5195-8

24V >----~I---f TO VPP PIN

t------4I-. OF NMC9716M

ERASE/WRITE (WRITE/Jili)

R1 120

R2 470

TUO/5195-9

FIGURE 4. VPP Switch Design with Electronic Shutdown for CE Pulsed Erase/Write

7-47


A characteristic of all E2PROMs is that the total number of erase/write cycles is not unlimited. The NMC9716M has been designed to meet applications requiring up to 1 X 104

erase/write cycles per byte. The erase/write cycling characteristic is completely byte independent. Adjacent bytes are not affected during erase/write cycling.,

Because the device is designed to be written in·system, all data sheet specifications (including write and erase operations) hold over the full operating temperature range (- 55°C to + 125°C).

OUTPUT OR·TYING

Because NMC9716Ms are usually used in larger memory arrays, a 2-line control function is provided that accommodates this use of multiple memory connections. The 2-line control function allows low power dissipation (by dese· lecting unused devices) and th'e removal of bus contention from the system environment.

7·48

To most effectively use these two control lines, it is recommended that CE (pin 18) be decoded from addresses as the primary device selection function. OE (pin 20) should be made a common connection to all devices in·system, and connected to the RD line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device.

STANDBY MODE

The NMC9716M has a standby mode which reduces active power. dissipation by 55% from 800 mW to 360 mW (ICC + IPP). The NMC9716M is placed in the standby mode by applying a TTL high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input.

Z ~National PRELIMINARY s: D Semiconductor NMC981716,384-Bit(2k x 8) ~PROM General Description The NMC9817 is a fast 5V-only E2PROM which ,offers many desired features, making it ideally suited for efficiency and ease in system design. The added features on the NMC9817 include: 5V-only operation provided by an onchip Vpp generator during erase-write; address and data latches to reduce part count and to free the microprocessor while the chip is busy during erase-write; 'Ready' line indicator to indicate status of chip to the microprocessor; and automatic erase before byte-write. It can meet applications requiring up to 104 write cycles per byte. The NMC9817 is a product of National's advanced E2PROM stepper technology and uses the powerful XMOS™ process for reliable, non-volatile data storage.

The NMC9817 sharply minimizes the interfacing hardware logic and firmware required to perform data writes. The device has complete self-timing which leaves the processor free to perform other tasks until the NMC9817 signals 'ready'. With an automatic erase before write, the user benefits by saving an erase command contributing to efficient usage of system processing time. On-chip address and data latching further enhances system performance.

The NMC9817's very fast read access times make it compatible with high performance microprocessor applications. It uses the proven two line control architecture which eliminates bus contention in a system environment. Combining these features with the NMC9817's open-drain 'Ready' signal makes the device an extremely powerful, yet simple to use, E2PROM memory.

Block and Connection Diagrams ~

Vpp GENERATDR ~ GND~------------~------------~

CHIP ENABLE/OUTPUT ENABLE LOGIC

AUTOMATIC WRITE TIMING

AUTOMATIC ERASE LOGIC

Pin Names

Y DECODER

X DECODER

FIGURE 1

Addresses 10-17 Data Inputs

The density, and level of integrated control, make the NMC9817 suitable for users requiring mi.nimum hardwa~e overhead, high system performance, minimal board space and design ease. Designing with and using the NMC9817 is extremely cost effective as the required high voltage and interfacing hardware required for other E2PROM devices has been eliminated by 5V-only operation and onchip latches. See Figures 1, 2, and 3 for the NMC9817 bl()ck diagram, pinout, and simple interface requirements.

Features • Single 5V supply (eliminates an external 21V Vpp)

.- Self-timed byte-write with auto erase

• No external capacitor or pulse shaping circuits

• On-Chip address and data latches

• Two line output control • TRI-STATEI!i outputs

• RDY pin indicator • Fast byte-writing

Write cycle (2 ms typical) E/W cycle (4 ms typical)

• Very fast access times NMC9817-20-200 ns NMC9817-25-250 ns NMC9817-35-350 ns

• Direct microprocessor interface capability

• No support components needed • Reliable E2PROM XMOS stepper technology

DATA INPUTS/OUTPUTS la/Oa-I7 /07

INPUT LATCHES

INPUT/OUTPUT BUFFERS

Y GATING

16.384·BIT CELL MATRIX

TLlD/504'-'

RDY/ nmY

NC

A7

A6

A5

A4

A3

A2

A1

AD

la/Oa

h/Ol

12/02

GNO


NMC9817 E2PROM

12

13

14

TOP VIEW

FIGURE 2

Vee

WE

NC

A8

A9

NC

liE

A10

~

17/07

16/06

15/05

14/04

13/03

TLlD/504'-2

AO-A10

CE Chip Enable ROY/BUSY Device Ready/Busy (Open·Draln Output) Order Number NMC9817J-20,

OE

-00-07

Output Enable NC No Connect

Data Outputs

NMC9817J-25 or NMC9817J·35 NS Package Number J28A

7-49

o CD co .... ---a

t-. "I"'"" co en o :E z

Absolute Ma~imum Ratings Temperature Under Bias

Storage Temperature

All Input or Output Voltages with Respect to Grounq

-10°C to + 80°C

- 65°Cto +125°C

+6Vto -0.3V

Lead Temperature (Soldering, 10 seconds)

Operating Conditions Temperature Range

V cc Power Supply (Notes 2 and 3)

O°Cto + 70°C

5V±5%

Note: Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics TA = O°C to 70°C, V cc = 5V ± 5% (Notes 2 and 3)

Symbol Parameter Conditions

READ OPERATION

III Input Leakage Current VIN =5.25V

ILO Output Leakage Current VOUT = 5.25V

ICCA V cc Current (Active) OE=CE=VIL

Iccs V cc Current (Standby) CE=VIH

VIL Input Low Voltage

VIH Input High Voltage

VOL Output Low Voltage IOL=2.1 mA

VOH Output High Voltage IOH= -400/LA

WRITE OPERATION

Iccw I Vcc'Current (Write) RDY/BUSY = VOL

CapacitanceTA=25°C, f=1 MHz (Note 1)

Symbol Parameter Conditions

CIN Input Capacitance VIN=OV

COUT Output Capacitance VOUT= OV


Input Pulse Levels

1 TTL gate and CL = 100 pF

0.45V to 2.4V

Timing Measurement Reference Level Input Output

1Vand2V 0.8V and 2V

40

12

-0.1

2.0

2.4

40

MiIJ Typ

. (Note 1)

5

7-50

Units

10 /LA

10 /LA

80 mA

25 mA

0.8 V

Vcc +1 V

0.45 V

V

, 80 mA

Max Units

10 pF

10 pF

Read Mode AC Electrical CharacteristicsTA=o·c to 70·C, Vee=5V±5% (Notes 2and3)

NMC9817·20 NMC9817·25 NMC9817·35 Symbol Parameter Conditions

Min Typ

Max Typ

(Note 1) Min (Note 1) Max Min

tAce Address to Output CE=OE=V1L 150 200 200 250 Delay

tCE CE to Output Delay OE=V1L 150 200 200 250

tOE Output Enable to CE=V1L 10 75 10 100 10 Output Delay

tOF Output Disable CE or OE=VIL 0 80 0 100 0 to Output Float

tOH Output Hold from CE,OE=V1L 0 0 0 Addresses, CE or OE Whichever Occurred First

Switching Time Waveforms Read

ADDRESSES _...;...._ ...... r : A"~~~~~:~~ ____ -'1 .... K'--__ _ I -r:== tACC-

CE I ~---l-----------~JI II_-U'=:J:-_I I ...

,I( ~-+--'--'--'---------'1

tOE~-

tt ------- VALID OUTPUT --------~ OUTPUT

. ----------------"~,."

tOF (NOTE 4)

TL1D/5O<O'·3

Typ (Note 1)

300

300

Write Mode AC Electrical Characteristics TA = o·c to 70·C, Vee = 5V ± 5% (Notes 2 and 3)


Max (Note 1)

tAS Address to Write Set-Up Time 20

tes CE to Write Set-Up Time 20

twp Write Pulse Width 100

tAH Address Hold Time 50

tos Data Set-Up Time OE=V1H 50

tOH Data Hold Time OE=VIH 20

teH CE Hold Time 20

tOB Time to Device Busy 120

tWA Byte-Write Cycle Time 4 10

Note 1: This parameter only sampled and not 100% tested.

Max

350

350

120

100

Units

ns

ns

ns

ns

ns

Units

ns

ns

ns

ns

ns

ns

ns

ns

ms

Note 2: To prevent spurious device erase or write, WE or CE = VIH must be applied simultaneously or before application of Vee. WE or ~ = VIH must be removed simultaneously or after Vee. Note 3: To prevent damage to the device It must not be Inserted Into or removed from a board with power applied. Note 4: t OF Is specified from OE or CE, whichever occurs first.

7-51

OIl

r--.. ,... co 0)

o ::E z


ADDRESSES

OIN----------~

ROY/BUSY

Device Operation The NMC9817 has 4 modes of user operation which are detailed in Table I. All modes are designed to enhance the NMC9817's functionality to the user and provide total microprocessor compatibility.

TABLE I. Vee';" 5V

~ Mode CE OE WE 10/00-17/07 ROY/BUSY

Read VIL VIL VIH DOUT Hi-Z

Standby VIH X X Hi-Z Hi-Z

Write VIL VIH 1..f DIN VOL

Busy X X X Hi-Z VOL

FROM DECODER

FROM iiii

FROM Wii

- TO INTERRUPT

AO-Al0

10/00-17/07 ~

Write

1-... -~---1 TlID/S041-4

WRITE MOOE

The NMC9817 is programmed electrically in-circuit, yet it provides the non-volatility usually obtained by optical erasure in EPROMS and by batteries with CMOS RAM. Writing to non-volatile memory has never been easier as no high voltage, external latching, erasing or timing is needed. When commanded to byte-write, the NMC9817 automatically latches the address, data, and control signals and starts the write cycle. Concurrently, the 'Ready' line goes low, indicating that the NMC9817 is busy and that it can be deselected to allow tt'le processor to perform other tasks. The ReadylBusy signal is an open-drain output. During the write, a high Vpp is generated on-chip to perform an automatic byte-erase, then write.

As a precaution against spurious signals which may cause an inadvertant write cycle, or interfere with a valid signal, ~ recommended that a pullup resistor be used on the WE pin, pin 27 (see Figure 4).

5 Voc

_ DE

NMC9817 E;2PROM

_WE

ROY /liiiSY

AD-Al0

• 10/00-17/07 GNO

":"

SYSTEM NMC9817 REQUIREMENTS REQUIREMENTS

TlID/S041-S

FIGURE 3. Simple NMC9817 Interface Requirements

7-52

Vee

R=4K TO 10 KG

WE 27 ~

NMC9817

TUDI5041·6

FIGURE 4. Pullup R on WE


READ MODE

One aspect of the NMC9817's high performance is its very fast read access time-typically less than 200 ns. Its read cycle is similar to that of EPROMS and static RAMs. It offers a two line control architecture to eliminate bus contention. The NMC9817 can be selected using decoded system address lines to CE and then the device can be read, within the device selection time, using the processor's RD signal connected to OE.

STANDBY MODE

The NMC9817 has a standby mode in which power consumption is reduced by 70%. This offers the user power supply cost benefits when designing a system with NMC9817s. This mode occurs when the device is deselected (CE = V1H). The data pins are put into the high impedance state regardless of the signals applied to OE and WE concurrent with the reading and writing of other devices.

SYSTEM IMPLEMENTATION AND APPLICATION

The NMC9817 is compatible with industry standard microprocessors. It requires no interface circuitry and no support circuitry.

The NMC9817 is ideal for non-volatile memory requirements in applications requiring storage of user defined functions, calibration constants, configuration parameters and accumulated totals. Soft key configuration in a graphics terminal is an example where user defined functions, such as protocol, color, margins and character fonts can be keyed in by the user. Calibration constants could be stored by the NMC9817 in the smart interface for a robot's axis of movement. Movement constants, compensation algorithms and learned axis characteristics can be stored. In programmable controllers and data loggers, configuration parameters for polling time, sequence and location,

7-53

could be stored in the NMC9817. Accumulated totals for dollars, energy consumption, volume and even the logging of service done on computer boards or systems can be stored in the NMC9817.

The NMC9817 is cost effective for lower density E2PROM applications and can therefore be used to provide a lower system cost to the user compared to the 2816 or 2817. The user will find that tangible cost savings per system include: board space and component reductions, reduced assembly costs, savings in inventory costs, handling costs and quality assurance. The designer will find the NMC9817 reduces design time by a sizable factor over the 2816 or 2817 due to the integration of timing, logic, latching and 5V-only operation.

The NMC9817 will also open up new applications in environments where flexible parameter/data storage could not be implemented before. For example, applications with board space constraints are ideal for the NMC9817. Several NMC9817s can reside in the same space asone(l) 2816 with its support circuits. This is due to the reduction of all components required including the Vpp generator.

WRITE TIME CHARACTERISTICS

The NMC9817's internal write cycle contains an automatic erase feature. The 2816 does not have this capability and must be given an external erase cycle prior to a write. Typically, these devices will write in times less than 9 ms, but the worst-case bit defines thE minimum specification.

The NMC9817's internal cycle consists of an automatic 2 ms (typical) erase followed by a 2 ms (typical) write. The total cycle is then typically 4 ms. This cycle is the time that 'Ready' is held low by the device. The NMC9817 maximum specification is 10 ms.

~ CD o co 0)

o :E z

~National . ~ Semiconductor

PRELIMINARY ~\~

microCMOS

NMC98C64A, 65,536-Bit (8K x 8) E2PROM

General Description The N MC98C64A is a 5V-only CMOS E2PROM with desirable ease-of-use features that facilitate in-circuit programming using a single supply and TTL-level signals. In addition, the NMC98C64A is operationally compatible with present high density EPROMs which require high voltage programming and UV erasing. The NMC9864A Is a stateof-the-art product that uses the advanced microCMOS stepper-based technology. The process is an enhancement of the proven XMOS™ process for reliable, nonvolatile data storage.

Writing data into NMC98C64A is analogous to writing to a SRAM. A 100-ns min TTL pulse to the WE pin initiates a byte write operation which is automatically timed out. Address and data latches free the system bus for the duration of the write. Ready/busy facilitates service by providing an interrupt to the controller; an open-drain output facilitates "wire-OR" connection in larger systems.

A 32-byte page write allows data to be accepted at an effective rate of 300 /Ls/page, or 2.6 seconds to write an entire chip. An optional chip erase feature is also available.

The NMC98C64A also features data.polling, a new feature that enables the E2PROM to signal the processor that a write operation is done, without requiring any extra hardware.

Ready/busy Interrupt output is another feature that enables the processor to know that a write operation is over. This employs an otherwise no-connect pin 1.

Connection Diagram

READY/BSY -1 '-.../ ~ Vee

A12.2 ~WE

Features The NMC98C64A offers the following smart features:

• Simple byte and page write _ - Single TTL-level, RAM-like WE - Address and data latches - Page mode write up to 32 bytes per page - DATA polling verification - Internal auto erase - On-chip timer - Optional chip erase - Ready/busy open-drain interrupt output - Write protection

• Byte or page write: 10 ms maximum - Effective 300 /Ls/write page - Entire chip write: 2.6 seconds

• Fast access time: 250 ns maximum • Low CMOS power: 10 rnA, active

100/LA, standby

• Single 5V supply • 28-pin JEDEC-approved byte-wide pin-out

A702 ~NC MODE SELECTION A6~ ~Aa

CE OE WE Mode 1/0 Readyl Power A5.J ~A9 Busy

A4..J ~A11 L L L Read Dour Hi-Z Active

L H l..r Write DIN 0 Active A3.2

NMC98C64A ~iiE

Standby and ~A10 H X X Hi-Z Hi-Z Standby A2..! . 8Kx8 Write Inhibit

A1...! ~CE X L X Write Inhibit - Hi-Z -Ao..1!!. t1!- 1/07 X X H Write Inhibit - Hi-Z -

1/00..11 ~1/06 L VOE L Chip Erase DIN=H Hi-Z Active

1/01..E ~1I05 L L H DATA 1107= 17* 0 Active Polling 1107=17 1 Active

1/02~ ~1/04 'During write cycle, 1100 through 1/07 are Hi-Z.

VSS~ ~1/03

TU017514-1

NS Package Number J16A

7-54

Block Diagram

GND 0--+

Vee EE DE

WE RDYIBUSY

An A4

A5 A6 A7 As Ag Al0 A11 A12

~

~

Vpp GENERATOR

CONTROL LOGIC

COLUMN ADDRESS BUFFERS

ROW ADDRESS BUFFERS

DEVICE OPERATION

Addresses (Ao-A12) E2PROM bytes are selected for reading or writing by the address pins.

CHIP ENABLE (CE)

A device is selected when CE is LOW. Power is reduced to less than .1 % during disable when CE is HIGH.

DATA·IN/DATA·OUT (1/00.1/°7)

Data is written into or read from a' selected device through the 110 pins. The 110 pins are in the high impedance state when CE is HIGH, or when DE is HIGH.

OUTPUT ENABLE (OE)

Reading data from the NMC98C64A is similar to reading data from a static RAM. Data is read from a selected device with WE HIGH and DE LOW.

NMC98C64A uses a 2-line output control architecture to eliminate bus contention in a system environment. The 110 pins are in a high impedance state whenever DE or CE is HIGH.

7·55

1/01 1/03 1/05 1/07 1100 1/02 lID. 1/06

Y DECODERS

8Kx8 E2PROM ARRAY

4 REDUNDANT ROWS

TUDI75'4-2

WRITE ENABLE (WE)

Writing data to the NMC98C64A is similar to writing data into a static RAM. A LOW·going WE pulse applied to a selected device with OE HIGH initiates a cycle that writes data at the 110 pins Into a location selected by the ad· dress pins. A byte write cycle once initiated will automat· ically continue to completion In 5 ms typically. During a byte write cycle, addresses are latched on the last failing edge of CE or WE; data is latched on the first rising edge of CE or WE. System design is greatly simplified, since writing requires only a single 5V supply and a single TTL· level WE signal. Addresses and data are conveniently latched in less than 100 ns during a byte write. As a precaution against spurious signals which may cause an in· advertant write cycle, or interfere with a valid signal, it is recommended that a pullup resistor be used on the WE pin, pin 27 (see Figure 1).

AUTOMATIC PAGE WRITE

The page write feature of NMC98C64A allows 1 to 32 bytes of data to be written into the E2PROM in a single write cycle. Following a byte write signal to the E2PROM, the user has 300 ILS to write 0-31 additional bytes of data Into the E2PROM, providing that the byte addresses are on the same 32-byte page In memory. This page mode al· lows the entire NMC98C64A to be rewritten In 2.6 sec·

<t ~ CD o co 0)

o :E z

onds. A page is defined by addresses A5-A12. The 32 bytes within the page are defined by Ao-A4' All bytes to be written must be loaded within the first 300 P.s after initiating the write of the first byte. All subsequent writes during the page load cycle must go to the same page (addresses A5-A12) as the first byte. The bytes may be written in any order.

OPTIONAL CHIP ERASE

All data can be written to "1", the erase state, in a chip erase cycle by raising OE to 15 volts and bringing WE low while holding all data inputs high.

DATA POLLING

The NMC98C64A features DATA polling to signal the completion of a byte or page write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of that byte at 11°7, After completion of the write cycle, true data is available. DATA polling

NMC9BC64A

allows a simple read/compare operation to determine the status of the chip, eliminating the need for external hardware.

WRITE PROTECTION

There are three features that protect the nonvolatile data from an inadvertent write. • Noise Protection - A WE pulse ofles5 than 20 ns will not

initiate a write cycle. • Vee Sense-When the Vee is approximately 4 volts, all

functions are inhibited. • Write Inhibit - Holding OE low, WE high, or CE high,

inhibits a write cycle during power-on and power-off (Ved·

ENDURANCE

National Semiconductor E2PROMs are designed for applications requiring up to 10,000 write cycles per byte.

Vee

~ : R=4KT01DKD

WE 27 ~

TU017514-3

FIGURE 1

7-56

Threshold Bit Mapping in EEPROMs (NMC2816)

Threshold bit mapping is designed to monitor the endurance of an E2PROM cell after a large (>105) number of erase/ write cycles. The technique calls for monitoring the cell current of a bit under identical voltage, timing and temperature conditions and repeating the same after x-number of erase/ write cycles. On a 'good' cell the variation in cell current will be no more than a few ( .. 21LA) microamps over 10,000 cycles under typical conditions of Vcc = Vpp - SV

Temp = 2S'C

Vin = 2V

Timing = same for each case

On a cell approaching 'wear out' a much larger variation would be noticed in the cell current. The variation could be in either direction depending on the nature of conductive degradation ,of the thin tunnel oxide as a result of free charge trapping in the insulation which is a gradual phenomena.

Figure 1 shows a plot of Vte and Vtw vs number of erase/ write cycles. The cell current under both erased, and write conditions will hold pretty stable in the flat region.

It must be noted that identical conditions of measurement are very important. The actual value of Vpp and erase/write pulse width must be kept the same prior to mea~urement.

The NMC2816/9716 are designed with a special test mode, which allow connecting each of the outputs with its respective bit. In this mode each I/O pin gets connected to the drain of the cell transistor allowing a cell-current measurement of the respective bit in the addressed byte. Figure 2 shows the threshold bit mapping circuit for a single bit. To put the NMC2816/9716 in the threshold bit mapping mode, the following set up is required:

National Semiconductor Application Brief 5 Masood Alavi, Sr. Apps. Mgr. February 1983

Vcc - Vpp .. SV ± (S%)

OE .. VIH = Logic 1 state

CE - 20V

addresses - selected locations

I/O = force 2V measure current in ILAmps

T A = constant .. 2S'C (arbitrary)

The cell current of any number of desired bits can be measured in an erased and written state. In the 'erased' state negligible current will exist till the onset of wearout. In the 'written' state a low magnitude current (of SO-60ILA) will be measurable till the onset of wearout. It is important that the amplitude and pulse width of erase/write pulse prior to measurement remains identical for aU measurements. The measurements can be repeated over a number of erase/write cycles and plotted against the same. At the onset of wearout there will be a radical change in the monitored currents; the erased state current will increase in magnitude while the written state current will faU in magnitude.

It is also possible to calculate Vte and Vtw from the cell current measurements and plot against erase/write cycles. It must be noticed that the resultant values are at best intelligent approximations designed to give an insight into the wearout phenomena due to erase/write cycles. At present the threshold bit mapping technique remains an observation technique. The purpose of this technique is to study the wearout phenomena and its effects in EEPROMS. It is however not recommended .as a screening technique at present.

8 M"VTE 1-------------____

o

10

FIGURE 1. ERASE/WRITE Cycles

TL/0/5191-1

7·S7

an .... CD -a: m a. a.

<C

FROM ARRAY

HIGH TRIP POINT A~D GATE

INPUT BUFFER

TRI·STATE® OUTPUT BUFFER

DE (TTL HIGH) FIGURE 2. Threshold Bit Mapping Circuitry

7·58

liD PAD

TL/D/5191-2

Protecting Data in the NMC9306/COP494 and NMC9346/COP495 Serial EEPROMs

The NMC9306/COP494 and NMC9346/COP495 are nonvolatile serial access memories with the following salient features:

• Low cost • Single supply read/write/erase operation (5V ± 10%)

• TIL compatible • MICROWIRETM compatible I/O

• 16 x 16 serial read/write memory (NMC9306/COP494) 64 x 16 serial read/write memory (NMC9346/COP495)

• Self-timed programming cycle (NMC9346/COP495 only) • Ready/busy status signal during programming

(NMC9346/COP495 only)

• Read-only mode

The read-only mode is provided to prevent accidental data disturb, especially during Vee power up, power down or excessive noise on the I/O or power supply pins.

Executing the EWDS instruction (Figure 1) activates this mode by disabling the programming modes and the high voltage pump. The READ instruction is not affected and can

EWEN EWDS

SK

National Semiconductor Application Brief 15 Asim Bajwa May 1984

be executed as usual. However, all programming instructions (ERASE, WRITE, ERAL and WRAL) are ignored until the EWEN instruction is executed to enable programming.

On Vee power up the device is designed to automatically enter the read-only mode to avoid accidental data loss due to power up transients. Putting the device in the read-only mode before powering down Vee avoids spurious programming during power down.

The following guidelines are presented and should be incorporated into the user's designs to achieve the maximum possible protection of stored data (Figure 2):

1) The device powers up in the read-only mode. However, as a backup, the EWDS instruction should be executed as soon as possible after Vee to the EEPROM is powered up to ensure that it is in the read-only mode.

2) Immediately preceding a programming instruction (ERASE, WRITE, ERAL or WRAL), the EWEN instruction should be executed to enable the device for programming; the EWDS instruction should be executed immediately following the programming instruction

~~ ____ S~~~N~D_BY ____ ___

DI----A~D----.D~""""-_~~""''''''''''"'''''''''''''A~; ____ _ ENABLE=11 DISABLE=DD TLIDi70B5·1

FIGURE 1. EWEN, EWDS Instruction Timing

MAIN POWER SUPPLY r 4.5V-5.5V r

Vee J

INSTRUCTIDN~~ (ERASE, WRITE, ERAl OR WRAL)

l~ ___ _

L 5.5V:2: Vee :2: 4.SV -l~I-----MAINTAINED ON CAPACITOR .

TUDi70B5-2

'EWDS must be executed before Vcc drops below 4.5V to prevent accidental data loss during subsequent power down and/or power up transients.

FIGURE 2. Typical Instruction Flow for Maximum Data Protection

7-59

l> "'C "'C

m :::!. CD -h

...... en

to return the device to the read~only mode and protect the stored data from accidental disturb during subsequent power transients or noise.

3) Special care must be taken in designs in which programming instructions are initiated to store data in the EEPROM after the main power supply has gone down. This is usually accomplished by maintaining Vee for the EEPROM and its controller on a capacitor for a sufficient amount of time (approximately 50 ms, depending on

7-60

the clock rate) to complete-these operations. This capacitor. must be large enough to. maintain Vee between 4.5 and 5.5 volts for the total duration of the store operation, INCLUDING the execution of the EWDS instruction immediately following the last programming instruction. FAILURE TO EXECUTE THE LAST EWDS INSTRUCTION BEFORE Vee DROPS BELOW 4.5 VOLTS MAY CAUSE INADVERTENT DATA DISTURB DURING SUBSEQUENT POWER DOWN ANDIOR POWER UP TRANSIENTS.

AN-328 EEPROM Application Note Vpp Generation on Board

The NMC2816 requires a 21V pulse for writing and erasing. The rise time on the pulse gOing from 5-21V is to be 600ILS ideally. The NMC 9716 requires a stable 21V. This application note discusses two methods of generating the required Vpp voltage or the high level pulse from a 5V supply.

The first method shows how to generate 21 V from a single 5V supply using an LM3524 switching voltage regulator, a power inductor and a number of capacitors as the main active elements. The principle involved is explained by the circuit of Figure 1.

VIN

National Semiconducter Application Note 328 Massood Alavi, Sr. Apps Mgr February 1983

THE STEP-UP SWITCHING REGULATOR

Figure 1 shows the basic circuit for a step-up switching regulator. In this circuit 01 is used as a switch to alternately apply VIN across inductor L 1. During the time, toN. 01 is ON and energy is drawn from VIN and stored in L 1 :01 is reverse biased and 10 is supplied from the charge stored in Co. When 01 opens during toFF, voltage V1 will rise positively to the point where 01 turns ON. The output current is now supplied through L 1,01 to the load and any charge lost from Co during toN is replenished. Here the current through L 1 has a DC component plus some boll. boll is selected to be approximately 40% of Il. Figure 2 shows the inductor's current in relation to 01's ON and OFF times.

Tl/0/5152-1

FIGURE 1. Basic Step-Up Switching Regulator

Tl/0/5152-2

FIGURE 2. Voltage and Current Waveforms at V1

7-61

» z I

W N Q)

co N C") • Z

c(

. The following equations are derived to give the reader a theoretical understanding of the operation.

From AI = VL T AI + e: VINtoN L L'L L1

and AI - "'" C'J 0 - VIN)toFF L L1

and neglecting VSAT and V01

The above equation shows the relationship between VIN, Vo and duty cycle.

In calculating input current IIN(OC), which equals the inductor's DC current, assume first 100% efficiency:

for '11 = 100%, POUT = PIN

10 VIN (1 + toN) = IIN(OC) VIN toFF

IIN(OC) = lo( 1 + toN) toFF

This equation shows that the input, or inductor, current is larger than the output current by the factor (~ + toN/toFF)' Since this factor is the same as the relation between Vo and VIN, IIN(OC) can also be expressed as:

2.

So far it is assumed '11 = 100%, where the actual efficiency or 'I1MAX will be somewhat less due to the saturation voltage of 01 and forward on voltage of 01. The internal power loss due to these voltages is the average IL current flowing, or liN, through either VSAT or V01. For VSAT = V01 = 1V this power loss becomes IIN(OC) (1 V). 'I1MAX is then:

Volo+ 10( 1 + toN) toFF .

7-62

From Vo = VIN(1 + toN), toFF

3.

This equation assumes only DC losses, however 'I1MAX is further decreased because of the switching time of 01 and 01.

In calculating the output capacitor Co it can be seen that Co supplies 10 during toN. The voltage change on Co during this time will be some A V c = AVo or the output ripple of the regulator. Calculation of Co is:

A V = 10toN or C = 10toN o Co 0 AVo

( T ) VIN From Vo = VIN -- ; toFF = -V T

toFF 0

1 where T = toN + toFF = f

toN = T - VIN T = T(VO - VIN) therefore: Vo Vo

4.

where: Co is in farads, f is the switching frequency,

AVo is the pop output ripple

Calculation of inductor L 1 is as follows:

L 1 = ~~~N, since during toN,

VIN is applied across L 1

AILp.p = 0.41L = O.4IIN = O.4lo(~~), therefore:

L 1 = VINtoN and since toN = T(V 0 - VIN)

( Vo) Vo

0.41 0 VIN

where: L 1 is in henrys, f is the switching frequency in Hz

To apply the above theory, a complete step-up switching regulator is shown in Figure 3. Since VIN is SV, VREF is tied to VIN. The input voltage is divided by 2 to bias the error amplifier's inverting input. The output voltage is:

VOUT = (1 + :~) • VINV = 2.S (1 + :~) 6.

Using equation 1 any desired supply voltage can be generated at Vo by selecting a suitable value for R2. If R2 is a pot in the 2SK-SOK range, it can be used to set Vo from 1SV-27.SV. For standard E2PROM and EPROM applications this range is very suitable for Vpp set up. Table 1 shows various values of R2 for corresponding values of Vo.

The network 01, C1 forms a slow start circuit. This holds the output of the error amplifier initially low thus reducing the duty-cycle to a minimum. Without the slow start circuit the inductor may saturate at turn-on because it has to supply high peak currents to charge the output capacitor from av. It should also be noted that this circuit has no supply rejection. By adding a reference voltage at the non-inverting input to the error amplifier, see Figure 4, the input voltage variations are rejected.

YIN ---

FIGURE 4. Voltage Reference

r-----, H2 I 35k-47k . t ,VOLTAGE ADJ

TL/0/5152-4

~~~~--~~----------~--------------~~------~-ITlT1 •• ~ 2k 240 5 mH :

...... "), ... - ...... oM;I----t.....--... -YO =20V-26V

1N914 T2

"'---4~ B0345

.... ------It-tYREF

R4 • 5k

.... -----II-fNI

.~ R3 R1 5k 5k

1~ T1 CA t-4 .......... ~~It-t~ 2N2219

CB -

• 1k . . _.!.. _'"-, .... "'V'V'v'~~INV LM3524 EAt----~~ .... -----~ ,_'"- _~

10I'F_~ _r- 0.1 I'F O.lI'F_~ _~ l0I'F

EB~-----"" 01

~2~~C_T ____ G~NO ___ C_OM_P~~----~~-1~N~~9~~4-~ ~

5Dk

T- '"- O.OOlI'F -.;!;.. C1 T 5 1'F

GNO~~--~~--_e-----------_e----~....._------... ------._---~-~~GND

FIGURE 3. A 5V-21V Vpp Voltage Generator Circuit for E2PROM Application

7-63

TUD/5152-3

» z I

W I\) CD

co N C")

I

Z <C

CHIP ERASE

TABLE I

R2 Vo

47K 26V 45K 25V 43K 24V 41K 23V 39K 22V 37K 21V 35K 20V

TO li£"PlN OF >-----..... ---- NMC971612816

24V "'~""'-5V 10k

The current sourcing capability of Vo can be made as high as 500mA. If no more than 100mA are desired, T 1 and 240 ohms resistor can be replaced by T 2 alone; the base of T 2 should be connected to the node at base of T 1; T 2 collector and emitter should be left intact. 1 OOmA is sufficient to support up to 20 NMC2816's or NMC9716's.

The Vpp voltage generated by the circuit of Figure 3, can be used to provide the E/W pulses on the NMC2816 or the stable Vpp on NMC9716. The 9V-15V needed for chip erase can also be generated. Figures 5, 6, 7 demonstrate how to achieve that.

24V>----..... _ VJN--t ~-~~----·~::~~6 -..... - .. R1 120

R2 470

ERASEIWRITE (WRITEiiiD)

FIGURE 5. OE Chip Erase Control for NMC2816/NMC9716

Tl/D/5152-5 FIGURE 6. VPP Switch Design with Electronic Shutdown for CE Pulsed Erase/Write for NMC9716

24V.-----~~~~---.-------------------------.,

VPP CONTROL (WRITE/D)

Note 1: 5k Is 21V fine adjust.

Note 2: Resistors are y~W.

5V

lN914

TO ... - ....... VPPPlN

OF NMC2816

FIGURE 7. Operational Amplifier VPP Switch Design for NMC2816

7-64

Tl/D/5152-6

Tl/D/5152-7

The following paragraphs outline a second method of generating a 21 V pulse from a single 5V supply. Figure 8 shows such a DC-DC converter circuit.

In the circuit, inductor L 1 in conjunction with transistors 01 & 02 form a self driven 5-30V converter. Transitors 03 & 04 are meant to strobe the converter allowing it to draw power and run only when a TIL high is presented at the input node A. Trace A, Figure 9 shows the signal to be applied at the input node. This makes the 03-04 transistor pair conduct biasing 01 & 02. Trace B, Figure 9 shows the resultant waveform generated at node B, the collector of 02. As the converter runs, its output at node C rises to the desired high voltage of 30V quickly. The output is lightly filtered by the .1 F capacitor. Trace C, Figure 9 shows this waveform.

The voltage at node C is used to charge the 12k, .05,...F combination at the desired RC of 600,...S. This signal cut off at 21 V by the Zener at the input to A 1 B is presented to the amplifier A 1 B to be outputted to node 0 as the desired Vpp. The amplitude and pulse shape is controlled by. setting the cut-off Zener voltage in conjunction with the gain of A 1 B set by R2. For example, if 7V Zener voltage is used for cut off a gain of 3 will have to be set for A 1 B to get a 21 V output pulse.

Ll

5V

500

R5 12k

When the capacitor reaches the Zener cut off, the Zener clamps, charging ceases and the circuit output sits at 21V.

When the signal at node A goes to TIL low, the open collector output of comparator A 1 A clamps low, discharging the .05 capacitor and getting the circuit ready for the next pulse. Any EEPROM programming requirement can be met by varying the gain of A 1 B, the time constant at its input and/or the Zener value across the capacitor. Any TIL detect value can be set by the voltage-divider on the A 1 A comparator in this case set at about 1.5V.

Transistor 05 is provided to source boosted output current. Diode 06 is provided to hold the output or Vpp as close to Vcc as possible when 21V is not desired. A Ge or Schottky diode must be used to optimize the diode forward drop at ~.2V. 05 is provided to maximize the reverse breakdown from node 0 to base of 05, when 21 volts is at node O. Figure 9 shows the idealized signals generated at various nodes. When the input at node A is at TIL low level, the output 0 sits at 4.BV. As the input A goes to a TIL high level the output 0 rises to 21V at RC of 600,...S. The waveform at node A may be derived from the CE by inverting the CE signal. The resulting waveform at node 0 is used for Vpp.

5V

~05I'F

10k

INPUT LM392 COMPARATOR

TL/D/5152-8

FIGURE 8. Vpp Pulse Generator Circuit

7-65

» z I

W N CO

co ~ Reference.: .

• Circuit of Figure 3 is derived from NSC voltage regulator Z application.

c( Circuit of Figure 9 is from Electronic design, October 15, 1981.

"Design DC-DC converters to catch noise at source" -J Williams.

A 5V...J OV

5V ..J OV

____ r-

FIGURE ~. Idealized Signals at Various Nodes

7-66

TLlD/5152-9

Designing with the NMC9306/COP494 a Versatile Simple to Use E2PROM

This application note outlines various methods of interfacing an NMC9306/COP494 with the COPS™family of microcontrollers and other microprocessors. Figures 1-6 show pin connections involved in such interfaces. Figure 7 shows how parallel data can be converted into a serial format to be inputted to the NMC9306; as well as how serial data outputted from an NMC9306 can be converted to a parallel-format.

The second part of the application note summarizes the key . points covering the critical electrical specifications to be kept in mind when using the NMC9306/COP494.

The third part of the application note shows a list of various applications that can use a NMC9306/COP494.

GENERIC CONSIDERATIONS

A typical application should meet the following generic criteria:

1. allow for no more than 10,000 E/W cycles for optimum and reliable performance.

2. allow for any number of read cycles.

3. allow for an erase or write cycle that operates in the 10-30 ms range, and not in the tens or hundreds of ns range as used in writing RAMs. (Read vs write speeds are distinctly different by orders of magnitude in E2PROM, not so in RAMs.

Vss

NMC9306! 00 COP494

00

SI

SO

National Semiconductor Application Note 338 Masood Alavi June 1983

4. no battery back-up required for data-retention, which is fully non-volatile for at least 10 years at room-ambient.

SYSTEM CONSIDERATIONS

When the control processor is turned on and off, power supply transitions between ground and operating voltage may cause undesired pulses to occur on data, address and control lines. By using WEEN and WEDS instructions in conjunction with a LO-HI transition on CS, accidental erasing or writing into the memory is prevented.

The duty cycle in conjunction with the maximum frequency translates into having a minimum Hi-time on the SK clock. If the minimum SK clock high time is greater than 1 J.ls, the duty cycle is not a critical factor as 10l')g as the frequency does not exceed the 250 kHz max. On the low side no limit exists on the minimum frequency. This makes it superior to the COP499 CMOS-RAM. The rise and fall times on the SK clock can also be slow enough not to require termination up to reasonable cable-lengths.

. Since the device operates off of a simple 5V supply, the signal levels on the inputs are non-critical and may be operated anywhere within the specified input range.

Vee

Vee 0.05/!oF

100 pF

GNOt-~""-"'"

LO-17. GO-G3. 01-03 TLlD/5286-1

FIGURE 1. NMC9306/COP494 - COP420 Interface

7-67

l> Z I

W W CO

co (W) (W) • Z

<C

Vee

AD '---"'IN1 SK.-----~~--~

SI ... -----tI-tl~1_t

STANDARD CE .---.... IIN2 COP ,.P Wii IN3 PROCESSOR DO t----+-+--......

iiii t----..... GO

IiRET RESET

-= ........ __ ..

TO OTHER ,.PI

FIGURE 2. NMC9306 - Standard p.P Interface Via COP Processor

ADD L..l ~ AD7 "l1li

, AD13 NSC800'M 1m

CPU WI! ALE

lOT/til iiEffi OUT

PAO ~ PA1 ~

PA2-7 ~

,.. ADO AD7 PAD

PA7

NSC810 PSD CE AD RAM PS7

iii 110 PeD

TIMER PeS ALE IOT/M RmT

'",,- ...... "l1li ,.. ~ .. "l1li

~ ~

"l1li ,..

PORTA 881TS

NMC9306 PORT B BANK BBITS

PORTC 681TS

TIMER·IN

TIMER-OUT

SK } DIlDO ' Common to all 9306's

6CS for 6- 9306's

• SK I. generated on port pin. by blt-aet and blt-c:leer operation. In eoftwara. A symmetrical duty cycle I. not critical

TL/D/5286-2

TL/D/5286-3

• CS I. aet In eonwara. To generate 10-30 m. wrlte/era .. the timer/counter I. uaed. During wrlte/era ... SK may be turned off.

FIGURE 3. NSC800TM to NMC9306lnterface (also Valid for 808S/808SA and 8156)

7-68

... ADD ,. DECODE

! , AD-A15 OO..ofl/L .. DO CE CID BIA NMC93D6

~ "" DATA BUS ,. 07 AD ~ .... BANK 1 MI ~ • BITS ... Mi A7 ~ PORT A 110 ~ (61

lORD lORD MK388D RD "" PliO CTRL ,. RD MKJ881

lBO CPU

iNf l801 PIO

lEI· BO 1..ofI/L ~

lEO· 87 ~ PORT B 1/0 ~ INTERRUPT

CONTROL LINES (3)

Z80-P10

AO A1

A2-A7

9306

SK } 01100 CS1-CS6

Common to all 9306's (Bank 1)

• Only used If priority Interrupt daisy chain Is desired .• Identical connection for Port B

NMC9306 BANKZ

(61

FIGURE 4. Z80 - NMC9306 Interface Using Z80-PIO Chip

DATA P2D P17 DI

NMC9J06 P23 DO '1

CLOCK P16 SK CSl

P15

P2. INS8048

Pl. A CSZ

P27 7.138 P13 B DECODER

P1Z CS9

DB8 EN

Pll

~-~:-CSZ

'-----CS9

TL/D/5286-4

TL/D/5286-5

* SK and DI are generated by software. It should be noted that at 2.72 ,.s/lnstruCtlon:The minimum SK period achievable will be 10.88,.s or 92 kHz, well within the NMC9306 frequency range.

• DO may be brought out on a separate port pin If desired.

FIGURE 5. 48 Series I4P - NMC9306 Interface

7·69

» z I

W W CO

co ('I) ('I)

I

Z c(

~ oBo oB7

":'

P20 P20

N{ P21 P21 P22 P22 P23 P23

IN58243 IN58048 110

\iii

EXPANDER P5

P6

PROG PRoG

liD P24 CS P7

.... CS CO --- A1 GO ---- AD 00 C1 ... DO IN58253 G1 ,. 07 01

C2

RiR G2

lOW 02

Expander outputs

Ol} (COMMON) SK

Port 4 .

Port 5-6

Port 7

CS1

CS2

CS3-CS10

00 (COMMON)

FIGURE 6. 8048 I/O Expansion

000 007

NMC93061 COP494

DO

5K

01

010 017

5

L..:I

o 51

S2

~-C

C

C53-C5611.. ,. CS7-C510~ ,.

0

TIMER 110

TL/D/5286-6

PARALLEL OUT SERIAL IN

CLOCK

PARALLEL IN SERIAL OUT

TLlD/5286-7

FIGURE 7. Converting Parallel Data Into Serial Input for NMC9306/COP494

7-70

SK

Min Max

tcVCLE 0 250 kHz

OJ DUTY CYCLE 25% 75%

tOIS 400 ns

t01H 400 ns

cs tess 200 ns

tCSHO ns

DO ... _____ Iro_l-~}-

tpoo 2!-,-s

tp01 2!-,-s

TL/D/5286-8

FIGURE 8. NMC9306/COP494 Timing

7-71

co C") C")

I

Z III(

THE NMC9306/COP494

Extremely simple to interface with any 1'P or hardware logic. The device has six pins for the following functions: Pin 1 CS· HI enabled Pin 2 SK Clock input for data bit

maneuvering Pin3 01 For instruction or data

input Pin 4 DO·· For data read TRI-STATE@

otherwise Pin 5 GND Pin 8 Vee For 5V power Pins 6-7 No Connect No termination required

Following an E/W instruction feed, CS is also toggled low for 10 ms (typical) for an E/W operation. This internally turns the VPP generator on (HI-LO on CS) and off (lO-HI on CS).

01 and DO can be on a common line since DO is TRISTATED when unselected DO is only on in the read mode.

USING THE NMC9306/COP494

The following points are worth noting:

1. SK clock frequency should be in the 0-250 kHz range. With most 1'PS in the 1-11 MHz range this is easily achieved when implemented in software by bit-set and bit-clear instructions, which take 4 instructions to execute a clock or a frequency in the 1 00 kHz range for standard 1'P speeds. Symmetrical duty cycle is irrele- . vant if SK HI time is ~ 21's.

2. CS low period following an E/W instruction must not exceed the 30 ms max. It should best be set at typical or minimum spec of 10 ms. This is easily done by timer or a software connect. The reason is that it minimizes the 'on time' for the high Vpp internal voltage, and so maximizes endurance. SK-clock during this period may be turned off if desired.

3. All E/W instructions must be preceded by EWEN and should be followed by an EWDS. This is to secure the stored data and avoid inadvertent erase or write.

4. A continuously 'on' SK clock does not hurt the stored data. Proper sequencing of instructions and data on 01 is essential to proper operation.

5. Stored data is fully non-volatile for up to ten years independent of Vee, which may be on or off. For all p'ractical purposes any number of read cycles have no adverse effects on data retention.

6. Up to 10,000 E/W cycles/register are possible. Under typical conditions, this number may actually approach 1 million. For applications requiring ,a large number of cycles, redundant use of internal registers beyond 10,000 cycles is recommended.

. 7. Data shows a fairly constant E/W Programming behavior over temperature. In this sense E2PROMs supersede EPROMs which are restricted to room temperature programming.

7-72

8. As shown in the timing diagrams, the start bit on 01 must be set by a ZERO - ONE transition following a CS enable (ZERO - ONE), when executing any instruction. ONE CS enable transition can only execute ONE instruction.

9. In the read mode, following an instruction and data train, the 01 can be a don't care, while the data is being outputted i.e., for next 17 bits or clocks. The same is true for other instructions after the instruction and data has been fed in.

10. The data-out train starts with a dummy bit 0 and is terminated by chip deselect. Any extra SK cycle after 16 bits is not essential. If CS is held on after all 16 of the data bits have been outputted, the DO will output the state of 01 till another CS lO-HI transition starts a new instruction cycle.

11. When a common line is used for 01 and DO, a probable overlap occurs between the last bit on 01 and start bit on DO.

12. After a read cycle, the CS must be brought low for 1 SK clock cycle before another instruction cycle can start.

INSTRUCTION SET

Commands Opcode Comments

READ 1 0000A3A2A1AO Read Register 0-15 . WRITE 11000A3A2A1AO Write Register 0-15 ERASE 101 00A3A2A 1 AO Erase Register 0-15 EWEN 111000 0 0 1 Write/Erase Enable ENDS 111000 0 0 Write/Erase Disable ···WRAl 111000 o 0 Write All Registers ERAl 111000 o 1 Erase All Registers

All commands, data in, and data out are shifted in/ out on rising edge of SK clock.

Write/erase is then done by pulSing CS low for 10 ms.

All instructions are initiated by a lO-HI transition on CS followed by a lO-HI transition on 01.

READ - After read command is shifted in 01 becomes don't care and data can be read out on data out, starting with dummy bit zero.

WRITE - Write command shifted in followed by data in (16 bits) then CS pulsed low for 10 ms minimum.

ERASE ERASE All- Command shifted in followed by WRITE All- Pulsing CS low for 10 ms. WRITE ENABLE/DISABLE - Command shifted in.

••• (This Instruction is not spaced on Data sheet.)

The following is a list of various systems that could use a NMC930S/COP494 A. Airline terminal

Alarm system Analog switch network Auto calibration system Automobile odometer . Auto engine control Avionics fire control

B. Bathroom scale Blood analyzer Bus interface

C. Cable T.V. tuner CAD graphics Calibration device Calculator-user programmable Camera system Code identifier Communications controller Computer terminal Control panel Crystal oscillator

D. Data acquisition system Data terminal

E. Electronic circuit breaker Electronic DIP switch Electronic potentiometer Emissions analyzer Encryption system Energy management system

F. Flow computer Frequency synthesizer Fuel computer

G. Gas analyzer Gasoline pump

H. Home energy management Hotel lock Industrial control Instrumentation

J. Joulemeter K. Keyboard -softkey L. Laser machine tool M. Machine control

Machine process control Medical imaging Memory bank selection Message c~nter control Mobile telephone

N.

O. P.

Q. A.

S.

T.

U.

V.

t

W. X.

Y. Z.

7-73

:J:-Z •

Modem W Motion picture projector W Navigation receiver 00 Network system Number comparison Oilfield equipment PABX Patient monitoring Plasma display driver Postal scale Process control Programmable communications Protocol converter Quiescent current meter Radio tuner Radar dectector Refinery controller Repeater Repertory dialer Secure communications system Self diagnostic test equipment Sona-Bouy Spectral scanner Spectrum analyzer Telecommunications switching system Teleconferencing system Telephone dialing system· T.V. tuner Terminal Test equipment Test system TouchTone· dialers Traffic signal controller Ultrasound diagnostics Utility telemetering Video games Video tape system Voice/data phone switch Winchester disk controller X-ray machine Xenon lamp system YAG-Iaser controller Zone/perimeter alarm system

N

~ Designing with I

z the NMC9817, « a 2nd Generation E2PROM

The NMC9817 offers the non volatile memory designer the following features: .

-16K bits of non-volatile storage organized as 2K x 8

- fully 5V only operation in all modes

- address, data and WE latches; upward and downward compatible with E2's, EPROMs, ROMs and SRAMs

- fast read access times

- direct microprocessor interfacing capability

-10,000 write cycles per byte open-drain ready/busy

-10 years data retention

The purpose of this application note is to detail the new features and the simple interface considerations inherent to using the NMC9817. '

The JEDEC 28 pin universal memory pin-out has been selected for the NMC9817. Figure 1 shows this pin-out and how it relates to other memory types. ,

This philosophy allows for interchanging memory types and to provide the required densities. E2PROMs can be mixed with PROMs, ROMs, RAMs or EPROMs. Upward or downward compatibility is possi~le in density selection, providIng great flexibility in system design requirements, even as they change through the' course. New features or upgrades can be added with minimal hardware modifications. With the 28 pin selected pin-out of the NMC9817, E2PROM devices from 4k to 128k will fit perfectly without external interface requirements. The pin-out also allows inserting 24 pin E2PROM devices because of common data, address and control pins.

Figure 2 shows a block diagram of the NMC9817.

The basic Constraints on 1st generation E2PROMs have been quite cumbersome. 10,000 erase/write cycies/byt~, 10 ms or more erase/write times, external 21V generation, lack

SRAM NOVRAM ROM EPROM E2PROM

8K 4K 8K 8K 4K J.. J.. J.. J..

256K 128K 256K 256K 128K

A14 NE NC Vpp ROY/BUSY Pinl I WE WE A14 PGM/A14 WE Pin27!

National Semiconductor Application Note 342 Masood Alavi November 1983

of on -chip buffers and latches have been the important generic considerations. Many support components have been essential to incorporate these requirements.

External programming voltage entailed either a DC-DC converter or a step down. voltage regulator (See AN-328). In addition, support circuitry for sequencing write cycles was necessary because 10ms erase/write time is a much longer period than a typical microprocessor cycle. This required external data and address latches and a counter to time out the erase/write periods. Analog pulse-shaping circuitry for, erase/write pulses is also an external interface requirement.

Figure 2 shows how all the above interface requirements are integrated on the NMC9817. This allows for a direct interface with any microprocessor capable of providing the required control signals. Even the generic constraint of 10ms write time has been efficiently designed around. To initiate a RAM like write cycle the microprocessor signals with a 100 ns WE pulse after CE is valid. Only one instruction is required to do so after which the intelligence in the NMC9817 takes care of the rest allowing the'microprocessor to execute other instructions while the E2PROM writes the byte. This is so because the NMC9817 contains all the necessary data in on-Chip latches. A ready/busy output is provided on pin ,1 which goes to logic low when the part goes into a write cycle and logic high when the write is done.

Not only can this pin be used to signal an interrupt to the microprocessor to put the E2PROM on or off line, it, also serves to optimize the best possible write time that a' part has. In other words, if the NMC9817 gets programmed in less than 10 ms, the ready/busy line output will allow the microprocessor to take advantage of this. This is implemented by a method referred to as multiple-hits of write pulses. Refer to Figure 3.

See Table 28 vee A12 27 See Table

A7 3 2& A13

A& 25 A8

A5 2A A9

A4 23 Al1

A3 7 22 DE A2 8 21 A10

A1 9 20 CE AD 10 19 1/07

1100 11 18 1/0&

1/01 12 17 1/05

i/02 13 1& 1/04

GNO 14 15 1/03

TUO/5477-1

FIGURE 1. Universal 28-Pln-out

7-74

V~r-____________________________ ~

DATA INPUTS/DUTPUTS 10/00-11/07 ~~ __________ VW __ G_EN~E_RA_J_OR __________ ~

CHIP ENABLE/OUTPUT ENABLE LOGIC

AUTOMATIC WRITE TIMING

AUTOMATIC ERASE lOGIC

y DECODER

X DECODER

INPUT LATCHES

INPUT/OUTPUT BUFFERS

Y GATING

16.384-BIT CELL MATRIX

TL/D/5477-6 FIGURE 2. Functional Block Diagram

WE v TL/D/5477-2

ROY/BUSY \ __ tw_p ---.If

TLlO/5477-3

FIGURE 3. Write Waveforms

As soon as the write pulse is detected by the device, the following sequence of events commences:

• Ready/busy goes low and puts the device off the microprocessor bus.

• A read before write is internally initiated to determine whether or not an Erase before write is required.

• If any zero is detected in the byte during the read a 5 ms max Erase cycle is initiated during which internal Vpp is raised to 21V. Following the Erase, a 5 ms max write cycle is executed.

7-75

• If all ones are detected in the byte during the read, the Erase before write cycle is skipped and a 5 ms max write cycle is executed.

• Once write is verified and completed, the ready/busy is raised to interrupt the microprocessor.

The above sequence allows for achieving fast write times without compromising data retention or data integrity.

l> Z I

W, ~ N

~~------------------------------------------------------------. ~ C") • z cc

For convenience in system design, full SV operation is designed in the NMC9817. This has been done by incorporating on chip a S-21V charge pump, a 21 volt regulator andpower up/ down sequencer to avoid inadvertent spurious writes. Regulation of the 21V internal supply is an important consideration. more so over temperature since it is directly related to endurance. Voltage spikes can cause early damage to the int~rity of the tunnel-oxides. .

Interface Requirements

Figure 4 shows the simple interface requirements in using the NMC9817. Besides the direct bus connections to the microprocessor, three or four (if ready/busy is used) connections are 'required viz CE to decoder, <5E to RD, WE to WR and ready/busy to an interrupt Ready/busy may be multiplexed for hardware handling. It can also be OR-tied if desired since it is an open-drain output; the slowest device will control the write time in such a case. .

FROM DECODER .

FROM lID

FROMD

TO INTERRUPT

AO-A10

IOIDo-17/D7

SYSTEM REQUIREMENTS •

Figure 5 shows a typical large system application with multiplexed ready/busy.

In summary. the NMC9817 has been deSigned as a monolithic solution to the problems that arose with the 1 st generation of E2PROMs. It attempts to establish a standard for future· E2PROMs, both from an electrical parametric viewpoint and ease-of-use system deSign considerations. It solves the follOwing problems that confronted the 1st generation E2PROMs:

1. A 21V external power supply.

2. A rise time restricted 10 ms wide minimum pulse for erase/write.

3. lack of on-chipaddress and data latches.

4. Absence of an interrupt ready/busy output.

S. Non integrated erase before write.

6. Non-upgradable package. .

NMC9817 E'PIIOM

5VDC.

n WE

RDY/I01Y'

AD-A10

10/DO-tr/07 GND

-NMCul7

REQUIREMENTS

TLlD/5477-4

FIGURE 4. Simple NUC9817 Interface Requirements

7-76

--a~BlfSYl

MUX ~ ~~2 ~ BUSYN

BifSvl

ADDRESS ... ) ,.

~ DATA .. \.. )

(/AP) .... y

(/AC) (CONTROLLER) CE ---..

OE-"

WR-"

BlfSYN

I

9817 BANKl

N -2 --1

FIGURE 5. A Typical NMC9817 System

7·77

I

9817 BANKN

N ~

2 ~

1

TLlD/5477-5

l> z I

CAl ~ N

fII

Section 8

Militaryl Aerospace

Military/Aerospace

Section Contents

Detailed Electrical Test and Burn-in Information ..................................... _ ... ___ ... _ .. _ ......... 8-3

883BIRETS™ Products ... _ ............................................................................ 8-4

8-2

Detailed Electrical Test and Burn·in information on the following MIL·STD·883, Class B tested memory devices may be found in Volume 2 of The Reliability Handbook. Screening is described in the brochure ''883BIRETS™ . Products from National Semiconductor," which follows.

MM2102AJ·Ll883B 1024·blt (1024 x 1) static RAM (NMOS)

MM2102AJ·4/883B 1024·bit (1024 x 1) static RAM (NMOS)

MM2114MJ·3/883B 4096·bit (1024 x 4) static RAM (NMOS)

MM2716QM/883B 16,384·bit (2Kx 8) UV erasable PROM (NMOS)

MM5290F·31883B 16,384·bit (16Kx 1) dynamic RAM (NMOS)

MM5290J·3/883B 16,384·bit (16Kx 1) dynamic RAM (NMOS)

NMC2147HF·3/883B 4096·blt (4K x 1) static RAM (NMOS)

NMC2147HJ·3/883B 4096·blt (4Kx 1) static RAM (NMOS)

NMC2147HJ/883B 4096·blt (4K x 1) static RAM (NMOS)

NMC27C16Q45/883B 16,384·bit (2Kx 8) UV erasable PROM (CMOS)




NMC27C32Q55/883B 32,768·bit (4K x 8) UV erasable PROM (CMOS)

NMC27C32Q65/883B 32,768·blt (4K x 8) UV erasable PROM (CMOS)

NMC2816ME·25/883B 16,384·blt (2K x 8) electrically erasable PROM (NMOS)

NMC2816ME·35/883B 16,384·bit (2Kx8) electrically erasable PROM (NMOS)

NMC2816ME·45/883B 16,384·bit (2K x 8) electrically erasable PROM (NMOS)

NMC2816MJ·25/883B 16,384·bit (2Kx 8) electrically erasable PROM (NMOS)

8·3

NMC2816MJ·35/883B 16,384·bit (2K x 8) electrically erasable PROM (NMOS)

NMC2816MJ·45/883B 16,384·bit (2K x 8) electrically erasable PROM (NMOS)

NMC9716E·25/883B 16,384·blt (2K x 8) electrically erasable PROM (NMOS)



NMC9716J·25/883B 16,384·blt (2K x 8) electrically erasable PROM (NMOS)

NMC9716J·35/883B 16,384·bit (2K x 8) electrically erasable PROM (NMOS)

NMC9716J·45/883B 16,384·bit (2K x 8) electrically erasable PROM (NMOS)

NMC9306J/883B 256·bit serial electrically erasable PROM (NMOS)

NMH2864D/MP 65,536·bit (8K x 8) E2PROM module

NMH9764D/MP 65,536-bit (8Kx8) E2PROM module

FUTURE MIL/AERO MEMORY PRODUCTS

As the following products become available, they will be submitted to our MIL·STD-883, Class B qualification program and will be offered as MIL·STD·883 Class B devices:

NMC27C64 65,536·bit (8K x 8) UV erasable PROM (CMOS)

N M C27C256 262,144·bit (32K x 8) UV erasable PROM (CMOS)

NMC3764 65,536·bit (64Kx 1) dynamic RAM (NMOS) NMC6164 65,536·bit (8Kx 8) static RAM (CMOS

with NMOS cells) NMC9346 1024·bit (64 x 16) serial electrically

erasable PROM (NMOS) NMC9817 16,384·bit (2Kx 8) electrically erasable

PROM with 5V programming (NMOS) NMC98C64 65,536·bit (8Kx 8) electrically erasable

PROM with 5V programming (NMOS)

National Semiconductor 883B/RETSTM

Products

from National Semiconductor

8·5


883BIRETS™ Integrated-Cir~uitsFrom National

1.0 SCOPE

1.1 PURPOSE

This document establishes the requirements for screening, processing, qualification, and quality conformance testing of monolithic integrated circuits in accordance with Class B of MIL-STD-883.

1.2 INTENT

The program defined herein is intended to provide standardized, off-the-shelf integrated circuits manufactured and tested in full compliance with MIL-STD-883.

2.0 APPLICABLE DOCUMENTS

The following specifications and standards; of the Issue in effect on the date of invitationJor bids or request for proposal, form a part of this specification to the extent specified herein. National Semiconductor reserves the right to change any or all of the requirements stated herein .inord~r to update those requirements in accordance with changes in the applicable military specifications. -

2.1 SPECIFICATIONS

MIL-M-38510 General Specification for Microcircuits MIL-M-55565 Microcircuits, Packaging of MIL-Q-9858 Quality System Requirements MIL-C-45662 Calibration System Requirements

2.2 STANDARDS

MIL-STD-105 Sampling 'Procedures and Tables MIL-STD-883 Test Methods and Procedures for

Microelectronics MIL-STD-977 Test Methods and Procedures for Line

Certification

2.3 HANDBOOKS

MIL-HDBK-217 Reliability Prediction of Ele9tronic Equipment

MIL-HDBK-263 Electrostatic Discharge Control Handbook

2.4 DETAIL SPECIFICATIONS

The applicable detail specification for a particular 883B/RETS microcircuit is the National Semiconductor RETS (Reliability Electrical Test Specification, see Figure 1) for that device. The RETS is a detailed listing of the parameters, test conditions, test limits, and applicable test temperatures which apply to electrical screening, Group A Quality Conformance Inspection,

, and electrical end points for other Quality Conformance Inspections. In addition, the RETS provides information relative to certain electrical characteristics which are of interest to the designer but are not directly measured.

883B1RETS Is a trademark of National Semlc~nductor Corporation.

Bifet Is a trademark of National Semiconductor Corporation.

2.5 ORDER OF PRECEDENCE

In the event of a conflict between this document and any of the references cited herein, the precedence in which requirements shall govern, in descending order, is as follows:

1. The applicable detail specification; 2. This document; . 3. MIL-STD-883; 4., MIL-M-38510; 5. Other documents listed in 2.1 through 2.3;

except that all differences between processing done herein and that specified in MIL-STD-883 must be clearly noted either in this document or in the applicable detail specification (as applicable).

3.0 GENERAL REQUIREMENTS

Only integrated circuits which have met the screening, , quality conformance and qualification procedures de

fined herein shall be shipped as 883B/RETS products.

3.1 TERMS, DEFINITIONS, AND SYMBOLS

All terms, definitions, and symbols shall be as specified in MIL-M-38510, except that the qualifying activity shall be National Semiconductor Corporation.

'3.2 QUALIFICATION

Integrated circuits furnished under this document shall be products which have passed the qualification testing defined in Paragraph 6.0 herein.

3.3 LINE CERTIFICATION

Integrated circuits furnished under this document shall be produced exclusively on those lines certified by the National Quality Assurance Department for the manufacture and test of Military/Aerospace products. The'MIL-M-38510 requirement that all devices be manufactured, assembled, and tested within the U.S.

. shall not apply.

3.4 SCREENING

Integrated Circuits furnished under this document shall have been subjected to and shall have passed all of the screening indicated in Paragraph 4.0 herein.

3.5 QUALITY CONFORMANCE INSPECTION

Integrated circuits furnished under this document shall come from lots which have been subjected to and have passed the Quality Conformance Inspection requirements defined in Paragraph 5.0 herein. The frequency of Quality Conforman'ce Inspection shall be as defined in MIL-STD-883 and MIL-M-38510.

3.6 TRACEABILITY

Lot traceability shall be maintained in accordance with MI L-M-3851 O.

8-6

Pagc 3 of 5

-----ji[is/S3',X' .--.--------- r' -.. . ---- - .-------.- ---------j---IIESfSYSTlM:-r£MDYNEJu31-oPffON--'--1 IIISll:ONIlIIIONS(UNIISSOlllI.RWISE I I Ol:PAHAMUI,HS IORln I I

H(VISION 8C ISP[CllllO) I I I LIMITS I I N I I I sliGRpTISI\GHP2TsliGRPlI (25°C) IUNITSI

~ 'PMIAMfHk------IS'lH-I--I--'------" I I N~~~c6 I +~~~~c6 I -55°C I I

I ~ I I I Vl:C I ITEST # Imin-[max-tm'iilliTiiXlmTnTmax-1 I

1--,ILogiciiT."i"-Olitii~tVOillil_:5v-h6ir'~nlA~-vO--:;-v~-O;_-----12~t-2:1d--t-T.-4_t--t2~t I V I I I vo I tag" I I I VO = VllO = 4V (Rcvr) I I I I I I I I I I I I (ll.5V IIBUS = -~.2mA, VO = .8V, VX ~ 0, 161,62, I 2.41 I 2.41 I 2.41 I V I I I I I I VOR = IIV, VIII) = 0 (Orivcr) 165,66 I I I I I I I I

1--it:,,-gii:iii"o"--OutPiit-"/vOL k-Sv-I i6L-;-16mil~il-;-vi5D---;-;jV;--,-,---b,25-· -H---:-ill--J -.-IjI--I-.-41 V I I I Voltagc I I I VllH = U (Rcvr) I I I I I I I I I I I'I.W IIBUS = 50mA, VO = 2V, VX = 0, 160,63, I I .51 .51 I .51 V I I I I I VOII = W, VOO = 0 164, 67 I I I I I I I I I (l1.5V IIOL = ;:>mA, VOO = .BV, VOH = 0, 1106 I I .111 .41 I .41 I I I I I VlJ = W ( 0 rive r ) I I I I I I I

V

I I I 14.5V IIOL = 2mA, VOH = .8V, VOO = 4V, 1105 I I .41 .41 I .41 I I I I I VB = IIV, V[) = 0 ( Rev r) I I I I I I I

V

I----1MaximUii1uus-curi'CiitITBus-k-5V!v~iiV~-;-O:vDO VUH - 4V 11i6:rr--l--l 801 8ol-I--t--1--;;:8';;'0-t--1----l-U-.A,--I I I I OV I VB = 4V, VO = VOO = VOR = 0 147,52 I I 60 I 60 I I 80 I uA I I I 1~.5V IVB = .W, VOo = VOR = W 1130 I I -401 -1101 I -401 uA

1--hoglcaTn .... lnput-~+njT1I5:W-_tviN~iN;--Vfio = VDir~6rlverd~--1 401 40+1-, -+!-..4:n0+1---+--,U""A;-I I Current I 15.~V IVIN = 2.W (Oisable)ll0l I I 401 401 I 401 uA I I 111112 15.5V IVIN = 5.5V, VllD = VOR = 0 (Driver) 172,75 I I 11 11 I 11 mA I I I 15.5V IVIN = 5.5V (Disable)ll02 I I 11 I 11 I 11 mA

1--ILOgicaT"on-filput-tnLk:-5V-1VfN~4V~D = Vli~ioriverrh~-hH-l.6t-1--t-I--;I;-.76+1----t-m::-;A;--I I Current I 15.5V IVIN = .W (Disablclll00 I 1-1.61 1-1.61 1-1.61 mA

I----1TriPlit Clampi~vrc-t5.5Vtn-N= -12mA,VlJlJ = VlJR = 4V (!Ius) I~O,51 1 1-1.51 1-1.51 1-1.51 I I Voltagc I 15.W IIIN= -12mA,VOO = VOR = 0 (Orivcr) 173,74 I 1-1.51 1-1.51 1-1.51 I I I I~.~v IIIN= -12mA (Oisable)ll03 I 1-1.51 1-1.51 1-1.51

I-Ioisabled Output hOZHI,I.~v IVOH - 2V, VIJIJ - 4V, VB = IIV, 11IJ4 I I 801 '801 I 801 I I Current I I I vo = 0, VOUT = 3V (Rcvr) I I I I I I I I I I (l1.5V IVOO = 2V, VOH = 0, VO = 4V, 1107 I 801 I 801 I 801 I I I I I VOUT = 3V (Driver) I I I I I I I I I I 15.5V Ivour = 2.W, Disable inputs at 2V 1251 I 1101 I 1101 I 1101 I, I I I I (Hcvr) I I I I I I I I I IIOll 15.5V IVOUT = .IIV, Disable Inputs at 2V 1250,253 I -401 I -401 I -401 I I I I I (Hcvr) I I I I I I I

I-~Short CirC"-i-t---hos-k~v lVOUI = O,-VB =-VOR - 0, 1110,111, -28t -70-' -281'-701 -261 -701 I I Current I I I VD=VOO=4V (Rcvr) 1114,115 I I I I I I I I I 15.5V IVOUT = 0, VD = 4V, VDO = von = 0 1116,117, -401-1201 -401-1201 -401-1201 I I I I I (Or i ve r) 1122, 123 I I I I I I I I .-l I I. I I I I I I I INOTE 6: Power dissipation must be externally controlled at elevated temperatures. I I I RETS7835X I I RR0066 les

3.7 DESIGN AND CONSTRUCTION

DEViCE: OS'1835 FUNCTION:

FIGURE 1. Sample RETS

3.8.1 INDEX POINT

QUAO TRI-STATE BUS TRANSCEIVERS

V, V V

uA

uA

uA

uA

mA

rnA

Design and Construction shall be in accordance with MIL-M-38510. Where differences exist, they shall be clearly noted in the applicable detail speCification. Design documentation shall be maintained on file.

3.8 MARKING OF MICROCIRCUITS

All marking shall be legible, complete, and shall meet the resistance to solvents requirements of MIL-STD-883, Method 2015. If any additional marking is used, it shall not intefera with the marking required herein. The following marking shall be placed on each device:

An index point, tab, or other marking shall be used to indicate the starting point for the numbering of leads or for mechanical orientation. It shall be so designed as to be visible from above when the microcircuit is installed in its normal mounting configuration. The electrostatic discharge sensitivity indicator (see 3.7.5) may also be used as the pin 1 identifier.

a. Index point (see 3.8.1) b. Part number (see 3.8.2) c. Inspection lot identification code (see 3.8.3) d. Manufacturer's identification (3.B.4) e. Electrostatic discharge sensitivity identifier

(see 3.B.5) f. Radiation hardness indicator, where applicable

(see 3.B.6)

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3.8.2 PART NUMBER

Each microcircuit shall be marked with the complete part number. The part number may be marked on more than one line, with "'883B" appearing on the second line. The part number shall be constructed as follows:

LM1234H/883B

LM 1234 H 883 B 11 ~l. Product Assurance Class ' L.: pr.ocessed in accordance with 883 Package designator

, Basic Part type Product Family Designator

3.8.3 INSPECTION LOT IDENTIFICATION CODE

Microcircuits shall be marked with a unique code to in· dicate the inspection lot from which they were taken. The basis for identification shall be the date of the first week in which devices from that inspection lot were sealed. The format shall be four (or five) digits, with the first two digits indicating the last two digits of the year, the next two digits indicating the week of seal (with a 0 prefix for weeks 1 through 9), and the final digit (where used) an alpha character to indicate the existence of more than one inspection"lot bearing the same basic in· spection lot code.

3.8.4 MANUFACTURER'S IDENTIFICATION

All devices shall be marked with the National Semicon· ductor logo, name, or trademark. The manufacturer's designating symbol (27014) need not be marked on the microcircuits.

3.8.5 ELECTROSTATIC DISCHARGE SENSITIVITY INDICATOR

Those microcircuits which are tested in accordance with Method 3015 of MIL·STD-883 and are found to be Category A devices, or those devices which are classified as Category A in lieu of testing, shall be marked with an isosceles triangle. (NOTE: MIL·M-38510 REQUIRES AN EQUILATERAL TRIANGLE.)

3.B.6 RADIATION HARDNESS ASSURANCE INDICATOR

Devices which have been tested In accordance with the radiation testing procedures defined in "Radiation Hardened Technologies from National Semiconductor" shall be marked with a ·RX suffix, where the X shall in· dlcate the radiation level to which the devices were tested (5 for 1x105 rads (Si), 6 for 1x106, 7 for 1x107).

3.8.7 MARKING LOCATION AND SEQUENCE

Marking location and sequence shall be in accordance with MIL·M-38510.

'3.8.8 MARKING ON CONTAINER

All of the markings indicated in 3.8 (except for the index point) shall be marked upon the microcircuit shipping container. In addition, the manufacturer's designating symbol (27014), the EIA·STD·RS-471 symbol for ESD sen· sltive devices, and (where applicable) the reinspection date code (see 3.9) shall also be marked on the shipping container.

3.9 PROCEDURE FOR LOTS HELD MORE THAN" 36 MONTHS

Microcircuits held by the manufacturer or by authorized distributors for a period exceeding thirty·six (36) months following the date of the inspection lot identification code, shall be reinspected by the manufacturer for all specified Group A inspection requirements. The devices shall retain the original inspection lot identification code, but the date code of reinspection shall be marked on the shipping container and in the certifying docu· mentation. Failure of any subgroup shall require 100% rescreening of the lot for the subgroup and removal from the lot of any device(s) failing the rescreening.

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3.10 WORKMANSHIP AND REWORK PROVISIONS

Workmanship and rework provisions shall be in accor· dance with MIL·M-38510.

4.0 SCREENING

Each microcircuit shall have been subjected and passed all of the screening tests detailed in Method 5004 of MIL·STD-883 (see Table I) in order to be acceptable for delivery. Devices which fail any test criteria in the screening sequence shall be removed from the lot at the time of observation or immediately at the conclusion of the test in which the failure was observed. Once reo Jected and verified as a test failure, no device may be retested for acceptance.

4.1 ELECTRICAL TEST PARAMETERS

Electrical Test parameters for interim and final elec· trical testing (see Table I) shall be as defined in the applicable detail specification (RETS). Applicable test temperatures shall be 25°C, 125°C, and - 55°C, unless otherwise specified in' the applicable detail specifica~ tion. Interim electrical test parameters are performed at the manufacturer's option.

4.2 PDA

All lots or sublots of microcircuits screened in accor· dance with this document shall be subject to a PDA (Percent Defective Allowable) for post·burn·in 25°C DC electrical test measurements. Lots failing PDA may be resubmitted to burn-in in accordance with 4.2.1. The ape plicable PDA shall be 5% for all devices.

4.2.1 LOTS RESUBMITIED FOR BURN·IN

Unless otherwise specified, lots and sublots may be resubmitted for burn·in one time only, provided the observed percent defective for 25°C DC measurements during the first submission does not exceed 20%. Re· submitted lots shall be kept separate from new lots, and shall be tested using a tightened inspection PDA of 3%.

5.0 QUALITY CONFORMANCE INSPECTION

Quality Conformance Inspection shall be conducted in accordance with the requirements of Groups A, B, C, and D of Method 5005. Inspection lot sampling shall be in accordance with Appendix B of MIL·M-38510. All lots submitted for quality conformance inspection shall have met the 100% screening requirements defined in 4.0 prior to submission (with'the exception of those subgroups for which eiectrical rejects may be used as test samples).

5.1 GROUP A INSPECTION

Group A inspection shall be performed on each lot to the LTPD levels indicated in Table II and shall consist of the electrical parameter tests defined by the applicable detail specification or RETS. Where no parameters are indicated as tested for a given subgroup, that subgroup will not be performed. The manufacturer reserves the right to combine subgroups for test purposes, provided the LTPD for the combined subgroup is equal to or less than the lowest L TPD specified for any of the subgroups so combined. If a lot is composed of multiple sublots, each sublot must pass Group A inspection as specified.

TABLE I: 100% Screening

1. Internal visual 2010, test condition B 100% External visual (Note 4) 2009 100%

2. Stabilization bake 1008 24 hrs. @ condition C min 100%

3. Temperature cycling 1010, test condition C 100%

4. Constant acceleration 2001, test condition E (Note 6) Y1

orientation only 100%

5. Visual inspection (Note 1) 100%

6. Initial (pre·burn·in) electrical parameters Per applicable device specification Op. at . mfr's

dis· cretion

7. Burn·in test 1015 160 hrs @ 125°C min 100% (or equivalent per Table I of Method 1015)

8. Interim (post·burn·in) electrical parameters Per applicable device specification 100%

9. Percent defective allowable (PDA) calculation See 4.2 All lots

10. Final electrical test Per applicable device specification (Note 5)

(a) Static'tests 100% (1) 25°C (subgroup 1, Table 2) (2) Maximum and minimum rated operating temp. 100%

(subgroups 2, 3, Table II) (b) Dynamic tests and switching tests 25°C 100%

(subgroups 4 and 9, Table 2) (c) Functional test 25°C (subgroup 7, Table 2) 100%

11. Seal 100% (a) Fine (Note 2) (b) Gross

12. Qualification or quality conformance inspection test (Note 3) sample selection

Note 1: At the manufacturer's option, visual Inspection for catastrophic failures may be conducted after each of the thermal/mechanical screens, after the sequence or after seal test. Catastrophic fail ures are defined as missing leads, broken packages or lids off.

Note 2: The fine and gross seal tests shall be performed separately or together in any sequence or order between steps 5 and 11, and they shall be per. formed after all forming and shearing operations on the terminals.

Note 3: Samples shall be selected for testing In accordance with the requirements of paragraph 5.0 and Tables 2 through 5.

Note 4: External visual Inspection shall be performed on the lot any time after step 11 and devices submitted to qualification and/or quality conformance testing shall undergo this testing prior to shipment.

Note 5: All devices whose lead finish is changed or reworked after final electrical testing shall be retested for subgroups 1 and 7 at a minimum.

Note 6: To·3 Devices use condition D Instead.

5.2 GROUP B INSPECTION

Group B inspection shali consist of the mechanical and environmental tests specified in Table III. Group Bin· spection shall be performed on each package type and lead finish for each week of assembly per assembly location. Alternately, Group B may be performed on each inspection lot, per package type, lead finish, and detail specification. Testing of one device type sublot in any subgroup shall be considered as complying with the requirements for that subgroup for ali device types covered by that Group B test. When Group B is per· formed per week of assembly, each sublot must be subjected to subgroup 4.

5.3 GROUP C INSPECTION

Group C Inspection shali consist of the die·related tests specified in Table IV. Group C tests are required for each

8-9

microcircuit group (see 5.3.1 and Table VI) and shall be performed on one device type or one inspection lot from each three months of production for each microcircuit group.

5.3.1 MICROCIRCUIT GROUP ASSIGNMENTS

A microcircuit group shall consist of devices utilizing a common fabrication technology to perform a similar cir· cuit function, utilizing the same supply, bias and signal voltages, and assembled using the same die·attach,and wire·bond methods. National's microcircuit group assignments as shown in Table VI.

5.3.2 GROUP C SAMPLE SELECTION

Samples for subgroups in Group C shall be randomly chosen from any inspection lot of a particular microcir· cuit group (see 5.3.1) which has been submitted to and

TABLE II: Group A Electrical Tests (Note 1)

Class B Subgroup (Notes 2 and 3) L TPD (Note 4)

Subgroup 1 2 Static tests at 25°C

Subgroup 2 3 Static tests at maximum rated operating temperature

Subgroup 3 5 Static tests at minimum rated operating temperature

Subgroup 4 2 Dynamic tests at 25 °C

Subgroup 5 3 Dynamic tests at maximum rated operating temperature

Subgroup 6 5 Dynamic tests at minimum rated operating temperature

Subgroup 7 2 Functional tests at 25°C

Subgroup 8 5 Functional tests at maximum and minimum operating temperatures

Subgroup 9 2 Switching tests at 25°C

Subgroup 10 3 Switching tests at maximum rated operating temperature

"-Subgroup 11 5 Switching tests at minimum rated operating temperature

Note 1: The specific parameters to be included for tests in each-subgroup'shall .be as specified in the applicable detail specification. Where no parameters have been identified in a particular subgroup or test within a subgroup, no group A testing is required for that-subgroup or tesno satisfy group A requirements. .' .

Note 2: A single sample may be used for all subgroup testing. Where the required size exceeds the lot size, 100% inspection shilll be allowed (see 30.2.5 of appendix B of MIL·M·38510). .

Note 3: Group A testing by subgroup or within subgroups may be per· formed in any sequence unless otherwise speCified.

Note 4: Maximum accept number allowed is 2.

has passed Group A quality conformance inspection. Testing of one device for each subgroup shall be con· sidered as complying with the requirements for that subgroup for all devices within the applicable microcir. cuit group. The product which may be accepted for delivery based upon a successful.completion of Group C testing shall be product within the tested microcircuit group with inspection lot identification codes of the 26 consecutive weeks beginning .with the inspection .Iot identification code of the successful Group C sample ..

5.4 GROUP D INSPECTION.- .

Group 0 Inspection shall consist of the package related testing shown in Table V. Group Dtests on each pack· age type shall be performed on devices from each six

8-10

months of production (based upon inspection lot iden· tification codes). Where the package tested is provided with more than one lead finish, each additional lead finish shall be subjected to subgroups 3, 5, and 7 of Group D.

5.4.1. G ROU P D SAMPLE SELECTION

Samples for subgroups in Group D shall be selected from any inspection lot containing the intended package and lead finish which has been submitted to and has passed Group A quality conformance inspection. The product which may ·be accepted for delivery based on a successful completion of Group D testing shall be product of the particular package type with inspection lot identification codes of the 36 consecutive weeks beginning with the inspection lot identification code of the successful Group D sample. Testing of a subgroup using a single device type enclosed in given package shall be considered as complying with the requirements of that subgroup for all device types utilizing that package and lead finish. Different device types may be used for each subgroup.

5.5 END POINT TESTS FOR GROUPS B, C, AND D

End point measurements and other specified post-test measurements shall be made for each microcircuit of the sample after completion of all other specified tests in each subgroup. The test limits for the end point measurements shall be the same as the limits for the respective Group A subgroup Inspections.

5.6 RESUBMISSION OF FAILED LOTS

Procedures for resubmission of lots failing Gr~up A, B, C, or D Quality Conformance Inspections shall be as specified in MIL-M-38510. .

6.0 QUALIFICATION TESTING

Qualification of individual device types or groups of related device types shall be accomplished by subject· ing them to and demonstrating that they meet all of the Group A, B, C, and 0 requirements of Method 5005 of MIL-STD·883. Qualification testing shall be performed on devices that have been screened in accordance with Paragraph 4.0.

6.1 END POINTS

Electrical end points shall be measured before starting and after completion of all tests in the subgroups of Groups S, C, and D for which electrical end point measurements are ,specified. Where no intervening tests have been performed, the final electrical measurements performed during 100% screening shall be considered as satisfying the requirement for testing prior to Group S, C, or D testing. End point measurements need not be recorded.

6.2 LOT SIZE

The inspection lot from which the qualification samples are to be selected shall contain a minimum of twice the number of devices required for the performance of the qualification testing.

6.3 QUALIFICATION STATUS

Two levels of qualifications shall exist. Levell and Level II. A Level I part shall be one which has successfully com·

TABLE III. Group B (Note 1)

Test MIL·STD·883 Quantlty/(Accept No.)

Method Condition or LTPD

Subgroup 1 (a) Physical dimensions (Note 2) 2016 2 devices

(no failures)

Subgroup 2 (a) Resistance to solvents 2015 4 devices

(no failures)

Subgroup 3 (a) Solderability (Note 5) 2022 Soldering temperature of 245 ± 5°C 15

or 2003

Subgroup 4 (a) Internal visual and 2014 Failure criteria from design and 1 device

mechanical (Note 7) construction requirements of applicable (no failures) procurement document

Subgroup 5 (a) Bond strength (Note 4) 2011 Test condition C or 0 15

Subgroup 6 (Note 3) (a) Internal water·vapor content 1018 1,000 ppm maximum water content at 100°C 3 devices (0 failure)

or (Note 6) 5 devices (1 failure)

Subgroup 7 (Note 8) (a) Seal 1014 As applicable 5

(1) Fine (2) Gross

Subgroup 8 (Note 9) (a) Electrical parameters Group A, subgroup 1 (b) Electrostatic discharge 3015 15(0)

sensitivity classification (c) Electrical parameters Group A, subgroup 1

Note 1: Electrical reject devices from the same inspection lot may be used for all subgroups when end·point measurements are not required, except devices being submitted to subgroup 7.

Note 2: 'Not required for qualification or quality conformance inspection where group 0 inspection is being performed on samples from the same inspec· tion lot. .

Note 3: Not required on National Products, since National does not use desiccants inside any packages.

Note 4: Test samples for bond strength may, at the manufacturer's option, unless otherwise specified, be randomly selected prior to or following internal visual (PRESEAL) inspection specified in method 5004, prior to sealing provided all other specifications requirements are satisfied (e.g. bond strength reo quirements shall apply to each inspection lot, bond strength samples shall be counted even if the bond would have failed internal visual exam). Unless otherwise specified, the LTPD sampie size for condition Cor 0 is the number of bond pulls selected from a minimum number of 4 devices, and for condition For H is the number of dice (not bonds) (see method 2011).

Note 5: All devices submitted for solderability test shall be in the lead finish that will be on the shipped product and which has been through the tempera· ture/tlme exposure of burn·in. In the case of hot solder dip or fused tin lead finishes, the burn·in screen may precede the soider dip or tin fusing operatlon.The LTPD for solderability test applies to the number of leads inspected except in no case shall less than 3 devices be used to provide the number of lead required.

Note 6: Test three devices; if one falls, test two additional devices with no failures.

Note 7: Test samples for internal, visual and mechanical shall be selected at any point following the seal operation.

Note 6: This test is not required if either the 100% screen or sample seal test is performed between 3.1.16 and 3.1.20 of method 5004.

Note 9: Unless otherwise speCified, test shall be performed for initial qualification and product redesign as a minimum. Alternately, devices may be classi·· fied as category A in lieu of testing.

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TABLE IV. Group C (Die· Related Tests)

MIL·STD·883 Test LTPD

Method Condition

Subgroup 1 (a) Steady state life test 1005 Test condition A, B, C, or D (1,000 hours at 125°C) 5

(Note 1) (b) End·point electrical Group A subgroup 1, 2 & 3 parameters per the

parameters applicable device specification

Subgroup 2 (a) Temperature cycling 1010 Test condition C 15 (b) Constant acceleration 2001 Test condition E min. (Note 3) Y 1 orientation only (c) Seal 1014 As applicable

(1) Fine (2) Gross

(d) Visual examination (Note 2) Group A subgroup 1, 2 & 3 parameters per the (e) End-point electrical applicable device specification

parameters

Note 1: See 40.4 of Appendix B of MIL·M·38510.

Note 2: Visual examination shall be in accordance with method 1010 or 1011.

Note 3: TO-3 Packages shall be tested to Condition D.

pleted all of the Group A, B, C, and D inspections. Where a device type that has not completed Level I qualification falls within a micrOCircuit group for which other devices have been qualified, and is manufactured in a package which has been qualified, it will be considered qualified fOr Level " (and therefore shippable) once it has successfully completed Group A and B testing. No device may remain on .. Level II status for more than one year without successfully completing qualification testing.

6.4 QUALIFICATION BY EXTENSION

Qualification by die-related testing or qualification by extension, where applicable, shall be in accordance with the procedures defined in MIL-M-38510.

7.0 PACKAGING

Packing and Packaging shall be in accordance with MILM-38510. All devices classified as Category A for electrostatic discharge sensitivity and so marked (see 3.7.5) shall be packaged In conductive material or packaged in antistatic material with an external conductive field shielding barrier.

8.0 DATA

All 883B/RETSTM microcircuits shipped shall I:)e accompanied by a Certificate of Conformance certifying their full compliance with the requirements of Methods 5004 and 5005 of MIL-STD-883 (as specified herein). Attributes data for the 100% screening and quality conformance inspection test data will not normally be provided but shall be retained on file for a period of three years from

8-12

the date of the inspection lot identification code (or in the case of the quality conformance data the inspection lot identification code of the last lot whose quality conformance test requirements were met by that lot).

9.0 MIL·HDBK-217 QUALITY FACTORS

Devices processed in accordance with the requirements defined herein meet Quality Level B-1 of Table 2.1.5-1 of MIL-HOBK-217 for failure rate modeling in accordance with MIL-HDBK-217.

10.0 HYBRID MICROCIRCUITS

Hybrid microcircuits are not processed in accordance with this document. For Class B hybrid microcircuits refer to "883B/RETSTM Hybrid Microcircuits from National Semiconductor."

11.0 CLASS S MICROCIRCUITS

National Semiconductor Corporation also maintains a program for providing integrated circuits processed to the requirements of MIL-STD-883, Class S. These procedures are defined in the brochures "883S/RETSTM Integrated Circuits from National Semiconductor" and "883S/RETSTM Hybrid Microcircuits from National Semiconductor."

12.0 LEAD FINISH FOR TO-3 (K) PACKAGE

When TO-3 packages with solder-dipped leads are provided to this document, the leads will be dipped only to .100 ± .050 inches from the seating plane.

TABLE V. Group 0 (Package Related Tests)

Test MIL·STD·883 Quantity/(Accept No.)

Method Condition or LTPD

Subgroup 1 (Note 1) (a) Physical dimensions 2016 15

Subgroup 2 (Note 1) (a) Lead integrity (Note 7) 2004 Test condition 82 (lead fatigue) 15 (b) Seal

(1) Fine 1014 As applicable (2) Gross

Subgroup 3 (Note 3) (a) Thermal shock 1011 Test condition 8 as a minimum, 15 cycles 15

minimum (b) Temperature cycling 1010 Test condition C, 100 cycles minimum (c) Moisture resistance (Note 8) 1004 (d) Seal 1014 As applicable

(1) Fine (2). Gross

(e) Visual examination Per visual criteria of method 1004 and 1010 (f) End·point electrical Group 8, subgroup 1, 2 & 3 parameters per

parameters (Note 4) the applicable device specification

Subgroup 4 (Note 3) (a) Mechanical shock 2002 Test condition 8 minimum 15 (b) Vibration, variable frequency 2007 Test condition A minimum (c) Constant acceleration 2001 Test condition E minimum (Note 11), Y1

orientation only (d) Seal 1014 As applicable

(1) Fine (2) Gross

(e) Visual examination (Note 5) (f) End·point electrical Group A, subgroup 1,2 & 3 parameter, per

parameters the applicable device specification

Subgroup 5 (Note 1) Test condition A minimum (a) Salt atmosphere 1009 15

(b) Seal 1014 As applicable (1) Fine (2) Gross

(c) Visual examination Per visual criteria of method 1009

Subgroup 6 (Note 1) (a) Internal water·vapor content 1018 5,000 ppm maximum water content at 100·C 3 devices (0) failures

or 5 devices (1 failure)

(Note 6)

Subgroup 7 (Note 1) (a) Adhesion of lead 2025 15

finish (Notes 9 and 10)

Subgroup 8 (a) Lid torque (Notes 1 and 2) 2024 5(0)

Note 1: Electrical reject devices from that same inspection lot may be used for samples.

Note 2: Lid torque test shall apply only to packages which use a glass·frit·seal to lead frame, lead or package body (i.e., wherever frit seal establishes hermeticlty or package integrity).

Note 3: Devices used In subgroup 3, "Thermal and Moisture Resistance" may be used In subgroup 4, "Mechanical".

Note 4: At the manufacturer's option, end-point electrical parameters may be performed after moisture resistance and prior to seal test.

Note 5: Visual examination shall be in accordance with method 10100r 1011.

Note 6: Test three devices; if one fails, test two additional devices with no failures. At the manufacturer's option, if the initial test sample (i.e., 3 or 5 devices) fails a second complete sample may be tested at an alternate laboratory that has been issued suitability by the qualifying activity. If this sample passes, the lot shall be accepted provided the devices and data from both submissions is submitted to the qualifying activity along with five additional devices from the same lot.

Note 7: For leadless chip carrier packages only, use test condition D.

Note 8: Lead bend stress. Initial conditioning is not required for leadless chip carrier packages.

Note 9: The adhesion of lead finish test shall not apply for leadless chip carrier packages.

Note 10: LTPD based upon number of leads.

Note 11: TO·3 Packages shall be tested to Condition D.

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TABLE VI. Microcircuit Group Assignments

Microcircuit Product

Group Microcircuit

Product Group

1 Standard TIL Logic 16 Regulator, Reference

2 Schottky TIL Logic 17 Other Linear

3 Bipolar RAMs 18 BiFETTM Amplifier

4 Bipolar PROMs 19 Other BiFET

5 Low Power TIL Logic 20 Bipolar Microprocessor

6 CMOS Logic 21 CMOS Microprocessor

7 HC CMOS Logic 22 CMOS COPS

8 CMOS RAMs 23 NMOS COPS

9 CMOS EPROMs 24 NMOS Microprocessors

10 MOS RAMs 25 Hybrid Switch

11 MOS EPROMs 26 Hybrid Driver

12 MOS E2PROMS 27 Linear Hybrid

13 Amplifiers 28 Not Assigned

14 Comparators 29 CMOS E2PROM

15 Interface 30 CMOS Gate Arrays

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Section 9

Reliability

Reliability

Section Contents

Introduction to the Reliability Military/Aerospace Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3

The A + Reliability Enhancement Program ................................................................ 9-12

MST™ Program The System Environment Approach to Memory Component Testing .... : ........................ 9-14

9-2

INTRODUCTION TO THE RELIABILITY MILITARY/AEROSPACE PROGRAMS

History

In the mid 1960's the various government agencies responsible for semiconductor reliability saw that screenable defects were resulting in an in-equipment failure rate of about 1 % per thousand hours_ In-depth failure analysis allowed them to determine what the predominate failure mechanisms were. The Solid State Applications Branch of the Air Force's Rome Air Development Center (RADC) was assigned the task of developing a screening procedure which would remove the infant mortality failures which had led to the nigh failure rate previously encountered. Working closely with other semiconductor reliability e~perts, the RADC staff developed MILSTD-883, which was first issued in 1968. The objective of MIL-STD-883 was to create an economically feaSible, standardized integrated circuit screening flow which would achieve an inequipment failure rate of 0.08% per thousand hours for Class Band 0.004% per thousand hours for Class A (which was later superseded by Class S). Over the years this standard has grown and matured with a number of new test methods added as reliability information and failure analysis results became more detailed. These developments have led to one of the strongest and most comprehensive screening specs available, MIL-STD-883.

Purpose and Structure

MIL-STD-883 states: this standard establishes uniform methods and procedures for testing microelectronic devices, Including basic environmental tests to determine resistance to deleterious effects of natural elements and conditions surrounding military and space operations, and physical and electrical tests_ What does this mean to the semiconductor user? To understand this, one must subdivide MIL-STD-883 into two primary areas: 1) Detailed how-to specifications (methods 1001 through 4007) and 2) Screening and qualification andlor quality conformance testing requirements (methods 5001 through 5009). By eX'amining each of these areas the thrust of MIL-STD-883 will become apparent.

Detailed How·to Specifications

MIL-STD-883 is a collection of environmental, . mechanical, visual, and electrical test methods. These methods define tests which enable manufacturers and users to screen for specific reliability concerns. The tests covered include moisture reSistance, high temperature storage,

9-3

neutron irradiation, shock and acceleration tests, visual radiography, and dimensional tests, to mention only a few. In the electrical test section, there are tests to examine load conditions, power supplies, short circuit currents, and other tests. Each of these tests is designed to look at specific reliability and quality concerns that affect semiconductor products.

Screening Flows

The overall reliability requirements for a system depend upon a numbe'r of factors, including cost-effectiveness. For example, a deep space probe, where component replacement is impossible once the system is launched, requires very high reliability, despite the inherent cost of complex screening. On the other hand, a groundbased radio unit can use a less stringent reliability testing sequence, since a failed component can be easily replaced at moderate cost. In line with this range of needs, MIL-STD-883 established three distinct product assurance levels to provide reliability commensurate with the product's intended application. The three levels are Class S (intended for critical applications, such as space), Class B (intended for less critical applications, such as airborne or ground systems), and Class C (intended for easily replaceable systems, which has since been eliminated).

National and MIL·M·38510

A major thrust exists among integrated circuit users, suppliers, and the U.S. Government to avoid proliferation of military procurement specifications by turning instead to standardized high reliability microcircuits. National Semiconductor endorses and supports this trend.

One major program to which National is heavily committed is the JAN MIL-M-38510 IC program. This is a standardization program administered by the U.S. Defense Department which allows a user to purchase a broad line of standard prod- . ucts from a variety of qualified suppliers.

There is only one MIL-M-38510 program. National is committed to supplying only OPL devices, and discourages any "pseudo-38150" alternates .

There are two levels specified within MIL-M-38510 - Classes Sand B. Class S is typically specified for space flight applications, while Class B is used for aircraft and ground systems.

MIL·M·38510

The Defense Electronic Supply Center (DESC) administers the integrated circuit standardiza· tion program known as MIL·M·38510 (sometimes referred to as the JAN IC Program). The specifi· cation set used to define the program consists of four documents: general specification MIL·M· 38510, which is an overall definition of the pro· cessing and testing to be performed; detail specifications (referred to as "slash sheets"), each of which defines the performance parameters for a unique generic device or a family of devices; MIL-STD·883, which defines specific screening procedures; and MIL-STD·976, which defines line certification requirements.

When a user orders a MIL-M-38510 device, he is guaranteed that he will get a device fully con· formant with the detail specification and which has also met all of the general testing and processing requirements. DESC requires semiconductor suppliers to become formally qualified under the MIL-M-38510 program and to be listed on the current Qualification Products List (QPL) before they are allowed to legally ship JAN devices.

Advantages to the User

The JAN 38510 program has numerous advantages for the integrated circuit user.

• A single explicit speCification eliminates guesswork concerning device electrical characteristics or processing flow.

• The rigorous schedule of quality conformance testing that is a mandatory part of the MIL·M-38510 program assures the user of long-term stability.

• Since the electrical characteristics of the devices are at least as tight as the "standard industry data sheet" parameters, device per· formance will meet the vast majority of system design requirements. Additionally, min.lmax. limits replace many data sheet typicals, making circuit design and worst case design analysis decisions easier.

• The user is spared the expense of researching and preparing his own procurement document.

• The user is spared the expense of qualification testing. The QPL tells him which suppli· ers have qualified the device he requires.

• The QPL gives the user a choice of qualified suppliers for devices that are fully interchangeable. In addition, the presence of several sources guarantees competitive pricing that· is typically lower than for devices to a user's own speCifications.

9·4

• Since MIL-M-38510 is a standard program, procurement lead times will be shorter. With a large number of programs using JAN devices, distributors and manufacturers are able to establish inventories of JAN devices. National in particular is committed to maintaining finished goods and work·in·process inventories to support our customers' needs.

• Spare parts will be readily available without excessive minimum order requirements. "

• Standard parts with volume requirements will remain in production longer.

• Device markings are consistent from one manufacturer to another.

• The program is extremely cost-effective. A user can purchase a few devices for engineering evaluation and prototyping and know that they will be identical to the devices he will get during production. When the cost factors as· sociated with spec. writing, supplier qualifica· tion, maintaining voluminous parts control documentation, and the more intangible benefits of device availability are totaled, use of JAN ICs is overwhelmingly the most costeffective approach.

Advantages to the Supplier

What motivates a supplier like National Semi· conductor to be so heavily committed to the MIL-M·38510 program? National has the broadest range of reliability processed products available in the semiconductor industry. A program such as MIL·M-38510 helps to standardize the processing required and to minimize the number of individual user specifications. This allows National to concentrate more resources on this program, thereby improving product quality and availability.

The Most Frequently Asked Questions and Answers about MIL·M·38510

"There are many questions which are frequently asked regarding the MIL-M·38510 program. We would like to answer some of them.

Q. WHAT MUST A MANUFACTURER DOTOGET HIS PARTS LISTED ON THE QPL?

A. There are two things which a manufacturer is required to do. First, he must get his facilities (including wafer fab, assembly, and rei processing areas) certified by DESC. This reo quires that each fab area used for QPL de· vices must be approved. Second, fOf each specific device and package combination listed on the QPL, the manufacturer must perform extensive qualification testing and provide detailed device information to DESC. This data is typically supplied in two phases.

In the first phase, the manufacturer must supply detailed information concerning the device construction and electrical characteristics. Once this data has been verified by DESC to confirm that the manufacturer's device meets the MIL·M-38510 requirements, the manufacturer is listed on Part II of the QPL. At this point the manufacturer is legally able to supply full JAN qualified devices meeting ALL of the MIL-M-38510 requirements. The manufacturer must then perform the full qualification testing of Method 5005 of MIL·STD·883 as specified in paragraph 4.4 of MIL·M·38510. Once this data has been

'reviewed and accepted by DESC, the manufacturer is listed on Part I of the QPL.

Q. IS THERE ANY DIFFERENCE IN DEVICES PRODUCED WHILE A MANUFACTURER IS LISTED ON PART II OFTHE QPLANDTHOSE PRODUCED AFTER PART I QUALIFICATION IS COMPLETED?'

A. There is absolutely no difference. A supplier must meet all of the device screening and quality conformance requirements no matter what his QPL status.

Q. HOW DOES A USER KNOW WHAT DEVICES ARE COVERED BY SLASH SHEET SPECIFICATIONS?

A. Supplement 1 to MIL·M-38510 contains a listing of the slash sheet specifications and a cross reference to the generic part type. This

, is updated as new slash sheets are released. National's Reliability Handbook also contains a cross reference.

Q. HOW CAN A USER OBTAIN COPIES OF THE QPL, SUPPLEMENT 1 OF MIL~M-38510, MILM-38510 ITSELF, AND MIL-STD-883?

A. Copies of these and other related documents may be obtained from:

Naval Publications and Forms Center 5801 Tabor Avenue Philadelphia, PA 19120 (212) 697-2179

Q. WHAT ABOUT THOSE DEVICES FOR WHICH NO DETAIL SPECIFICATION EXISTS?

A. The ultimate aim of a standardization program must be to furnish all parts. Requests for addition of a part to MIL-M-38510 should be made to DESC Directorate of Engineering, Dayton, Ohio 45444, indicating a need for slash sheets andlor suppliers to be qualified for the additional devices. National has a form (available through local sales offices) which may be used for this purpose. In addi· tion, if only some parts are available, a user can still see significant savings on those that are available.

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Q. HOW IS A JAN QPL DEVICE MARKED?

A. Tables I and II explain the details of the mark-ing for JAN ICs. .

TABLE I. MIL-M-38510 Part Marking

~~~/XXXXXYYY

L the Lead Finish A = Solder Dipped B=Tin Plate C = Gold Plate X = Any lead finish above

is acceptable

'- the Device Package (see Table II) ,

'--- the Screening Level S or, B

'---- the Device Number on the Slash Sheet

'-----the Slash Sheet Number

'-------MIL·M·385810

'---------The JAN prefix (which may be applied only to a fully conformant device per paragraphs 3.6.2.1 and 3.6.7 of MIL-M·38510)

TABLE II. JAN Package Codes

38510 MICROCIRCUIT INDUSTRY PACKAGE

DESIGNATION DESCRIPTION

A 14'pin 1/4"x 1/4" (metal) flatpack' B 14·pin 3/16" x 1/4" flatpack C 14'pin 114" x 3/4" dual-in·line D 14·pin 114" x 3/8" (ceramic) flatpack E 16·pin 1/4" x 7/8" dual·in·line F 16-pin 1/4" x 3/8" (metal or ceramic)

flatpack, G 8·pin TO·99 can or header H 10'pin 1/4" x 114" (metal) ilatpack I 10'pin TO·100 can or header J 24-pin 112" x 1·114" dual·in·line K 24-pin 3/8" x 5/8" flatpack M 12'pin TO·101 can or header,' P 8-pin 1/4" x 3/8" dual·in·line a 40'pin 8/16" x 2·1/16" dual·in·line

'R 26'pin 1/4" x 1·1/16" dual·in·line S 20'pin 1/4" x 1/2" flatpack V 18'pin 3/8" x 1·15/16" dual·in·line W 22·pin 3/8" x 1-1/8" dual-in·line

n Unassigned - Reserved for identifying special packages whose dimensions are carried in the detail specifications.

Q. ARE DEVICES CALLED "M38510, JAN PROCESSED, JAN EQUIVALENT, ETC." REALLY QPL PRODUCTS?

A. Absolutely not. There is only oneQPL product - it is a JM38510 marked device. "JAN Equivalent" is expressly forbidden by para-

graphs 3.1 and 3.6.7 of MIL·M·38510. MIL·M~ 38510 does provide for the production of devices when no qualified sources exist, but this may be done only with prior DESC ap· proval, and products produced under this provision must meet all requirements of MIL· M·38510 other than qualification. .

Q. HOW LONG CAN A SUPPLIER REMAIN ON PART II OF THE QPL?

A. For Class B, a manufacturer can remain on Part II for two years or until 90 days after another supplier becomes qualified for the same device package, screening level, and lead finish combination on Part I of the QPL. Class S devices may remain on Part II for one year after another manufacturer reaches Part I. '

Q. WHEN ANOTHER SUPPLIER OBTAINS PART I QUALIFICATION, ARE THE OTHER QUALI· FlED SUPPLIERS REMOVED FROM PART II IMMEDIATELY?

A. No. The supplier is given 90 days before being removed from Part II for a Class B de· vice and one year for a Class S device. During that time a supplier may legally accept orders for those devices. After the end of the 90·day or one year period, he may no longer accept orders but may complete and ship those or· ders received prior to that time, no matter how long it takes him to complete them.

Q. IS A SUPPLIER EVER REMOVED FROM PART I QUALIFICATION?

A. Generally not. As long as a supplier contino ues to manufacture the device, maintains ap· propriate facility approvals, and submits all required reports and information to DESC within stipulated time limits, he will retain QPL I listing. Violation of these requirements can be cause for removal from QPL.

Q. CAN AN AUTHORIZED DISTRIBUTOR SHIP JAN DEVICES FROM HIS SHELVES IF THE MANUFACTURER HAS LOST HIS QPL LIST· ING FOR THOSE DEVICES?

A. Yes. As long as those devices were .ordered by the authorized distributor while the manu· facturer had QPL listing for those devices, the distributor may subsequently ship those devices from his shelves.

Q. CAN A MANUFACTURER LEGALLY SHIP JAN QPL MATERIAL'HE ASSEMBLED AND TESTED BEFORE HE RECEIVED A QPL LISTING?

A. Yes. The manufacturer must assemble and screen parts to prove his ability to comply with the speCifications before he can be

.' placed on QPL. As a result, his first lot of

. material, which is fully conformant to QPL

9-6

product requirements, will have a date code that is earlier than the date he is placed on the QPL. However, the manufacturer may not begin to assemble and test unless he has a line certification and an approval to proceed with qualification.

Q. WHAT IS THE RELATIONSHIP .BETWEEN MIL·M·38510 AND MIL·STD·883?

A. MIL·M·38510 defines complete program requirements and the detail device electri· cal performance parameters. The device processing requirements are specified in MIL·STD·883.

Q. SUPPOSE DEVICES ARE KEPT ON A MANU· FACTURER'S .oR DISTRIBUTOR'S SHELVES FOR A PERIOD OF TIME; MUST THEY EVER BERETESTEI) TO VALIDATE THAT THEY STILL MEET SLASH SHEET CHARACTER· ISTICS?

A. Yes. Devices held by a manufacturer orby his authorized distributor which have a date code older than 24 months must be retested

. by the manufacturer in accordance with Group A sampling requirements prior to ship· ment to a customer or return to inventory.

Q.WHY SHOULD A USER SPECIFY "X" IN THE LEAD FINISH DESIGNATION FOR A PART TYPE?

A. A manufacturer who receives an order for a specific lead finish for which he is qualified but has no inventory at the time of order may not be able to fill the order in a timely man· ner, even though he might have substantial inventory of another lead finish. Unless a user has a specific reason for wanting a par· ticular lead finish, he should, ailow' his sup· pliers the flexibility of shipping whatever finish is available.

Q. WHAT DATA IS A MANUFACTURER RE· QUIRED TO SHIP WITH A JAN PART?

A. A certificate of conformance is all that is reo quired. However, he must retain all data for three years.

Q. CAN· A DEVICE FOR WHICH THERE IS NO SLASH SHEET BE PROCESSED TO MIL·M· 38510?

A. Since MIL·M·38510 invokes a combination of the processing requirements of MIL·STD·883 and the detail device performance paramo eters contained in each individual slash sheet, the answer is obviously no. However, National's 883B/RETSTM program does pro· vide parts which meet all of the screening requirements of the MIL·STD·883 specifica· tion and which have been subjected to all of the MIL·M·38510 controls (except for domestic. assembly).

TABLE III. Sample MIL·M·38510 Listing

GOVERNMENT DESIGNATION TEST REPORT MANUFACTURER'S NAME DEVICE DEVICE CASE LEAD MATERIAL NUMBER

TYPE* CLASS OUTLINE AND FINISH

.M3851 0/008 01 S only A C 38510·953·81 National Semiconductor Corp.

01 B C A 38510·953·81 National Semiconductor Corp. 02 0 B 38510·30· 7T

03 B C A 38510·520·83 National Semiconductor Corp. B

·"M38510" is the military deSignator for MIL·M·38510. The QPL shows this notation even though the parts are fully qualified devices and are marked JM38510IXXXXXYYY.

Q. WHAT DOES A QPL LISTING LOOK LIKE AND HOW DO YOU READ IT?

A. Sample QPL listings are shown in Table III.

JM3851 0/00801 SAC JM3851 0/00801 BCA JM3851 0/00801 BCB JM3851 0/00801 BOA JM3851 0/00801 BDB JM38510/00802BCA J M3851 0/00802BCB JM38510/00802BDA J M3851 0/00802BDB JM38510/00803BCA JM38510/00803BCB

Q. WHAT QUALITY CONFORMANCE TESTS ARE CONDUCTED? ARE ALL DEVICES IN A GENERIC FAMILY EVENTUALLY SUB· JECTED TO QUALITY CONFORMANCE TESTING?

A. For B level devices quality conformance tests must be conducted as follows:

Group A-Each inspection lot or sublot.

Group B-Each inspection lot for each pack· age type and lead finish on each detail specification.

Group C-Periodically at 3·month intervals on one device type or one inspec· tion lot from each mircocircuit group in which a manufacturer has qualified device types (die related tests).

Group D-Periodically at a 6·month interval for each package type for which a manufacturer holds qualifications (package related tests).

Different devices within a generic family are chosen for successive quality conformance tests until all of the devices have been sub· jected to testing. The sequence is then reo peated. The manufacturer must submit attri· butes data to DESC for all quality confor· mance tests performed.

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Q. HOW IS AN INSPECTION LOT DEFINED?

A. For Class B devices, each inspection lot shall consist of microcircuits of a Single device type, in a single package type and lead finish, or may consist of inspection .sublots of sev· eral different device types, in a single pack· age type and lead finish, defined by a single detail specification. Each' inspection iot shall be manufactured on the same production

. line(s) through final seal by the same produc· tion techniques, and to the same device design rules and case with the same material requirements, and. sealed within the same period not exceeding 6 weeks.

Q. WHAT IS NATIONAL SEMICONDUCTOR'S COMMITMENT TO MIL·M·38510?

A. National Semiconductor is convinced that the level of standardization offered by a pro· gram like MIL·M-38510 is the key to long·term military component procurement viability. We have a corporate commitment to MIL·M· 38510. We believe that the program will be of significant benefit in lessening the problem of product obsolescence, for the volume pro· vided will help to keep many key devices in production. We believe that the program will make possible the procurement of devices in small quantities with reasonable lead times for long·term spares or field maintenance requirements.

National Semiconductor will continue to maintain a broad base of line certifications and an extensive list of Class B and Class S device qualifications. We will continue to work with the Department of Defense, con· cerned users, and other semiconductor man· ufacturers to update and redefine the. appli· cable specifications. We feel that this level of support is essential if MIL·M·38510 is to reo main the strongest standardization program available.

In addition, we will continue to add capacity and to build up substantial inventories of a large spectrum of products to ensure the

availability and the lead times that are needed for key military programs.

National Mil/Aero Standardization Programs

Your 'customer has imposed upon you requirements for product reliability that you must meet on every single component you buy. In most cases, these requirements mandate that you buy JAN MIL-M-38510 parts where they are available, and that all other devices must be as close to JAN as is achievable. We don't consider this unreasonable. In fact, we believe that this is the only reasonable and intelligent approach.

To meet this objective, we designed oLir 883B/ RETS program around requirements that were already imposed for the MIL-M-38510 program.· We realize that there are many so-called standardization programs avaiiable in the marketplace which lack the compliance that you need. Our 883B/RETS program is totally compliant. We invite you to make this comparison between what we offer and what you need. Our screening flow, our 5% PDA, our quality conformance test frequency, and the other items that you consider important, match exactly the requirements defined in MIL-M-38510." If they did not, we could not offer Total Standardization.

Standardization provides the manufacturing efficiencies needed by the semiconductor manufacturers if they are to meet military semiconductor needs. To the user, standardization offers the highest guarantee of quality and reliability through production consistency and uniformity. The most significant benefit of standardization to the Department of Defense, however, is that it ensures the availability of component level spares to key programs with the pricing, delivery, and reliability needed for the field support and maintenance of our key defense electronics systems.

National's MIL-M-38510 Emphasis

To implement this view of standardization, we have based our entire approach to military screening upon the Class S and Class B requirements of MIL-M-38510. We are convinced that to do less than this would be to provide an inferior product, one that does not meet the true needs of the Department of Defense. Our 883B/RETS microcircuits are processed through the most comprehensive and compliant Class B screening program offered by any semiconductor man-

·Requirements that were subsequently incorporated into MIL· STO·883

• ·and MIL·STO·883.

9·8

ufacturer. We have tried to emulate MIL-M-38510 to the fullest extent pOSSible, with the same production controls, calibration schedules, rework and resubmission procedures, operator certification requirements, and all ofthe other key elements ofMIL-M-38510. The procedures that we employ in the production of MIL-M-38510 devices are used for all of the military devices we manufacture.

Our 883S/RETS microcircuits are processed through a screening flow that matches the MIL-M-38510 Class S flow exactly. Our commitment to MIL-M-38510 Class S is such that once qualified for a given device type we will sell that part only as a JAN Class S part. Class S QPL listing will

. reslJlt in the immediate removal from production of the 883S/RETS version of the device.

National's Commitment

But compliance flows are obviously meaningless unless the capacity is in place to support them. We have the industry's largest screening capacity. Over the past few years we have reinvested substantial sums in additional capital equipment in both buildings and the equipment with which to fill those buildings. Our Tucson, Arizona plant was the first plant in the entire industry to be totally dedicated to the production of military integrated circuits. We will continue to add capacity for military assembly and test, even during those periods when others turn away from the military marketplace in pursuit of what they view to be the more attractive commercial market. We feel that a commitment to the needs of the military/aerospace user community should not be based upon the conditions encountered in the commercial marketplace. We have no plans for other than a continued longterm commitment to military/aerospace component production and screening. And we will not deviate from the highest standards of quality and reliability in our execution of that commitment. There are no shortcuts to semiconductor reliability. It can only be achieved through rigid adherence to established standards.

However, we also acknowledge the quite obvious fact that through refinement and redefinition, standards are subject to change. As those changes occur, we will update our current procedures to reflect the changes that find their way into MIL-M-38510 and MIL-STD-883. We will, where our understanding of semiconductor reliability and screening indicates the need, actively pursue those changes that we feel will allow our industry to provide a better product to the sys· tems manufacturers. We will also steadfastly resist those changes which we feel sacrifice reli ability to the less important question of expediency .

National's Standard Programs

MIL-M-38510 is the key military standardization program for ICs. National is equally committed to the support of the requirements of the space segment of the market for MIL-M-38510 Class S devices. To support these needs we have established dedicated Class S assembly and test facilities. The realization that users could not obtain all the device types they required through these programs led National's Military/Aerospace Products Group to the development of two of the strongest and most compliant inhouse programs in the industry. National programs for 883B/RETS and 883S/RETS microcircuits provide the systems manufacturer with an easy mechanism for obtaining those devices not listed on the MIL-M-38510 QPL. In response to other user needs, National also developed a program for radiation hardened devices (both CMOS and linear), a comprehensive program for radiation susceptibility testing for Class S devices, and a program for the production of devices in lead less chip carriers (LCCs).

RETS and Burn-In

One of the primary advantages of MIL-M-38510 is its clear definition and standardization of electrical test and burn-in requirements. One of the major drawbacks seen in the standard reliability screening programs of most semiconductor manufacturers is that electrical testing is invariably performed to some document that is not available to the user. The user has the right to know what he is buying. At National that testing is never vague or undefined. Both in-house programs (883B/RETS and 883S/RETS) are based upon a document called the RETS (an acronym for Reliability Electrical Test Specification. The RETS is a simplified but complete description of the testing performed as part of National's standard Rei electrical test programs, and is controlled by our QA department. The burn-in circuits and electrical test parameters for the MILM-38510 Class S and Class B devices produced by National Semiconductor are defined by the applicable detail specification.

Ordering ICs from National

Ordering National Semiconductor High Reliability integrated circuits is very simple. National sales offices and sales representatives can provide price and delivery information on our entire line of JM38510 Class B, JM38510 Class S, 883B/ RETS and 883S/RETS microcircuits. A large percentage of these devices are available from inventory at either the factory or at one of our many distributors.

9-9

Ordering to Control Specifications

We also acknowledge the fact that many military systems manufacturers must, for contractual purposes, maintain their own specifications for many of the devices that they purchase. We have no objection to the use of contractor prepared procurement specifications, for we have found that the majority of these documents are written in compliance with the requirements of MIL-M-38510. Where this is true, we have found that they are also totally compatible with our inhouse standardization programs. Where drawings submitted to National differ from the requirements outlined in MIL-M-38510, we welcome the opportunity to work with our customers to develop specifications which do meet the intent of MIL-M-38510.

Where customer specifications and our 883B/ RETS product specifications correspond, we have the ability to expedite delivery by adding the customer part number in addition to the basic 883B/RETS part number. Customers who understand our program and wish to use the program in their parts procurement may order by placing "M/O" after their part number on their purchase order, thus allowing us to mark their part number on our 883B/RETS devices without the lengthy delay normally required for a com-

. prehensive specifications review cycle. We have tried to provide programs that offer the maximum level of flexibility within the constraints of standardization.

Standardization is the key to cost-effective procurement of high reliability semiconductor devices. National Semiconductor Corporation is committed to that standardization.

Military Processing: A Corporate Commitment

The National Semiconductor Military/Aerospace Products Division draws upon the total resources of National Semiconductor. National is one of the world's largest manufacturers of semiconductor products, offering the largest number of product types available from any single source in the industry. This product line is growing faster than that of any other worldwide semiconductor manufacturer. Each new product is carefully evaluated for possible military/aerospace usage potential, and new product designs must comply with the reliability and quality constraints required by that segment of the industry. All new product designs are targeted to full military temperature range operation.

In addition, a dedicated Reliability Engineering Department within the Military/Aerospace Prod-

ucts Division coordinates burn-in circuit design, test tape development, test fixturing, support documentation, and new product release paperwork to ensure the earliest possible introduction of fully compliant 883B/RETS versions of the new products introduced by the company.

We are able to do this well, for National is no newcomer to this business. Founded in Danbury, Connecticut in 1959, National acquired an entire new management team in 1967 and moved corporate headquarters to Santa Clara, California. The new management team focused its attention on the transistor product line, and rapidly made that line profitable. Then the company's talents were turned to the development of linear,· digital, and MOS integrated circuits - the fastest-growing segments of the semiconductor marketplace. Finally, an OEM representative and distributor network was established to develop and service a broad customer base, and facilities were added around the world to provide

. competitive products to worldwide markets.

The Reliability Test Department was initially formed in 1968 and reported at that time to the Director of Quality Assurance. The Rei Department developed the same rapid growth rate that the company as a whole had shown. From a small staff occupying several thousand square feet in Santa Clara, these reliability test operations grew until today they employ over 3000 people worldwide. Well over 200,000 square feet are devoted to the testing and assembly of high reliability products. During 1981, the Military/ Aerospace Products Group became the Military/ Aerospace Products Division. The company is currently involved in a number of military research and development programs, including a Phase I VHSIC contract.

VHSIC involvement was natural since National's technological leadership has enabled the company to consistently be one of the major suppliers of military/aerospace semiconductors. Having continued to develop a high technology image through the development olf Megarad hardened CMOS and linear device types, and the development of TRI-CODETM logic, National is now expanding technology frontiers in the areas of memory, microprocessor, and data acquisi-

tion products. As a result of all this innovation, National has become the only company in the entire semiconductor industry capable of providing high reliability devices from all of the following product lines:

linear hybrid CMOS logic Megarad CMOS logic bipolar memory MOS RAMs CMOS RAMs MOS EPROMs CMOS EPROMs MOS EEPROMs data acquisition devices standard TTL low power TTL low power Schottky standard Schottky interface devices bipolar microprocessors MOS microprocessors CMOS microprocessors COPSTM microcontrollers high-speed CMOS Schottky advanced low power Schottky advanced Schottky

National Semiconductor has wafer fabrication plants in Santa Clara, California; Salt Lake City, Utah; Arlington, Texas; and Danbury, Connecticut. Many of these fabrication plants, along with our assembly and test lines in Santa Clara, California and Tucson, Arizona, have been fully certified for the production of Class S and Class B MIL-M·38510 circuits.

. To support the requirements of the Class S marketplace, we have our own SEM and radiation testing facilities. Our screening capabilities are backed up by one of the most extensive failure analysis labs in the industry.

9-10

National is the leader in the military/aerospace integrated circuit market. We have achieved that leadership by offering an unmatched combination of technology,· product breadth, understanding, commitment and capacity.

883B/883S/RETS Screening Flows WAFER FABRICATION &

DEVICE ASSEMBLY

PRE CAP VISUAL INSPECTION MIL·STD·BB3 METHOD 2010

CONDITION B

SEALING

STABLILIZATION BAKE MIL·STD·883 METHOD 1008

CONDITION C

TEMPERATURE CYClING MIL·STD·S83 METHOD 1010

CONOITION C

CONSTANT ACCELERATION MIL·STO·883 METHOD 2001

CONDITION E (Yl ONL YI

FINE LEAK TEST MIL·STD·883 METHOD 1014

CONDITION A OR B

GROSS LEAK TEST MIL·STD·8S3 METHOD 1014

CONDITION C

INTERIM ELECTRICALS AT + 2S'C DC PER RETS

(AT MANUFACTURER'S OPTION)

BURN·IN TEST MIL·STD·S83 METHOD lOIS. CONOITION A. 8. COR D. 160 HOURS AT 12S'C

OR EOUIVALENT

INTERIM ElECTRICALS 2S'C OC PER RETS

PDA = S'I.

FINAL ELECTRICAL TEST PER NSC RETS

+ 12S·C. -SS'C DC (INCLUDES FUNCTIONAL

TESTS + 2S'C AC

OUALITY CONFORMANCE TESTING GROUP A - EACH SUBLOT GROUP B - EACH LOG GROUP C - EVERY 90 OAYS PER

MICROCIRCUIT GROUP

GROUP 0 - EVERY 6 MONTHS PER PACKAGE TYPE

EXTERNAL VISUAL MIL·STD·8S3 METHOD 2009

NATIONAL OFF·THE·SHELF INVENTORY PROGRAM

FIGURE 1. NATIONAL'S 883B/RETS CLASS B SCREENING FLOW

NOTES: 1. ALL METHODS REFERENCED ARE MIL·STO·SB3 TEST METHODS. 2. THESE TESTS ARE PERFORMED ON A SAMPLE BASIS. ALL OTHER

TESTS ARE PERFORMED 100%. 3. ACCEPTANCE CRITERIA SHALL BE IN ACCORDANCE WITH

Mll·M·3SS1D. 4. THE PDA FOR STATIC I AND STATIC II BURN·IN SHALL BE 5'1.

TOTAl. S. THE PDA INCLUDES .1 FAILURES. 6. GROUP A AND BOND PUll AND DIE SHEAR TESTING OF GROUP 8

MAY BE PERFORMED ON·lINE. 7. ALL ELECTRICAL TESTING SHAll BE IN ACCORDANCE WITH THE

APPLICABLE RETS OR THE APPLICABLE MIL·S·3851D DETAil SPECIFICATION.

WAFER lOT ACCEPTANCE PER METHOD 5007

ASSEM8LY DIE SHEAR TESTING

ASSEMBL Y BONO PUll

TESTING

STABILIZATION BAKE (METHOD 100B. COND. C)

TEMPERATURE CYCLING (METHOD lDOS. COND. C)

CONSTANT ACCELERATION (METHOD 2001. COND. E)

Yl AXIS ONLY

SERIALIZATION

INTERIM ELECTRICAL TEST 2S'C DC

READ·AND·RECORD ALL PARAMETERS

STATIC I BURN·IN 24 HRS - 12S'C

VIN",VOUT-O

INTERIM ELECTRICAL TEST

2S'C DC COMPUTE .11

PDA PER NOTE 4

STATIC II BURN·IN 24 HRS - 12S'C VIN = VOUT = Vee

INTERIM elECTRICAL TEST

2S'C DC COMPUTE .1S

POA PER NOTE 4

DYNAMIC BURN·IN 240 HRS - 125'C

VIN-VOUT-O TO Vee' AT 100 kHz

INTERIM ELECTRICAL TF~~ (POST BURN·IN) DC 2S'C

PDA-S'I.

DRIFT (.1) CALCULATION

FINAL ELECTRICAL TESTS DC AT 12S'C -5S"C

INCLUDING FUNCTIONAL TESTS) 25'C AC

FINE lEAK TEST (METHOD 1014. COND. B)

GROSS LEAK TEST (METHOD 1014. COND. C)

X·RAY INSPECTION (METHOD 2012)

FIGURE 2. NATIONAL'S 883S/RETS CLASS S SCREENING FLOW

9-11

NOTE 2

NOTE 2

NOTE 2

NOTE 3

NOTE 7

NOTE 7

NOTE 7

NOTES 5.7

NOTE 5

NOTE 7

NOTES 2. 6

THE A + RELIABILITY ENHANCEMENT PROGRAM

The quality and reliability of National Semiconductor's products have always stood among the best in the business.

But as the complexity of semiconductor devices increased over the years, many of our customersespecially those whose products were highly sensitive to warranty and repair considerations-began asking us for the benefits associated with additional processing.

So we set out to develop ways to provide the extra measure of quality and reliability needed for high-stress or difficult-to-service applications; to make these enhanced products available on an immediate-delivery basis; and to do it all for a cost low enough that our customers could remain competitive in their own markets.

This led to the A + product reliability enhancement program which incorporates lot stress screening and testing beyond that which standard product receives.

HERE'S HOW WE DO IT

Quality-the measure of a component's conformance to specification-and reliability-the measure of the component's performance over time-both depend upon the tight control of materials; on precision design and fabrication techniques; and on the perfection of a component's assembly and packaging.

But quality and reliability also depend upon the kind of thorough testing that we do at National Semiconductor.

Using state-of-the-art, automated test equipment and handling methods, we test each and every A + device under the most extreme conditions in which it might be used. We monitor test results, and feed those results to our special failure-analysis laboratory. And we do it all for only pennies a unit.

WEIGH THE ADVANTAGES

Our A + program allows you:

• To minimize the need for incoming electrical inspection.

• To eliminate the need for (and cost of) using an independent testing laboratory and purchasing excess inventory to cover expected yield loss.

• A reduction in infant mortality rate.

• A reduction in the cost of reworking boards.

• A reduction in warranty and service costs.

ABOUTA+PRODUCTENHANCEMENT

If your business is driven by the need to minimize electrical inspection, to cut down on board rework, and to gain a further reduction in infant mortality rate, National's A + Product Enhancement is the program you should consider.

9-12

A + incorporates the benefits of the multiple-pass and elevated temperture testing found in the B+ Program, along with an additional test-a combination of increased temperature and applied voltage known as "burn-in"-that in just hours can stress a device to the equivalent of years of normal operation.

The A + Program gives you:

• High-temperature electrical testing at or above the commercial ambient limit.

• 100% multiple-pass electrical testing.

• A "burn-in" test combining increased temperature with applied voltage.

• Acceptable Quality Levels many times more stringent than the industry norm.

2 w ~ a:: w a:: 3 ff

EARLY LIFE USEFUL LIFETIME (DECREASING (CONSTANT FAILURE RATE) FAILURE RATE)

INFANT MORTALITY FAILURES

I IMPROVE BY BURN·IN PRIOR TO TlME=1o

WEAROUT (INCREASING FAILURE RATE)

to

10

IMPROVEMENT ATTRIBUTED TO REDUCTION OF INFANT MORTALITY THROUGH BURN-IN.

I

TIME-

COMPONENT BURN-IN FEATURED IN THE A+ PROGRAM. REDUCES INFANT MORTALITY FAILURES AND TOTAL COMPONENT FAILURES OVER THE

LIFE OF YOUR PRODUCTS.

THEA+ FLOW

• SEM: Randomly selected wafers are regularly taken from production and subjected to SEM analysis.

• Assembly and seal: All assembly processes are designed and monitored to produce products of the highest quality and reliability. Molded semiconductors are encapsulated with epoxy B.

• Six hour, 150·e bake. This stress places the die bond and all wire bonds into a combined tensile and shear stress mode, eliminating marginal bonds and insuring an optl,mum pl~stic seal.

• Five temperature cycles (o·e to 100·C) based on Mil·STD·883 method 1011, condition A, exercising each device over a 100·e temperature range pro· vides an additional die and package stress.

• Electrical test: Each device is electrically tested prior to submission to burn·in.

• Burn·in: Each device is burned·in for the equivalent of 160 hours at + 125·e. The combina· tion of elevated temperature and applied voltages places the die and package under severe stress.

• DC parametric and functional tests: These room temperature and high temperature functional and parametric tests are the comprehensive final tests through which all parts pass and are designed to guarantee compliance to data sheet parameters and functionality over the specified operating range.

• Tightened quality control inspection plans: Each lot is guaranteed to meet the AQL's listed in the following table:

9·13

Product Availability

The following MOS Memory Parts are currently available with A + screening:

HMC2147H 4K NMOS Static RAM HMC2148H 4K NMOS Static RAM MM2716 16K NMOS EPROM NMC27C16 16K CMOS EPROM NMC27C32 32K CMOS EPROM

At National Semiconductor we turn out more than six million semiconductor products every day, and we build each one to standards that have been called the best in the business.

But If your business requires the benefits associated with additional processing, take a look at the A + Product Enhancement Program from National Semiconductor.

You'll find a combination of state·of·the·art processing, manufacturing and testing facilities combined with quality and reliability monitoring that provides you with the broadest base of enhanced semiconductor products available in the market.

CALL US ON IT.

If you would like to know more about how our off·the· shelf product enhancement programs can benefit you, give us a call. We'd be happy to show you, in detail, how our A + Programs can work for you.

When it comes to the many uses of semiconductor tech· nology, National Semiconductor is making the most of a good thing.

MSrMProg~m , ' , The System Environment Approach to Memory Component Testing

The Memory System Test (MSn program is designed to provide our customers with mainframe memory components that have already been through the test/temperature processing that the user normally implements at the board level.

This program assures memory components of significantly better quality and higher reliability than that achieved by the usual approach to memory component testing. MST processed components have experienced board level environmental testing over the temperature range of 25°C to 70°C.

Specifying MST processing offers you the following:

• Eliminates the need for additional burn-in and testing at independent test laboratori~s.

• Eliminates inventory throughput time at incoming test or at independent test laboratories.

• Simplifies system checkout and shortens card burn-i nltest.

• Reduces board rework. • Reduces field failures and equipment downtime.

• Provides soft error detection during component processing.

• P~ovides mobile ion drift detection during component processing.

• Increases reliability. • Provides parts 'that have already operated in a

system environment within system margins at maximum operating temperature.

The result is you get higher quality at lower cost.

THE MST SCREEN

The screening performed by National for MST products has a very significant Improvement over standard product flows done by most dynamic RAM suppliers. National employs a Memory System Test (MST) which is a burn-in oven with added capability for driving components with various test patterns and monitoring component outputs for proper data. Parts are loaded in the MST oven and burned-in. They are then tested in the MST oven immediately after burn-in and are verified to operate properly over an extended test time at high and low temperatures.

MST parts are thus tested in a system environment with thousands of other RAMs operating in close proximity. This test more closely approximates a field environment than does a Single insertion test.

9-14

Testing the parts in the burn-in chamber immediately following burn-in also weeds out mobile ion problems. During burn-in mobile ions migrate to the silicon-oxide Interface where they are most likely.to cause failures. Thus a test Immediately after burn-in will detect mobile ions in a worst case condition.

The extended test time of MST parts at both high and low temperature will also detect intermittent failures. A Single insertion test normally runs a pattern only once, whereas the MST will run all patterns over and over, giving an intermittent problem many opportunities to occur.

The MST also gives absolute knowledge of burn-in. If a part does not make total electrical contact when plugged into the burn-in socket, it will malfunction during MST and be classified as a reject. Thus the electrical stressing as well as the high temperature of burn-in are insured.

The MST screen detects the above possible defects, as well as accomplishing normal burn-in screen. The normal burn-in performs the early life operation at an accelerated rate and weeds out infant mortalities. The MST burn-in is done at 125°C minimum and at voltage levels above 'nominal for additional stress on the parts.

In addition to the above screening, MST parts are tested at high temperature and room temperature with heavy timing guardbands or critical parameters. Parts are tested with power supply voltages and input drivers" guardbanded beyond the data sheet specifications. _ The parts are also tested to a very tight AOL at outgoing CA. Thus customers using MST products not only profit from excellent long term reliability, but they also experience fewer system incompatibility problems and have negligibly small incoming reject rates.

PRODUCT AVAILABILITY

National has shipped millions of MST screened parts and the program has been well received in the industry. Many users have seen board problems disappear and reject rates decrease by an order of magnitude after converting to MST.

All NMOS dynamic RAMs that National builds are available with MST screen.

OPERATING LIFE TEST RESULTS

The Biased Life Test at accelerated temperatures is the principal method of evaluating microcircuit reliability. This method is particularly useful because it provides a means of accelerating time·to-failure of temperaturesensitive failure mechanisms. By this method small sample tests can be used to predict actual field performance of the product lots sampled.

The nature of the operating stress selected differs for each unique circuit. Elevated ambient temperatures are used to accelerate thermally sensitive failure mechanisms. Voltage bias conditions are selected to approximate best the system bias conditions in normal design

.applications. Acceleration of bias or current stresses Is not attempted.

Test ambient temperatures are selected to assure that junction temperatures do not exceed the critical molded thermal-expansion transition temperature of 140°C for Epoxy-B materials.

FAILURE RATE TREND AT TJ:s 140°C

If a Weibul plot of failure-times were made, the Welbul parameter estimation of the rate of reliability Improvement with life test (13) would be approximately equal to 0.50. The Weibul function is one which is commonly used to describe mathematically the failure rate of a solid state device as a fUnction of time. It is also known as the Type III Extreme Value Distribution. Its probability density function may then be shown to be,:

, {3 (T-'Y) f(T-'Y)=",(;," (T-'Y){3-1 e- --;-

'Y (the location parameter) is assumed to be equal to a hours. {3 is the key parameter estimator for this product and may be used to tell when a failure rate is constant, increasing, or decreasing. In this instance, because the estimated value of {3 is less than 1.0, the Interpretation Is that the basic failure rate for these products improves with time.

A second approach to estimating failure distributions is to use the log-normal distribution. Using Information from current product tests, Figure 1 was constructed to assist in estimating the effectivity of various burn-In time pe'riods (based on 1 ,OOO-hour test results) by taking all failures occuring within 1,000 hours and plotting them as a normal density function with respect to the log of time. In Figure 1, the statistical fit with observed data is good. In that figure it is estimated that one-fourth of all failures occured within the first 70 hours of testing.

ESTIMATION OF USE-CONDITION FAILURE RATE

All National products are subjected to ongoing reliability evaluations. These evaluations employ various accelerated life tests, including dynamic high-temperature operating life, temperature-humidity life, temperature cycling, and thermal shock. A guide to the use of these tests in estimating equipment reliability Is provided by accelerated life testing. The following discussion analyzes the effects of temperature and the use of the Arrhenius failure rate model in estimating failure rates at other temperatures.

THE ARRHENIUS MODEL

The time and temperature dependence of virtually all long-term semiconductor failure mechanisms is a well established fact. The occurrence of this failure dependency can be represented by the Arrhenius Model. This model includes the effect of temperature and activation energy of the failure mechanism, permitting it to be used to characterize failure modes and predict reliability at normal operating temperatures based on tests performed at above-normal device junction temperatures.

Originally developed In the 1880s to describe chemical reaction rates, the Arrhenius Model was adapted to accelerated life testing for logical reasons. Faced with the critical need for full validation of accelerated life test data, researchers easily theorized that chemical processes were the cause of degradation of electronic parts. And, since temperature' was commonly used In

SCREENING EFFICIENCY OF BURN-IN PLOTS PERCENT OF LIFE TEST FAILURES EXPECTED TO BE SCREENED VI TIME ON BURN-IN

99

95

90

80

PERCENT 50

SCREENED 40

20

10

5.0

1.0

FIGURE 1_ Screening Efficiency of Burn-In

10

~

/ /

/ V

/ /

/ 100

ACCUMULATED BURN-IN TIME (HOURS)

9-15

1000

accelerated testing, the Arrhenius Model was applied and found to fit the data. The model was subsequently validated by years of reliability testing and found to be both a valuable design tool and a useful adjunct to the state of the art of accelerated life testing technology.

As applied to accelerated life testing of semiconductors, the Arrhenius Model assumes that degradation of a performance parameter is linear with time, with the MTBF a function of the temperature stress. The temperature dependence is taken to be the exponential function that defines the probability of occurrence, resulting in the following formula for defining the lifetime or MTBF at a given temperature stress level when knowing the MTBF at a second temperature stress level.

t,1 = t2 exp ..5...(.2.._.2..) , , K T1 T2

where: t1 = MTBF at junction temperature T1 t2 =MTBF at junction temperature T 2 T = Junction temperature in OK (absolute) E = Thermal activation energy in electron volts

(eV) K = Boltzman's constant (8.617 x 10- 5 eV/oK)

Given the temperature and failure rate for a specific reliability test, the remaining unknown is the activation energy E. The value for E can be arrived at through experimentation or by assumption of the validity of the historical data.

The activation energy serves as a convenient means of characterizing the failure mechanisms. If the activation energy is known, or can be estimated, the acceleration factor can be determined, allowing field failure rate and useful life to be calculated from the accelerated life tests.

In calculating the field reliability of a semiconductor device, it is first necessary to calculate the junction temperature both for the reliability test and for actual field operating conditions. In general, the junction temperature will depend on the ambient temperature, cooling, package type, operating cycle times, supply voltage and current. In these terms, the junction temperature Tj is given as:

Tj =TA+(lee x VeC> (Af) (JA) where: Tj = Junction temperature

T A = Ambient temperature lee = Supply current Vee = Supply voltage At = Air flow factor (0.75) JA = Package thermal resistance

Now by estimating the failure rate at test temperature, converting the test temperature and use condition temperature to absolute temperatures (OK= °C+ 273°), and by assuming an activation energy, the use condition failure rate can be estimated. This is the procedure performed in estimating the failure rates where the value for the activation energy was selected as 0.7eV.

9-16

TEMPERATURE AND HUMIDITY BIASED TEST RESULTS

For molded products, the most important test used to evaluate package resistance to external moisture contaminants has been the DC-biased low-power life test conducted in an ambient temperature of 85°C, with relative humidity constant at 85%. In this test, the package is placed in a chamber specially designed to assure that the density of water vapor in the vicinity of the device under test is constant for the duration of the test. By this means, comparing the respective rates of failure in humid and dry environments gives an indication of the permissivity of the package.

The principal failure mechanism expected to be induced by this "85/85" test is corrosion or one of its ancillary effects. However this test is most effective because it will also measure the long term potential for failure due to other failure mechanisms as well. Some other potential failure mechanisms include those induced by bias and temperature alone, by moisture induced changes in surface states resulting in changed electrical performance characteristics, and by those ,environmental stresses on package materials. Each such failure mechanism will have distinct failure characteristics that area function of time on test. Each has its own characteristic probability density function.

Numerous techniques are used to predict the acceleration of the failure mechanisms by stressing at T A = 85°C and RH = 85% under bias. While each technique arrives at the same general conclusions (i.e., the epoxy package is fully able to withstand normal earth-level environments such as those found in the vicinity of the Panama Canal), little agreement has yet been reached as to the exact method of 'extrapolation. National Semiconductor uses standard methods of calculating failure rates for 1,000 hours of testing, and combines temperature and relative humidity as independent variables in the reliability equation. Prediction of extrapolated failure-acceleration factors using this model then becomes the product of the estimated' acceleration which is· due to temperature times the estimated acceleration which is due to relative humidity.

TIME TO MEDIAN FAILURE

When time to median failure is of concern, this factor can be treated similarly.

Using the acceleration factor 208X provided by in-house experiments for correlation with T A = 30°C and RH = 85%, and recognizing an average internal system ambient temperature rise of 10°C, the time median failure is increased to 38.0 years. The ambient conditions of 30°C and 85% RH are seldom realized on an annual average basis in actual use conditions; except in those places with, extreme Climates, a more reasonable assumption of the annual average environment would be 30°C ambient temperature and 50% relative humidity. Under these more normal conditions, the time to median failure increases another 7 X.

FIGURE 2. Biased Humidity Life Test Summary

w ex: :3 ~ w

'" ~ ~ ~ c

S :::I ::;: 13 ~

100 90 80

70

60

50

40

30

20

10 1000

J I I

I /

/ I BIASED HUMIDITY LIFE TEST

TA = 85·C. A.H. = 85%

140.PIN rDLDIED riGEl

2000 3000 5000 7000 10.000

TIME ON TEST (HOUAS)

STORAGE LIFE TEST RESULTS

Storage at a maximum rated condition has long been used to test for atmospheric and chemical contaminants which are accelerated by temperature alone, and which can adversely affect microcircuit performance. The significance of this test has diminished as surface passivation technology has matured and as internal atmospheric control within hermetically sealed devices has effectively removed active ions from the die's presence. Its role for molded DIPs has been reduced to that of a test control only.

AUTOCLAVE OR "PRESSURE COOKER" TEST RESULTS

The autoclave test is performed as an accelerated moisture-resistance test for molded microcircuit packages. As the words "pressure cooker" imply, the test samples are supported above a well of water in a saturated atmosphere at an ambient temperature of approximately 121 ·C. At this temperature, two absolute atmospheres of pressure (1520 mm Hg) are maintained in the vessel, and the saturated water vapor density is 1.144 kg/m3. While maintaining the relative humidity at

9-17

100%, the thermal activity of the water molecules is increased significantly, thus increasing the saturated water vapor pressure ninety-six times the normal 0.02156 kg/cm2 at 30·C and 50% RH, orto 2.066 kg/cm2

at 121 ·C, 100% RH.

It is this increased activity and density of the water molecules that provide the storage acceleration for this test:As in the "85/85" test, failure comes as a result of corrosion or its by-products.

TEMPERATURE CYCLING TEST RESULTS

Temperture cycling tests the thermal compatibility of the materials and metal used to make a microcircuit. In testing molded packages, a 2,000 cycle "fatigue" test is conducted to assure not only initial thermal compatibility, but comparative thermal compatibility throughout the life of the circuit.

Each cycle consists of a minimum of 10 minutes at the high temperature (TA = 125·C), immediately followed by 10 minutes at the low temperature (T A = O·C). This cycling is repeated 2,000 times, with intermediate readings taken at the 1 ,OOO-cycle point.

Section 10

Physical Dimensions

~National all dimensions are in inches (millimeters)

~ Semiconductor

PACKAGES

Dual-In-Line Packages

(N) Devices ordered with "N" suffix are supplied in plastic molded dual·in·line packages. Molding material is a highly reliable compound suitable for military as well as commercial temperature range applications. Lead material is copper or alloy 42 with a hot solder dipped surface to allow ease of solderability.

(J) Devices ordered with the "J" suffix are supplied in a CERDIP package (ceramic lid and base sealed with high temperature vitreous glass). Lead material is solder dipped alloy 42.

(D) Devices ordered with the "D" suffix are supplied in side brazed, multi·layer, ceramic dual-in·line packages. The leads are Kovar or alloy 42 and either tin·plated, gold·plated, or solder-plated.

(0) Devices ordered with the "a" suffix are supplied in either a "D" or "J" package, but with a UV window.

Metal Can Packages

(H) Devices ordered with the "H" suffix are supplied in a metal can package. The cap is nickel finish and the leads are gold· plated Kovar. Gold free construction using epoxy D/A is also available, with a tin-plated finish.

Flat Packages

(F) Devices ordered with the "F" suffix are supplied in a multi·layer, c~ramic bottom brazed flat package. The lid is plated alloy 42, and leads are gold-plated, tin-plated, or solder-plated alloy 42 or Kovar.

(W) Devices ordered with the "W" suffix are supplied in a low-temperature ceramic flat package.

, ~(~:!~!=~O~~~)J --.. 0.090

, (2.286)

0.092 8 7 6 5

(2.337) DlA~' + 0.250±0.005

PIN NO. 1 IDENT 0 (6.35±0.127)

OPTION 1 ---*-

d I OPTION 2 !

95°±5° 4·(4X)~ 0.065

0.009-0.015 jl~ ~~3\2:5) (1.651) ~ (0.229-0.381) DIA '

0325 +0.025 ' NOM . -0.015

fa 255 + 0.635) ~. -0.381 ,

0.045+0.015 ~ (1.143±0.381)

TYP

0.125-0.140 (3.175-3.556)

~6"940

0.018±0.003 TYP (0.457 ± 0.076)

0.100 ± 0.010

*-~(2'540±0'254)

I.- 0.060 (1.524)

NS Package N08E 8-Lead Molded DIP (N)

10-3 .

0'032+0'005~7 (0.813 ± 0.127)

RAO

PIN NO. 1IDENT~

1

0.020 (0.508)

MIN

OPTION 2

NOSE (REV E)

~ (~:~~~) ~ O.OlO MIN --

0.lOO-0.l20 (~~6i) I (7.620-8.128) j

t"-"'tt 9~o±5° 0.009-0.015 tJ (0.229-0.l81 )

/. ./ 0.075 ±0.015 ~ J +0.025 (+)

0.l25 -0.015 1.905 -0.l81

( 0

0.100 ±0.010 8255 + .6l5)

. -0.l81 (2.540 ±0.254)

~.

~ ~ TYP . (::~~~)

0.018 ±O.OOl 0.125-0.140. MIN - - (0.457 ±0.07G) (l.175-l.556)

N16A (REV 0)

0.025 (0.G35)

RAO

NS Package N16A 16·Lead Molded DIP (N)

0.785~ (19.939)

MAX . 13 12 11 10 9 -r

0.220 - 0.310 (5.588-7.874)

~~'T":"T"T":'~~

~0.018±0.003 11 __

(0.457 ±0.076)--J

0.100±0.010 (2.540 ± 0.254)

NS Package J16A 16·Lead Cerdip (J)

10·4

0.005-0.020 (0.127 -0.508) RAD TYP

0.200 (5.080)

MAX

J16A(REVJ)

0.033 (0.838) R NOM

(~]):J

12 11 10 9

~ 0.252±0.00B

(6.401 ±0.203)

0.039 (0.991) R NOM

~~~~~~~~~7~~8 U

0.020 (0.508) RAO MAX. TYP

0.063±0.004 O.136±0.006 (1.600±0.102) (3.454±0.152)

+ .

NS Package N16F . 16·Lead Molded DIP (N)

-t

1..- 0.040 (1.016)

TYP

0.310 (7.874) MAX

~~~~,...,........"...,..."..,...~U

N16F(REV C)

0.200 (5.080) MAX

- 0.290-0.320 0.056+0.003 0.020-0.060 . ----J (7.366-8.128) I.. (1.422 ± 0.076) TYP (0.508-1.524)

O.'M~~. ':::::::T"r.----------~~-----------+W,.-.-4~--~(-~:-~~-:~=-~:~~~_~) (~~:) ~950 ±~r (0.203-0.305)

J L 86°94°

. 0.310 - 0.410 TYP (7.874 -10.41)

L 0.100±0.010 TYP LJ (2.540±0.254)

0.01B±0.003 TYP(0.457±0.076)


10·5

0.098 --- (2.489)

MAX 80TH ENOS

J18A (REV K)

0.092 (2.337)

OIA NOM (2X)

MIN 0.030

0.300-0.320 . (0.762)

0.843-0.870 -:-:J (21.41-22.10)

15 14 13 12 11 10 .-0.250 ±0.005

(6.350 ±0.127)

~::r=;::::;=r.:;=~::;:::::;:::;=;:::;=r=rJ--1

~(~:!~~)~

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0.040

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-D.015 . 0.100 ±O.olo

(S.255 ~:;~~) (2.540 ±0.254)

1 __ 11 0.018 ±0.003

~ I- (0.457 ".0161

(0.50S) 0.125-0.140 MIN

(3.175-3.556) .

0.180 (4.572)

Mi I--- 0.590-0.620 --I L--f-r=:(14 986-15.748):::::l1

0.025 (0.635)

RAD

0.030-0.055 (0.762-1.397)

RAD TYP

0.005 (0.127)

MIN

TVP

NS Package N18A 18·Lead Molded DIP (N)

1.290 ~-------------(32.7~)--------------~

MAX

N18AIREV01

0.560 r (14.22) MAX GLASS

0.514 -0.526 (13.06-13.36)

~~~_l 0.225

(5.175) MAX

f5 II '\-fj95

0

±50

0.ooa_0.015J (0.203 - 0.381)

0.685 ~~:: 0.060-0.100

f--(1740+0.635) -I ~ 1- 0.100±O.010 I (2.540 ±0.254) -l

1_ - II _ 0.018 ±o.OO3 I-- II (0.457 ± 0.076)

~~.070 ~ml

0.125 (3.175)

MIN . -1.524 TYP

J24A·OjREVF,

NS Package J24A·Q 24·Lead EPROM Cerdlp (JQ) Small Window

10-6

0.025

(0.635) RAD

_, 0.600

~~~~~~~~~Ll~lITLi~~~~ITil- (15.240) r fMAX

~GlASS

0.514-0.526

0.030-0.055 I umml]Dl::rr"'1]n"'iTTin'iT"""'-:~"""''''''''~ "'·"rJ61

(0.762-1.397) J RAD TYP

I 0.590-0 620

~-(14.986-15.748)-1 0005 rt II . (D~:~

Y" ;'", ."" ~ ;:=::~::IJ I-- -0060 _I 0098

(17.40 +0635) (2.489)

-1.524 MAX


0.125-0.200

(3.175-5.080) MIN

0.150

(3.810) MIN

1.490 (37.846) MAX -------- -I 0.600

(~~~~~~~~liLflnJliLffilillLITilillw@~ ri15.240) -.-lMAX GLASS

0.025

(0.635) RAD

0.030-0.055

(0.762-1.397) RAD TYP

1 0.514-0.526

~lITT1~nr~roITlIrrn-rsTTor~~~~----~ 1""1'1.361

0.180

(4.572) MAX

LfffEflm~~~~

II 0.100 '0.010

(2.540' 0.254)


10·7

J28AIREvEI

- 0.580 MIN =:J (14.73)

0625 +0.025 . -0.015

(1588+ 0.635) . -0.381

PIN NO. llDENT

NS Package N288 28·Lead Molded DIP (N)

10-8

0.125-0.145 (3.175-3.683)

N28BIREVEI

.1

Documents

A Corporate Dedication to - Computer History Museum