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A DEFECTIVITY STUDY ON DRY DEVELOPMENT RINSE PROCESS
(DDRP)
Maastricht, The Netherlands - October 5-7, 2015 – EUVL International Symposium
Harold Stokes1, Yan Thouroude1, Lucia D’Urzo2, Safak Sayan3, Philippe Foubert4, Danilo De Simone4
1) SCREEN SPE GmbH, Mundelheimer Weg 39, 40472 Dusseldorf, Germany
2) Entegris GmbH, Hugo-Junkers-Ring 5, Gebäude 107/W, 01109, Dresden, Germany
3) Intel Corp. Assignee at IMEC, Kapeldreef 75, 3001 Leuven, Belgium
4) Imec, Kapeldreef 75, 3001 Leuven, Belgium
2
© IMEC 2015
OUTLINE
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
• Dry Development Rinse Process (DDRP) introduction for EUVL
• Concept and key benefits
• First Dry Development Rinse Material (DDRM) patterning images on
NXE3300
• DDRM Defectivity: Pathfinding work for EUV
• Defectivity and Coating Uniformity on blanket 300mm wafers: setup &
optimization on SOKUDO DUO track
• Learning on DDRM LS pattern reversal defectivity using 193i
lithography as patterning vehicle.
• Summary and Outlook
3
© IMEC 2015
DRY DEVELOPMENT RINSE PROCESS BY
NISSAN CHEMICAL - CONCEPT
Peculiarity: Pattern reversal process
Strengths: Line collapse reduction, etch resistance improvement
exposure post-expo-bake
developer
puddle
dry dev. rinse
(developer replacement)
spin dry and bake dry etch resist stripping
resist
same development cup unit
1 2 3 4
5 6 7
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
4
© IMEC 2015
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
NXE3100 - DIP60X EL%
Resist DDRM
LWR = 3.4nm LWR = 3.7nm
Pattern reversal process Resolution improvement
KEY BENEFITS FROM DDRP
Exposures on NXE3100
[1] S. Sayan et al. Proc. of SPIE Vol. 9425 942516-1 2015
5
© IMEC 2015
NXE3300 – RESIST PROCESS VS DDR PROCESS
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
Half Pitch = 13 nm
Resist-C 50nm FT
Associated
DDRP
Resolution Improvement: Pattern collapse mitigated by application of DDRM
6
© IMEC 2015
OUTLINE
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
• Dry Development Rinse Process introduction for EUVL
• Concept and key Benefits
• First DDRM patterning images on NXE3300
• DDRM Defectivity:
• Pathfinding work for EUV to investigate Defectivity and Coating
Uniformity: setup & optimization on SOKUDO DUO 300mm track
• Learning on DDRM LS pattern reversal defectivity using 193i
lithography as patterning vehicle.
• Summary and Outlook
7
© IMEC 2015
PROCESS SETUP
Entegris customized surface modified UPE membranes
NCR43
R3: improved solubility in DIW,
enhanced shelf life
Water based solvent
KLA eDR-7100® KLA-Tencor SP3® and 2835®
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
8
© IMEC 2015
DDRM DEFECT COUNTS INDEPENDENT
FROM RUN ORDER
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7 8
No
rma
lize
d D
efe
ct
Co
un
t
Wafer Run Order
>> 3s
9
© IMEC 2015
DDRM DEFECT PERFORMANCE NOT
DEPENDENT ON DISPENSE VOLUME
Run T1/T2 Dispense
Volume
Normalized
Defect
Counts
1 2 2X 1.0
2 2 4X 0.4
3 1 3X 0.5
4 2 X .05
5 1 4X .05
6 1 X .05
7 2 3X .04
8 1 2X .05
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
X 2X 3X 4X
No
rma
lize
d D
efe
ct
Co
un
t Dispense Volume/wafer (mL)
Test 1
Test 2
10
© IMEC 2015
DDRM COATING UNIFORMITY TESTING
• Range best for lowest dispense volume
• Lowest volume used for all subsequent testing
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
No
rma
lize
d 3
sig
ma
Dispense volume for Test 1 / Test 2
Test 1
Test 2
X 2X 3X 4X 0.0
0.5
1.0
1.5
2.0
2.5
3.0
No
rma
lize
d R
an
ge
Dispense volume for Test 1 / Test 2
Test 1
Test 2
X 2X 3X 4X
11
© IMEC 2015
DEFECT OPTIMIZATION PATH -1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Baseline A B C D E F
Rela
tive D
efe
ct
Co
un
ts 99% defect reduction
from: • Dispense method
• Optimal filter
• Surface preparation
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
Driving down defects on bare silicon wafers
12
© IMEC 2015
DEFECT OPTIMIZATION PATH -2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Baseline D E F
Rela
tive
Defe
ct
Co
un
ts
Class 1
Class 2
Class 3
Class 4
Class 5
0
0.002
0.004
0.006
0.008
0.01
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
Driving down defects on bare silicon wafers
13
© IMEC 2015
OUTLINE
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
• Dry Development Rinse Process introduction for EUVL
• Concept and key Benefits
• First DDRM patterning images on NXE3300
• DDRM Defectivity:
• Pathfinding work pro EUV to investigate Defectivity and Coating
Uniformity: setup & optimization on SOKUDO DUO 300mm track
• Learning on DDRM LS pattern reversal defectivity using 193i
lithography as patterning vehicle.
• Summary and Outlook
14
© IMEC 2015
PROGRAM DEFECT TRANSFER FROM RESIST TO DDRM
Defect on resist Defect on DDRM
Gap patterning area
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
Bridge patterning area Defect on resist Defect on DDRM
Program defect inspection demonstrates defect pattern reversal (Ex. Bridge Gap, Gap
Bridge)
15
© IMEC 2015
Resist Pattern Defect count for each class Total
(DoI) Top Bottom Bridge Gap Block
PR-D Resist 21 7 3 0 0 31
DDRM 13 15 2 6 2 38
Top Bottom Bridge Block Gap
DEFECT CLASSIFICATION RESULTS
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
• DDRM and Resist have comparable total DoI
Defect
samples
Defects of Interest (DoI) on target wafer area
16
© IMEC 2015
SUMMARY AND OUTLOOK
Demonstrated defect reduction Unpatterned substrate in preparation for optimal process
performance
Initial understanding of patterned DDRM defects based on
classification
Extend DDRM defect studies to NXE3300 EUV system Utilize similarities to reduce EUV pattern defects
Demonstrate DDRM process capable of being transferred to HVM
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
17
© IMEC 2015
ACKNOWLEDGEMENTS
MAASTRICHT, THE NETHERLANDS - OCTOBER 5-7, 2015 – EUVL INTERNATIONAL SYMPOSIUM
Ryuji Onishi - Nissan Chemical assignee at IMEC
Naomi Inoue - Nihon Entegris KK, Liquid Micro-contamination Control
Applications Development