A Digital Pipelined Cathode Front End Board (DCFEB) Stan Durkin

Stan Durkin CMS Upgrade Week

1

A Digital Pipelined Cathode Front End Board (DCFEB) Stan Durkin The Ohio State University


2

Present Cathode Front End Board (CFEB)

Inputs Signal 96 channels input from chamber strips LCT from DMB, if CLCT is available, CLCT-->DMB--

>CFEB, if CLCT is not available, -->FTC-->DMB-->CFEB, if Calibration mode, DMB-->CFEB

L1ACC From DAQMB, - if CCB is available, CCB-->DMB-->CFEB, or CCB-->FTC-->DMB-->CFEB - if CCB is not available, FTC (LCT delay)-->DMB-->CFEB, or, DMB (LCTdelay)-->CFEB, - if Calibration mode, DMB-->CFEB;

DAC 0-5V adjustable for external, internal charge injection for BUCKEYE from DAC on DMB

BUCKEYE +10V and -5V voltage references from DMB Outputs

DAQ data Strip charge ADC data, Through 21-bit channel link to DMB

Trigger data Comparator Triads through two 28-bit multiplexers to CLCT; End channel signals to neighboring boards, analog preamp signals and digital comparator signals

Monitor Temperature sensor output, to DMB, program done Controls

Global-reset from DMB, reset DMB and CFEBs, and synchronize the 50ns clock on DMB and CFEBs

Clock 40MHz, from DMB FPGA-program from DMB, re-program the FPGA from PROM on CFEB JTAG port from DMB, controls: BUCKEYE data shift, FPGA

resets, ISP-PROM download, CFEB status monitor, etc. Downloaded Constants

PREBLOCKEND (4 bits) Block Phase Shift PROM programming data (about 500K bits); BUCKEYE working mode (normal, internal capacitor select, external, kill, 3bits/channel); Comparator timing (3 bits), working mode (2 bits) and threshold

Power +6V: for BUCKEYE clean power (550-600mA) +5V: for SCA, ADC, comparator, etc. (900-1000mA) +3.3V: for FPGA, Channel link, CPLD, etc.(450-500mA) +5V and +3.3V power supplies are subject to change.

BUCKEYE (ASIC) - amplifies andshapes input pulse

SCA (ASIC) - analog storage for 20 MHz sampled input pulse

ADC - events with LVL1ACCdigitized and sent to DAQ Motherboard (25 nsec/word)

Controller FPGA - controls SCA storage and digitization

Comparator ASIC - generatestrigger hit primitives from shapedpulse

Input/Output

- 5 cfebs/chamber, 96 strips/cfeb- 96 switch capacitors/channel- system is self triggering

Optimized for Precision Position Measurement


3

- 6 Buckeyes serve 6 planes x 16 strips- 6 SCA’s serve 96 strips with 96 caps each 50 nsec/sampling no pedestals (< 1%)-6 ADC’s (150 nsec digitization) 12-bit + overflow bit output 1 strip charge/25 nsec 8 samples digitized for each of 96 strips-6 SCA’s (96 caps/strip) LVDS signaling no cap pedestals-Control FPGA 12 blocks of 8 caps each grey-code (1 bit flip) addressing (see movie for algorithm)

16 Cap Delay Cap Storage (Poisson) Cap Digization (Queue)

Beam Crossing PreLCT L1A·LCT

0.8sec 2.2sec 26sec

Caps can be usedfor storage whenall others in use

16 caps set aside forpossible use

For L1ALCT use LCT to choose which 8 capacitors to digitize

Done

CFEB 50 nsec Sampling and Digitization

Each Strip Amplifier Charge stored every 50 nsec in capacitors


4

Simulation Single Strip Capacitor Usage A Nontrivial FPGA Algorithm 8 capacitors/block

Green – recently used Blue – set aside waiting for L1A Red- digitizing


5

16 Cap Delay Cap Storage (Poisson) Cap Digization (Queue)

Beam Crossing LCT L1A·LCT

0.8sec 2.2sec 26sec

Transfer toDMB Complete

Caps can be usedfor storage whenall others in use

For SLHC this is themain capacitor usage

Data Bottlenecks in CSC DAQ at SLHC

• CFEB’s 96 Capacitors/channel is main DAQ rate limiter

• DCC’s SLINK-64 is second DAQ rate limiter (configurable)

Simple Model CFEB Capacitor Storage


6

Strip Channels

Time (50ns/bin)

Neutron/Gamma Event from X5 Beam test (Aug 99)Neutron/Gamma Event from X5 Beam test (Aug 99)

Random coincidence between L1A and Neutron/Gamma Background Dominates Rate


7

SCA Occupancy: LHC Rate AssumptionsL1 Accept: 100 kHzLCT rate: 69 kHz per CFEB (worst case – ME1/1) Estimated LCT rate for 10**34 lumi (D. Acosta et al, 2001) Chamber Type LCT rate per CFEB (kHz) ME1/1 69 ME1/2 4 ME1/3 2 ME2/1 21 ME2/2 3 ME3/1 11 ME3/2 2 ME4/1 8 ME4/2 9

L1-LCT coincidence rate per CFEB: 100 kHz x 70 kHz x 75 ns = 0.5 kH

Digitization time (with 6 ADCs on each CFEB) 16 channels x 16 samples/channel x 100 ns = 26 sNote: This is Monte Carlo, We haven’t measure rates yet!

Problem! ‘ME1/1 LCT 96kHz/chamber (20 kHz) CMS Note 2002-007’ Hauser


8

ME1/1 Effective SCA Buffer Occupancy at SLHC

• At SLHC: use same L1 accept rate assuming rates go up linearly. Maximum LCT rate is 700 kHz (ME1/1),

L1-LCT match rate is 5.25 kHz.• Average number of LCTs during 5.2 s (=6s-0.8s) holding time for

2-blocks: =5.2x10-6x700x103=3.64• Average number of L1-LCT matches during 26 s digitization time:

=26x10-6x5.25x103=0.1365• Probability of overuse of SCA: 0.09 !!!!!!!!!

n Free Used P( ,n) Q( ,n)0 12 0 0.026 0.861 10 2 0.095 0.122 8 4 0.174 1.60E-023 6 6 0.211 2.10E-034 4 8 0.192 3.00E-045 2 10 1.40E-01 4.10E-056 0 12 8.50E-02 5.60E-06


9

Digital CFEB – A Nice Idea for the SLHCReplace Conventional ADC and SCA storage with Flash ADC and Digital Storage• New System Deadtimeless, Removes rate worries• Similar cost to old systemFairly Radical Design – Couldn’t build 8 Years Ago


10

Fix ME1/1 Ganged Strips

• Removes ganged strips in ME1/1a (aka ME1/4)Gets rid of ghost tracks trigger and offline

software • Requires 7 DCFEBs per ME1/1 Chamber

Cathode charges

Improve Cathode Trigger Primitives

-presently an ASIC chip-do digitally on new board

=1.5

=2.0

=2.4

Besides Deadtimeless there are other Advantages


11

Overall Scope of Upgrade ME1/1 Electronics Upgrade 504 DCFEBs 72 DMBs 72 TMB (d.c.) 12 MPC 72 LVDB (+more power) 72 LVMB1008 Cables (default skewclear)

LVDB


12

Evaluation of Flash ADCs (B. Bylsma O.S.U)

ADC choices:(8 ch, 12 bit, 20-65 MSPS, Serial LVDS output)MAX1437 (Maxim) 1.8V supply, 1.4Vpp rangeADC12EU050 (National) 1.2V supply, 2.1Vpp rangeAD9222 (Analog Devices) 1.8V supply, 2Vpp rangeADS5281 (Texas Instr.) 3.3V analog, 1.8V digital, 2Vpp range


13

No Flash ADC is a drop-in replacements for SCA/ADC

-ADC’sAll have differential inputsLimits on common modeHave internal input bias network

-Pre-AmpSingle ended outputLimited range of baseline levelDesigned to drive small capacitive load

-Pre-Amp/ADC InterfaceMnfr. suggest transformer coupling

(not an option for us)Amplifier to generate differential signal

(requires 96 amplifiers)Direct couple single ended signal

(common mode consequences)(level shifting/scaling)

AC couple single ended signal(common mode consequences)(no level shifting, but still have biasing to consider

Flash ADC/Amplifier Coupling Issues


14

Common Mode Constraints (ADS5281)

•ADC Constraints:Vcm -600mV < (IN+ + IN-)/2 < Vcm +300mV (1.8Vpp on IN+)(IN- -1V) < IN+ < (IN-+1V) (ADC output range)

•Pre-Amp Constraints:Baseline Level

-Currently 1.8V-Max ~2.0V-Min ~1.2V (maybe 1.0V)

Drive Capability-Small (few mA at best)

•Scaling:Scale down inputAdd digital gain on outputResistor divider

Direct Coupling Difficult Common Mode

Data Sheet: Vcm = 1.5V How far from nominal? Baseline Level

-Range Digital output range is 2V But is linear range of common mode 2V


15

DCFEB R&D plans

Short Term Goal: Install Prototype System on a ME4/2 Chamber during 2012 Shutdown

DCFEB Critical Item so Divide Labor (Generic R&D)• DCFEB R&D Board, OSU • FPGA Firmware, Florida• Virtex 6 R&D Board, TAMU• Virtex 6 Radiation Testing, NEU• Optical Cable Interface DCFEBDMB/TMB

50 nsec Samples

Buckeye Amp -> ADC5281 Evaluation Board

• Preliminary Tests are Encouraging• Flash ADC sensitive to common mode gain• Need R&D board to fully test coupling and noise


16

DCFEB R&D BoardDesigned to study (there will be issues): - Coupling single ended Buckeye Amp to bipolar flash SCAs - Linearity/Shape …Noise on Analog-Digital boards can be problems - use old PC board’s analog isolation


17

DCFEB R&D Board Available Late this Summer

Then: - noise tests - linearity/pulse shape tests - radiation tests, SEU and lifetime measurements

If all goes well layout and schematics of a DCFEB Prototype boardwill start late Fall

Conclusions

Documents

A Digital Pipelined Cathode Front End Board (DCFEB) Stan Durkin