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DIGITAL CLOCK A Digital Timer Implementatio n using 7 Segment Displays

A Digital Timer Implementation using 7 Segment Displays

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Page 1: A Digital Timer Implementation using 7 Segment Displays

DIGITAL CLOCK A Digital Timer Implementation using 7 Segment Displays

Page 2: A Digital Timer Implementation using 7 Segment Displays

GROUP MEMBERS

Arsalan Arif Maryam Ikram Fahad Tariq

Page 3: A Digital Timer Implementation using 7 Segment Displays

A digital display which consists of seven LED segments is commonly utilized to display decimal numerals in digital systems. Various familiar illustrations are electronic calculators and watches where one 7-segment display device is utilized for displaying one numeral 0 through 9. To use this display device, the data has to be converted by some binary code to the code essential for the display. Frequently the binary code utilized is Natural BCD.

BCD-TO-SEVEN-SEGMENT DECODER:

Page 4: A Digital Timer Implementation using 7 Segment Displays

BLOCK DIAGRAM

Page 5: A Digital Timer Implementation using 7 Segment Displays

TRUTH TABLE

Decimal Digits   Input   Output    A B C D a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 01 0 0 0 1 0 1 1 0 0 0 02 0 0 1 0 1 1 0 1 1 0 13 0 0 1 1 1 1 1 1 0 0 14 0 1 0 0 0 1 1 0 0 1 15 0 1 0 1 1 0 1 1 0 1 16 0 1 1 0 0 0 1 1 1 1 17 0 1 1 1 1 1 1 0 0 0 08 1 0 0 0 1 1 1 1 1 1 19 1 0 0 1 1 1 1 0 0 1 1

Page 6: A Digital Timer Implementation using 7 Segment Displays

K-mappingi) K-map and Logic Diagram for Digital Output ‘a’

A = B‾ D‾ + BD + CD + A

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K-mappingi) K-map and Logic Diagram for Digital Output ‘b’

B = B‾ + C‾D‾ + CD

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K-mappingi) K-map and Logic Diagram for Digital Output ‘c’

C = B + C‾ + D

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K-mappingi) K-map and Logic Diagram for Digital Output ‘d’

D = B‾D‾ + CD‾ + B‾C +BC‾D

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K-mappingi) K-map and Logic Diagram for Digital Output ‘e’

E = B‾D‾ + CD‾

Page 11: A Digital Timer Implementation using 7 Segment Displays

K-mappingi) K-map and Logic Diagram for Digital Output ‘f’

F = A + C‾ D‾ + BC‾ +BD‾

Page 12: A Digital Timer Implementation using 7 Segment Displays

K-mappingi) K-map and Logic Diagram for Digital Output ‘g’

G = A + BC‾ + B‾C+ CD‾

Page 13: A Digital Timer Implementation using 7 Segment Displays

CIRCUIT DIAGRAM

Page 14: A Digital Timer Implementation using 7 Segment Displays

COMPONENTS USED 7 SEG COM ANODE 74LS90 COUNTER

AND GATES BCD TO 7 SEG DECODER

ALTERNATOR INVERTER

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TOOL USED

PROTEUS DESIGN SUITE 8.0

PROFESSIONAL

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THANKS FOR YOUR

ATTENTION.