A Fast-Response Pseudo-PWM Buck Converter With

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 7, JULY 2012 1167

A Fast-Response Pseudo-PWM Buck Converter WithPLL-Based Hysteresis Control

Yanqi Zheng, Hua Chen, and Ka Nang Leung , Senior Member, IEEE

Abstract—Hysteresis voltage-mode control is a simple and fastcontrol scheme for switched-mode power converters. However, itis well-known that the switching frequency of a switched-modepower converter with hysteresis control depends on many factorssuch as loading current and delay of the controller which varyfrom time to time. It results in a wide noise spectrum and leads todifficulty in shielding electro-magnetic interference. In this work,a phase-lock loop (PLL) is utilized to control the hysteresis levelof the comparator used in the controller, while not interferingwith the intrinsic behavior of the hysteresis controller. Somedesign techniques are used to solve the integration problem andto improve the settling speed of the PLL. Moreover, different

control modes are implemented. A buck converter with proposedcontrol scheme is fabricated using a commercial 0.35- m CMOStechnology. The chip area is 1900 m 2200 m. The switchingfrequency is locked to 1 MHz, and the measured frequency de-viation is within 1%. The measured load transient responsebetween 160 and 360 mA is 5 s only.

Index Terms—Buck converter, hysteresis control, phase-lockedloop (PLL).

I. INTRODUCTION

FAST transient response is important for high-speed elec-

tronic applications [1]–[4]. Hysteresis voltage-modecontrol is a simple and straightforward control scheme

for switched-mode power converters. Directly operating

on the output voltage, the hysteresis voltage-mode control

has very fast transient response against load changes and

output-voltage spiking. For some other control schemes such

as the widely-used pulse-width modulation (PWM) control, it

takes several switching cycles, due to the duty-cycle limitation,

to recover the output voltage in response to step changes of

loading current. In contrast, for hysteresis control, it might take

only one switching cycle to complete the same load transient

response.

It is well-known that the switching frequency of a hysteresis-

control switched-mode power converter depends on many fac-

tors such as loading current, input/output voltage, output ca-

pacitance and inductance in the power stage. It is also a strong

function of some design values such as the equivalent series re-

sistance (ESR) and the equivalent series inductance (ESL) of

the output capacitor, as well as the delay of the comparators in

Manuscript received November 29, 2010; revised March 28, 2011; acceptedMay 05, 2011. Date of publication June 16, 2011; date of current version June01, 2012. This work was supported by a grant from the Research Grant Councilof Hong Kong SAR Government under project CUHK414210.

Y. Zheng, H. Chen, and K. N. Leung are with the Department of ElectronicEngineering, The Chinese University of Hong Kong, Shatin, Hong Kong SAR.

Digital Object Identifier 10.1109/TVLSI.2011.2156437

the hysteresis controller, which are difficult to accurately con-

trol. In practice, people can only estimate the working frequency

but not set the target frequency strictly. Moreover, during op-

eration, the switching frequency is drifted seriously under dif-

ferent loading conditions. The uncertain switching frequency

leads to a wide noise spectrum and leads to difficulty in shielding

electro-magnetic interference (EMI), which is considered as a

congenital defect of the hysteresis-control scheme. Therefore,

PWM control scheme is generally more preferred than the hys-

teresis counterparts in many applications. Recently, some ideas

have been proposed to regulate the switching frequency of ahysteresis switched-mode power converter, such as the designs

reported in [5]–[14]. In [5], a design artificially introduces a

small ramp signal that dominates the feedback voltage ripple

to control the switching frequency. The designs proposed in

[6]–[9] sense the output-voltage node and the switching node

of the inductor in the power stage with some RC filters, and the

switching frequency is correlated to the filter parameters. How-

ever, the switching frequency cannot be accurately defined and

the variations are still very large. The power converter in [10]

introduces a ramp signal in the lower boundary of the hysteresis

comparator to guarantee a minimum switching frequency under

light load. Both designs in [11] and [12] propose to control thedelay in the control loop in order to adjust the switching fre-

quency. The design in [13] utilizes a frequency-to-voltage block

to control the hysteresis level according to the switching fre-

quency, however, with an extra compensation circuit required.

For the work presented in this paper, a hysteresis

voltage-mode buck converter will be introduced. A phase-lock

loop (PLL) is utilized to control the hysteresis level of the

comparator, while not interfere with the intrinsic behavior of

the hysteresis controller. The proposed buck converter has the

intrinsic fast transient response and its switching frequency in

steady state is set by an extra control loop which is controlled

by a PLL. As a matter of fact, the design presented in [14]

illustrates this concept, however, with no substantiated circuitimplementation. This paper focuses on the circuit implemen-

tation of the PLL-based hysteresis-control buck converter by

considering important circuit design issues. The contributions

of the works presented in this paper are: 1) an effective way

to use PLL circuit to adjust the hysteresis level to achieve

fixed-frequency fast-transient buck converter with hysteresis

control is developed and 2) a capacitance-reduction method

to reduce the capacitance needed for the PLL circuit is im-

plemented and thus all required components of the controller

have been successfully implemented on-chip. In Section II, the

proposed switching-frequency control loop will be introduced.

In Section III, some design techniques are used to solve the

1063-8210/$26.00 © 2011 IEEE



1168 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 7, JULY 2012

Fig. 1. Structure of conventional voltage-mode hysteresis control buck converter.

Fig. 2. Waveform of the feedback voltage of the conventional voltage-modehysteresis control buck converter.

integration problem and to improve the settling speed of the

PLL. In addition, a full control system to cover a wide rangeof the loading is implemented. Additional functions included

are pulse-frequency modulation (PFM) control and a standby

mode for the light-load scenario. Experimental results will be

reported in Section IV. Finally, the conclusion of this paper is

presented in Section V.

II. SWITCHING FREQUENCY CONTROL LOOP

The concept of the proposed design is derived from the basic

hysteresis voltage-mode control buck converter, as shown in

Fig. 1. The power stage consists of high-side switch , low-

side switch , inductor , loading capacitor andloading . and model the ESR and ESL of the loading

capacitor. is the supply voltage and is the output

voltage. The control circuit consists of and that sense

output voltage, a hysteresis comparator with hysteresis level

and , and some control logic. The feedback voltage is fed

into the hysteresis comparator. When is lower than

is on and is off, connecting switching node to , and

will ramp up. When is higher than is off

and is on, connecting to the ground, and then

will ramp down. The waveform of is illustrated in Fig. 2.

denotes the switching frequency and is the duty cycle. This

control scheme directly senses and controls the output voltage,

and, in consequence, it has very fast response to sudden changesof the loading and spiking. The control system is also simple in

Fig. 3. Conceptual diagram of the proposed pseudo-PWM voltage-mode hys-teresis control.

Fig. 4. Waveform of the feedback voltage of the proposed buck converter.

implementation. However, when the input voltage is changed,

the switching frequency will also be different.

As suggested in [15], the switching frequency of a hys-

teresis voltage-mode control buck converter can be estimatedas

(1)

where is the delay of the feedback control loop. From (1),

it is observed that the switching frequency can be adjusted by

varying the hysteresis boundary (i.e., ). With this model, the

buck converter can be regarded as a voltage-controlled oscillator

(VCO) where is the control voltage. As shown in Fig. 3, a

phase detector is introduced to compare the phase difference

between the switching signal and a reference clock and then

adjust the control voltage to tune the switching frequency.The whole system can be regarded as a PLL which locks the

switching frequency to the reference clock. For instance, when

the input voltage is large, the output voltage ramps faster. There-

fore, is set to a higher voltage to guarantee the switching

frequency is fixed, as shown in Fig. 4.

Although the designs reported in [11] and [12] proposed a

similar approach to control the signal, both of them control

the switching signal via instead of the hysteresis boundary.

However, in practice, is usually very large and the ESR

of the capacitor is desired to be relatively small. Therefore, ac-

cording to (1), is not a very effective variable to control

the switching frequency. On the other hand, can always be

chosen with a proper value, and so is more effective in con-trolling the frequency under a close scrutiny.



ZHENG et al.: FAST-RESPONSE PSEUDO-PWM BUCK CONVERTER WITH PLL-BASED HYSTERESIS CONTROL 1169

Fig. 5. Mathematically modeled transient response of the proposedpseudo-PWM voltage-mode hysteresis control buck converter.

With the introduced PLL, the buck converter is actually con-

trolled by two control loops. One is the standard feedback loop

which consists of hysteresis comparator, and the other loop is

controlled by the PLL. As suggested in [13], since the duty cycle

is estimated as

(2)

where is the on-resistance of the high-side switch, and

is the series resistance in the inductor. It can be seen that

is independent of hysteresis level (i.e., ). Therefore, theintroduced PLL does not change the intrinsic behavior of the

hysteresis comparator which provides the regulation, fast tran-

sient response and robustness. In contrast to the hysteresis com-

parator control loop with fast response, the PLL loop has rela-

tively slower response, while its main usage is to regulate the

switching frequency in the steady state.

In Fig. 5, the load transient response of a buck converter

with the proposed control scheme is modeled by a mathematical

model in MATLAB. It is observed that the hysteresis comparator

responses quickly and regulates the output within one switching

cycle. In contrast, the PLL loop responds relatively slower.

is settled after several cycles and the frequency is not locked

instantaneously. During transient, the switching frequency sud-denly drops for long charging period for at least one cycle, and

slowly recovers eventually. Thus, the dual-loop control guaran-

tees both fast responses in transient as well as robustness in the

steady state.

III. SYSTEM IMPLEMENTATION

In the full-system implementation, in additional of the fixed-

frequency hysteresis control, or saypseudo-PWM control, a cur-

rent-mode PFM control and a standby mode (STB) are also im-

plemented and included to the buck converter. When, in light-

load condition, in order to reduce switching loss, the system is

taken over the control by the PFM scheme. In the ultra-light loadcondition, the system is switched to the standby mode.

The whole system of the buck converter is illustrated in Fig. 6.

The system is partitioned into power stage and drivers, zero gen-

erator, control circuit and phase-lock loop. The startup operates

in PFM and uses a RC constant to set up the startup time. The

details of the circuit implementation of each part will be given

in the following sub-sections.

A. PLL Design

The switching signal is compared with a reference clock.

Their phase difference is detected by the phase detector, which

controls the charge pump to charge or discharge the capacitor

at the output node. In this design, a variable-gain charge pump

is implemented to attenuate slew-rate limit of a constant-gain

charge pump. The low-pass filter (LPF) is used to integrate the

charge-pump current and convert it into voltage . In this

design, an active LPF is implemented to reduce the capacitor

size. The voltage is further bounded by an output-bound

circuit and attenuated before generate . The details will be

explained later.

The variable-gain charge pump with phase detector is con-veyed in Fig. 7. When the phase difference between the two

input signals (i.e., “input” and “Ref”) is large, the counter begins

to count and increase the charge/discharge current in discrete

levels. For situations such as start-up, the variable-gain charge

pump can charge with larger current, causing to ramp up

faster.

The conventional LPF for PLL is shown in Fig. 8. Since usu-

ally , the transfer function from to is

(3)

However, in this buck-converter design, the switching fre-quency is relatively low (about 1 MHz). When using the

approach shown in Fig. 8, the required value of is very

large and it is difficult to integrate on chip. The circuit in

the “Low Pass Filter” block shown in Fig. 6 uses a capacitance

multiplying technique reported in [16] to reduce the size of

. For the LPF in Fig. 6, the small-signal expressions can be

written as

(4)

Since the size ratio of to is and the drain currentratio of to is also is obtained.

The equation can be solved as

(5)

Compared with (3), it can be concluded that

(6)

Therefore, the size of is reduced by a factor of . In this

design, is chosen to be around 200. Since, in this work,

the system is implemented with a hybrid control scheme, incase that the pseudo-PWM mode is inactive, the output of the




Fig. 6. Complete system of the proposed pseudo-PWM voltage-mode hysteresis control buck converter (notex : STB = “Standby Mode”).

Fig. 7. Phase detector and charge pump in the PLL.

PLL (i.e., ) may diverge to an inappropriate value. Theslow loop response impedes prompt recovery of when

pseudo-PWM mode is active again. To prevent this,is deliberately bounded between and to generate ,




Fig. 8. Conventional low-pass filter.

where and are defined by a voltage-reference circuit and

. As a remark, this approach also helps

to settle faster during start up. However, the output bound is

expected to be active only when some inter-system transitions

happen, and it will not affect the normal operation. Therefore,

and are positioned far away from the normal dynamics

of .

The output bound circuit is shown in Fig. 9, where

. When is too low, may shut off, then

. The offset current

is to prevent from shutting off. When

will turn on and will begin to discharge the LPF by

, pulling down toward . The size ratio

of to is designed as 2: 1 to attenuate . This

further helps to reduce the required capacitor size in LPF.

B. Control Block

The pseudo-PWM control, as shown in Fig. 6, is simply a

hysteresis comparator, which its lower boundary (i.e., ) is set

by a voltage reference and its upper boundary (i.e., ) is set

by the output of the PLL. It is noted that the control logic block

will determine which control mode in the system should be used

according to the loading. It is designed that when the loading

current is less than around 15 mA, the system is switched to

PFM mode control. In the current-mode PFM control, the

node will switch to when is lower than the reference

voltage. The node will switch to the ground when the sensed

inductor current is larger than a reference current . In

the standby mode, a hysteresis comparator with fixed hysteresis

level is used to compare and . Blocks including the clock

generator, the PLL, the pseudo-PWM, and PFM control parts

are all shut down in the standby mode to save power.

The current-limit block compares the sensed inductor current

signal (in voltage form: ) with the maximum allowed cur-

rent. It will turn the high-side switch off in case that the inductor

current is too large to avoid damage of the inductor. The dead-

time block generates the non-overlapping driving signal from

the input. The discontinuous-conduction-mode (DCM) control

block compares with the ground to determine whether the

inductor current is zero or not. When the inductor current is zero,

the DCM block turns off and the system will enter the

DCM. The switching signals are fed into the drivers to driveand .

C. Zero Generator

In general, the ESR of the output capacitor creates a left-half-

plane (LHP) zero, which helps to stabilize the system. How-

ever, usually, a small ESR capacitor is desired in switched-mode

power converter design to reduce the voltage spikes. In that case,

the output voltage ripple is very small and the hysteresis power

converter may not function properly [17]. To solve this problem,a zero generator is inserted into the feedback path. The zero gen-

erator is a typical high-pass filter with gain. It is used to amplify

the ripple of the feedback voltage.

Fig. 10 shows the zero generator where and are the

transconductance and output resistance of the amplifier, and

and form the feedback network. A parasitic capacitor

is added to model the gate capacitance of further stages. The

small-signal equation is written as

(7)

Based on the valid condition of the amplifier that ,(7) is simplified and becomes

(8)

A LHP zero at is therefore created. Two LHP

poles at higher frequency are also generated. One is caused by

and the other iscaused by . The poles limit the bandwidth

of the zero generator, which should be higher than the switching

frequency but should not be too high since it will degrade thephase margin of the loop gain.

IV. EXPERIMENTAL RESULTS

The proposed fixed-frequency buck converter with voltage-

mode hysteresis control is fabricated using AMS 0.35- m tech-

nology. The die area is around 1900 m 2200 m. The output

bound block occupies around 0.036 mm chip area and con-

sumes around 0.3 mW during normal operation. The chip mi-

crograph is shown in Fig. 11. Extra capacitors are added in the

LPF of the PLL for tuning in the testing, and the actual capacitor

utilization is only about 50%. In the chip testing, 3.3 V,

1.8 V, 4.7 F and 4.7 H are used. Anexternal reference clock of 1 MHz is used. In the real applica-

tions, the clock signal can be generated internally.

The steady-state pseudo-PWM control in the continuous-con-

duction mode (CCM) at 200-mA loading is shown in Fig. 12.

Both the switching frequency and phase is locked to the refer-

ence clock (i.e., 1 MHz). The output voltage ripple is within

40 mV. Fig. 13 shows the pseudo-PWM control in the CCM

at 380-mA loading. The output voltage ripple is also within

40 mV. Although the loading current level is greatly different,

the switching frequency, phase and duty cycle are kept nearly

unchanged. This result reveals a fact that the voltage ripple is

not changed much while the switching frequency can be fixed.

The buck converter operates in the DCM when the loadingcurrent is about below 50 mA. The steady-state pseudo-PWM




Fig. 9. Circuit of the output bound.

Fig. 10. Equivalent circuit modelling of the zero generator.

Fig. 11. Chip micrograph of the proposed buck converter.

controlled in the DCM at 25-mA loading is shown in Fig. 14.

Slight ringing is observed due to the floating node of when

the inductor current approaches to zero. However, the switching

frequency still locks to the reference clock.

The switching frequency at different loading conditions is

measured and plotted in Fig. 15(a) for different loading cur-

rents and Fig. 15(b) for different input voltages. With averageswitching frequency around 1 MHz, the frequency error is

Fig. 12. Steady-state waveform in the CCM at 200-mA loading.

Fig. 13. Steady-state waveform in the CCM at 380-mA loading.

Fig. 14. Steady-state waveform in the DCM at 25-mA loading.




Fig. 15. Measured switching frequency at (a) different loading currents (b) dif-ferent input voltages.

Fig. 16. Measured load transient response for loading changing between 160and 360 mA.

within 10 kHz (i.e., 1%), while the frequency variation of

the conventional hysteresis voltage-mode buck converter could

be more than 100% as stated in [15] and [18]. This measure-ment proves the proposed scheme can significantly reduce the

Fig. 17. Zoom-in view of themeasured load transientresponse for I changingfrom 160 to 360 mA.

Fig. 18. Measured efficiency versus loading current in the pseudo-PWM mode.

TABLE ISUMMARY OF SPECIFICATION OF THE PROPOSED BUCK CONVERTER

variation of switching frequency of a hysteresis voltage-mode

buck converter.

The load transient response between 160 and 360 mA is mea-

sured and shown in Figs. 16 and 17. Benefiting from the intrinsic

behavior of the hysteresis control scheme, the response time is

5 s. The measured voltage spike is about 40 mV.

The efficiency at different loading conditions in the pseudo-

PWM mode is measured and plotted in Fig. 18. It is close to

95% up to the loading of 400-mA and drops to 75% when the

loading is 500 mA. The drop of efficiency when the loading is

higher than 400 mA is due to large conduction loss occurred atthe power stage. Table I summarizes the specifications of design.




V. CONCLUSION

A pseudo-PWM buck converter with hysteresis control

achieved by adjusting the hysteresis level of the comparator

using a PLL has been presented in this paper. Some design

techniques have been used to solve the integration and set-

tling-speed problem of the PLL. Moreover, different control

modes have been implemented and included to the buck con-verter. The design has been fabricated using AMS 0.35- m

technology. The measured load transient response between 160

and 360 mA is 5 s. The variation of the switching frequency

has been proven to be within 1%.

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Yanqi Zheng received the B.S. degree in microelec-tronic technology from the South China Universityof Technology, Guangzhou, China, in 2004, and thePh.D. degree from the Department of Electronic En-gineering, Chinese University of Hong Kong, HongKong, in 2010.

From 2004 to2006, he worked ineWaveIntegratedCircuit Design House Co., Ltd., GuangZhou, China,as a Design Engineer. He is now a Post-doc Fellowwith the Department of Electronic Engineering, Chi-

nese University of Hong Kong. His design interest ispower management IC, especially in switching mode power converter design.

Hua Chen received the B.Eng. degree in electronicengineering from the Chinese University of HongKong, Hong Kong, in 2010.

From 2008 to 2009, he worked for an internshipwith Advanced Analogic Technologies Inc. as anAssistant Engineer. He is currently working with theDepartment of Electronic Engineering of the Chi-nese University of Hong Kong as a Junior ResearchAssistant. His current research interests includepower-management IC and digital controlled powerconverter.

Ka Nang Leung (S’02–M’03–SM’08) received theB.Eng., M.Phil., and Ph.D. degrees from The HongKong University of Science and Technology, HongKong, all in electrical and electronic engineering.His Ph.D. research area was power-managementintegrated circuits in CMOS technology.

He joined the Department of Electronic Engi-neering, The Chinese University of Hong Kong,Hong Kong, in September 2005 as an AssistantProfessor. He was a Visiting Assistant Professorwith the Department of Electrical and Electronic

Engineering, The Hong Kong University of Science and Technology. Hiscurrent research interests include power-management IC for wireless telecom-munication systems in nano-scale CMOS technologies, ultra-low-voltageanalogue IC, RFIC, and biomedical IC for health care.

Prof. Leung was a recipient of a Best Teaching Assistant Award from theDepartment of Electrical and Electronic Engineering, Hong Kong University of Science andTechnology, in 1996. In 2007 and2010, he received theDepartmentExemplary Teaching Awards from The Chinese University of Hong Kong. Hereceived the 2003 Young Scientist Award of the Hong Kong Institution of Sci-ence. He is a technicalpaper reviewerof severalIEEE journals andinternationalconferences.

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