A Fault Diagnosis Technique for Flash ADC's - Circuits …apps.olin.wustl.edu/workingpapers/pdf/2006-09-001.pdf · IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 6, JUNE 1996 445

A Fault Diagnosis Technique for Flash ADC’s Anchada Charoenrook and Mani Soma

Abstract- This paper addresses the problem of diagnosis of flash ADC’s and proposes a fault diagnosis technique which employs the Differential NonLinearity (DNL) test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of DNL data from the ideal one. Hence, DNL data can be considered as a functional signature of the ADC. This property is employed for fault diagnosis. DNL patterns are used for fault location, and DNL data are used to calculate the fault values. Both single fault cases and multiple fault cases are considered. The technique proposed here relies only on DNL test data and not on the test method, thus the diagnosis can he carried out using at-operating- speed test data. This paper describes the concept and the detailed diagnosis algorithm. Experiments have been carried out to verify the practicality of the technique. They are presented and discussed in detail. The limitations and practical implementation issues relating to the technique are also addressed.

I. INTRODUCTION

HIS PAPER addresses the problem of fault diagnosis in T parallel or flash Analog to Digital Converters (ADC’s). Testing and diagnosis of mixed signal circuits, such as ADC’s, have been identified as being among the most serious problems faced by the development and manufacturing companies today [l]. Cost in production test time for ADC’s can account for as much as 25% of the total manufacturing cost; verification and debugging of first silicon can account for as much as 20-30% of the development cycle time. These problems are expected to aggravate as the circuit becomes more complex and more functions are added to the converters. In particular, high performance ADC’s such as the flash ADC’s, are in very high demand for use in the rapidly expanding telecommu- nication and video applications. Because of the performance requirements, these ADC’s are predominantly parallel in their design structure, require a large die area, and require high precision components. The number of components in an N-bit flash ADC is proportional to 2 N ; a 9-b flash converter consists of more than 1500 comparators and other components. Large die area increases the probability of failure, requiring diagnosis techniques for both design verification and production low- yield analysis. Due to poor device matching ability, most high performance ADC’s require calibration and trimming [ 11. Present calibration techniques compensate for deviations

Manuscript received April 4, 1994; revised May 26, 1995. This work was supported in part by the National Science Foundation (NSF Grant MIPS-9 21 1 504) and the Washington Technology Center. This paper was recommended by Associate Editor N. K. Jba.

The authors are with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195 USA.

Publisher Item Identifier S 1057-7130(96)03763-9.

in the measured parameters and do not correct the faulty value, because the faulty value cannot be obtained [ 11. A fault diagnosis technique able to perform fault identification (obtain fault values) will lay the groundwork for the development of more effective calibration techniques.

While decades of research have greatly advanced the diagnosis techniques of purely analog circuits, a number of unre- solved issues still exist: parametric fault issues, the problem of high computational complexity (generally combinatorial in nature) in some algorithms such as SBT (Simulation-Before- Test), and the problem of multiple faults and fault masking [2], [3]. Proposed analog diagnosis techniques with no internal access are still feasible for relatively small analog circuits (containing -10 op-amps), and are not applicable to mixed- signal circuits [4]. The problem of diagnosis of ADC’s is more complicated. In addition to the above problems pertaining to purely analog circuits, difficulties in diagnosis of ADC’s are due to the tightly coupled characteristics of the analog and digital signals, the lack of internal observation points on the IC, the nonlinear nature of the problem, and the lack of fault models.

Some general Designs For Test (DFT) and fault diagnosis techniques for mixed signal circuits have been proposed [5]. The application of a proposed framework for DFT of mixed signal circuits to the flash ADC is not practical, due to the excessive overhead circuitry required. Diagnosis techniques employing probing test systems-although applicable to a large number of circuits-are expensive, require expert per- sonnel to operate, and are geared toward diagnosis of prototype systems [6]. Other diagnosis techniques specific to ADC’s have been proposed [7] , [8]. However, they are diagnosis techniques of ADC nonlinearity at bit level, and hence, are only useful for bit weight conversion ADC’s, and not for flash ADC’s.

This paper proposes a fault diagnosis technique for flash ADC’s which uses the Differential NonLinearity (DNL) test data for diagnosis. In this paper, we dlemonstrate that there exists a direct relationship between faults and the DNL data of the converter, and that each fault iiffects the DNL data differently. Hence, DNL data can be considered as a functional signature of a flash ADC. This property is employed for fault diagnosis. The relation between faults and the DNL data is derived analytically, assuming’ that the digital encoder in the converter is fault free. In the diagnosis algorithm, the DNL pattern (DNL data over all output codes) is used to locate the fault and the analytical relation is usedl to compute the fault value. Because this technique uses DNL test data, it does not

‘This assumption is verified in Section VI.

1057-7130/96$05.00 0 1996 IEEE

446 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 6, JUNE 1996

rely on a specific ADC test method. Hence, it can identify v,, faults from a manufacturing test where the ADC is exercised at its operating speed (dynamic test), and it does not require

R2N-J

-v/\ Jeff "c,k+l

"Off vc,k

w

I , , . I , , , , I

a special tester as in the diagnosis using probing testers. The diagnosis algorithm does not rely on simulation. The technique performs fault location (obtaining fault locations) and fault identification (obtaining fault values).

The paper is organized as follows. In the next section, fault models considered in this paper are described. The definition of the DNL data is given in Section 111. In Section IV, we derive the analytical relation between faults and DNL data. Section V presents the general diagnosis methodology. Each of the steps in the diagnosis method are elaborated upon in the consecutive sections. Section VI describes the diagnosis of faults in the digital encoder. Section VI1 describes the fault diagnosis technique of the analog faults for the single fault case. Simulation and experimental results are presented. Practical implementation issues of the diagnosis technique are also discussed in Section VII. The detailed diagnosis algorithm for analog faults in the case of multiple faults is presented in Section VIII. The diagnosis algorithm for multiple faults differs from the algorithm for the single fault case in that it accounts for fault effects specific to the multiple fault case such as fault masking and fault equivalence. Simulation and experimental results of the multiple fault cases are presented in Section VIII. The paper concludes with Section IX.

11. FAULT MODEL

Flash converters consist of two subcircuits: the analog subcircuit which consists of the resistor string, and the comparators; and the digital subcircuit which consists of the encoder (see Fig. 1). The widely used stuck-at fault model is assumed for the digital circuitry [9]. The authors also extend the proposed fault diagnosis technique to include the stuck- open faults. Faulty behaviors in analog circuits are not well characterized at the macro level, and there are no widely used comprehensive fault models. As a result, most analog components are tested based on their behavioral specifications, i.e., functional testing [lo]-[13]. In this paper, we consider analog functional level fault models which include

1) resistor value out of specification; 2) comparator's offset voltage out of specification; 3) comparator's bias current out of specification. These faults have been shown in earlier work to closely

represent physical faults in the circuit [131, [141. For instance, a MOS comparator fault model estimated from manufacturing statistics and the device's nominal layout, shows offset voltage as a major fault [13]. These faults can also be derived from the specifications available from the manufacturer's data sheet [15]. The fault models cover both parametric and catastrophic faults, provided that they manifest themselves in the deviation of specification parameters.

This paper considers both the single fault case and the multiple fault case. In the presence of multiple faults, different fault cases may result in the same effect on the output of the circuit due to fault masking or equivalent faults. Fault masking and fault equivalence have been defined comprehensively in

R2

RI

RO

E I N

C 0 E- I I--) N

G L 1 1 0 G I C

N bits

Fig. 1. Schematic diagram of a flash ADC.

the context of multifrequency testing in [16]. In a similar way, we define functional equivalence as follows: For a test set T , a fault case d is equivalent to a fault case g if and only if the output response of the circuit of the two fault cases cannot be distinguished from each other. The output response of the two fault cases are compared. If their Root Mean Square Error (FWSE) is smaller than a margin 6, where 6 is the resolution of the measurement instrument, faults d and g are equivalent. The relation of equivalence partitions the set of possible faults into equivalence fault classes. An equivalent fault class can span both the analog and the digital domains.

111. DIFFERENTIAL NONLINEARITY ERROR

Deviation from ideal of the transfer function is categorized by different types of errors which include offset error, gain error, Integral NonLinearity error (INL), and DNL. DNL values are measures of step size deviations from the ideal ones (Fig. 2). DNL error is defined as the difference between successive code edges and the mean code width expressed in units of LSB [17]

Sj - LSB - ASj - DNLj = - LSB LSB

where DNLj is the DNL at code j, and Sj is the actual step size at code j in the transfer function.

An N bit flash converter generates 2 N output codes. Each code has one corresponding DNL data. Thus, theoretically there are 2N DNL data in the DNL test results. In practice, some histogram based DNL test methods discard the first and last codes. The DNL at the first and last codes in those tests are artificially large because overdrive input signals are used to ascertain that the tests cover all the output codes [17].

Iv. RELATION OF THE DNL AND ANALOG FAULTS

Deviation from the ideal of a component causes the transfer function of the ADC to deviate from ideal. If this deviation

CHAROENROOK AND SOMA: FAULT DIAGNOSIS TECHNIQUE 441

Output code word

voltage

Vj+l

Fig. 2. Transfer function of a flash ADC.

Fig. 3 . Modeling faults in various analog components.

exceeds a specified value, the ADC is classified as bad or faulty. Consequently, the DNL also deviates from its ideal value. Hence, there exists a relation f between faults ( e ) in

From Fig. 3, the voltage in the resistoir string can be written as

. , the analog components and the DNL data such that

2 N - 1 DNLj = f ( e l , e 2 , ” . , e F ) , f o r j E {1,...,2N} (2)

where F = number of faults. If the encoder is assumed fault (4)

free, f can be derived analytically. Given the fault models described in Section 11, we next derive this relation. As a general notation, the prefix A denotes deviation of a variable from its ideal or nominal value. SuperscripU i denotes the ideal value of the variable. Superscript n denotes the normalized value of the variable with respect to ideal values in the circuit as follows:

AlZ is the bias current fault value normalized with respect to the ideal current in the resistor string. ARE is the resistor fault value normalized with respect to its ideal value. AV; is the comparator’s offset voltage fault normalized with respect to voltage of one LSB. Consider a general topology of a flash converter shown in

Fig. 1. DNL data at an output j can be written in terms of the physical voltage at the input of the comparators and the fault models in Fig. 3 as

where Vc is defined as the ideal voltage at the negative input of the comparator without any offset voltage (V&), Ij is the current through resistor Rj, Rj is the resistor with the index number j , and 2 = Aqn where 1 E B, and B = {x I x is the index of a comparator’s offset voltage fault, where xi < xi+l <, . . . , < x,b, and nb <_ 2 N } ~

where Vref is the reference voltage of tlhe ADC, and ci E C, and C = {x 1 x is the index of a comparator’s bias current fault, where xi < x,+1 <, . . . , < xnc, and ne 5 2 N } . The bias current fault value is bounded by the current in the resistor string as

T I nc

Rearranging (4) we obtain

Defining a function h(VI ) j as

448 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS -11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 6, JUNE 1996

and substituting in ( 5 ) , we have

l=cn,

(9)

(AI,) R; Vref where AI: =

Substituting (9) in (8) and in (2), and noting that R; + C&AR1, we obtain a general 2 N - 1 Z N - 1

Cl=O Rl,Cl=, equation for DNL data at output code j as

DNLj = -1 + - AT+,, 1 + (ARjn) +

1 + cccz"=", A R W N )

where U , E A, and A = {x I x is the index of a resistor fault, where x, < x,+1 <, . . . , < x,,, and nu 5 a N } .

Equation (10) is the general relation between the DNL data at any output code j due to analog faults in the converter. In the fault free case, all the deviation values AR",AV", and AIn are zero, h(AI") becomes zero ((10)); DNL, = 0 for

i = 1; . . . , j , which is the DNL data expected from an ideal ADC. For large N , where N/2N << 1, (10) simplifies to

The first and second terms on the right-hand side of (1 1) are the effects of comparators' offset voltage out of specification fault from comparators number j and j + 1 on DNL data at output code j . The third term on the right hand side of (1 1) is the effect of resistor out of specification fault. If all current faults are zero, h(AIn) is zero, the DNL at code j is only affected by the fault in resistor j. The last term in (11) is the effect of the comparators' bias current out of specification fault. Assuming only bias current faults and expanding h(AIn) , , (11) reduces to The effect of multiple current faults on the DNL at output code j is proportional to the value of each current fault weighted by the relative position of the current faults (cz) to the position of code j. From (12) shown at the bottom of the page, if both resistor out of specification fault and biasing current out of specification fault are present, resistor faults behave as an additional weighting factor for each current fault.

V. DIAGNOSIS METHOD In Section IV, we showed that a relation exists between

faults and the DNL data of a flash converter. This relation is key to the diagnosis technique proposed in two aspects. First, (10) is used to calculate the error values of the fault given a DNL data or to calculate the DNL data of a possible fault case given the estimated fault value-no simulation of the circuit is required. With no internal access to the converter, 2" independent equations can be formulated; thus, the number of maximum simultaneous faults diagnosable using DNL data is 2N faults.

Second, (10) provides the information on how each fault affects DNL data at each and every output code. The characteristics in the DNL pattern (DNL data over all output codes) indicates the location and type of the fault. These patterns are illustrated in Fig. 4. In the single fault case, this pattern is unique for each fault. An exact fault case is identified by inspecting the DNL pattern. Equation (lo), which reduces to a linear equation, is used to calculate the error value. In the multiple fault case, although the DNL patterns are not unique to a fault case, they still provide information about possible type of faults and the position of the faults. DNL patterns are used in a heuristic scheme for selecting a possible fault case.

A flash ADC is tested using a manufacturing test method [7] , [SI. Once a flash ADC is tested and rejected, the complete DNL data from the manufacturing test are kept for diagnosis. A general procedure for diagnosis of faults in the flash ADC

c 1 q + C Z A I , " , + . . . + jAIj" - ( 2 N - m)AIZ - ( 2 N - c,c)AI~nc 2 N

DNLj =


Fig. 4. DNL patterns: (a) Resistor fault. (b) Comparator's offset voltage fault. (c) Comparator's bias current fault.

using DNL data is given in Fig. 5. Detailed description of each step is presented in the following sections. In the diagnosis method, faults in the encoder are examined first. Subsequently, analog faults are examined. Faults in the digital and analog circuitry are diagnosed separately. Multiple faults consisting of both faults in the analog and digital circuit are considered and treated as digital faults because digital fault masking restricts the ability to identify the analog faults. For instance, in Fig. 1, a stuck-at 0 at the output BO (the least significant bit) masks the resistor out of specification fault at R1. The diagnosis algorithm of analog components illustratedl as Steps 1 through 4 in Fig. 5, are described in detail, separately for the single fault case and for the multiple fault case, in Sections VI1 and VIII, respectively. In the multiple fault case, because DNL patterns cannot be used to exactly obtain the fault case, Step 1 is replaced by a heuristic fault case selection scheme which is based on the pattern of the DNL data. Steps 1 through 4 outlined above are iterated until a matching fault case is found.

VI. THE ENCODER We propose here two approaches for fault identification and

diagnosis of the digital circuitry in the encoder: identifying faults in the digital circuitry using DNL d.ata, and using DFT techniques.

A. Identification of Digital Faults Using DNL Data

For the case where the converter's DNL test data con- currently guarantees that the digital subcircuit is good, no

Step 0) Analyze the encoder.

IF no digital faults, THEN proceed with Step 1).

ELSE identi5 faults using digital fault diagnosis techniques.

##Diagnosis of analog faults.

Step 1) Identify the fault case (number of faults (F), type of faults, and location of faults).

Step 2) For F faults construct DNLl = f(ea,,e 02,....eoF) for j = I to F. Solve for estimated

fault values, eo, ,

Step 3) Use the estimated fault values to reconstruct the entire DNL data. Compute DNL',

fo r j = 1 to ZN. (DNL'is the computed DNL data, and DN,Lr is the actual DNL data).

Step 4) Compute the root mean square error (RMSE) between DNL', and DNLT,.

Step 4-1) IF (DNL,'- DNL,r)z > 6 , and e < e h o '< 0.1 THEN e = ekeo x 0.02,

The e, are changed according to the noise in the ADC. Repeat Steps 3) to Step 4). 2 N

Step 4-2) ELSE

is found. I = ' STOP.

2*

I = I

(DNL:- DNL,T)2 < 6 , where 6 is the error margin. The fault

Fig. 5. Diagnosis algorithm

additional test circuitry is required in either the analog or the digital subcircuit. We define a simple encoder as an encoder which does not contain any redundant dlevices or connections, and one which consists of a latch or flip-flop circuitry, a level detection circuitry, and a NOR logic encoder. An example of such a circuit is shown in Fig. 6(a).

Proposition: If the testing results of a flash ADC which contains a simple encoder do not show any missing code error, then for the stuck-at fault model, the eincoder is fault-free.

Proof: Consider a good simple encoder with no missing codes and start analyzing from the output. If the output of the encoder shows no missing codes, it can be deduced that its


d o c k Sour

needed. However, if ADC test methods used cannot detect all the stuck-open faults, such as the histogram test, additional testing to detect stuck-open faults must be performed prior to analog fault diagnosis. Several test generation algorithms and DFT techniques have been proposed for testing stuck-open faults [18]-[20].

VII. DIAGNOSIS OF ANALOG FAULTS (SINGLE FAULT CASE)

A. The Algorithm

For the single fault case, the relation between DNL data and each fault case from (10) is reduced to the following set of linear equations:

Resistor Out of SpeciJcation Fault: For j = k (a) (b)

Fig. 6. (a) Circuit diagram of a simple encoder. (b) Encoder circuit with scan path.

DNL, x 2 p ] - 1 E ARE

for 2N >> ARE. (13)

output bits can be individually set to 1 and 0. Consequently, the following can be deduced:

For j # k 1

I) The product lines i (Fig. 6(a)) in the NOR array can be DNLj = x 2 q - 1 E 0 individually set to 1 and 0.

for 2N >> ARE. (14) 11) Each product line can be set to 1 while the others are 0. From I, since line i can be set to 1, lines i l and i~ can be set to 1 as well. From both I and 11, since line z can be set to 0 and each line i can be set to 1 while other product lines are 0, it can be deduced that lines i l and 22 can be set to 0. Moving further back in the circuit, it can also be deduced that all the input lines to the flip-flops can be set to 1 and 0.

The above deduction shows that all the lines in the encoder can be set to 1 and 0. Hence, in an ADC with a simple encoder, if the DNL output data have no missing codes, for the stuck-at fault model, the encoder is fault-free. In this case, DNL data can readily be used for diagnosis of the analog components. If, however, the digital circuitry is faulty, then diagnosis can be performed using previously proposed digital fault diagnosis techniques [9].

B. IdentiJication of Digital Faults Using DFT

The second method used for non-simple encoders consists of incorporating extra test circuitry in the digital subcircuit or converting the latches between the comparator and the encoder into a scan path (Fig. 6(b)). The digital subcircuit is then tested prior to obtaining the DNL data. Test vectors are generated by a digital test generation technique [9]. If the digital circuit is faulty, previously proposed digital fault diagnosis techniques can be used [9]. No additional circuitry is needed for the analog subcircuit and the area overhead is <lo% in an 8-b flash ADC.

Although the stuck-at fault model is widely used, when CMOS technology is considered, the stuck-open fault has been pointed out to be a contributor to circuit failure [19]. Detection of stuck-open faults using this technique depends on the test method used to test the ADC itself. If the method is able to detect and identify a stuck-open fault, then this diagnosis technique can be readily applied to DNL data where no faults in the digital circuit have been found-no additional test is

Comparator’s Offset Voltage Out of SpeciJcation Fault.

DNL, = A V , for j = k , (15) DNL, = - A V , for j = k - 1, (16) DNL, = 0 (17) for j # (5, k - I}.

Comparator’s Bias Current Out of SpeciJication Fault: 2N-1

DNL, = ~ ~ ; ~ , Ri ai; for j < IC

DNL, = E$yp’ AI; for j 2 k .

(18) L o Ri

and IC-1

(19)

Equations (13)-(19) show that there is a unique DNL pattern corresponding to a fault case. Each type of fault is distinguishable by the major characteristics in its DNL pattern, which are the peak code and the transition code. The peak code is the output code where DNL data has a peak, and the transition code is the output code where the average of the cumulative DNL data changes sign. From (13) and (14), we can observed that resistor fault generates one peak data at code k , where k is the location of the fault. Equations (15)-(17), show that the comparator’s offset fault generates two complementary peak codes at k and k - 1. The comparator’s biasing current fault, on the other hand, generates a transition code at output code k . Fig. 4 gives an illustrative view of the peak and transition codes in the DNL pattems. In the diagnosis algorithm of Fig. 7, the number of peak codes and transition codes and their locations are used to identify the type and location of the fault. Based on the fault case, the corresponding equation is formulated at either the peak code or the transition code, and solved for the estimated fault value, eo.

L o R1

CHAROENROOK AND SOMA: FAULT DIAGNOSIS TECHNIQUE 45 1

Step 1) Find peak codes and transition codes.

Step 1-1) IF one peak code at k THEN fault case = resistor fault at k .

IF two complementiuy peaks at k , k + l THEN fault case = comparator's offset fault at k + l .

IF transition code at k THEN fault case = comparator's biasing current fault at k .

Step 2) Formulate eo = f ' ( D N L T k ) at peak or transition code k using the corresponding

equation from Eqs. (13.19). Solve for eo (DNLTk = actual test data).

Step 3) Using the estimated fault value, e', recompute DNL', f o r j = 1 to ZN.

Step 4) Compute RMSE between DNL', and DNL;.

Step4-1)IF ~ ( D N L ' L , C - D N L J ' ) I > 6 . a n d e < e f e 0 x 0 . 1 T H E N e = e f e o x 0 . 0 2 .

The sign of the increment corresponds to the sign of DNL noise at code k.

Repeat Step 3) to Step 4). 2"

Step 4-2) ELSE IF

Step 4-3) ELSE No match.

STOP.

Fig. 7.

2'

Z N 1 = I

( DNL,'-DNLJr)2 < 6 . Fault is identified. 2 : = ,

Diagnosis of analog faults (single fault case:).

The peak measurement data is used to calculate the estimated error value because its absolute value is largest, and hence its value is corrupted to a lesser extent by noise. The diagnosis algorithm for the single fault case below corresponds to Steps 1 through 4 in the general diagnosis method (described in Fig. 5.

B. Practical Implementation Issues

In practice, DNL value at each output code of a good converter is not zero, but varies within a small acceptable level, defined here as DNL noise (e.g., 0.05 LSB) If the noise is high comparable to the largest DNL data in the faulty converter, it is difficult for the algorithm to distinguish a faulty pattern from noise. Hence, while 6, which is the maximum matching error margin, should be as small as possible in order to obtain a good fit between the diagnosis and actual test data, it must be set higher than the average DNL noise of the good converter. The diagnosis technique proposed here is limited by DNL noise. DNL noise is determined by the accuracy of the test method used in locating transition edges in the transfer function (ADC test method); the noise signal generated from the ADC; and the uncertainty of the transition edges inherent in the circuit itself due to integrated circuit process statistical variations. To increase the robustness of the algorithm in the case of high noise level corrupting the DNL data at peak codes, Step 4-1 and Step 4-2 in Fig. 7 were incorporated into the algorithm.

The absolute DNL noise levels vary from one ADC to another. The design and measurements of a flash converter guarantee that the noise is at least within maximum DNL specifications, which is usually between 0.2 to 0.5 LSB [15]. Typically, noise is an order of magnitude less than the DNL specification. The higher the number of bits in the converter, the smaller the required absolute noise levels. Thus, the design of the flash converter ensures that the DNL noise scales with each ADC design to conform to specifications. Regarding the frequency of operation, the relation between the DNL data and faults in the circuit derived in Section IV shows no relation to the operating frequency. In very high frequency flash converters (over 200 MHz), clock jitter can increase the DNL noise level which consequently decreases the diagnosis

vcc= 5v L -

Fig. 8. Flash ADC.

resolution. However, DNL noise is still rjestricted to lower than the maximum DNL specifications. Hence, the limitation of the proposed technique is not directly dependent on the number of bits of the converter or to the frequency of operation, but to the DNL noise level related to the LSB in each converter. The resolution of the diagnosis algorithm is better than or equal to the DNL specifications of a converter, provided that only DNL noise is considered. In terms of diagnosability, the algorithm is limited to the fault models that were considered a priori. This is the case for all SBT-based techniques and most diagnosis algorithms which are based on fault models.

C. Results

Two kinds of test data were used for diagnosis: test data from from

1)

2)

simulation results using Saber simulator, and test data experimental results. DNL data from fault simulation of 12 analog fault cases and 10 digital fault cases from a 3 b flash ADC, and 8 analog fault cases and 14 digital fault cases from a 4-b flash ADC were used for fault diagnosis (ADC with simple encoders). The analog fault values ranged from 4 to 80%. All the analog faults were correctly diagnosed to within 5% of the injected fault value, and all the digital faults resulted in missing codes in DNL data. In order to verify the practicality of the proposed diagnosis technique using DNL data, the actual test data from a 3-b ADC with a simple encoder (Fig. 8) were used for diagnosis. The flash converter was constructed with discrete devices. The operating frequency of the converter was 100 kHz. The converter was tested using a histogram test with full scale sine wave input signal of 4 V at 1.1 kHz. A resistor fault was injected into the circuit by replacing the resistor of nominal value with a faulty one. A comparator's offset fault was injected by connecting a dc voltage source of AV; at the input of the comparator. Comparator's bias current fault was injected by connecting a dc current source at the inputs of the comparator. The circuit was tested for 10 analog faults comprising all the single fault cases, with fault values ranging from 2 to 70% with respect to their


Fault injected

R 2 +70%

Fig. 9.

D ~ ~ ~ ~ ~ ~ s RMSE' Fault injected D'agnos's results RMSE

R2 +69.7 % 0.0060 C2 -16% C2 -17.8 % 0.02

TABLE I DIAGNOSIS RESULTS FROM EXPERIMENTAL DATA

R 2 -20%

R2 -5%

R2+1.9%3

R2 -19.2 % 0 0024 C2 -3.68 '70 C2 -3.4% 0.013

R2 -4.6 % 0.0019 C2 +3.68 % C2 +4.1 % 0 013

R2+13% 0002 I2+20% I2+21.4% 0.011

C2+16% , C2 16.4% 10.05 I13+20% 112+21 6 % 10.007 1 Digital faults all DNL data BO s-I, BO s-0 12 s-l , i2 s-0 a3 s-I, a3 s-0 a4 s-I, a4 s-0

had missing codes

nominal values. The circuit was also tested for 8 digital faults. The DNL in each case were used for diagnosis. Table I shows a summary of the diagnosis results. All the analog faults were correctly diagnosed to within 8% accuracy of the fault value injected, and all digital faults resulted in missing codes in DNL data as expected.

To illustrate the diagnosis approach, a case study using the DNL test data from an actual flash ADC with -20% fault value injected at resistor 2 shown in Fig. 9 is presented below:

1) DNL data showed no missing codes. Thus, the encoder is good.

2) Found one peak code at output code 2. The number of peak codes indicates resistor fault; thus the fault is at resistor 2.

3) Computed initial fault value eo to be equal to -19.2% [solving (13)l.

4) Computed DNL? for j = 1 to 2 N . DNLC is shown in Fig. 9.

5) Compared actual and computed DNL data. Computed

6) Fault case identified as resistor fault of -19.2% at

In Table I, the lower accuracy obtained from the 1.9% resistor fault is due to the accuracy of the resistor used to inject the fault (&l% resistor) and due to DNL noise. DNL noise from the flash converter under test which can be observed from DNL data of a good converter varies from 3 x to

N $ c:,~(DNL; - DNL;)~ < 0.02.

resistor 2.

-3 x LSB [see Fig. 10(a)]. The peak DNL output data in the case of 1.9% resistor fault is 11 x LSB [Fig. 10(b)]. The DNL noise is nearly 30% of the peak DNL data which is approximately the difference between the fault value injected and the value diagnosed.

The 1.9% fault case shows that, indeed, the primary factor limiting the resolution of the diagnosis technique is the DNL noise. Dependency of DNL noise on the frequency of operation of the converter is related to the design of the ADC. DNL noise is usually higher in high frequency ADC's, but high frequency converters typically incorporate noise reduction techniques or are fabricated in a low noise technology. On the contrary, low frequency converters can have high DNL noise if they are poorly designed. Therefore the resolution of the diagnosis algorithm is directly dependent on DNL noise (which varies in different flash converters), and not on the frequency of operation itself. The upper bound of the DNL noise in any ADC is its DNL specification. Thus, the resolution of the diagnosis algorithm as applied to a specific converter is at least equal to or better than its DNL specification.

VIII. DIAGNOSIS OF ANALOG FAULT (MULTIPLE FAULT CASE)

The diagnosis of the multiple fault case differs from the single fault case in two main aspects. First, due to the presence of fault masking and fault equivalence, a number of different fault cases may cause the same DNL data pattern. Therefore, peak and transition codes in the DNL pattern cannot be used to exactly identify the location and the type of the fault as in the single fault case. Instead, a fault case selection scheme is developed to guide the search for a possible fault case matching between the DNL data from a faulty converter and DNL data from calculation. The diagnosis algorithm becomes an iterative procedure. Second, because of fault masking and functionally equivalent faults, the maximum resolution of the diagnosis algorithm is achieved to within an equivalent fault class.

A. Fault Case Selection Scheme The objective of the fault case selection scheme is to

systematically select a possible fault case, given a DNL pattern


* x lo-=

- - - - * - - - - -

- DNLT DNL

* - 0

-2

-4 - -8

I‘

- ,t

-

-*+ 2 3 4 S OUtPUt =Ode

Fig. 10. (a) DNL noise. (h) DNL of 1.9% resistor 2 fault.

P= {xlxisapeakcode, wherexi<xi+l<..... ~ x . ~ a n d n P 5 ZN1 T= [xlx is a transition code, where X , < X ~ + ~ < , ..., <xnT and nT 5 :LN] M is a inask vcctvr. Step 1) # N o clouding effects. Step 1-1) IFM # 1, For i = 1 to nP do

IF Pi and P,+1 are complementary and M,+1 = 0 THEN set of possible faults= set of possible faults U comparator’s offset fault at P,+l M , + I = 1;

ELSE set uf possible faults = set of possible faults U resistsx fault at P,. next i.

END Step 2) #Select faults with clouding effects. Step 2-1) IF M = l THEN Step 22) Compare number of peak codes to the table of similar faults. Step 2-3) IF list not empty

Obtain next fault case IF fault case = old fault case, GOT0 Step 2-3) ELSE old fault case = set of old fault case + new fault case.

Step 3) For all transition codes 4

STOP set of possible faults = set of possible fault l.J bias cunent fault at 4.

Fig. 11. Fault case selection scheme.

of a faulty ADC with multiple faults anld the possibility of fault masking. The scheme employs the rmmber of peak and transition codes as indications of a possible fault. Here, we define the clouding effect as the process by which multiple faults which come within a certain distance from one another interact and change the number of peak codes. The clouding effect happens under three conditions: lwo adjacent offset voltage faults, a resistor fault adjacent to a comparator’s offset voltage fault, and a resistor fault at the s,ame position as the comparator’s offset voltage fault. In the iselection scheme in Fig. 11, the fault case selection is divided into two parts: selection of a fault case from faults cases without clouding effects, and selection of a fault case fralm fault cases with clouding effects.

In the first part, because there is no clouding effect, each fault retains its peak and transition effect on the DNL pattern. The DNL pattern is interpreted as follows;. One isolated peak code or consecutive uniform-sign peak codes at code P, are

a resistor fault at is. Consecutive complementary peak codes at P, to can be either all comparator’s offset fault at i + 1, i + 3, . . , t , or all resistor faults at i , i + 1, . . . , t , or any combination of the two. A transition code at i is a comparator’s biasing current fault at i . Step 1 in Fig. 11 selects all the possible fault cases in this category.

In the second section, the fault case selection scheme selects fault cases with clouding effects. A list of similar faults is a precompiled list which tabulates faults with clouding effects based on their corresponding number of peak codes. Faults are selected from the set of faults in thls list of similar faults, with the same number of peak codes as those of the faulty ADC until the set is empty. Then, faults are chosen from other nonmatching sets until all the fault cases are exhausted or the program is aborted. A possible fault case is the union of a fault case selected from the similar fault list and the bias current faults obtained based on the transition (codes’ position.

The list of similar faults contains the number of peak codes relating to the corresponding fault cases. The test engineer chooses the maximum number of faults, F , that will be considered by the algorithm based on the probability of defects and the layout area of the ADC. The list is created by computing DNL data for all the combinations of faults with clouding effect. Faults are then grouped into different sets of similar faults based on their number of peak codes. Within a set of similar faults, the possible fault cases are tabulated in increasing order by their probability of occurrence. The probability of occurrence is obtained from physical fault analysis. In the case where no physical fault data is available, it is assumed that the faults in the integrated circuits are statistically independent and equally likely. Thus, fault cases with higher number of faults have lower probability of occumng than fault cases with less number of faults. As a

454

Major characteristics

1. One peak code (pl)

2. Two peak codes (pi, p2 where pl<p2)

3. Three peak codes (PI, p l+l , p1+2)

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 6, JUNE 1996

Set of possible faults

1.1 One resistor fault at pl and one comparator’s offset fault at p 1 + 1. 1.2 One comparator’ offset fault at p l+ l and one resistor fault at p l + l .

2.1 One resistor fault at p2 and one comparator’s offset fault p2, where pi+l=p2. 2.2 One resistor fault at p l and one comparator’s offset fault at p2, where pl+l=p2. 2.3 Two comparator’s offset fault at p i+ ] , and p2.

3.1 Two comparator’s offset fault at p l+ l and p1+2.

result, members in a set of similar fault cases are tabulated in increasing order by their number of faults. Table I1 presents the list of similar faults for the case of 2 faults.

The complexity of generating the list of similar faults is determined by examining the combinations of faults that result in clouding effects. Clouding effects occur when faults are at least within 2 j - 1 positions apart, where j is the number of faults. The combination of faults that need to be computed is 2 j - 1 choose j . In addition, each fault interaction can cause peak data or nullification of existing peak data. Therefore, both effects are examined requiring another 2j-l cases for each combination. Thus, the total number of computations is ET=1(2jJT1)2j-1. For F equal 2 and 4, the number of computations needed are 6 and 326, respectively. For large number of faults ( F > 5), using ( 2 ) S a 2 - / 6 , the complexity of generating the list of possible faults is approximated as 2 3 F

Although the complexity of generating the table grows rapidly, the number of maximum faults that need to be considered F is small. In general, the probability of occurrence of multiple faults decreases rapidly as the number of faults increases, and the probability of occurrence of multiple faults higher than a specific number of faults is negligible. This depends on the die area, the fabrication process, and the technology used. In [21], it has been shown that, on the average, the probability of occurrence of two faults is one order of magnitude lower than that of the single fault. Thus, in most cases multiple faults larger than 4 can be disregarded. Thus, the cost of generating this table is justifiable because F is small, and because the table is generated only once for a specific number of maximum faults.

d T ( ( F 2 t F W 2 ) .

B. Diagnosis Algorithm

The diagnosis algorithm is basically a pattern recognition technique which maps the test DNL data to a DNL pattern of a fault calculated using the equations derived in the previous section. The major difference between this algorithm and the algorithm for the single fault case presented in Section VI1 is that the diagnosis algorithm is enhanced to account for fault masking and fault equivalence. Also, the resulting system of equations is, in most fault cases, nonlinear.

Given the test data of the DNL test of a faulty ADC (DNLT), the algorithm in Fig. 12 examines the DNL pattern

Step 1) #Identify the fault case by using number of peak and transition codes

Step 1-1) Find peak codes and transition codes. Vector M=O in fault case selection scheme.

Step 1-2) Select fault case using the fault case selection scheme

Step 2) Fork faults formulate k equations fork DNL values at peak or transition codes:

DNLl =A el, e2, .. ex) DNL2 =fl el, e2, ..., ek)

DNLk =A el. e , ..., eiJ Solve for eoI, eo2, ... eok using a numerical method [22].

Step 3) Use eo to recompute D N L ~ , for j = I to zN. Step 4) #Compute the RMSE between DNL‘, and DNL:.

Step4-1)IF ~ C ( D N L / C - D N L , ~ ) ~ > B , ~ ~ et<e,?e:xO.l

THEN e , = er*ep x 0.02 I where the sign of the increment corresponds the sign to DNL

noise at code i. Repeat Steps 3 to 4.

Step 4-2) ELSE 1 Step 4-3) ELSE IF fault set is not empty GOT0 Step 1-2).

STOP.

Y

2”,=,

2”

(DNL: - DNL;)’ < 6 . Fault identified 2”, = I

Fig. 12. Diagnosis algorithm for multiple fault case.

for peak and transition codes. It selects a possible fault case using the fault case selection scheme. For a case of k faults, the algorithm formulates IC equations from DNL values at the output codes corresponding to the location of the IC faults. These are chosen because in the case of no clouding effects, high absolute DNL value occurs at the location of the faults. The system of nonlinear equations is solved for expected fault values by using a numerical method such as methods employing successive approximation or iteration [22]. The expected fault values are used to calculate the DNL data at all other output codes, DNLC . DNLC and DNLT are compared. If the patterns match, then the fault case and the error values are found. If they do not match, the algorithm selects another fault case and repeats the computation and matching steps. The procedure is continued until a match is found, or the fault cases are exhausted, or the program is aborted. The diagnosis algorithm shown in Fig. 12 corresponds to Steps 1 through 4 of the general method presented in Fig. 5.

As in the case of the single fault, Step 4-1 in Fig. 12 is a simple optimization step incorporated into the algorithm to guard against DNL noise and to increase the robustness of the algorithm. The error value, e,, corresponding to peak code or transition code, i, is changed according to the noise at code a. Information on the DNL noise is obtained from DNL data of a good flash ADC of the same type.

Due to functionally equivalent faults, DNLT data may be a representation of an equivalent fault class which has more than one fault case. Other functionally equivalent faults corresponding to the same equivalent class of faults can be obtained from a prederived list of functionally equivalent faults, or they can be obtained in real time by continuing the diagnosis algorithm to search for other fault cases that also match the same DNLT data. The diagnosis results in Table 111, case of C3 20% and C4 20% faults, illustrate the equivalent faults.

The worst case number of iterations of the diagnosis algorithm occurs when all possible faults are searched. Each peak data can result from either a comparator offset fault or a resistor fault. The maximum number of peaks for F faults is 2F. Thus the maximum number of fault cases is E:=,( ).

CHAROENROOK AND SOMA: FAULT DIAGNOSIS TECHNIQUE

Fault injected

RI 30%, R3 20%

R2 -30%. C5 20%

c 3 20%. c 4 20%

I5 20%. c 3 20%

1 I 1 I

Injected error values &e +70% and -70% respectively. Calciilated error 0.8

-0.2 - . . . .

2 3 4 5 6 -0.8,

output code

Fig. 13. DNL data of resistor 2 and 4 out of specification fault case.

Diagnosis results RMSE4 Iterations

R128.12%, R3 18.53%

R2 -29.04, C5 20.83%

R2 -20.21, R4 20.13% 0.0013 c 3 20.2%, c4 20.14% 0.0014

I5 20.24%, C3 20.8% 0.0028

TABLE I11 DIAGNOSIS RESULTS OF MULTIPLE FAULTS

R5 40%, C5 20%, 12 5%

R3 40%, C4 20%. 12 5%

R2 40%. C3 20%, 13 5%

R5 40.7%, C5 20%, 12 5.17%

R3 40.8%, C4 19.6%. 12 5.19%

R2 42 6%. C3 20%. 13 7 0% -

I l l Digital faults BO s-1 B1 s-0

All DNL data had missing codes

i l s-l and i4 s-1 a4 s- I and a6 5-0 B1 s-I, RI 40%

This is smaller than the complexity of generating the table of similar faults because a fault case in the table may be repeated in different sets in the table, but they are examined by the algorithm once. This worst case complexity of the algorithm using the fault case selection scheme is much less than a blind search which requires E,’=, ( ”;” ) operations, especially when F << 2 N .

For each iteration, the computational complexity of generating 2N DNL data in Step 3) is not proportional to 2 N , but to the number of maximum faults F . This is because DNL data only changes value at the position of the fault or at the position adjacent to the fault. For example, a resistor fault at position k and a current fault at position m. DNL values from 0 to k - 1 are equal and need to be computed only once. DNL at output IC needs to be computed. DNL values from k + 1 to m - 1 are equal and are computed once. Two more computations are required for code m and another for codes m + 1 to 2 N . Thus, for this case, 5 computations are needed. The worst case computational complexity for each fault case is 3F + 1, and less than or equal to 2 N . This worst case applies to all offset voltage fault cases. Thus, total worst case computational complexity of thle algorithm is 3F +

N

l(c:=,(?)) N ( 3 F 2 F ) / ( J a ( F ) ) . This is much smaller than the computational complexity of any previously proposed SBT-based technique (- 3m2N!, where m is the number of discretization levels of continuum faults) [2]. However, from the diagnosis results of 2 and 3 fault cases, it was found that for fault values > lo%, peak codes are g~ood indications of the fault location. None of the fault cases required searching out of its own set of similar faults. The search required < 5% of the total fault cases.

C. Results Two kinds of test data were used for diagnosis: test data

from simulation results using Saber simulator, and test data from experimental results.

1) Test data from 12 fault simulations of the circuit shown in Fig. 8 were used for fault (diagnosis. The faults covered 2-fault cases and 3-fault cases with and without clouding effects. Results from the diagnosis are presented in Table 111.

2) To verify the practicality of the proposed algorithm, we also applied the diagnosis algorithm to actual test data from the circuit shown in Fig. 8. A histogram test was used to obtain DNL data. The operating frequency of the ADC was 100 kHz, and the input test signal was 1.1 1 kHz. The fault case corresponding to resistor 2, and 4, deviation of 70 and -70%, respectively, is chosen to illustrate the approach. Fig. 13 sholws the DNL data from the actual test and the DNL data calculated from the diagnosis algorithm. The fault was correctly diagnosed and the fault values identified were within 10% of the actual injected faults. RMSE was 0.0037, where S =0.02 was used in the diagnosis algorithm. One iteration was required in this case.

D. Special Fault Cases The flash ADC consists of many repetitive cell structures

such as 2N resistors, 2N - 1 comparators, and flip-flops. The majority of the design is carried out by developing one design


of each cell, and they are layout and compiled into macro cells. These macro cells are then replicated and used in the design of the converter. Thus, design and layout errors are likely to repeat themselves in all the components that use the same macro cell. This section examines the effect of identical faults in all the components using the same macro cell on the DNL data, and investigates their detectabilities.

Resistor Out of Specijication Faults In the case where all resistors deviate from their nominal values by AR“, from (lo), the DNL data at an output code j is given by

The DNL data at all the output codes for this case are zero provided that the error values are equal. Thus a flash ADC with all matching resistors has DNL = 0, equal to its ideal value. This is because if all the other parameters in the flash converter are ideal, the structure of the resistor string divides the reference voltage according to the ratios of the resistors. Hence, theoretically, the absolute value of the resistors are irrelevant, provided that their ratios are correct. Comparator’s Offset Voltage Out of Speci$cation Faults: In the case where all the comparators have an offset voltage fault value A V , from (lo), DNL data at an output j is

DNLj 1 AV” - AV” = 0 for all j,where

j f 2 N - I, (21) j = 2N - 1. (22) DNLj = AVn for

The DNL data at all the output codes are zero except that of the last code of the converter. At the last code DNL is equal to AV“. This is because the effect of the offset voltage error from consecutive comparators at position j and j + 1 canceled out. However, at the last comparator, its offset voltage is not canceled out because it is the last one. The effect of this fault on the first code in the transfer function appears as the offset error of the A D C . Comparator’s Bias Current Out of Specijication Faults: In the case where all the comparators have biasing current fault value of AI“, from (9) and (IO), DNL data at an output j is

DNLj = ( g + j + 0.5) AI“.

The summation of all the bias current error values is bounded by the current in the resistor string. Thus for this case, li 2 E:=,’ AI. Expressing the bias current fault value in normalized form with respect to the ideal current in the resistor string, we obtain l / (aN - 1) 2 AIn . DNL data at the first code is most negative. The DNL value increases with increasing output code, and is highest at the last output code.

The case of identical faults in macro cells are likely due to design and layout errors. To incorporate these fault cases in the algorithm, they are added to the list of possible faults (such as Table 11). The diagnosis algorithm automatically examines these fault cases.

N

IX. CONCLUSION This paper has presented a fault diagnosis technique for

flash ADC’s based on the use of DNL data. Because this technique uses DNL test data, it does not rely on a specific test method to test the ADC. Hence, it can identify faults from a manufacturing test where the ADC is exercised at its operating speed (dynamic test). The diagnosis algorithm does not rely on simulation, requiring much less computational cost than SBT- based techniques. In the paper, we demonstrated that there exists a direct relationship between faults and the DNL data of the converter, and we have derived it analytically. Each fault effects the DNL data differently. DNL data is used in the diagnosis as a functional signature of a flash ADC. The diagnosis algorithm for analog faults uses the DNL pattern to locate a fault, and uses the mathematical relation derived to compute the fault values. The algorithm is presented for the single fault case and the multiple fault case. The multiple fault case differs from the single fault case in that it takes into account fault masking and fault equivalence. Simulation and experimental results are presented for both cases. They verify the practicality of the technique. Practical implementations issues were also discussed.

ACKNOWLEDGMENT

The authors wish to thank Integrated Measurement Systems Inc. (IMS) for supporting the experiments reported in this paper.

REFERENCES

2. Gu and W. M. Snelgrove, “A novel self-calibrating scheme for video- rated 2-step flash analog-to-digital converter,” in Proc. ISCAS 1992, pp. 601-604. R. Liu, Testing and Diagnosis of Analog Integrated Circuits and Systems. New York: Van Nostrand Reinhold, 1991. M. Slamani and B. Kaminska, “Analog circuit fault diagnosis based on sensitivity computation and functional testing,” IEEE Design Test Comput., pp. 30-39, Mar. 1992. A. E. Salama, J. A. Starzyk, and 5. W. Bandler, “A unified decompo- sltion approach for fault location in large analog circuit,” IEEE Trans. Circuits Syst., vol. CAS-31, pp. 609-621, July 1984. K. D. Wagner and T. W. Williams, “Design for testability of mixed signal integrated circuits,” in Proc. IEEE lnt. Test Con$, Wash., DC, Sept. 12-14, 1988, pp. 823-829. M. Marzouki and F. L. Vargas, “Knowledge-based debugging of ASICs: Real case study and performance analysis,” IEEE Znt. Con$ Computer- 4ided Design, Dig. Tech. Paper, Santa Clara, CA, Nov. 11-14, 1991, pp. 198-201. M. Vanden Bossche, J. Schoukens, and J. Renneboog, “Dynamic testing and diagnostics of A/D converters,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 175-785, Aug. 1986. M. F. Wagdy, “Diagnosing ADC nonlinearity at the bit level,” IEEE Trans. lnstrum. Measure., vol. 38, pp. 1139-41, Dec. 1989. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital System Testing and Testable Design. New York Computer Science Press, 1990. M. Soma, “A design-for-test methodology for active analog filters,” in Proc. IEEE Int. Test Con$, Wash., DC, Sept. 10-14, 1990, pp. 183-192. N. B. Hamida and B. Kaminska, “Multiple fault analog circuit testing by sensitivity analysis,” Analog Integrated Circuits and Signal Processing, vol. 4, no. 3, pp. 23143. Nov. 1993. A. Charoenrook and M. Soma “Fault diagnosis of flash ADC using DNL test,” in Proc. IEEE Int. Test Con$, Baltimore, MD, Oct. 1993, pp. 680-690. G. Devarayanadurg and M. Soma, “Realistic fault modeling and simulation for mixed signal integrated circuits,” Univ. Wash., EE-Report 12/93.


P. R. Gray and R. G. Meyer, Analog Integrated Circuits. New York: Wiley, 1993. Analog Devices, Datu Converter Reference Manual Volume II. Nor- wood, MA: Analog Devices. M. Slamani and B. Kaminska, “Multifrequency testability analysis for analog circuits,” in Proc. 12th IEEE VLSZ Test Symp., Apr. 25-28, 1994, pp. 54-59. M. Mahoney, Tutoriul DSP-Based Testing of Analog and Mixed-Signal Circuits. R. L. Wasdack, “Fault modeling and logic simulation of CMOS and MOS integrated circuits.” Bell Svst. Technol. J.. DD. 1449-1473.

Wash., DC: Computer Society Press of IEEE, 1987.

. May-June 1987.

[19] R. Chandramouli, “On testing stuck-open faults.,” in Proc. Int. Symp. Fault-Tolerant Computing, 1983, pp. 258-265.

[20] S . D. Millman and E. J . McCluskey, “Detecting stuck-open faults with stuck-at test sets,” in Proc. IEEE 1989 Custom Inregrated Circuits Con$. May 15-18, 1989, pp. 22.3/1-4.

[21] NEC Corp., Tokyo, Japan, “Latest trends and advances in VLSI technology,” Elektronika, vol. 32, no. 12, pp. 19-22, 1991.

[22] K. L. Nielsen, Methods in Numerical Analysis. New York: Macmillan, 1968.

Anchada Charoenrook reclwed the B.S.E E degree from Chulalongkorn University, Thailand in 1988. She received the M S and Ph.D degrees in electrical engineenng from the University of Washington in 1992 and 1995, respectively.

She is currently working in the area of design and test of mixed-analog and digital integrated circuits and systems.

Mani Soma received the B.S.E.E. degree from California State University, Fresno in 1975. He also received the M.S. and Ph.D. degrees from Stanford University in 1977 and 1080, respectively.

From 1980 to 1982, he was with the General Electric Research and Development Center, Sch- enectady, NY. He is now a Professor with the Department of Electrical Engineering at the Uni- versity of Washington, w’srking on design and test methodologies for VLSI circuits and systems.

Documents

A Fault Diagnosis Technique for Flash ADC's - Circuits …apps.olin.wustl.edu/workingpapers/pdf/2006-09-001.pdf · IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL