A Four-quadrant Analog Multiplier Under a Single Power Supply

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A four-quadrant analog multiplier under a single power supplyvoltage

Xiaobing Tao Chao Liu Tao Zhao

Received: 21 August 2008 / Accepted: 7 July 2011 / Published online: 20 July 2011

Springer Science+Business Media, LLC 2011

Abstract An analog multiplier driven by a single supply

voltage is proposed. Some improvements are introduced so

as to get a higher performance. The proposed analog mul-

tiplier can work precisely in four quadrants with a very small

THD. An added OTA keeps the linearity error of the circuit

smaller than 1%. The presented multiplier is designed on the

0.6 lm BCD process and the simulation results by HSPICE

shows a perfect performance. It can be used in any system

that requires a high performance analog multiplier.

Keywords Analog multiplier Single supply voltage Four quadrants Small linearity error

1 Introduction

Analog multipliers have been widely applied in many fields

such as adaptive filtering, modulation, detection and auto-

matic gain control, and it is an indispensable part especially

in the active power factor correct (APFC) controllers.

There are many approaches to design analog multipliers.

Some multipliers use the quadratic relationship between

drain current and gate-source voltage of the MOS transis-

tors in the saturation region [1], some use the linearity of

drain current of MOS transistors in the ohmic region [2],

some are implemented in current mode [35]. But the

common shortcomings are small linear input range, large

linearity error and high distortion. In this paper, a four-

quadrant analog multiplier with high-linearity based on an

improved Gilbert Cell is presented. By adding a level

shifter to the input, the linear input range is extended. The

linearity is improved by adopting an OTA to supply tail

currents for Gilbert Cell, which also decreases the THD.

Driven by a single supply voltage of?7 V, the proposed

circuit is characterized by large linear input range, small

linearity error and low THD.

2 Principles

2.1 Analog multiplier

Figure1 shows a simplified differential amplifier [6]. With

Q1 and Q2 biased in the active region, the relationship

between emitter current and base-emitter voltage is given

below

Ie1 IseVBE1=VT 1 Ise

VBE1=VT 1

Ie2 IseVBE2=VT 1 Ise

VBE2=VT 2

where Is is the saturation current and VT= kT/q is thethermal voltage.

As is known from Fig.1 that I= Ie1 ? Ie2 and

Vx = VBE1 - VBE2, so

I Ie1 1Ie2

Ie1

Ic11e

Vx=VT 3

I Ie2 1Ie1

Ie2

Ic21e

Vx=VT 4

Then the collector currents are obtained as follows:

X. Tao (&) C. Liu T. ZhaoXidian University, No. 2 TaiBai South Road, Xian,

Shannxi, China

e-mail: [email protected]

C. Liu


T. Zhao


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Analog Integr Circ Sig Process (2012) 71:525530

DOI 10.1007/s10470-011-9692-8



Ic1 I

1eVx=VT

I

2

I

2

eVx=2VT eVx=2VT

eVx=2VT eVx=2VT

I

2

I

2tan

Vx

2VT

5

Ic2 I1eVx=VT

I2

I2

tan Vx

2VT

6

Therefore

Vout Ic1Rc Ic2Rc Ic1 Ic2Rc

RcItan Vx

2VT

7

gm2oIc1

oVx

I

2VT8

Av oVout

oVx

Rc

2VTI 9

Equations8 and9 give the result that the transconductance

gm and differential gain Av are proportional to the tail

currentI, so automatic gain control can be implemented by

changing I. Furthermore, if I is proportional to a certain

inputVy, that isI= bVy, then the output can be expressed as

Vout AvVx Rc

2VTbVyVx aVxVy 10

wherea Rc2VT

bis a constant. In this case the differential

amplifier operates the multiplication of two analog

voltages.

2.2 Gilbert Cell

For the multiplier in Fig.1,Vymust be positive, leading the

multiplier only to work in two quadrants, which is not

suitable for the system that requires large swing and a

bidirectional variation in the gain. In this case, it is con-

siderable to adopt Gilbert Cell [7].

As shown in Fig. 2, Gilbert Cell contains a combination

of two differential pairs, which enables the gain to vary

continuously from negative to positive. The principle is as

follows: Suppose that Q1Q4 are absolutely identical (The

transconductance of each transistor is gm) and neglect the

base current of the transistors. Consider the pair of Q1Q2only, then

Av1Vout

Vxdue toQ1;Q2 gmRD 11

Similarly, consider the pair of Q3Q4 only, then

Av2Vout

Vxdue toQ3;Q4

gmRD 12Thus, the output can be written as

Fig. 1 A simplified differential amplifier

Fig. 2 Gilbert Cell

Fig. 3 Improved Gilbert Cell

526 Analog Integr Circ Sig Process (2012) 71:525530

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Vout Vout due toQ1;Q2 Vout due to Q3;Q4

Av1Vx Av2Vx13

By Eqs.8and9, |Av1| and |Av2| vary inversely asIc5and Ic6change in the same manner, which leads to a continuous

variation of the gain from negative to positive, and then

the four-quadrant multiplication of analog signals is

implemented.

The inverse variations inIc5and Ic6are implemented by

the differential pair of Q5 and Q6. Because Ic5 plus Ic6always equals Iss, they change in the opposite directions.

In actual applications, as a result of the nonlinearity

between the emitter current and VBE of a transistor, non-

linearity compensation should be added to the inputs of Q5

an Q6, or Q5 and Q6 are replaced by a MOSFET in triode

region.

2.3 Improved Gilbert Cell

Figure3shows an improved Gilbert Cell. Firstly, the input

Vx is sent to Gilbert Cell after being pulled up by a level

shifter with a differential output, which extends the linear

input range of Vx. Secondly, the input Vy supplies tail

currents to the pairs of Q1Q2and Q3Q4 through an OTA

with a differential output, which not only extends the linear

input range of Vy but also improves the linearity of the

multiplier.

3 Circuit

The proposed multiplier is shown in Fig. 4. Q1Q6 con-

stitute a level shifter, which extends the input range ofVx.

R1and R2are used to modulate the linearity of the input Vx.

The gain of the multiplier can be improved by decreasing

R3R4 or increasing R5R6. Q13 and Q14 are introduced

to improve the precision of current mirrors.

From Fig.4, the voltages and currents in the multiplier

can be expressed as

V1V2 Vxgm5;61

gm5;6gm3;4

1

gm1;2 jj R1

1

gm3;4

1gm3;4R1

1gm1;2gm3;4

1gm3;4R1 Vx 14

Fig. 4 The high-linearity

analog multiplier with low THD

Fig. 5 The DC-characteristic of proposed multiplier

Analog Integr Circ Sig Process (2012) 71:525530 527

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Ic10 kIc9 kVy

2 gm2

k

2gmVy 15

Ic12 kIc11 kVy

2 gm1

k

2gmVy 16

where k is the aspect ratio of the current mirrors Q9Q10

and Q11Q12. Therefore, the output can be written as

Vout Ic10

2VTR7V1 V2

Ic12

2VTR8V1 V2

Ic12 Ic10R

2VTV1 V2

kgm1;2

2VT

1gm3;4R1;21

gm1;2gm3;4

1gm3;4R1;2R7;8VxVy

aVxVy

17

wherea kgm1;2

2VT

1gm3;4R1;2

1gm1;2gm3;4

1gm3;4R1;2R7;8 is a constant.

Equation17 shows that the output Vout is a multiplica-

tion of the inputs Vx and Vy.

4 Performances

The performances of the proposed multiplier in Fig. 4 can

be confirmed by HSpice on the basis of UMC 0.6 lm BCD

technology with VTN = 0.83 V and VTP = 0.87 V.

The DC characteristic is shown in Fig. 5(a) and (b). It

can be shown the linearity and a dynamic range of2 V.

Figure6(a) and (b) show the linearity error of the pro-

posed multiplier while Vx and Vy input, respectively. From

Fig.6, the linearity error is smaller than 1% in all the input

range, especially smaller than 0.1% in [-1,1].

One of the realistic application of the proposed multi-

plier is amplitude modulation (AM). The frequency of

carrier and modulate waves are 500 kHz and 20 kHz,

respectively. The amplitude of both inputs are 2Vp-p. The

input signals and AM output are shown in Fig. 7.

Fig. 6 The linearity error of proposed multiplier

Fig. 7 aInput signals.b Output

signal


1 3



Figure8 shows the THD of the proposed multiplier. By

making Vx at 20 kHz with varied amplitude between 0.2

and 2Vp-p, The THD is smaller than 0.3% for different Vy.

The bandwidth of the proposed multiplier is shown in

Fig.9, which is larger than 10 MHz.

The comparison of the proposed multiplier with the

circuits proposed in the reference is presented in Table 1.

5 Conclusion

In the paper, a four-quadrant analog multiplier with high-

linearity is proposed with linearity error and THD smallerthan 1 and 0.3%, respectively. The achieved linear input

range is 2 V and the bandwidth is 10 MHz, so the pro-

posed multiplier is suitable for the system that is under high

voltage and requires large linear input range, low THD and

low linearity error.

References

1. Oliaei, O., & Loumeau, P. (1997). A CMOS class AB current-

multiplier. InISCAS 97. Proceedings of 1997 IEEE internationalsymposium on circuits and systems (Vol. 1, pp. 245248), 912

June 1997.

2. Prommee, P., Somdunyakanok, M., Angkaew, K., Jodtang, A., &

Dejhan, K. (2005). Single low-supply and low-distortion CMOS

analog multiplier. InISCIT 2005. IEEE international symposium on

communications and information technology(Vol. 1, pp. 251254),

1214 October 2005.

3. Diotalevi, F., & Valle, M. (2001). An analog CMOS four quadrant

current-mode multiplier for low power artificial neural networks

implementation. In ECCTD01 (pp. III325III328). Helsinki,

Finland, 2831 August 2001.

4. Gravati, M., Valle, M., Ferri, G., Guerrini, N., & Reyes, N. (2005).

A novel current-mode very low power analog CMOS four

quadrant multiplier. In ESSCIRC 2005. Proceedings of the 31st

European solid-state circuits conference (pp. 495498), 1216Sept 2005.

5. Liu, S. I., & Chang, C. C. (1997). Low-voltage CMOS four-

quadrant multiplier. Electronics Letters, 33(3), 207208.

6. Gray, P. R., Hurst, P. J., Lewis, S. H., & Meyer, R. G. (2001).

Analysis and design of analog integrated circuits (4th ed.,

pp. 708716). New York: Wiley.

7. Razavi, B. (2003). Design of analog CMOS integrated circuits

(McGraw-Hill International Edition, pp. 126129).

Xiaobing Tao got his MD in

XidianUniversity, Shanxi, China.

He has been studying design of

analog integrated circuits in

Institute of Electronic CAD,Xidian University for2 years and

specialize in design of Switch

Mode Power Supply (SMPS)

chips.

Fig. 8 The THD of proposed circuit

Fig. 9 The bandwidth of proposed circuit

Table 1 The comparison of proposed circuit with previous works

[2] [3] [5] Proposed

Supply (V) 1.5 1.25 1.5 ?7

THD 0.22%

@1 MHz

6%

@100 kHz

2%

@3 kHz

0.3%

@20 kHzLinearity

error (%)

0.5 2 1

Input range

(V)

0.4 1 0.8 2

Freq -3 dB

(MHz)

34 1 5 10

Technology

(lm)

0.2 0.8 0.8 0.6

Analog Integr Circ Sig Process (2012) 71:525530 529

1 3



Chao Liu is a member of Insti-

tute of Electronic CAD, Xidian

University. She has participated

in the design of several SMPS

chips. Now she is researching the

design of active power factor

correct (APFC) chips.

Tao Zhao is a graduate student

of the Xidian University and is

specialized in high speed

CMOS integrated circuit.


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A Four-quadrant Analog Multiplier Under a Single Power Supply