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A High-Density Subthreshold SRAM
with Data-Independent Bitline Leakage
and Virtual Ground Replica Scheme
Tae-Hyoung Kim, Jason Liu,
John Keane, and Chris H. Kim
University of Minnesota, Minneapolis
2/23
Agenda
• Introduction to Subthreshold Operation
• Proposed Subthreshold SRAM– Decoupled 10T SRAM Cell
– Write margin improvement utilizing Reverse Short Channel Effect (RSCE)
– Data-independent bitline leakage
– Virtual ground replica scheme
– Write-back scheme for stability
• 0.2V 480kb SRAM Measurements
• Conclusions
3/23
Introduction to Subthreshold Operation
• Characteristics– VGS is smaller than VTH
– Exponential current equation
– For low power, minimum energy applications
• Applications of Subthreshold SRAM– Wireless sensor nodes: data memory for DSPs
– Medical devices: hearing aids, pacemakers
– Portable electronics: cellular phones, PDAs
)1(0
t
DS
t
thGS
V
V
mV
VV
eff
DD eeL
WII
−−−−−−−−
−−−−====
4/23
Subthreshold SRAM Design Issues
• Mainly due to small Ion-to-Ioff ratio and current variation in subthreshold
– Read failure
: Reduced SNM, small bitline sensing margin
– Write failure
: Weak write path
– Limited array efficiency
: Data-dependent bitline leakage
– Performance and power variation
5/23
SNM of 6T SRAM Cell
QB (m
V)
RB
LB
RBL
• Read SNM is 18% of hold SNM at 0.2V• Read SNM is too small for robust subthreshold
operation
0
1
1
1
0
1
1
1
6/23
SNM of Proposed 10T SRAM Cell
0
1
1
1
• Decoupled cell node
• Read SNM is equal to hold SNM
• SNM = 38% of supply voltage
• Stability only limited by cross-coupled latch
VD
D
7/23
Write Margin Improvement
• Conventional Techniques
– Sizing: access TR vs. PMOS in latch
– Higher WL voltage for access TR
– Virtual VDD
• Proposed
– Utilize Reverse Short Channel Effect (RSCE) to strengthen write path
RBLB
RB
L
Higher voltage
Sizing
8/23
HALO Impact in Subthreshold
pppp++++
VDDVDDVDDVDD====1111....2222VVVV
pppp++++nnnn++++ nnnn++++
pppp++++ pppp++++nnnn++++ nnnn++++
HaloHaloHaloHalo
VDDVDDVDDVDD====0000....2222VVVV
Strong Strong Strong Strong
DIBLDIBLDIBLDIBL
WeakWeakWeakWeak
DIBLDIBLDIBLDIBL
SS SSuu uurr rr ff ff
aa aacc ccee ee dd dd
oo oopp ppii ii nn nn
gg gg
aa aacc ccrr rr oo oo
ss ssss ss cc cc
hh hhaa aann nnnn nnee eell ll High dopingHigh dopingHigh dopingHigh doping
Depletion Depletion Depletion Depletion
regionregionregionregion • HALO to mitigate Short Channel Effect (SCE) in superthreshold
• Negligible SCE in subthreshold region
• Dominant RSCE in subthreshold region
9/23
Utilizing RSCE for ImprovedDrive Current
• Optimal channel length in subthreshold region– Lopt=0.55µm for max. current/width– Lopt=0.36µm for max. performance/width
Channel Length (µm)
0
01
3
1
2
1
1.2
1.4
0 0.2 0.4 0.6 0.8 1
2
T. Kim, et al., ISLPED06
Lmin =0.13μμμμm
10/23
Utilizing RSCE for Write Margin Improvement
• Write access TRs utilizing RSCE (L=3xLmin)
• Increased current drivability: 3.3x at 0.2V
• Write margin improvement of 70mV at 0.2V
TR utilizing RSCEAdditional 8.5% area increase
11/23
Utilizing RSCE for Delay Improvement
• Narrower width for the same current drivability
• Reduced junction capacitance
• Improved delay due to reduced capacitance
Fat NMOS devices to utilize RSCE
12/23
Data-Dependent BL Leakage Problem
• Undetermined region due to data-dependency
• Possible read failure using single threshold read buffer
RBL
RB
L
ISSCC06
13/23
Proposed Scheme with Data-Independent BL Leakage
• Bitline logic high and low levels are fixed
• Logic level difference of 130mV at 0.2V with 1kcells/bitline
Q
N-1 Cells
RWL
RWLQ
RWL
Accessed Cell
N-1 Cells
Q= High Q= Low
Accessed Cell
RWL
RWL
RWL
QBB
14/23
Virtual Ground Replica Scheme
• Conventional: fixed switching threshold
• This work: VGND tracks RBL logic low level
15/23
Virtual Ground Replica Scheme
• Shared VGND across multiple read buffers• Replica bitline with fixed data to generate VGND
VG
ND
16/23
Pseudo-Write Problem
• Pseudo-write problem in unselected columns
• Worst case SNM due to current path
0 1 1 1
17/23
Write-Back Technique
• Write after read to solve pseudo-write problem
• Write-back to unselected columns
18/23
480kb SRAM Chip Implementation
19/23
Vmin and Leakage Measurements
0.14
0.15
0.16
0.17
0.18
1 2 3 4
1
10
100
0 0.2 0.4 0.6 0.8 1 1.2
10.2µA @ 0.2V, 27°C
(480kb SRAM)
0.17V @ 1k cells/
bitline, 27°C
• Vmin_read = 0.17V @ 1k cells/bitline
• Vmin_write = 0.20V
• 90% Ileak reduction at 0.2V compared to 1.2V
20/23
Performance Measurements
• 4.5x delay difference between four quadrants
• Exponential delay reduction with higher supply
0
2
4
6
8
10
12
14
0.1 0.2 0.3 0.4 0.5 0.6
0
2
4
6
8
10
12
128 256 512 1024
21/23
VGND Measurements
• Exponential increase of normalized VGND
• 0.1V bitline swing at VDD=0.2V
• VGND relatively constant with temperature
RBL
22/23
Improved Delay Utilizing RSCE
• Differential delay measurement circuit
• 28% delay improvement in predecoderutilizing RSCE
Td1+Td2Td1+Td_ckt+Td2
P: Proposed, C: Conventional
23/23
Conclusions
• Circuit techniques proposed to enable a 0.2V 480kb subthreshold SRAM
– Decoupled 10T cell for improved read stability
– Utilization of RSCE for improved write margin
– Data-independent leakage for enabling 1k cells/bitline
– Virtual ground replica scheme for optimal read buffer sensing margin
– Write-back scheme to eliminate pseudo-write problem