A Low Stress Bond Pad Design for Low Temperature Solder Interconnections on Through Silicon Vias (TSVs)

A Low Stress Bond Pad Design for Low Temperature Solder Interconnections on Through Silicon Vias (TSVs)

Xiaowu Zhang, R. Rajoo, C. S. Selvanayagam, C S Premachandran, W. K. Choi, S. W. Ho, S. W. Ong, Ling Xie, D. Pinjala, V. N. Sekhar, D.-L. Kwong

Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685, [email protected], Tel: (65) 67705423; Fax: (65) 67745747

Abstract Low temperature bonds are thin intermetallic bonds that

are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure.

This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Introduction 3D chip-stacking technology with TSVs is the next

generation integration technology for IC packaging. The benefits of 3D integration with TSV technology for future ICs include reduced interconnection delay due to shorter chip to chip interconnection lengths, smaller die size which is motivated by the portable and hand held applications, and ability to use distinct, even heterogeneous technologies (analog, logic, RF, MEMS, SiGe, III-V) on separate vertically interconnected layers to build complex systems [1-13]. In the new applications (such as Bio, MEMS, Optical, and RF devices), the vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance. The current method uses higher temperature of more than 300°C for bonding and interconnecting the different devices or wafers in the vertical fashion [8]. A high bonding temperature degrades the performance and sensitivity of the Bio, MEMS, Optical, and RF devices. Therefore, a low temperature bonding at less than 200°C is a must for vertically integrating the different systems such as multifunctional devices into a system in package.

However, low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints that fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This phenomenon is expected in thin interconnects and microbumps which are placed on TSVs.

Fig 1: Schematic of stacked dies fabricated by low

temperature bonding

This paper presents a novel pad design to overcome the situation of high stress in the joints. This results in significantly decreased tensile stress. This proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Test vehicle description Fig. 1 shows schematic of stacked dies fabricated by low temperature bonding. Table 1 shows the test vehicle specification. The test vehicle had ~600 I/O with 200-300 µm pitch. Die 1 has a size of 10.1 x 10.4 mm without TSV. Die 2 has a size of 9 x 8 mm with TSV. Die 3 has a size of 8 x 5 mm with TSV. The test vehicle for the die stacking was fabricated on 8” Si wafers with SiO2 coating.

D1 (750 µm thickness)

D2 200µm

200µm D3

TSV Thin IMC interconnection (~5µm)

1657978-1-4244-6412-8/10/$26.00 ©2010 IEEE 2010 Electronic Components and Technology Conference

Table 1: Test vehicle specification Size 10.1 x 10.4 mm Die 1

Thickness 0.76 mm Size 9 x 8 mm

Thickness 0.2 mm Die 2

TSV (tapered shape) 100 μm /50 μm Size 8 x 5 mm

Thickness 0.2 mm Die 3

TSV (tapered shape) 100 μm / 50 μm RDL Materials

(thickness) Ti (1 kA)/ Cu (1 μm)/ Au

(0.05 μm)

Passivation (PI)

Front side/Back side PI materials

PECVD SiN/ polymer (InterVia)

UBM Sputtered Ti (1KA) /Au (1 μm) Solder Thin film Indium

based (Evaporated) In-based solder

Fig. 2: Mesh and materials constituting (a) Global model (b) Submodel

Mechanical modeling and analysis Mechanical modeling simulations were carried out to determine the effectiveness of the proposed design. In particular, the tensile stresses which tend to pry open the joint were compared for two designs – the conventional pad (i.e., usual full pad) and the proposed pad design. All materials are modeled as elastic materials except copper material. The copper material is modeled as elastic-plastic materials. All material properties are shown in Table 2. The temperature loading for stress analysis is from 180ºC to 25ºC.

As the area of concern is the small bond in a large chip-to-chip bonded structure, and analysing such a detailed large model would use up a lot of computer time, the submodelling method was used. With this method, a large model with a coarse mesh is first modeled as shown in Fig. 2(a). The results from this model are then applied as boundary conditions to a finely-meshed cut-out of the original model. These cut-outs are termed submodels and one such submodel is shown in Fig. 2 (b).

Table 2: material properties used in modeling Material Cu Si Si

oxide Bond (IMC)

Ti

Young’s Modulus

(GPa)

130 130 70 80 116

Poisson Ratio

0.34 0.28 0.16 0.3 0.34

CTE

(10-6/°C)

18 2.9 0.6 11.41 8.9

Conductivity (Wm-1K-1)

400 149 1.38 17

Plastic properties

(MPa)

240 (0) 250 (0.008) 260 (0.010)

Fig. 3: Stress contour S33 in the axial direction in

Submodel

Fig. 3 shows the stress contour in the axial direction in submodel. There is a stress of about 150MPa in the joint. In order to reduce this stress, a pad design with a cavity at centre that the pad is decouped from the via was proposed. Submodel was further simplified into an axi-symmetric model subjected to a temperature change for even quicker analysis of both pad designs.

An axi-symmetric model of a single joint was used to simulate the effect of the contracting copper in the via on the interconnect during post formation cool down. The structures modeled include the TSV, IMC bonds and the pads. Schematic diagrams of the models used for the full pad and ring pad are shown in Figures 4 (a) and (b) respectively. Tensile stress in IMC joint used to assess effectiveness of ring pad design compared to full pad.

The tensile stress along the mid-plane of the IMC joint for the two above-mentioned models is shown in Fig. 5. It shows that with usual pad design, the joint is in a general state of high stress (150MPa) at the center as copper deforms most in the z-direction. On the other hand, with the ring pad design the stress at the center decreases to zero because the contraction of the copper in the via no longer pulls the pad

(a)

(b)

silicon

Ti pad

IMC bond

oxide

copper via

1658 2010 Electronic Components and Technology Conference

and the bond upwards. There is a comparatively higher stress at the edges of the bond with the ring pad.

(a) (b)

Fig. 4: Schematic diagram showing dimensions used in mechanical modelling for (a) full pad and (b) ring pad

Fig.5: Graph of stress (S33) along mid plane of bond for the conventional pad (i.e., full pad) and ring pad

From Fig. 5, it can be seen that the maximum tensile stress in the joint decreases by 50% with use of the ring pad. In addition, the bond length which experiences maximum stress decreases from 50% in the normal pad to 4% in the ring pad. This general decrease in the stress state of the joint will increase its reliability.

Test vehicle fabrication The TSV fabrication processes using via first approach are achieved for the TSV interposer of 200um thick with daisy chain structure as shown in steps 1-4 of Fig. 6. The 50um diameter via is tapered with 83 degree angle. The processes involved are silicon tapered via etch, sidewall dielectric isolation, barrier/seed metallization, via Cu plating and Cu chemical mechanical polishing (CMP).

Fig. 6: TSV interposer fabrication process & integration flow

Via etching The tapered silicon via has been developed in two stages as follows. 1) A non-BOSCH etch process consisting of a reactive ion

etching (RIE) process is used to produce the required tapered sidewall profile. This is basically a controlled isotropic etch process which uses SF6 + O2 + Ar (Argon) etch chemistry. The oxygen used helps in sidewall passivation and also controls excessive lateral etch rate. A proper balance between SF6 and O2 provides the desired taper angle to the via structure. As a consequence of this process, a sharp curvature is formed at the top. At the end of stage-1 (non-BOSCH process), the required via depth and taper angle is almost achieved except for the sharp curvature at the top.

2) After completing the stage-1, the etch mask is fully stripped and cleaned. The wafer is then subjected to a mask-less global isotropic etch process. In this etch step, the etched via patterns are mainly subjected to an isotropic etch plasma which is rich in fluorine radical. As the reaction in this step is mainly chemical in nature and mostly diffusion limited, it reacts more on the rough edges and sharp corners in the top region of the

1. Via Etch

2. Oxide/barrier/seed deposition & plating

3. Cu CMP

7-8. Back side passivation, metallization and UBM

10. Back-side solder deposition

9. De-bonding

4. Front side passivation / pattern

silicon

joint

25 m

35

5 m

200 m

pads

Cu

silicon

ring pad joint

25 m

35 m

5 m

5 m

200 m

-300

-250

-200

-150

-100

-50

0

50

100

150

200

-5 5 15 25 35

Distance along Path 1 (μm)

Str

ess

(MP

a)

Full pad Ring pad

5. Front side metallization / UBM pattern

6. Support wafer bonding & thinning


microstructures resulting in a well-rounded smooth sidewalls inside the vias (Fig. 7).

Fig. 7: SEM images of Silicon via after 2nd etching step with

well-rounded and smooth sidewall

Fig. 8: X-ray image showing the typical electroplated Cu via

Table 3: Key process parameters for barrier/Cu seed layer

Process Ti Cu Thickness 3 KA 2 μm DC Power 8 kW 8 kW Coil Power 600 W 600 W Bias Power 1000 W 1000 W

Ar Flow / Ch. Pressure 10 / 1.5 mT 20 / 2 mT Bias Voltage 100 V 150 V

Target Voltage 550 V 630 V Dielectric isolation/Barrier/Cu seed layer/Cu via plating The thermal oxidation was used for the isolation in this project. 1 μm SiO2 was grown in MFL furnace. Hydrogen and oxygen were mixed in the quartz bulb where they reacted to create a flame and steam water in 1050°C. The oxidation time of Si is three and half hours. Uniformity of SiO2 is within ±5%.

Barrier (3kA Ti) and Cu seed layer (2μm) has been deposited with help from Tango System. Good coverage at via bottom and via side wall has been achieved. The PVD machine used is Tango System AXCECATM. The key process parameters are shown in Table 3. The Cu electroplating solution for the via-filling application can be either copper sulfate or cyanide-based. Typical composition of an electrolyte includes CuSO4, H2SO4, Cl-, and additives including Suppressor, Accelerator and Leveler. The electroplating system used for the via filling is a research system from Rena. The plating solution is from Shanghai Sinyang Semiconductor Materials Co., Ltd. The typical wafer-level Cu-filled for 200μm deep vias are shown in Fig. 8. It should be noted that plating chemistry, low plating current and pre-treatment (i.e., wetting + DI rinsing + pre-absorbing accelerator) are the key contributors to void-free Cu-filling for the tapered via.

Fig. 9: Final CMP results

Cu CMP and annealing A thick layer (~40 μm) of Cu overburden was plated on the wafer surface because of long plating time (~30 hours) required to fill the 200 μm deep via. The wafer bowed due to the thick Cu on the surface. A suitable method was evaluated for removal of the copper. Chemical etching took a long time to remove the thick Cu and resulted in a non-uniform etch. Okamoto GNX 200 was used for the higher stress Cu CMP. Soft polishing pad and strong removal rate slurry from Rohms and Hass were used for the thicker copper removal. The load of polishing was 340g/cm2. The speed of pad and chuck was 90 rpm. Speed of slurry feeding was 185 cc/min. The wafer after final CMP is shown in Fig. 9.

Front side passivation/metallization/UBM processes Front side metallization process starts with SiN deposition and patterning on the planarized Cu filled TSV wafer to isolate the Si surface from the TSV and further metallization. Annealing was carried out after SiN deposition to relieve the internal stresses induced during SiN deposition. Conventional photo lithography and electroplating processes were used for RDL fabrication. RDL materials are Ti/Cu/Au. Under bump metallization (UBM) of Ti/Au was deposited using electroplating. Optical images of top view of front side UBM on TSV wafer is shown in Fig. 10.

Edge of wafer

200µm


Fig. 10: Front side metallization and UBM on TSV wafer

Fig. 11: Optical images of TSV at the backside of the wafer after via exposer

Support wafer bonding & thinning After front side metallization, the wafer with 200 µm deep Cu solid filled vias, need to thin down to the thickness, to expose the vias at the backside and to bring the interconnects from front side to backside of the TSV wafer. Thin wafer handling system is required to handle 200 µm thick wafer during backside metallization. Support wafer bonding using temporary adhesive material HT10.10 from Brewer Science was used for thin wafer handling. Temporary adhesive material of 12 µm thickness was coated on to the support wafer surface and backed at 110ºC for 5 min to remove the solvent from the coated material layer, and then bonded to the TSV wafer. Support wafer bonding was carried out under vacuum of 1 X 10e-4 torr, at 220ºC with 3500 N force for 5 min using EVG bonder. Finally, optimized support wafer bonding process was successfully achieved to handle 200 µm thick TSV wafer fabrication processes such as via exposer and backside metallization. Cu solid filled TSVs were exposed at the backside of the TSV wafer using Okamoto back grinder/polisher. Initially, final polishing after via exposure was carried out using Si backgrinding and polishing using Si polishing slurry. It was observed that 5 µm Cu protrusions were present at the vias which leads litho issues in further dielectric layer process. Cu protrusions height was reduced to below 1 µm by introducing CMP process after via exposure and achieved very good

control on Cu protrusion height by using the Fujimi Cu CMP slurry RDS-10901 with equal etch selectivity for both Si and Cu. The CMP parameters used for via exposer to reduce the Cu protrusions is tabulated in Table 4. Optical image of TSV after backgrinding and Cu CMP is shown in Fig. 11.

Table 4: CMP parameters used for Cu protrusions removal Polishing Parameter Units

Time 150 sec Load 150 g/cm2

Pad Speed 90 rpm Chuck table speed 80 rpm

Slurry feed rate 180 cc/min

Fig. 12: Optical images of back side passivation and opening

Back side passivation/metallization/UBM processes After via exposure, passivation layer deposition and patterning is required to passivate the Si surface from the backside metallization and to connect the Cu filled TSV to backside metallization respectively. Generally, SiN is used for Si isolation from further metallization. However, SiN deposition temperature is 250ºC or above, and temporary adhesive material used for support wafer bonding cannot withstand such high temperatures. So, low cure temperature spin-on dielectric material InterVia was evaluated on bare Si surface in terms of adhesion using peel test. Evaluation results showed very good adhesion of InterVia dielectric film to bare Si surface even after critical moisture sensitivity test level 1 (MST L1). As a result, SiN passivation was replaced with spin-on dielectric InterVia and it was cured at 175ºC for 3 hours to avoid high temperature process. Optical images of back side passivation with InterVia photodielectric 8023-2 and opening was shown in Fig. 12. Backside metallization process was optimized for single RDL of Ti/Cu/Au and InterVia dielectric film of 5 μm as RDL passivation with support wafer. Electroplate Ti of 1KA thickness/Au of 1µm thickness was used as UBM for low temperature solder bumps on the backside of the wafer.

Support wafer de-bonding/Back-side solder deposition After back side metallization process and UBM pattern process, support wafer was de-bonded along with dry film layer by sliding the wafer at high temperature of 220-250ºC

Ø 30µm


and then followed by dry film stripping and cleaning of adhesive material cleaning on the front side of the wafer using cleaning chemical from brewer Science. In-based low temperature solder metallization was deposited on the Au UBM layer on the 8” TSV wafer with e-beam evaporation chamber. 0.05 µm Au was coated to prevent oxidation of the In-based layer.

Fig. 13: C2C process for die stacking using low temperature process for comparison of the conventional pad design with

the proposed pad design

Low temperature bonding process Based on the previous work [14], we could manage to bond uniformly with In-based alloy solder at 180°C as the lowest temperature. In this study, the bonding temperature was fixed at 180°C, and the bonding time and the bonding pressure were optimized together with the annealing temperature and time. Finally, the optimal condition was obtained as follows: 45 sec. as a bonding time, 6 MPa as a bonding pressure, 120°C as an annealing temperature, and 12 hours as an annealing time.

C2C bonding process using the low temperature solder The next process was to stack 3 chips using the C2C process. The top two chips were with TSVs while the bottom chip was without TSVs as shown Fig. 1. The two pad designs (i.e., the conventional pad design and the new pad design) were used for comparison purpose. C2C bonding was carried out with the low temperature solder and bonding was done with a highly accurate flip chip bonder. C2C process for 3 die stacking is shown in Fig. 13. The bonding temperature was at 180°C and the entire bonding was done at the flip chip bonder. After bonding the chips were annealed at 120°C for 12 hours to completely transform the solder into intermetallics (IMC) phase [14]. A cross-sectional SEM image of the stacked dies fabricated by using the new pad design is shown in Fig. 14a. A top view of the proposal pad is shown in Fig. 14b. In short, test vehicle fabrication for the chip to chip (C2C) stacking with the conventional pad design and the new pad design has been demonstrated

Fig. 14a: A cross-sectional SEM image of the stacked dies

fabricated by using new pad design

Fig. 14b: A top view of the proposal pad

Mechanical shear tests/drop impact reliability assessment In order to investigate the effect of pad design on the shear strength of the solder joint, mechanical shear tests were carried out on the bonded samples with two pad designs. Results are shown in Fig. 15. It is found that the samples with the proposal pad design have a higher shear strength than those with conventional pad design. In order to investigate the effect of pad design on the drop impact performance of the solder joint, JEDEC drop tests were carried out on the bonded samples with two pad designs. Results are shown in Fig. 16. It is found that the samples with the proposed pad design have a better drop impact performance than those with conventional pad design. In short, mechanical reliability tests show improvement in reliability with proposed pad design.

Fig. 15: Influence of pad design on the shear strength of the solder joint

170u

95um

1st bonding

2nd bonding

Annealing at 120oC for ~12hrs

D1 (750 m thickness)

D1 (750 m thickness)D

D2

D3

0

0.05

0.1

0.15

0.2

0.25

0.3

Conventional paddesign

Proposed paddesign

Shea

r Str

engt

h (M

Pa)

Max

Min

Ave


Fig. 16: Influence of pad design on the shear strength of the solder joint

Conclusions A low stress bond pad design for low temperature solder

interconnections on TSVs has made a few significant achievements. Some of the important results are summarized below: 1 A novel bond pad (which decouples the interconnect

from the TSV) has been designed and simulated to reduce the joint stress by 50%.

2 The tapered TSV processes (e.g., silicon tapered via etch, sidewall dielectric isolation, barrier/seed metallization, deep via Cu filling) have been established. Dishing issue on Cu via after Cu CMP has been successfully overcome by using the new pad design.

3 A double-sided multilayer metallization process on 200 µm TSV wafer with low temperature and low volume Pb-free solder have been demonstrated.

4 Drop impact test shows improvement in reliability with proposed pad design.

5 Shear test shows the samples with the proposal pad design have a higher shear strength than those with conventional pad design.

Acknowledgments Part of this work is the result of a project initiated by the

9th IME Electronic Packaging Research Consortium (EPRC-9), the members of which are ASM Technology Singapore Pte Ltd, Chartered Semiconductor Manufacturing Ltd., EVG, Hitachi Cable, Infineon Technologies Asia Pacific, National Semiconductor, STATSChipPAC, Institute of Microelectronics (IME), Institute of High Performance Computing (IHPC) and Institute of Materials Research and Engineering (IMRE) under A*STAR in Singapore. The authors are grateful to members of EPRC 9 - Project 4 as well as IME staffs who had contributed and made this work possible.

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12. Xiaowu Zhang, T. C. Chai, John H. Lau, C. S. Selvanayagam, K. Biswas, S. Liu, et al, “Development of through silicon via (TSV) interposer technology for large die (21x21mm) fine-pitch Cu/low-k FCBGA package,” Proc. of the 59th ECTC, San Diego, CA, USA, May 2009, pp. 305-312.

13. Khan, N., Rao, V. S., Lim, S., Ho, S. W., V. Lee, Xiaowu Zhang, et al, “Development of 3D silicon module with TSV for system in packaging,” Proc 58th Electronic Components and Technology Conf, Lake Beuna Vista, FL, May. 2008, pp. 550-555.

14. W. K. Choi, C. S. Premachandran, S. C. Ong, L. Xie, E. B. Liao, K. Ahmad, et al, “Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking,” Proc. of the 59th ECTC, San Diego, CA, USA, May 2009, pp. 333-338.

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A Low Stress Bond Pad Design for Low Temperature Solder Interconnections on Through Silicon Vias (TSVs)