A Modular and Retargetable Framework for Tree-based WCET analysis Antoine Colin Isabelle Puaut IRISA - Solidor Rennes, France

A Modular and Retargetable Framework for Tree-based WCET analysis

Antoine ColinIsabelle Puaut

IRISA - SolidorRennes, France

2ECRTS 2001, Delft, The Netherlands

Hard real time

Real time tasks must meet their deadlines Hard real-time: critical applications

Deadline miss catastrophic consequences

Scheduling algorithm Must ensure that all tasks will meet their deadlines

Schedulability analysis (off-line) Require information on scheduled task

WCET : worst case execution time


Estimating the WCET

Test and Measurement How to exhibit the worst

case behaviour of the program ?

Exhaustive testing: practically impossible

Unsafe

Static analysis Safe, but pessimist Mainly automatic Requires the source code of

the analysed programs The programming language

must be adapted: restrictions: no indirect calls,

... annotations: loop bounds, ...

Unsafe estimates

Exact WCET

OverestimatedWCETs

Measurements Static analysis


Static WCET analysis

The static analysis result Should be a safe and tight estimate of the worst execution time

Depends on a specific hardware

Is provided for isolated code

The two levels of WCET analysis High level analysis: statically determine the longest execution

path in the program, and estimate the WCET along this path

Low level analysis: determine the execution time of basic

blocks, taking hardware effects into account


High level: tree-based analysis

Requires well-structured programs

WCET calculation using a timing schema

Loop [4]

If

BB1

BB2

BB0

BB5

BB4BB3

Sequence

Sequence BB6

BB7

int x,p=0,i=0;for(x=0;x<5;x++) { if(i%2) { p++; } else { i++; }}

Asse

mbl

yco

de

BB0

BB1

BB7

...

Basic blocks

WCET(SEQ) WCET(S1) + … + WCET(Sn)S1;…;Sn

WCET(IF) WCET(test) + if(test) max( WCET(then) , WCET(else) ) then else

WCET(LOOP) maxiter*(WCET(tst)+WCET(body)+WCET(inc))for(;tst;inc) + WCET(test)+WCET(exit) {body}

Timing schema

Equation system


Low level: hardware effects

Goal: reducing the pessimism of the low level analysis

Pipeline effect: WCET(Basic Block) < WCET(instruction)

Cache and branch prediction effect:

WCET(instruction) is variant, depending on the internal hardware state

Last decade Various architectural features have been considered (Caches, Pipeline, Branch prediction, …)

Several methods proposed, and often designed independently

Leads to an integration issue instruction BB


Integration issue: the modular approach

Definition of modules Modules are in charge of analysing architectural

features effects Co-operation through well defined interfaces

New WCET representation and extended timing schema

Retargetability Changing modules in the framework Using a new architecture description file


Salto : Assembly manipulation tool

Assemblydescription file

Modular and Retargetablestatic analysis framework

Heptane

Syntactictree

Control flowgraph

Sou

rce

file

WCET

Maple

.maple

Front-

end

BBI-Cache Branch Pred.

Pipeline

WCET of BBs ExtendedTiming schema

Modular partsDataFramework


Loop

Loop

Ln-levels are associated with loop constructs ex: [ ], [0], [0.0], [0.1], [0.1.0], etc.

Partial order on ln-levels

Useful for characterising analysis results Analysis results (events/estimates)

depend on the considered ln-level

Ex: I-Cache conflict

(BBa,[0]) (BBb,[0.1.0])

BBb prefetch

Cache miss when loop [0] is executed, hit otherwise

(BBb-miss,[0]) : ln-level < [0] = hit , ln-level [0] = miss

Loop nesting level information

Loop

Loop

Seq

[ ]

[0]

[0.0]

[0.1.0]

[0.1]


Instruction cache analysis

I-Cache analysis module

Adaptation layer

I-Cache AnalysisResults

adaptation

Basic block

I-Cache WCET information

Basic block -> Instruction blocks Portion of basic block that fit exactly into a cache line (instructions and instruction fragments) Allows to take into account various instruction sets

Existing I-Cache analysis technique Example: static cache simulation

Iblock misses are expressed using ln-levels Pair: (Iblock,miss-level) I-Cache analysis result: a set of pairs

< (IB16,[0.2]) , (IB17,[0]) , (IB18,never)

>


Branch prediction analysis

Similar to I-Cache module

Adaptation layer

Branch Pred. AnalysisResults

adaptation

Basic block

B.Pred. WCET information

Basic block -> Control Transfer Instructions At most two branching possibilities at the end of the BB

Existing branch prediction analysis technique Example: static BTB simulation [JRTS00]

Two miss-prediction levels (ln-level): jmp/seq

< (BBjmp4,[0.1]) , (BBseq

4,never) >


Pipeline analysis (1/2)

Adaptation layer

Pipeline simulation

I-Cache WCET information

I-Cache WCETinformation

Representation of

the WCET of basic blocks

Branch Pred. WCET information

Use I-Cache and BTB analysis results

WCET info require adaptation Ex: I-Blocks -> Instructions

Existing pipeline simulation technique Reservation table, simulator, ... Inter/intra basic block effect

Results expressed using ln-levels 2 WCETs (jmp/seq) per ln-level


Incremental representation of the WCET (1) basic WCET associated with the lowest ln-level of the

basic block (2) difference between WCET of subsequent ln-levels

One WCET representation per outgoing edge

WCETseq(BB) = <(15,[0.1.0]),(+2,[0]),(+3,[]) >

Pipeline analysis (2/2)

[0.1.0] 15[0.1] 15[0] 17[ ] 20

Pipeline analysis results

WCETjmp(BB) = <(15,[0.1.0]),(+4,[0]),(+3,[]) >

[0.1.0] 15[0.1] 19[0] 21[ ] 24

Seq jmp


10 <(15,[0.1.0]) , (2,[0]) , (3,[ ])> = <(150,[0]),(20,[0]),(3,[ ])>

One basic block Two WCETs select WCETseq/WCETjmp

Use sets of pairs : + and are redefined

Operator : union of two sets of pair

Operator : M (wcet,ln-lev) = (Mwcet,L) if L ln-lev

= (wcet,ln-lev) otherwise

Adapted timing schema

L

+L

L

[0]

[ ]

[0]

Seq

Loop [10]

WCET Repr.


Conclusion and future work

Co-operation of several HW analysis techniques Prototype configuration: Intel Pentium Reduction of the pessimism of estimates

Analysis results: presentation on Friday, session 10 Future work

New modules: ex: pipeline analysis (super-scalar, out of order execution)

Extend the framework to handle data caches, ... Retarget the analyser Make the analyser available for community use

Further information: www.irisa.fr/solidor/work/hades

Documents

A Modular and Retargetable Framework for Tree-based WCET analysis Antoine Colin Isabelle Puaut IRISA - Solidor Rennes, France