A. Nardulli, ETH Zurich1 1.What is PET? 2.The a-Si:H material 3.The Thin Film on ASIC (TFA) technology 4.Quantum Efficiency measurement with laser 5.QE

1A. Nardulli, ETH Zurich

1. What is PET? 2. The a-Si:H material3. The Thin Film on ASIC (TFA) technology4. Quantum Efficiency measurement with laser5. QE optimization: study of a-Si:H photodiodes deposited on glass and on chip5. The new photo detector structure6. Final layout of the ASIPET chip7. Conclusions

CHIPP Meeting Geneva, 12 June 2008 A. Nardulli

ETH, Institut for Particle Physics (IPP), Zürich Switzerland.

ASIPET: a low noise optoelectronic integrated readout with a-Si:H photodiode array for PET


What is PET?(Positron Emission Tomography)

• Compound like sugars (glucose) are labeled with signal-emitting tracers and are injected into the patient.

• The short-lived isotope decays, emitting a positron.

• After a positronium annihilation process 2 back-to-back photons of energy 511KeV are emitted.

• The photons are detected by scintillating crystals and read out by a matrix of photo-sensors (PMT, APD,…)

• A computer reassembles the signals into actual images.

Because cancer cells are highlymetabolic, they are easily seen by a PET scan.

Is a nuclear medical imaging technique which produces an image of a functional process in the body


The a-Si:H material

Silicon atoms not arranged in an ordered structure

• Defects such as dangling bonds and distorted Si-Si bonds (in both lengths and angles)

Defects yield energy levels in the energy gap where e-h recombine

• Reduced mobility • Band edges of the Si are replaced

by a broadened tail of states Hydrogen atoms saturate dangling and

weak bonds reducing traps• Increases the tolerance to

impurities

a-Si:Ha-Si:HHydrogenated amorphous silicon is a tetrahedrally bonded amorphous semiconductor

a-Si:H is known to be a radiation hard material may be attractive for High Energy Physics


Introduction to the project

The idea is to develop a new photo-sensor technology: Vertical integration of a:Si-H n-i-p photodiode and a pixel readout chip. The a:Si-H is used as photosensor for a PET to detect the output light from the LYSO

crystal (420 nm).

• Interesting points:– High degree of system integration.– Low cost.– High Photo Detection Efficiency after QE optimization – Low bias voltage.

• Critical points are:– Optimization of Quantum Efficiency for 420 nm wavelength – Ultra low noise signal retrieval.– Full depletion of photodiodes.– Leakage current.


TFA (Thin Film on ASIC) technology

• Vertical integration technique comprises the deposition of a detecting layer on top of a readout chip.• In our case TFA technology is achieved by deposition of a hydrogenated amorphous silicon (a-Si:H) film

(n-i-p diode structure) on top of an ASIC chip that perform both charge amplification and read-out processing.

• Advantages of TFA using a-Si:H:

» a-Si:H presents the technological advantage of being deposited at low temperature on large area .

» Simple detector construction, compared to hybrid detector schemes.» Large potential for system cost reduction.» No need of bump bonding.

Deposition based on VHF-PE-CVD technique by IMT Neuchatel

ASIC

a-Si:H Detector

Particle

ASIC

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Insulation layer/ASIC passivation

a-Si:H diode } Detector


•The photons detected in the i-layer create e-h pairs.

•Motion of electrons and holes generated in the depleted region induce a current.

•The non depleted zone in the diode acts as a high resistive layer for the signal, because of the low conductivity of intrinsic a-Si:H

•For UV detection a thin layer (~1 μm) coupled with a crystal is in principle fine, but Cdet ~(1/d)

Photodiode thickness: 10-12 μm

The photo-detector structure


a-Si:H diodes deposited on glass: QE results

• The top transparent conductive layer is made of indium tin oxide (ITO) and for standard a-Si:H diodes has a thickness of 65 nm which corresponds to a deposition time of 1’45’’ .

• Studies performed on samples on glass have shown that reducing the deposition time to 45’’, for the ITO layer, optimizes the quantum efficiency at wavelengths from 350 to 450 nm. This deposition time corresponds to an estimated reduced thickness of the layer of 28 nm.

• For the reduction of the optical loss the thickness of the p-layer has been reduced. The optimized photodiodes have a deposition time for the p-layer of 4’ to 5’ compare to 10’ for a standard p-layer. The thickness of the p-layer has been reduced to approximately 20 nm, while the thickness of the n-layer is between 30 and 40 nm.

Measurement of a-Si:H photodiodesdeposited on glass before and after treatment of top layers: one can see the increase of QE for shorter wavelengths(pin thickness ~5 μm)

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The photo-detector prototype

The first photo-detector prototype (MACROPAD chip) originally designed for particle detection. Top view before and after photo-sensor deposition; 4x4mm2 ASIC with an array of 8x6 octagonal pixels with 150m pad.

•Implemented in 0.25m CMOS technology.•Each channel consists of a charge amplifier and a shaper stage. •Optimized to detect 0.1fC (625e-) signal with a measured noise of 30e- noise:

OPTIMIZED FOR SMALLER PIXELS AND INPUT CAPACITANCE


QE: measurement with light source

Instead of a crystal, a pulsed laser (λ~405nm) is used to simulate the incoming signal. The laser is mounted together with the attenuator and the 100 μm diameter collimator; it is then centered with the 150 μm width pixel of the a-Si:H photodiode by means of micromanipulators.

LASER 405 nm

Light attenuator ~:300

100 μm Collimator

The laser, in AC mode is controlled by a pulse generatorwith TTL signal level and variable pulse width (50-500 ns)


Calibration of the light source

LASER 405 nm

CalibratedAPD

Calibratedamplifier

Light attenuator ~300

100 μm collimator

Gain 175+/-2QE=75%+/-3%T under control

Amplifiercalibrated in HSPICE

A test setup using calibrated amplifier and an APDhas been used to determine the number of incoming photons from the laser for a given pulse width: this number will be used for the QE calculations for the a-Si:H photodiode deposited on chip.

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a-Si:H diodes deposited on chip: QE results

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QE measured at λ=405nm: Average value ~ 45%Non optimized diode deposited on chip

QE~45%

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QE measured for λ=405nm in average 77% (min=69% max=83%)Optimized diode deposited on chip

QE~77%

Number of photons~4100 +/-120;A good uniformity response is also visible from the study.


Input specifications for 9-pixel structure

LYSO crystal: 32000 ph/MeV ~16350ph@511KeV

Experimentally on a 2x2mm2 surface one collect ~40% of the light because of the solid angle, the LYSO-photosensor coupling and reflections6540ph•6540ph/9 pixel Number of photo-electrons in input=725•QE~77% and FillFactor~95% gives a PDE=QE*FF~73%

Input charge=725*PDE=530e-

Using an other crystal with high light output like Lantanium Bromide (LABr3-60.000ph/MeV) could improve the input signal of a factor 4, but it sacrifices spatial resolution to improve energy resolution.

•Pad Width=squares 0.6x0.6 mm^2 Detector Capacitance~10pF


Readout electronics of the ASIPET chip

New structure: regulated cascode to enhance the open loop gain.Noise optimization brings to increase the input bias current with consequent reduction of the output resistance and of the gain of the stage: the regulated cascode guarantees a sufficiently high open loop gain and eliminates the influence of the input capacitance on the dominant pole.

•Rise time~750 ns•Feedback capacitance=6 fF•Bias Current input Transistor= 4.5 mA•Gain preamplifier@1MHz 80 dB•Gain preamplifier & shaper@1MHz 100 dB•Closed loop gain ~800 mV/fC

Total noise in simulation (includes flicker, GIC & other thermal contrib.) ENC~52e- for a 490 μm pixel



Linearity for (-1,1) fCGain is ~800mV/fC

Reduction of the amplitudefor an increase of the leakage currentin the feedback branch



preamplifierDecoupling capacitors

CR RC filter


Layout of the ASIPET chip

4 x 5.5 mm2


Conclusions

Photo-diode: QE on optimized samples measured: ~75-80%. PDE~70-75% P and ITO layer of photodiodes reduced for an optimization of

photodiode at 350-450 nm Study on different thicknesses of the diodes have shown that 10-12 μm

will ensure full depletion of the diode without influencing drastically the input detector capacitance

3x3 pixels of 660 μm width gives optimum PDE with 2x2 mm2 LYSO crystal, but a 4x4 pixels structure minimizes the leakage current.

Input capacitance has been calculated for the different pixel sizes: it varies from 7 to 10 pF for the two structures.

Readout electronics: Leakage currents up to 5 nA per channel can be compensated by feedback circuit.A mathematical model of the circuit, which agrees with the HSPICE simulations, shows that ENC=50-60e- for the 2 structures with a total SNR of 22-26.The ASIPET chip is in production (IBM) and will be delivered June-July 2008.


CR-RC Shaper

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The shaper stage consists of a high-pass filter built with component C1 and R1 and an integrator built with two cascaded stage of amplifiers working in common source configuration t~120ns

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Output response in the time domain obtained with this simple MATHEMATICA model mathes quite well the HSPICE simulator output plot.

1fC input charge


Noise results and SNR

Expected input signal: 300e- and 545e-

Simulation noise results:Series noise 30 and 44e-

Leakage current expected= 300-500 pAParallel noise ~30e- & 24e-

Total noise in simulation (includes flicker, GIC & other thermal contrib.) ENC~52e- for the 490um and 62 for the 660 um width pixels

Total Signal to Noise ratio is respectively multiplied by 3 and 4 for the 3xe and 4x4 macro pixel structures: i.e. assuming that in the 3x3 structure the 9 pixels get the same amount of light, the 9 signals are summed, while the total rms noise is 3 times higher

3x3: SNRpixel~8-9 SNRcrystal~264x4: SNRpixel~5-6 SNRcrystal~22


CMOS chip

Metallic back contacts

a-Si:H i-layer

a-Si:H n-layer

a-Si:H p-layer

ITO

Light orparticles

Oxide

a-Si:H i-layer

a-Si:H n-layer

a-Si:H p-layer

ITO

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Oxide

The leakage current is:

• Dependent from the Electric field and diode thickness.

• Strongly influenced by the geometry of the substrate: a‑Si:H diodes deposited on non-planar substrates exhibit increased leakage currents due to corner and border effects.

– field concentration at substrate steps, spikes or other sharp surface features

• Bigger opening on the passivation reduces the total leakage current!

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The leakage current measurement

Leakage current Measurement (nA)

Documents

A. Nardulli, ETH Zurich1 1.What is PET? 2.The a-Si:H material 3.The Thin Film on ASIC (TFA) technology 4.Quantum Efficiency measurement with laser 5.QE