Embed Size (px)
Citation preview
Microelectronics Journal 90 (2019) 342–352
Contents lists available at ScienceDirect
Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo
A new low-power, universal, multi-mode Gm-C filter in CNTFET technology
S. Mohammad Ali Zanjani a, Massoud Dousti b,*, Mehdi Dolatshahi a
a Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iranb Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
A R T I C L E I N F O
Keywords:Low-powerUniversal Gm-C filterInverterCarbon nano tube field-effect transistor(CNTFET)
* Corresponding author.E-mail addresses: [email protected] (S.
https://doi.org/10.1016/j.mejo.2019.01.003Received 15 March 2018; Received in revised formAvailable online 15 February 20190026-2692/© 2019 Published by Elsevier Ltd.
A B S T R A C T
In this paper, a new low-power multi-mode Gm-C universal filter is proposed in carbon nanotube field-effecttransistor (CNTFET) technology using only 11 inverters and 2 grounded capacitors. The proposed circuit re-duces the power consumption effectively due to the proper use of inverters as operational transconductanceamplifier (OTA) blocks. Moreover, the center frequency and quality factor of the proposed filter can be tunedelectronically with low sensitivity values. The proposed circuit is simulated in HSPICE using 32 nm CNTFETtechnology parameters at �0.2 V supply voltage, and its performance is compared with the circuit proposed in32 nm CMOS technology. As simulation results show, for certain value of center frequency, the proposed CNTFETfilter not only reduces the power consumption by 66%, but also extends the center frequency up to 54%, at thesame power consumption value in comparison with 32 nm CMOS technology. Finally, the proposed CNTFET filterbenefits from a considerable reduction in chip area.
1. Introduction
In the recent years, continuous-time integrated filters have beenwidely used in both wired and wireless applications; these applicationsare categorized into major groups based on some considerations such asprocessing elements (active/passive), the type of input/output configu-ration, signal operation mode, frequency bandwidth, supply voltage,power dissipation and kind of integrated capacitors used in the circuit[1–10]. Various Gm-C filters have attracted extensive attentions due totheir high frequency bandwidth, simple circuit realization, integrationcapability and electronic tunability of the filter parameters such as centerfrequency (ω0) and quality factor (Q) [3–8]. Analog “Current-Mode”integrated circuits are widely used due to their lower required supplyvoltage as well as lower power consumption, better linearity behavior,fewer number of components, wide dynamic range and higher frequencybandwidth in comparison with their “Voltage-Mode” counterparts[9–17]. Mathematical operations on signals in current-mode circuits aresimpler to perform in comparison with voltage-mode circuits [9,10].Moreover, current-mode circuits can be used as direct cascading circuitsto achieve the low/high input/output impedance requirements for real-izing analog filters [11,12]. In analog signal processing domain, thedesigner requires active filters that can properly operate with eithercurrent/voltage input or output signals [4,11,18–21]. Therefore,designing “Multi-Mode” universal filters that can generate all the
M.A. Zanjani), [email protected]
24 October 2018; Accepted 6 Ja
filtering responses (i.e., high-pass filter (HPF), low-pass filter (LPF),band-pass filter (BPF), band-stop filter (BSF) and all-pass filter (APF)) inall modes of operation, using just one circuit configuration, is verychallenging [4,7,10,17–25]. In other words, multi-mode Gm-C universalfilters have attracted more attentions due to their reduced chip size andtheir lower power consumption and cost [4,18–21].
Due to the increasing demand for portable electronic devices andimplantable medical systems, low power design of integrated circuits is achallenging task [2,4,6,8,14,16,24,25]. On the other hand, due to someproblems that are caused by miniaturizing the dimensions of transistorsbeyond the 45 nm technology node, the conventional CMOS technologyfaces more complex issues and challenges. In fact, further miniaturizationcauses the following problems: process variations, leakage currents, theeffects of short channel transistors, effect of high electric field, limitationsin lithographic process and quantum confinement effects [3,16,26–38].
Considering the above facts, nanometer integrated circuit designersshould contemplate emerging technologies such as carbon nanotubefield-effect transistor (CNTFET), which delivers some benefits such aslower power consumption, smaller size (nanoscale) and scalability [16,27–38], MOSFET-like circuit behavior, ballistic transfer and highermobility of carriers. Another important benefit of using CNTFET tech-nology includes the similar values of carrier mobility for both N-type andP-type CNTFET devices (μn¼ μp) with the same transistor dimensionsthat leads to an identical driving capability and I-V characteristics
c.ir, [email protected] (M. Dousti), [email protected] (M. Dolatshahi).
nuary 2019
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
[32–34]. Furthermore, lower values of intrinsic (parasitic) capacitancesthat leads to a higher frequency bandwidth and lower intrinsic delay forCNTFET integrated circuits in comparison with CMOS technologies areother advantages of CNTFET over CMOS technology [16,28–34,38].
Therefore, CNT devices with two major types of single-walled(SWCNT) (Fig. 1a) and multi-walled (MWCNT) structures are the mostpromising candidates to substitute CMOS technology nodes for less than45 nm. Furthermore, conducting or insulating behaviors of CNTFET de-vices are determined by the chirality vector (m, n), which is the wrappingvector that the graphite sheet is rolled up along it as it is shown in Fig. 1b[29–38]. The indices (m, n) specify the chiral angle of the carbon atomsalong the nanotube structure. If (m� n) 6¼ 3k, where k is an integernumber, the SWCNT acts as a semiconductor, else it shows a conductive(metallic) behavior [25,28,32–40].
Due to the high-speed carriers, quasi-ballistic transport andnanometer-scale structure, SWCNT is successfully used in the design ofVLSI systems such as digital combinational logic gates, full adders,multiplexers, SRAM, etc. [25–28,39,40]. On the other hand, the design ofanalog integrated circuits such as OTA, current conveyor and filter cir-cuits in the CNTFET technology is still demanding high research efforts[16,38,41].
This paper presents the design of a new low-power, inverter-based,universal, multi-mode Gm-C Filter in 32 nm CNTFET technology. Themain purpose of this design is to introduce a new circuit topology plus atechnology migration from CMOS to CNTFET in order to maximize theadvantages of CNTFET technology. Therefore, the proper combination ofthese two benefits results in an improved overall performance of theproposed structure.
This paper is organized as follows. In section 2, the physical structureand the descriptive parameters of CNT transistors are introduced. The useof an inverter block as an OTA circuit in both CMOS and CNTFET tech-nologies are analyzed and compared in section 3, where the structure ofthe proposed Gm-C filter is also presented and its ability of multi-modeoperation, as well as the sensitivity analysis is discussed in details. In
Fig. 1. a) A typical single-walled carbon nanotube (SW
Fig. 2. Typical structure of a MOSFET-like CN
343
section 4, the results of circuit simulation, temperature analysis andMonte-Carlo simulation result are presented; in addition, the perfor-mance of the proposed circuit is compared with other reported designs.Finally, in section 5, some conclusions are presented.
2. CNTFET structure and parameters
A typical structure of a MOSFET-like CNTFET is shown in Fig. 2. As itis obvious from this figure, a CNTFET is a three-terminal device con-sisting of semiconducting nanotubes between the source and drain ter-minals. These nanotubes act as the transistor channel that is controlledelectrically via the gate terminal. The structural parameters used formodeling a CNTFET in HSPICE are summarized in Table 1.
As it is discussed in Refs. [25–28,35,38], the diameter of a carbonnanotube (DCNT) can be calculated from Eq. (1), in which a¼ 2.49 Å isthe distance between the centers of two adjacent nanotubes (latticeconstant).
DCNT ¼ affiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffim2 þ n2 þ mn
p
π(1)
The width of the CNT transistor (W) can be calculated using otherstructural parameters such as the diameter of the CNT (DCNT), number ofCNTs (N) and inter-CNT pitch (S), as it is expressed in Eq. (2) [16,28,38,41]:
W ¼ ðN � 1ÞSþ DCNT (2)
Analytical threshold voltage VT is expressed in Eq. (3a), and theTaylor series expansion of VT shows a linear relationship with Eg and aninverse relationship with the diameter of CNTFET Therefore, thethreshold voltage can be simplified as it is given in Eq. (3b), whereVπ ¼ 3.033 eV is the carbon π–π bond energy and e is the electric charge[25–28,38,43].
CNT) structure, b) The chirality vector concept.
TFET, a) cross section view, b) top view.
Table 1CNTFET structural parameters used for circuit simulations [42].
Design Parameter Symbol Value
Physical channel length Lch 32 nmThe length of doped CNT source/drain extension region Lss (Ldd) 32 nmThe mean free path in intrinsic CNT channel (due to non-ideal elastic scattering)
Lgeff 200 nm
The width of metal gate (Sub-lithographic pitch) Wgate 6.4 nmThe dielectric constant of high-k top (planer) gate dielectricmaterial (HfO2)
Kgate 16
The thickness of high-k top (planer) gate dielectric material(HfO2)
Tox 4 nm
Diameter of CNT DCNT 1.49 nmThe distance between the centers of two adjacent CNTs Pitch¼ S 20 nmThe Fermi level of the doped source/drain tube Efi 0.6 eVThe optical phonon backscattering mean-free-path inmetallic CNTs
λop 15 nm
The acoustic phonon backscattering mean-free-path inmetallic CNTs
λap 500 nm
CNT work function ϕs 4.5 eVThe chirality vector of tubes (m, n) (19, 0)The number of tubes in the device N 3
(typical)
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
VT ¼ KT ln112eEgþαevD
2kT
�eαevDkT þ 24 � e
αevD2kT
�(3a)
� � ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiq �
�VT � aVπffiffiffi
3p
eDCNT
(3b)
In Ref. [37], with the aim of CNTFET quantum simulation usingnon-equilibrium Green's function, the effects of changing the chiralityvector and oxide thickness on the variations of V-I characteristics areinvestigated. On the other hand, the use of a reliable and computationallycompact model for circuit design with considering the intrinsic CNTFETproperties, parasitic capacitors and the effects of source to drain directtunneling in a small gate length is important for the perspective ofsimulation and experimental results [25,36]. Therefore, in this paper, theCNTFET model proposed in Refs. [30,31] is used for circuit simulations.Additionally, analytical current and voltage equations for the ballisticCNTFET devices based on some modifications on the equations discussedin Refs. [43,44] are presented as follows:
Fig. 3. (gm=ID) comparison between CNTFET and CMOS technologies.
Fig. 4. a) Inverter circuit. b) Invert
344
Rq ¼ h4e2
� 6:45 KΩ (4)
Where Rq is the quantum resistance of the CNTFET. Equation (5)expresses the value of ON-current for a CNT transistor in saturation re-gion; ϕs is the analytical surface potential, which shifts the bands. For asmall gate voltage, ϕs is close or equal to VG.
Ion � kTeRq
ln�1þ e
2eϕs�Eg2kT
�(5)
The transconductance and channel conductance of the CNTFET areobtained as follows:
gm ¼�
1
1þ e2eφs�2αevDS�Eg
2kT
� 1
1þ e2eφs�Eg
2kT
�1Rq
∂φs
∂VGS(6)
gds ¼ αRq
�1þ e
�2eφsþ2αevDSþEg2kT
��1(7)
It is worth mentioning that to increase the transconductance of eachtransistor, the channel width should be increased; nevertheless, this alsoincreases the parasitic capacitances and power consumption.
Fig. 3 shows the parameter gm=ID versus the normalized drain current
(In ¼ ID=�
WL
�) for both CNTFET and MOSFET transistors. As it is obvious
in this figure, for identical specifications of aspect ratios of the transistorsand the same bias conditions for both the CNTFET and its MOSFETcounterpart, the CNTFET transistor generates a higher transconductance(gm) value for a specific drain current in comparison with its MOSFETcounterpart. This shows the superiority of the CNTFET technology overCMOS technology in analog integrated circuit designs [45].
3. The proposed Gm-C filter structure
As it is mentioned before, the proposed Gm-C filter is designed basedon the use of inverter circuit as an OTA block. Although inverters areusually used in digital circuits, but OTA blocks are used in various analogcontinuous-time applications such as low noise amplifiers, oscillators andfilters, as it is discussed in Refs. [6,24,46,47]. In Ref. [46], a CMOSinverter is used as a voltage controlled OTA stage, according to themethod of the Nauta and Seevinck [7]. In Ref. [6], the dual CMOS pairstructure is used as an OTA block. In Ref. [8], an ultra-low-power CMOSOTA is used for low frequency Gm-C applications.
Giving the above facts, the inverter circuit shown in Fig. 4 is used as atransconductance block. The relationship between the input voltage andthe output current is as follows:
iout ¼ gmvin ¼�gmn þ gmp
vin (8)
Where gm is the total transconductance of the N-type and P-typetransistors.
In Fig. 5, the frequency responses of both CNTFET and CMOS in-verters in 32 nm technology are presented using the same supply voltage
er as a transconductance stage.
Fig. 5. Frequency response comparison of CNTFET and MOSFET inverters.
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
value (�0.2 V) and load capacitances. As it is obvious, the MOSFETinverter shows a gain amplitude of 10.92 dB at a gain-bandwidth (GBW)frequency of 6.7MHz, while the CNTFET inverter shows a gain of38.63 dB and a GBW frequency of 10.6MHz for three nanotubes (N¼ 3)with the chirality vector (19, 0). In fact, in analog integrated circuitdesign, a better gain-bandwidth performance can be concluded for theCNTFET technology compared to CMOS technology.
Table 2 compares the performances of the simulated OTAs in bothCNT and CMOS technologies. As it is obvious in Table 2, the simulatedOTAs in this paper use the lowest supply voltage value (�0.2 V), whilethey present the best power-bandwidth trade-off at the same capacitiveload value (0.1 pF). The CNTFET OTA has the maximum unity-gain fre-quency and slew-rate values at the similar power consumption in com-parison with its CMOS counterpart. Furthermore, the CNTFET OTA
Table 2Performance comparison of the proposed CNTFET and CMOS inverter-basedOTAs.
Performances of OTAinverter
First simulatedCMOS OTA
Second simulatedCMOS OTA
Proposed CNFETOTA
Technology 32 nm 32 nm 32 nm (m,n)¼(19,0), N¼ 3
Power Supply 0.2 V� 0.2 V� 0.2 V�Open loop gain (A0) 10.92 dB 10.92 dB 38.63 dBUnit gain freq. (fT) 6.7MHz 10.6MHz 10.6MHzPower Consumption(pd)
40.3 nW 64.3 nW 40.3 nW
Transconductance(gm)
4.99 μA/V 7.97 μA/V 6.73 μA/V
Phase Margin 73.6� 73.8� 89.3�
THD 0.4% 0.4% 0.19%PSRR 13.92 dB 13.92 dB 49.74 dBSlew Rate 14.6 V/μs 14.7 V/μs 87 V/μsActive OTA Area 26048 nm2 41216 nm2 2655 nm2
FOM ¼ A0 :fTVDD:pd
1460 KHz/(V.nW)
1452 KHz/(V.nW)
56161 KHz/(V.nW)
Fig. 6. Proposed universal current-mode (core circuit)
345
consumes the lowest power compared to CMOS OTA at the same unitygain frequency. This makes the CNTFET OTA the best candidate for high-frequency and low-power analog integrated circuits design. The CNTFETOTA has an open-loop gain of 24.3 times higher than the gain value of itsCMOS counterpart while consumes 37.4% less power at the same unity-gain frequency. Moreover, at the same power consumption value, theunity-frequency bandwidth of the CNTFET OTA is extended by 58.2,while a considerable increase in the slew-rate is obtained for a consid-erable reduction (i.e., 90%) of the chip size. It is worth mentioning thatdue to the existence of gain-speed trade-off in deep submicron technol-ogies including 32 nm CMOS technology, the intrinsic gain factor (gmro)degrades substantially [41]. Furthermore, due to a higher gm=ID in theCNT technology, higher gm and gain values are obtained for a CNTFETOTA at the same normalized drain current. As it is discussed in Refs. [16,35,38], due to the ballistic transport of carriers in CNT technology, theeffective mobility of a CNT transistor is higher than its CMOS counter-part; this leads to a considerable increase in the unity-gain bandwidthand speed (slew-rate) of the CNTFET OTA.
With regard to the above facts, as it is shown in Fig. 6, a new current-mode universal Gm-C filter is proposed based on the method discussed inRef. [48]. This filter uses only 8 inverters (16 transistors) as OTA blocks.In order to extend the ability of the proposed Gm-C current-mode filter tooperate in all modes of operation, three inverter blocks should be addedto the main current-mode core of the circuit, as shown with cross-lines inthe left-hand side of Fig. 6. Accordingly, the proposed current-modeGm-C filter circuit can be evolved to a multi-mode filter. From Fig. 6,Iin1, Iin2 and Iin3 are the input currents, and vin1, vin2 and vin3 are thecorresponding input voltages; Iout and Vout represent the output currentand voltage signals, respectively. Additionally, the proposed circuit usestwo grounded capacitors to reduce the noise and eliminate the parasiticeffects of active elements.
Assuming Iin1¼ Iin2¼ Iin3¼ 0, by applying Kirchhoff's current law(KCL) equations to the nodes v1 to v3, the following equations areobtained:
gm1vin1 þ gm2v3 þ SC1v1 ¼ 0 (9)
gm1v1 þ gm1v2 ¼ 0 (10)
�gm1v2 � gm1vin2 ¼ SC2v3 þ gm2v3 (11)
gm2v3 þ gm1vin3 þ gm1vout ¼ 0 (12)
The transfer function of the proposed filter is obtained as follows:
(vout ¼ N1ðSÞ � vin3DðSÞ
DðSÞDðSÞ ¼ S2C1C2 þ Sgm2C1 þ gm1gm2
N1ðSÞ ¼ Svin2gm2C1 þ vin1gm1gm2(13)
and multi-mode (extended) Gm-C filter structure.
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
On the other hand, for current-mode filter, assumingvin1¼ vin2¼ vin3¼ 0, the current-mode transfer function of the proposedfilter is obtained as follows:
Iout ¼ N2ðSÞ � Iin3DðSÞDðSÞ N2ðSÞ ¼ SIin2gm2C1 þ Iin1gm1gm2 (14)
According to the above equations, the responses of the filter in allmodes of operation are summarized as follows:
Current-mode and transresistance modeIf vin1¼ vin2¼ vin3¼ 0, the filter responses are as follows:
AÞ LPF: Iin1 ¼ Iin; Iin2 ¼ Iin3 ¼ 0 ⇒IoutðLPÞ
Iin¼ gm1gm2
DðSÞ (15)
BÞ BPF: Iin2 ¼ Iin; Iin1 ¼ Iin3 ¼ 0 ⇒IoutðBPÞ
Iin¼ Sgm2C1
DðSÞ (16)
CÞ HPF: Iin1 ¼ Iin2 ¼ Iin3 ¼ Iin ⇒IoutðHPÞ
Iin¼ �S2C1C2
DðSÞ (17)
DÞ BSF: Iin2 ¼ Iin3 ¼ Iin; Iin1 ¼ 0 ⇒IoutðBSÞ
Iin¼ �gm1gm2 þ S2C1C2
DðSÞ (18)
EÞ APF: ðIin2 ¼ 2Iin; Iin3 ¼ IinÞ Or ðIin2 ¼ 0; Iin3 ¼ IinÞ; Iin1 ¼ 0
⇒IoutðAPÞ
Iin¼ �1 or � gm1gm2 � Sgm2C1 þ S2C1C2
DðSÞ(19)
Voltage-mode and transconductance modeIf Iin1¼ Iin2¼ Iin3¼ 0, the filter responses are as follows:
AÞ LPF: vin1 ¼ vin; vin2 ¼ vin3 ¼ 0 ⇒voutðLPÞ
vin¼ gm1gm2
DðSÞ (20)
Fig. 7. Design algorithm for the proposed
346
BÞ BPF: vin2 ¼ vin; vin1 ¼ vin3 ¼ 0 ⇒voutðBPÞ
vin¼ Sgm2C1
DðSÞ (21)
CÞ HPF: vin1 ¼ vin2 ¼ vin3 ¼ vin ⇒voutðHPÞ
vin¼ �S2C1C2
DðSÞ (22)
DÞ BSF: vin2 ¼ vin3 ¼ vin; vin1 ¼ 0 ⇒voutðBSÞ
vin¼ �gm1gm2 þ S2C1C2
DðSÞ (23)
EÞ APF: vin2 ¼ 2vin; vin3 ¼ vin; vin1 ¼ 0
⇒voutðAPÞ
vin¼ �1 or � gm1gm2 � Sgm2C1 þ S2C1C2
DðSÞ(24)
Sensitivity analysisConsidering the denominator of the transfer function for the proposed
circuit, the center frequency (ω0) and quality factor (Q) of the proposedGm-C filter are obtained as expressed in Eqs. (25) and (26):
ω0 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffigm1gm2C1C2
r(25)
Q ¼ffiffiffiffiffiffiffiffiffiffiffiffigm1C2
gm2C1
s(26)
Sensitivity of the parameters ω0 and Q parameters to the values ofpassive and active elements (i.e., C and gm) are presented in Eq. (27) asfollows:
8>><>>:
Sω0C1
¼ Sω0C2
¼ �12
Sω0gm1
¼ Sω0gm2
¼ 12
SQgm1 ¼ �SQgm2 ¼12
SQC1¼ �SQC2
¼ �12
(27)
It is worth mentioning that the sensitivity of all filtering functions to
filter circuit in CNTFET technology.
Fig. 8. Frequency response of the proposed universal current-mode filter.
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
the values of gmi and Ci are obtained as expressed in Eqs. (28)–(31); thisimplies another advantage of the proposed circuit that the summation ofsensitivities of the proposed circuit to the values of active and passiveelements is zero.
SLPFgm1¼ �SLPFC1
¼ C1C2S2 þ gm2C1sDðSÞ (28)
SLPFgm2¼ �SLPFC2
¼ SBPFgm2¼ �SBPFC2
¼ C1C2S2
DðSÞ (29)
SHPFgm1¼ �SHPFC1
¼ SBPFgm1¼ �SBPFC1
¼ �gm1gm2DðSÞ (30)
SHPFgm2¼ �SHPFC2
¼ �ðgm1 þ C1SÞgm2DðSÞ (31)
4. Simulation results
The proposed universal filter circuit is designed based on the designalgorithm shown in Fig. 7 in which both structural and physical speci-fications of the CNTFETs are considered as inputs to the design algo-rithm. These specifications are as follows: structural specifications suchas chirality vector (m, n), number of tubes (N), the values of supplyvoltage (VDD), passive capacitances (C1, C2) and physical specificationssuch as temperature (T), lattice constant (α), quantum resistance of theCNTFET (Rq) and CNT work function ( φS). Then, based on the structuraland physical specifications of the nanotube technology, the main designparameters as well as the bias voltages and currents are calculated.
In the next step, based on the calculated design parameters and biasconditions, the main performance measures of the proposed universalfilter, such as center frequency, power consumption, etc. can be calcu-lated. Therefore, if the computed performances meet the pre-definedrequirements, the design procedure is terminated. Nevertheless, ifsome performance measures do not meet the design requirements, thedesign variables (structural specifications) are modified and the designalgorithm is run using the updated design variables. Finally, this designprocess continues until all of the performance measures are met.
In Table 3, the simulation results of the proposed Gm-C circuit aresummarized (assuming C1¼ C2¼ 1 pF), where the performances of theproposed circuit in both MOSFET and CNTFET technologies arecompared.
As it is obvious from Table 3, the proposed circuit in CNTFET tech-nology shows 54% extension in the center frequency, while the activechip area is considerably reduced (99%) in comparison with its 32 nmCMOS counterpart, for the same values of power consumption and supplyvoltage. For the same value of the center frequency, the CNTFET filtercircuit consumes only 66% of power consumed by the CMOS filter, andthe active chip area is reduced by 92.7% in comparison with CMOStechnology. By properly selecting the chirality vector and the number ofnanotubes, power consumption may decrease further. In addition, the
Table 3Performance comparison of the proposed Gm-C filters in 32 nm MOSFET and CNTFE
TECH. Aspect ratio or N, (m,n)
VDD, VSS(V)
Dissipated Power(Pd) nW
Central FKHz
CMOS 32 nm 400 nm=45 nm 0.2� 678.8 1100CMOS 32 nm 2606 nm=45 nm 0.2� 447.5 712.85CNTFET32 nm
N¼ 3, (m, n)¼(19, 0) 0.2� 447.5 1100
CNTFET32 nm
N¼ 11, (m, n)¼(15,0)
0.2� 86.6 217
CNTFET32 nm
N¼ 5, (m, n)¼(15, 0) 0.2� 39.3 100
CNTFET32 nm
N¼ 3, (m, n)¼(13, 0) 0.2� 2.61 6.46
347
proposed CNTFET filter circuit shows a superiority in terms of FOMperformance parameter over other designs, and it is observed that thebest performance is obtained for N¼ 3 and the chirality vector (19, 0).
Figs. 8–11 show the simulation results of the frequency response forthe proposed CNTFET inverter-based universal Gm-C filters in all modesof operation for 1.1MHz center frequency at�0.2 V supply voltage, usingN¼ 3 nanotubes with the chirality vector (19, 0).
There is a good compliance between the theoretical results in MAT-LAB and HSPICE circuit simulations. As it is expressed in Eqs. (32)–(35),considering the assumed gm values for N and P CNTFET transistors, thecenter frequency of the circuit is mathematically calculated 1.1MHz inMATLAB and 1.07MHz in HSPICE; this shows a close agreement thatconfirms the good design accuracy of the proposed circuit.
Theoretical : gm:inverter ¼ gm:nch þ gm:pch ¼ 3450nAV
þ 3450nAV
¼ 6900μAV(32)
f0 ¼ 12π
ffiffiffiffiffiffiffiffiffiffiffiffiffiffigm1gm2c1c2
r¼ 1098 kHz � 1:1 MHz (33)
T technologies.
req. (f0) Quality Factor(Q)
Min Area of Transistorsμm2
FOM¼ (f0.Q)/(Pd.Area)KHz/nW.μm2
0.73 0.396 2.9870.71 2.58 0.440.97 0.0289 82.5
0.96 0.141 17.06
0.95 0.0571 42.25
0.96 0.0289 82.21
Fig. 9. Frequency response of the proposed voltage-mode universal filter.
Fig. 11. Frequency response of the proposed transresistance-mode univer-sal filter.
Fig. 13. Sensitivity of the center frequency of the band-pass filter to the valuesof external capacitances.
Fig. 10. Frequency response of the proposed transconductance-mode univer-sal filter.
Table 4Center frequency variations due to changing the filter's capacitances consideringparasitic effects.
C1¼ C2 1 pF 0.1 pF 10 fF 1 fF 0.1 fF 10 aFCenterfrequency
1.1MHz 11MHz 110MHz 1 GHz 6.8 GHz 14.8 GHz
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
Circuit simulations : gm:inverter ¼ gm:nch þ gm:pch ¼ 6730μAV
(34)
f0 ¼ 12π
ffiffiffiffiffiffiffiffiffiffiffiffiffiffigm1gm2c1c2
r¼ 1071 kHz � 1:07 MHz (35)
4.1. Filter tunability
As it is shown in Fig. 12, by changing the supply voltage from 0.16 Vto 0.24 V, the center frequency of the band-pass filter can be varied in therange of 300 kHz to 3.3MHz. According to Eq. (25), by increasing thesupply voltage, the transconductance of the inverters and the centerfrequency of the filter increase; nevertheless, considering Eq. (26), thequality factor remains constant.
Fig. 12. Variations of the band-pass filter's center frequency versus differentsupply voltage values.
348
In order to investigate the sensitivity of the filter's performances to thevalues of capacitors C1 and C2, simulation results of sensitivity analysisare shown in Fig. 13, in which the capacitances are varied in the range of�10% of their typical values of 1 pF. As it is obvious in Fig. 13, the centerfrequency varies in the range of �10% of its typical value of 1.1MHz.
Due to the fact that the parasitic capacitances, which are imposed bythe circuit layout, have some impacts on the circuit performance, theperformance degradation induced by the parasitic capacitances isinvestigated, and the results are summarized in Table 4, and the overallbehavior is illustrated in Fig. 14. From Table 4, the effects of parasiticcapacitances are more visible for the filter's capacitance values of lessthan 1 fF. In Eq. (25), the center frequency increases if the values of thefilter's capacitances decrease; but as it is clear in Fig. 14, for filter ca-pacitances of less than 1 fF, the center frequency does not increase line-arly due to the appearance of parasitic capacitances that are comparablewith filter's capacitances. This issue justifies the performance degrada-tion for the proposed filter due to the capacitive parasitic effects. In orderto avoid such parasitic effects in the design of the proposed filter, thevalues of C1 and C2 are chosen to be 1 pF that is far from the values ofparasitic capacitances approximated in this design, i.e., 50-70 aF.
Fig. 14. Center frequency performance degradation due to the filter's parasiticcapacitances.
Fig. 17. Monte-Carlo simulation results for the effect of �2.5% thresholdvoltage variations on the center frequency of the proposed band-pass filter.
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
4.2. Temperature and Monte-Carlo analysis
As it is discussed in Ref. [49], the effects of self-heating andnon-self-heating of carbon nanotubes on the current-voltage character-istics, delay and cut-off frequency of CNTFET transistors are investigatedby solving a one-dimensional equation of thermal conductivity usingfinite difference method. It is shown that the performance qualitydegradation for CNTFETs is much less than MOSFETs, which justifies thegood electro-thermal properties of CNTFET technology [43,49,50]. As itis discussed in Ref. [50], the thermal conductivity of a SWCNT transistorshows a linear temperature dependency (see Fig. 15). The effect oftemperature variations in the range of (�10 �C to þ40 �C) on the fre-quency response of the proposed filter is simulated. The results of tem-perature analysis presented in Fig. 16 verify that increasing thetemperature leads to a quasi-linear increase in center frequency andpower consumption for the proposed filter.
For investigating the effects of non-idealities of non-uniform growthof carbon nanotubes in the fabrication process and inaccurate litho-graphic effects (i.e., dimensions of CNTFET transistors and effectivemobility of carriers) on the performances of CNTFETs, the Monte-Carloanalysis is performed. Therefore, the effects of threshold voltage varia-tions in the range of �2.5% of its nominal value are analyzed in HSPICE,based on the method discussed in Refs. [51,52], which is shown inFig. 17. From Fig. 17, the center frequency varies between 961 KHz and1.19MHz for 70 different iterations around a mean value of 1.0774MHz.
Fig. 15. Frequency response variations versus different temperatures for theproposed band-pass filter.
Fig. 16. Power and center frequency variations due to the changing of oper-ating temperature.
349
Fig. 18 shows the Monte-Carlo simulation results of the frequencyresponse for the pitch variations in the range of 18–22 nm. Figs. 19 and20 show the Monte-Carlo simulation results of the transient responses forthe proposed high-pass and low-pass filters, respectively; these resultsverify the good performance and design robustness of the proposedCNTFET filter. Moreover, the Monte-Carlo simulation results of �10%pitch variations for the center frequency performance of the proposedfilter is analyzed and shown in Fig. 21.
The dependencies of the filter's performances on CNTFET structuralparameters, such as number of nanotubes, diameter of CNT and pitchparameter, are investigated and simulated in HSPICE. For example, bychanging the pitch parameter in its maximum allowable range from10 nm to 27 nm, the center frequency of the proposed filter varies
Fig. 18. Monte-Carlo simulation results of frequency response of the proposeduniversal filter for pitch variations.
Fig. 19. Monte-Carlo simulation results of transient response of the proposedhigh-pass filter for pitch variations in the range of 18-22 nm.
Fig. 20. Monte-Carlo simulation results of transient response of the proposedlow-pass filter for pitch variations in the range of 18-22 nm.
Fig. 21. Monte-Carlo simulation results for the effect of �10% pitch variationson the center frequency of the proposed band-pass filter.
Table 5Effects of changing the pitch parameter on the performances of the proposedfilter.
Pitch (nm) 10 14 17 20 24 27Center frequency (KHz) 977 1000 1040 1100 1115 1125Power Consumption(nW)
405.3 431.5 441.4 447.5 452.6 455.7
Fig. 22. Center frequency and power consumption variations due to changingof CNT's diameter.
Fig. 23. Variations of the band-pass filter's center frequency versus differentnumber of nanotubes.
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
between 977 kHz and 1.125MHz, and power consumption varies be-tween 405.3 nW and 455.7 nW, as summarized in Table 5.
Similarly, increasing the diameter of a carbon nanotube by control-ling the chirality vector shows an exponential increase in the centerfrequency and power consumption of the proposed filter, as summarizedin Table 6 and illustrated in Fig. 22.
One of the major structural CNTFET parameters, which has a signif-icant impact on the performance of the proposed filter, is the number ofnanotubes. Therefore, N varies from 3 to 15, assuming a fixed chiralityvector (m, n) ¼ (19, 0) for all CNT devices in the proposed band-passfilter. The simulation results for the variations of major filter perfor-mances, such as center frequency (ω0), power consumption and totalharmonic distortion (THD%) due to the changing of N, are illustrated inFigs. 23–25. By increasing the number of nanotubes, power consumptionand center frequency of the filter increase in a quasi-linear manner.
Fig. 25 indicates the variations of total harmonic distortion (THD%)versus the number of nanotubes. In order to achieve the minimum value
Table 6Effects of chirality vector variations on the performances of the proposed filter.
Chirality vector (10, 1) (11, 3) (13, 0)DCNT (nm) 0.839 1.012 1.0303Center frequency (KHz) 0.138 5.2 7.13Power Consumption (nW) 0.058 1.93 2.61
350
of THD, the designer may selectN� 5, which leads to the minimum valueof THD of only 1.16%.
4.3. Comparison with other designs
Finally, Table 7 summarizes the performances of the proposed fil-ter, where they are compared with other previously published designs.The proposed circuit has the lowest power consumption and supplyvoltage values in comparison with other reported designs. Moreover,the proposed filter implements a universal filter with the capability ofworking in all modes of operation, while some other designs cannotoperate in all modes or cannot generate all filtering responses in areduced chip size. The performances of the proposed universal filterare compared with other reported designs in the CNTFET technology.As it is clear in Table 7, the proposed universal filter has the lowestpower consumption and supply voltage values in comparison with [56,57], while the circuits discussed in Refs. [56,57], suffer from the lackof multi-mode operation or generating universal filtering responses[57]. On the other hand, the proposed circuit suffers from the
(11, 8) (17, 0) (19, 0) (20, 2) (30, 2)1.309 1.347 1.506 1.670 2.461214 307 1100 2690 1550086.7 124 447.5 1230 11370
Fig. 24. Center frequency and power dissipation variations versus changing thenumber of nanotubes (N).
Fig. 25. THD% variations versus increasing the number of nanotubes for theproposed band-pass filter.
Table 7Performance comparison of the proposed filter with other reported designs.
Ref Technology No of ABBs(Active BuildingBlocks)
No of C/R
SupplyVoltage
[4] 0.18 μm-CMOS
2 gm for biquad. 2C/0R –
[6] 0.35 μm-CMOS
4 OTAs 4C/0R 3.3 V
[9] 0.35 μm-CMOS
Direct design – �1.5 V
[11] 0.35 μm-CMOS
3 DVCCs 2C/3R �1.5 V
[15] 0.35 μm-CMOS
2 DCCIIs 1C/3R �1.25 V
[17] 0.13 μm-CMOS
2 ICIIsþ1MOSFET 1C/0R �0.75 V
[20] 0.18 μm-CMOS
1 FDCCII þ1 DDCC 2C/6R �0.9 V
[21] 0.35 μm-CMOS
3 DVCCs 2C/3R �1.5 V
[48] 0.35 μm-CMOS
4 OTAs 4C/0R 2.5 V
[53] 0.18 μm-CMOS
1 VDTA 3C/1R �0.9 V
[54] 0.25 μm-CMOS
2 OTAs 3C/0R �1.8 V
[55] 0.18 μm-CMOS
3 DDCCs 2C/4R �0.9 V
[56] 32 nm-CNTFET
2 ICC-II 2C/3R �0.9 V
[57] 32 nm-CNTFET
2 ICC-II 2C/2R �0.7 V
ThisWORK
32 nm-CNTFET
8/11 Inverters 2C/0R ±0.2V
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
351
relatively higher THD value in comparison with [4,48], but the circuitdiscussed in Ref. [48], is not a universal filter and implements only theband-pass frequency response, while both the circuits in Refs. [4,48]suffer from the higher power consumption in comparison with theproposed circuit. Giving the above facts, the main contribution of thiswork is the proper combination of the benefits of the new filterstructure design and the benefits of the technology migration (CMOSto CNTFET). The former improves the circuit performances and spec-ifications such as universal frequency responses, multi-mode operationand tunability of the filter, and the latter results in a betterpower-bandwidth trade-off for the proposed circuit.
5. Conclusions
In this paper, a new CNTFET-based, low-power universal Gm-C filterwas designed in current-mode using inverters as OTA blocks. The pro-posed current-mode filter has a reduced chip size and low power con-sumption, and is able to function in all modes of operation by adding onlythree inverters to the main current-mode core circuit. Actually, inclusionof these three inverters enables the proposed circuit to be used with allinput/output signal types (current/voltage) without the requirement ofany additional I/V converter circuits. The center frequency and qualityfactor of the proposed filter can be tuned electronically with a lowsensitivity to the values of active and passive components. The perfor-mance of the proposed circuit was simulated in HSPICE using 32 nmCNTFET technology parameters and compared with the performance ofthe proposed circuit in 32 nm CMOS technology. It was found that byproper selection of CNTFET design parameters, such as chirality vectorand the number of carbon nanotubes, improved total harmonic distortionas well as power-bandwidth trade-off can be achieved. Moreover, inorder to further decrease the power consumption, the sub-thresholdtechnique can be used in the design process and the performance ofthe proposed circuit can be investigated in future studies. Finally, the
Powerdiss.
Universal Multi-mode
QualityFactor
THD
309 μW ✓ ✓ – 0.74%
178 μW LP ✓ – �40 dB at 400mV
6.6mW LP-HP-BP C.M. 0.707 �1.74% (BP)
5.67 mW LP-BP-HP/BS
✓ 0.707 1.3%
1.3mW AP ✓ – –
2.75mW ✓ C.M. – �0.233%experimental
– ✓ ✓ �1 1% at 150mVapplied
3.47 mW ✓ V.M. 1 �0.932 until 13%
800 μW BP ✓ – 0.46%
540 μW LP-HP-BP ✓ 0.5,1,5 4% at 400mVapplied7% at 200 μAapplied
– LP-HP-BP ✓ – �4% for 300mV
– ✓ V.M. 1–8 3% at 400mVapplied
54 μW ✓ V.M. – –
430 μW BP V.M. 0.12 –
447 nW ✓ ✓ 0.97 ≥1.16%
S.M.A. Zanjani et al. Microelectronics Journal 90 (2019) 342–352
theoretical results showed a very good agreement with the results ob-tained from circuit simulations, which verify a good design accuracy.
References
[1] J. Koton, N. Herencsar, J.W. Horng, Differential second-order voltage-mode all-passfilter using current conveyors, Elektron. Elektrotech. 22 (5) (2016) 52–57.
[2] A. Namdari, M. Dolatshahi, A new ultra low-power, universal OTA-C filter insubthreshold region using bulk-drive technique, AEU-Int. J. Electron. Commun. 82(2017) 458–466.
[3] H. Uhrmann, R. Kolm, H. Zimmermann, Analog Filters in Nanometer CMOS,Springer Science & Business Media, 2013.
[4] M.A. Jeshvaghani, M. Dolatshahi, A low-power multi-mode and multi-output high-order CMOS universal Gm-C filter, Analog Integr. Circuits Signal Process. 79 (1)(2014) 95–104.
[5] R.F. Moreno, F.A. Barúqui, A. Petraglia, Bulk-tuned Gm–C filter using currentcancellation, Microelectron. J. 46 (8) (2015) 777–782.
[6] A. Pirmohammadi, M.H. Zarifi, A low power tunable Gm–C filter based on doubleCMOS inverters in 0.35μm, Analog Integr. Circuits Signal Process. 71 (3) (2012)473–479.
[7] B. Nauta, A CMOS transconductance-C filter technique for very high frequencies,IEEE J. Solid State Circ. 27 (2) (1992) 142–153.
[8] E.D. Cotrim, L.H. de Carvalho Ferreira, An ultra-low-power CMOS symmetrical OTAfor low-frequency Gm-C applications, Analog Integr. Circuits Signal Process. 71 (2)(2012) 275–282.
[9] S. Minaei, O.K. Sayin, H. Kuntman, A new CMOS electronically tunable currentconveyor and its application to current-mode filters, IEEE Trans. Circuits Syst. I:Reg. Pap. 53 (7) (2006) 1448–1457.
[10] C.M. Chang, S.K. Pai, Universal current-mode OTA-C biquad with the minimumcomponents, IEEE Trans. Circuits Syst. I: Fundam. Theor. Appl. 47 (8) (2000)1235–1238.
[11] S. Minaei, M.A. Ibrahim, A mixed-mode KHN-biquad using DVCC and groundedpassive elements suitable for direct cascading, Int. J. Circ. Theor. Appl. 37 (7)(2009) 793–810.
[12] L. Safari, S. Minaei, A simple low voltage, high output impedance resistor basedcurrent mirror with extremely low input and output voltage requirements, in:Telecommunications and Signal Processing (TSP), IEEE, 2016, pp. 254–256, 39thInternational Conference on.
[13] R. Arslanalp, E. Yuce, A. Tola, Two lossy integrator loop based current-modeelectronically tunable universal filter employing only grounded capacitors,Microelectron. J. 59 (2017) 1–9.
[14] L. Safari, A new low voltage low power class AB current output stage with highcurrent drive capability of 320mA, Trans. Electr. Electron. Circuits Syst. 6 (1)(2016) 1–9.
[15] E. Arslan, K. Pal, N. Herencsar, B. Metin, Design of novel CMOS DCCII with reducedparasitic and its all-pass filter applications, Elektron. Elektrotech. 22 (6) (2016)46–50.
[16] A. Imran, M. Hasan, A. Islam, S.A. Abbasi, Optimized design of a 32-nm CNFET-based low-power ultra-wideband CCII, IEEE Trans. Nanotechnol. 11 (6) (2012)1100–1109.
[17] L. Safari, E. Yuce, S. Minaei, A new ICCII based resistor-less current-mode first-orderuniversal filter with electronic tuning capability, Microelectron. J. 67 (2017)101–110.
[18] M.T. Abuelma'atti, A. Bentrcia, A novel mixed-mode OTA-C universal filter, Int. J.Electron. 92 (7) (2005) 375–383.
[19] H.P. Chen, Y.Z. Liao, W.T. Lee, Tunable mixed-mode OTA-C universal filter, AnalogIntegr. Circuits Signal Process. 58 (2) (2009) 135–141.
[20] C.N. Lee, Independently tunable mixed-mode universal biquad filter with versatileinput/output functions, AEU-Int. J. Electron. Commun. 70 (8) (2016) 1006–1019.
[21] S. Minaei, E. Yuce, All-grounded passive elements voltage-mode DVCC-baseduniversal filters, Circ. Syst. Signal Process. 29 (2) (2010) 295–309.
[22] J. Koton, N. Herencs�ar, K. Vrba, KHN-equivalent voltage-mode filters usinguniversal voltage conveyors, AEU-Int. J. Electron. Commun. 65 (2) (2011)154–160.
[23] S. Sangyaem, S. Siripongdee, W. Jaikla, F. Khateb, Five-inputs single-output voltagemode universal filter with high input and low output impedance using VDDDAs,Optik-Int. J. Light Electron Opt. 128 (2017) 14–25.
[24] M.T. Hsu, Y.H. Lin, Y. Jing-Cheng, Low power high gain CMOS LNA based oninverter cell and self-body bias for UWB receivers, Microelectron. J. 45 (11) (2014)1463–1469.
[25] K.R. Pasupathy, B. Bindu, Low power, high speed carbon nanotube fet based levelshifters for multi-vdd systems-on-chips, Microelectron. J. 46 (12) (2015)1269–1274.
[26] S.A. Ebrahimi, M.R. Reshadinezhad, A. Bohlooli, M. Shahsavari, Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits, Microelectron. J. 53(2016) 156–166.
[27] H. Samadi, A. Shahhoseini, F. Aghaei-liavali, A new method on designing andsimulating CNTFET-based ternary gates and arithmetic circuits, Microelectron. J. 63(2017) 41–48.
[28] F. Sharifi, M.H. Moaiyeri, K. Navi, N. Bagherzadeh, Robust and energy-efficientcarbon nanotube FET-based MVL gates: a novel design approach, Microelectron. J.46 (12) (2015) 1333–1342.
[29] A. Javey, J. Guo, D.B. Farmer, Q. Wang, D. Wang, R.G. Gordon, M. Lundstrom,H. Dai, Carbon nanotube field-effect transistors with integrated ohmic contacts andhigh-k gate dielectrics, Nano Lett. (3) (2004) 447–450.
352
[30] J. Deng, H.S. Wong, A compact SPICE model for carbon-nanotube field-effecttransistors including non-idealities and its application—Part I: model of theintrinsic channel region, IEEE Trans. Electron. Dev. 54 (12) (2007) 3186–3194.
[31] J. Deng, H.S. Wong, A compact SPICE model for carbon-nanotube field-effecttransistors including non-idealities and its application—Part II: full device modeland circuit performance benchmarking, IEEE Trans. Electron. Dev. 54 (12) (2007)3195–3205.
[32] G. Cho, Y.B. Kim, F. Lombardi, M. Choi, Performance evaluation of CNFET-basedlogic gates, in: Instrumentation and Measurement Technology Conference, IEEE,2009, pp. 909–912. I2MTC'09. IEEE.
[33] M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robustternary circuits for nanotechnology, IET Circuits, Devices Syst. 5 (4) (2011)285–296.
[34] M.H. Moaiyeri, A. Rahi, F. Sharifi, K. Navi, Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits,J. Appl. Res. Technol. 15 (3) (2017) 233–241.
[35] P.L. Mc Euen, M.S. Fuhrer, H. Park, Single-walled carbon nanotube electronics, IEEETrans. Nanotechnol. 99 (1) (2002) 78–85.
[36] J. Luo, L. Wei, C.S. Lee, A.D. Franklin, X. Guan, E. Pop, D.A. Antoniadis, H.S. Wong,Compact model for carbon nanotube field-effect transistors including non-idealitiesand calibrated with experimental data down to 9-nm gate length, IEEE Trans.Electron. Dev. 60 (6) (2013) 1834–1843.
[37] P.G. Sankar, K.U. Kumar, Investigating the effect of chirality on coaxial carbonnanotube field effect transistor, in: Computing, Electronics and ElectricalTechnologies (ICCEET), International Conference on, IEEE, 2012, pp. 663–671.
[38] S.M.A. Zanjani, M. Dousti, M. Dolatshahi, High-precision, resistor less gas pressuresensor and instrumentation amplifier in CNT technology, AEU-Int. J. Electron.Commun. 93 (2018) 325–336.
[39] A. Al-Shaggah, M. Khasawneh, A. Rjoub, Carbon nano tube field effect inverter:delay time & power consumption analysis, in: Electrical and ElectronicsEngineering Conference (JIEEEC), 2015 9th Jordanian International, IEEE, 2015,pp. 1–4.
[40] Y.S. Mehrabani, M. Eshghi, A symmetric, multi-threshold, high-speed and efficient-energy 1-bit full adder cell design using CNFET technology, Circ. Syst. SignalProcess. 34 (3) (2015) 739–759.
[41] M. Nizamuddin, S.A. Loan, A.R. Alamoud, S.A. Abbassi, Design, simulation andcomparative analysis of CNT based cascode operational transconductanceamplifiers, Nanotechnology 26 (39) (2015), 395201.
[42] A Quick User Guide on Stanford University Carbon Nanotube Field EffectTransistors (CNFET) HSPICE Model V. 2.2.1.
[43] D. Akinwande, J. Liang, S. Chong, Y. Nishi, H.S. Wong, Analytical ballistic theory ofcarbon nanotube transistors: experimental validation, device physics, parameterextraction, and performance projection, J. Appl. Phys. 104 (12) (2008), 124514.
[44] H.S. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H.Y. Chen, X. Chen,G. Close, J. Deng, A. Hazeghi, J. Liang, Carbon nanotube electronics-materials,devices, circuits, design, modeling, and performance projection, in: ElectronDevices Meeting (IEDM), IEEE International, 2011, p. 23-1.
[45] H.D. Dammak, S. Bensalem, S. Zouari, M. Loulou, Design of folded cascode OTA indifferent regions of operation through gm/ID methodology, Int. J. Electr. Electron.Eng. 1 (3) (2008) 178–183.
[46] H. Barth�elemy, S. Meill�ere, J. Gaubert, N. Dehaese, S. Bourdel, OTA based on CMOSinverters and application in the design of tunable band-pass filter, Analog Integr.Circuits Signal Process. 57 (3) (2008) 169–178.
[47] A. Yarahmadi, A. Jannesari, Two-path inverter-based low noise amplifier for 10–12GHz applications, Microelectron. J. 50 (2016) 76–82.
[48] B. Nauta, Analog CMOS Filters for Very High Frequencies, Springer Science &Business Media, 2012 Dec 6.
[49] C.J. Xing, W.Y. Yin, L.T. Liu, J. Huang, Investigation on self-heating effect in carbonnanotube field-effect transistors, IEEE Trans. Electron. Dev. 58 (2) (2011) 523–529.
[50] M.C. Llaguno, J. Hone, A.T. Johnson, J.E. Fischer, Thermal conductivity of singlewall carbon nanotubes: diameter and annealing dependence, AIP Conf. Proceed.591 (1) (2001) 384–387.
[51] B. Ghavami, M. Raji, Failure characterization of carbon nanotube FETs underprocess variations: technology scaling issues, IEEE Trans. Device Mater. Reliab. 16(2) (2016) 164–171.
[52] P. Lim, X. Wang, H. Dai, Y. Nishi, J. Harris, Threshold voltage and 1/f noisedegradation in carbon nanotube field effect transistors under Hot-Carrier Stress, in:Device Research Conference, IEEE, 2008, pp. 109–110.
[53] R. Pandey, N. Pandey, N. Singhal, Single VDTA based dual mode single inputmultioutput biquad filter, J. Eng. 2016 (2016), https://doi.org/10.1155/2016/1674343.
[54] P. Mongkolwai, W. Tangsrirat, Electronically controllable resistorless dual-modemultifunction filter, in: Proceedings of the International Multi-Conference ofEngineers and Computer Scientists, vol. 2, 2017.
[55] C.N. Lee, Independently tunable plus-type DDCC-based voltage-mode universalbiquad filter with MISO and SIMO types, Microelectron. J. 67 (2017) 71–81.
[56] S.K. Tripathi, M.S. Ansari, Voltage-mode universal filter for ZigBee using �0.9V32nm CNFET ICC-II, in: Confluence the Next Generation Information TechnologySummit, IEEE, 2014, pp. 471–475.
[57] S.K. Tripathi, M.S. Ansari, A.M. Joshi, Low-noise tunable band-pass filter for ISM2.4GHz bluetooth transceiver in �0.7V 32nm CNFET technology, in: Proceedings ofthe International Conference on Data Engineering and Communication Technology,Springer, Singapore, 2017, pp. 435–443.
