A Novel Self-Aligned 4-bit SONOS-Type Non-Volatile Memory Cell with T-Gate and I-Shaped FinFET Structure and Low Current Sense Amplifier

Sunyeong. Lee, Y.W. Jeon, J. Jang, J.S. Sin, H.J. Kim, H.Y. Bae, D.H. Yun, D.H. Kim, and D.M. Kim

School of Electrical Engineering, Kookmin University, Seoul 136-702, Korea

AbstractA novel 4-bit self-aligned SONOS-type non-volatile memory

(NVM) cell with a T-gate and I-shaped FinFET structure is proposed for high manufacturability and high density of storage devices. TCAD simulation result is provided for the scalability (down to LG=50 nm) and reliability prediction. We also propose a novel low current (0.01n~1 nA) sense amplifier that is immune to variations of the supply voltage VDD (0.7~1.8 V) and temperature in determining the GIDL current for data sensing.

I. Introduction

High storage density with improved performance in the retention and endurance is a key issue for continued scaling down of the cell size in flash memory storage systems. As the cell size is shrunk down, the second bit effect [1] and long term reliability are getting more important and should be fully considered in the cell design process. In this work, we propose a self-aligned four-bit flash memory cell with a T-gate and I-shaped FinFET structure (TGIF) having immunity to the second bit effect and improved reliability characteristics with low current sense amplifier.

II. Device Structure and Electrical Characteristics

The proposed 4-bit self-aligned T-shape Gate and I-shape FinFET SONOS NVM cell structure and its fabrication flow are shown in Fig.1 for practical implementation. We note that a thermally grown oxide (SiO2) is adopted as a control oxide instead of a deposited oxide and four storage nodes are formed by the self-aligned process. We also confirmed that TGIF NVM operates well even though gates are misaligned up to 20 % in the fabrication process. To achieve a high density of storage system, the cells are placed in crossing arrays. The gate2 electrode of each row is designed to share a word line with the gate1 electrodes of the next one. In the case of the bit line, the source/drain electrodes are connected to the odd/even row to reduce both the parasitic capacitance and the leakage current for improved performance.

The typical ID-VG characteristics from TCAD simulation [2] are summarized in Fig.2 Assuming a uniform distribution stored charges in both space and energy, the volume density of the stored charges is set to 2×1019 C/cm3 in the simulation. For high sensitivity, stored charges in

logic states are sensed by the gate-induced drain leakage (GIDL) current (IGIDL) method [3] for the proposed TGIF NVM. Depending on the charge states with programmed electrons in the storage node, the energy-band of the channel is bent and therefore a difference in the GIDL current can be used for sensing of the data.

For the improvement of the reliability caused by cycled program/erase process, program and erase paths are separated. A modified F-N tunneling [4] is employed for “program” through the gate-to-drain overlap region (in lateral direction) applying a moderately low voltage. In order to erase the cell, a band-to-band hot hole injection [3] is employed (in vertical direction). Simulated transient characteristics for program and erase of the selected Bit2 are shown in Fig.3. We note that the erase condition is similar to the read condition. However, the transient characteristic is significantly different from each other as comparatively shown in Fig.4.

For the second bit effect, additional simulations were performed with various widths and lengths of the TGIF cells. Fig.5 shows that the second bit effect in narrow fin width cell structure is expected to be negligible. In the case of the memory cells with a scaled short channel length, the separation of the IGIDL is even large enough for sensing at LG=50 nm as shown in Fig.6.

III. Sense Amplifier for Low Current Detection

In the proposed TGIF SONOS cell, IGIDL for data sensing from TGIF NVM is expected to be very low (0.01~1 nA) to conventional sense amplifiers (SA). The proposed ultra low current SA (0.13 µm tech., VDD=1.2 V) as shown in Fig.7, however, operates well when the supply voltage (VDD: 0.7~1.8 V) is fluctuated over the temperature T=-25~125 ℃ by utilizing the body effect. The simulation results for the temperature variation and supply voltage fluctuation are shown in Fig.8 (a) and (b), respectively.

IV. Summary and Conclusions

We proposed a new self-aligned sandwiched four-bit flash (TGIF NVM) memory cell structure to achieve high density, better scalability, and robust reliability of NVM cells. TCAD simulation result for the proposed TGIF NVM memory can be scaled down to

I - shape Fin patterning

Formed field oxide and field oxide wet etchingThermal oxidation

(Tunnel oxide)

Thermal oxidation(Control oxide)

Si3N4 spacer formation(Self-aligned storage node)

CMP(Si, SiO2, Nitride)

Poly silicon depositionT - shape gate patterning

p-Substrate

Active region

p-SubstrateField oxide

p-SubstrateField oxide

Oxide

p-SubstrateField oxide

Oxide

p-SubstrateField oxide

Oxide

Si3N4

p-SubstrateField oxide

Oxide

DSGate1

Gate2 p-SubstrateField oxide

Poly Silicon

Si active region

(b) (c)

(d)

(e)(g)

(a)

(f)

Fig.1 Fabrication process flow for TGIF NVM cell. (a) I-shaped active fin patterning (b) Field oxide formation (c) Tunnel oxide formation by thermal oxidation (d) Poly-silicon gate electrode patterning (e) Poly-silicon thermal oxidation for control oxide (f) Filling of the 4 holes between the control and tunnel oxides by Si3N4 deposition and etch-back, S/D doping (g) Separation of the front- and back-gates and Si3N4 charge-storage regions by CMP

제17회 한국반도체학술대회

LG= 50 nm without the second bit effect. The low IGIDL (0.01~1 nA) can be sensed by the proposed current sense amplifier (0.13 µm tech., VDD= 0.7~1.8 V).

Acknowledgements

This work was supported by the National Research Foundation (NRF) grant funded by the Korean government (MEST) (No. R01-2007-000-20879-0). References [1] C. C. Yeh et al., NVSM Workshop, p. 44, 2003 [2] Synopsys, Inc. Sentaurus User’s Manual , 2006 [3] A. Padilla et al., Symp. VLSI Tech. Dig. p. 142, 2008 [4] A. K. Sharma, Advanced Semiconductor Memories, Wiley

Inter-Science, p. 349, 2003 [5] A. Furnemont et al., IEEE-TED , vol. 54, p. 1351, 2007

(a)

(b) -3 -2 -1 0 1

10 -14

10 -12

10 -10

10 -8

10 -6

10 -4

10 -2

I D(S

) (A/µ

m)

V G 1 (V )

x1xx

x0xx

V D S = 1 .5V

(c) Fig.2 (a) TGIF NVM cell 3D structure, (b) 2D top view and (c) IDS-VG characteristic at VDS=1.5 V . IGIDL is determined at VG= -3 V and is higher when the electrons are captured.

10-9 10-8 10-7 10-6 10-5

0.1

1

10

10-9 10-8 10-7 10-6 10-5

Bit 1

ERS @ VG1= -4 V, VDS= 2 V PGM @ VG1=5 V, VDS= -2 V

I GID

L (n

A/µ

m)

Time (sec)

Bit 2

Time (sec) Fig.3 Optimized program ( )/erase ( )characteristics. (a) Bit2 is

selected and (b) Bit1 is unselected.

10-9 10-8 10-7 10-6 10-5 10-4

0.1

1

10 Bit 2

Time (sec)

I GID

L (n

A/µ

m)

Read condition (VG1= -3 V, VDS=1.5 V)

Erase condition (VG1= -4 V, VDS=2.0 V)

Fig.4 Simulation results of IGIDL transient characteristics. : read condition and : erase condition

25 30 35 40

10-10

10-9

10-8

LG = 100 nm VG1(2)= -3.0 V VDS = 1.5 V

I GID

L (A

/µm

)

WFin (nm)

x1x0 x0x1

Fig. 5 IGIDL versus the width of the fin body for the two states with

the smallest IGIDL separation (i.e. states ‘x1x0’ and ‘x0x1’) for comparison of the second bit effect.

-3 -2 -1 0 110-1210-1110-1010-910-810-710-610-510-410-3

I D (A

/µm

)VG1 (V)

LG = 50nmVG1 FWD sweepVDS = 1.5V

x1xx

x0xx

Fig. 6 Gate length scalability. IDS-VG characteristics of LG=50 nm

Fig. 7 Low current sense amplifier schematic. Icell =0.01~1 nA,

Iref=0.1 nA, 0.13 µm tech., VDD=1.2 V

40 42 44 46 48 500.00.20.40.60.81.01.2

T em p. (°C ) 125 85 50 25 0 -25

Vol

tage

(V)

T im e (µsec) (a)

40 42 44 46 48 50 520.00.51.01.5 V DD

1.8 1.5 1.2 0.9 0.7

Vol

tage

(V)

T ime (µsec) (b)

Fig. 8 Transient characteristics of the output voltage as a function of the variable (a) temperature (-25~125 ℃) and (b) VDD (0.7~1.8 V)

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