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A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig Tanner Research, Inc. Ashutosh Nagle

A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

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A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig Tanner Research, Inc. Ashutosh Nagle. Why this paper?. Paper on parallel GA – The Requirement Lets understand GA part without knowing too much of domain specifics - PowerPoint PPT Presentation

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Page 1: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

A Parallel Genetic Algorithm For Performance-Driven VLSI Routing

By

Jens Lienig

Tanner Research, Inc.

Ashutosh Nagle

Page 2: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Why this paper?

• Paper on parallel GA – The Requirement • Lets understand GA part without knowing too

much of domain specifics• Claims to be the first paper that considered

crosstalk – a performance parameter in VLSI

• Still a negative point – Gauges performance more by VLSI parameters than parallelism – true with most papers

Page 3: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Problem Description

• Groups of pins – called nets.

• Pins of a net to be connected together.

• No two of different nets connected together.

Page 4: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Sample Solution[1]

Page 5: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

A good solution

Is the one that minimizes

– Crosstalk

– Network delays

Page 6: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Issues and Influencing Factors

• Issues in generating a routing solution– Pins very closely located Crosstalk– Electrical delays smaller the better

• Factors– Crosstalk – depends on the total length of

parallel segments of different nets– Network delays

• Number of joints – vias• Total length of connection – netlength

Page 7: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

– Number of vias

– Netlength – square for “increased pressure” on longer nets

– Total length of parallel net segments

Problem Formulation

• A “good solution” minimizes –

– Crosstalk

– Network delays

• Use user defined weights for the three

Page 8: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Fitness Function

ω1 * lp + ω2 * vp + ω3 * pp

1F =

Lp= Netlength as sum of quadratic function of the length of each net

vp = Number of vias

Pp = Sum of lengths of parallel net segments

ω 1, ω 2, ω3 = User defined weights

[1]

Page 9: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Algorithm – Characteristics

• Population is comprised of possible routing solutions

• Topology – torus with 8 SPARC workstations• Uses stepping stone model – Migration only with

neighbors• Selection – Roulette-wheel• 1 bit crossover• Uses mutation• Migration after configurable number of

generations

Page 10: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Algorithm Details – Encoding

G (x, y, z) = j

j = 0 Point is unoccupied

j positive Point occupied by net j

j negative point is a pin of net j and so can not be moved

[2]

Page 11: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Selection

• Roulette-wheel – Stochastic sampling with replacement– Probability of an individual x getting selected

from population P is –

Prob{x gets selected} =F(x)

∑yЄP F(y)

[3]

Page 12: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Crossover

• Uses single point crossover

[1]

Page 13: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Mutation

•Random Mutation

-A rectangle of random size width × height around a random center (x, y, z) is selected and all connections in it are erased.

- The connections are reestablished randomly

Page 14: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Reduction

• Subpopulation size = 50

• Number of offspring = 20

• Fittest 50 go to the next generation

• Advantages:– Size of subpopulation maintained – “Good” individuals of previous generations

survive in subsequent ones

Page 15: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Results

Time Taken

0

500

1000

1500

2000

2500

YKBDC

J6_1

2

J6_1

3

J6_1

6

J6_1

7PS

BDS DSADS

Benchmark Problems

Tim

e in

sec

on

ds

Sequential

GAP

Outperformed

Page 16: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Results – With No Migration

VLSI Score

0

2

4

6

8

10

BDC J6_13 J6_16 J6_17 PS

Benchmark Problems

Sco

re Sequential

Parallel

Page 17: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Results – With Epoch 25Gen.VLSI Score

0

1

2

3

45

6

7

8

9

BDC J6_13 J6_16 J6_17 PS

Benchmark Problems

Sc

ore

Sequential

2 Migrants

4 Migrants

6 Migrants

Page 18: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Results – With Epoch 50Gen.

VLSI Score

0123456789

BDC J6_13 J6_16 J6_17 PS

Benchmark Problems

Sco

re

Sequential

2 Migrants

4 Migrants

6 Migrants

Page 19: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Results – With Epoch 75Gen.VLSI Score

0123456789

J6_13 J6_16 J6_17 PS

Benchmark Problems

Sco

re

Sequential

2 Migrants

4 Migrants

6 Migrants

Page 20: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Conclusion

The paper proposes an effective way of applying parallel genetic algorithm to VLSI routing problem, but does not give detailed comparison of parallel and sequential algorithms as far as time is concerned.

Page 21: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

References

• [1] J. Lienig, “A Parallel Genetic Algorithm for Performance-Driven VLSI Routing”, IEEE Transactions on Evolutionary Computation, 1997.

• [2] J . Lienig and Thulasiraman, “A Genetic Algorithm for Channel Routing in VLSI Circuits”, Evolutionary Computation, vol. 1, no. 4, 1994.

• [3] D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Reading, MA: Addison-Wesley, 1989.

Page 22: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

• Questions?

Page 23: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Random solution generation[2]

Page 24: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Abbreviations:

• GAP = Genetic Algorithm – Parallel;• YK =Yoshimura-Kuh Channel; • BDC = Burstein’s Difficult Channel; • J6_12 = Joo6_12;• J6_13 = Joo6_13; • J6_16 = Joo6_16; • J6_17 = Joo6_17; • PS = Pedagogical Switchbox;• BDS = Burstein’s Difficult Switchbox; • DS = Dense Switchbox; • ADS = Augmented Dense Switchbox.

Page 25: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Sequential Algorithms

• WEAVER

• Yosh.-Kuh

• PACKER

• SAR

• Monreale

• Silk

• BEAVER

Page 26: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing By Jens Lienig

Notes

• Best results with

• W1 = 1.0

• W2 = 2.0

• W3 = 1.0– Other w3 values – 0.01 and 4.0