A Practical Guide for Accurate Broadband On-Wafer ...mos-ak.org/sanfrancisco/papers/09_Rumiantsev_MOS-AK_SF08.pdf · A Practical Guide for Accurate Broadband On-Wafer Calibration

A Practical Guide for Accurate Broadband On-Wafer Calibration in

RF Silicon ApplicationsAndrej Rumiantsev

1st International MOS-AK Meeting, Dec.13 2008, San Francisco, CA

A Practical Guide for Accurate Broadband On-WCalibration in RF Silicon Applications, A.Rumiantsev, 1st International MOS-AK MeetingDec. 13, 2008 © All Rights Reserved

Outline

Motivation

Standard Technique vs. On-Wafer Calibration

Suitable Calibration Methods

Implementation

Practical Results

Summary


Motivation

The operation frequency of modern RF CMOS devices approaches 110GHz and beyond

Accurate device characterization at operation frequencies is a must

Limited accuracy of the standard technique beyond 40 GHz (with the pad parasitic de-embedding)


Motivation

Historical view: Microwave community: customized on-chip calibration is the standard technique Digital community (Si): off-chip calibration + de-embedding

Progress in development of customized calibration on silicon over the last years

Work from NIST (US), PTB (Germany)


Outline

Motivation



Implementation

Practical Results

Summary


Standard Technique

Line Reflect Load (Match) Reference plane at probe-tips after step 1

(off-wafer calibration)

Step 2: Reference plane after de-embeddingStep 1: calibration to the probe tip end

with commercial calibration substrateStep 2: de-embedding of DUT contact pads and interconnects

Step1:

off-wafer calibration

Standard technique: a two-step approach


Standard Technique

Why de-embedding failsBased on the impedance equivalent model of pads and interconnectsAssumes that a dummy pad represents (a part of) the parasitic impedanceSubtracts impedances

Frequency ↑ accuracy ↓


On-Wafer Calibration

One step approachExample: LRM+ calibration with wafer embedded standards

Thru Load Reflect (Short)

⇒+ +

Measurement reference plane after the on-wafer calibration


On-Wafer Calibration

Why calibration worksApplies the measurement theory: the concept of systematic measurement errorsUses (partly) known standards to define error termsDetermines DUT parameters over the error correction procedure

No frequency limitation

P1

DUT

P2 P1

DUT

P2Forward Direction Reverse Direction

Error Box Error Box Error Box Error Box


Outline

Motivation



Implementation

Practical Results

Summary



Multiline TRL:Developed at NIST in early 90s [1]Original application: semi-insulating wafers (GaAs) [2]End of 90s: application techniques for Si [3]

LRM+:First application: SiGe:C [4] Comparison vs. multiline TRL: GaAs [5], bulk Si [6]


On-Wafer TRL/ NIST Multiline TRL

AdvantagesFundamental calibrationDoes not require ideal Open or ShortMeasures line propagation constantSelf-consistent

ChallengesMany lines are required for broadband measurementsReference impedance is the line Z0

Measurement of the line Z0 on lossy substrates


On-Wafer TRL: Residual Calibration Errors

0 20 40 60 80 100 120Frequency (GHz)

Calibration Accuracy Verification

0

0.05

0.1

0.15

0.2

0.25

Upper

bound |

Sij'-

Sij|/

|Sij|

and |

Sii'

-Sii|

TRL

System Drift

0 20 40 60 80 100Frequency (GHz)

Re(

Zo),

Ohm

45

47.5

50

52.5

55CPW Line Impedance (ISS)

Alumina CPW TRL (4 Lines) with respect to the 50 Ohm calibration [7]

Methods to characterize the line accuracy improvement(NIST approaches), e.g. [3]


On-Wafer LRM+

AdvantagesNot sensitive to Load asymmetry Arbitrary impedance elements can be used as LoadsDoes not require known Open or ShortSelf-consistent

ChallengesRequires known Loads and Thru


Outline

Motivation



Implementation

Practical Results

Summary


Characterization of Customized Standards

Measurement• Lines (multilineTRL)• Lumped standards• “Chicken and egg…”

Model• EM-simulation• Network• Fabrication tolerances?

Mixed• Meas.-based model

(e.g. LRM+)

Mixed approach addresses fabrication tolerances


Implementation Challenges

High loss of silicon substrate:Difficulties in implementing TRL calibration

Many metal layers:Difficulties in 3D EM simulation of on-wafer standards

High fabrication tolerances:Inaccurate lumped (open, short and load) and distributed (thru and line) standards

High price of wafer space


Design of Standards

GSG pad set

Ground and signal pads are at the high-level metal

Lines: high-level metal

Load, short, and open are at the bottom of the via stacks, at the plane “D”

Special methods to improve electrical properties of the line

DUT Plane

“D”Plane


Characterization of Standards: Simulation

EM simulation technique:Not practical for the complete structures

Simplified representation: A line with a solid, reference conductor, and a single dielectric (addressing physical dimensions)

Simulated model of the load standard


Characterization of Standards: Measurements

Measurement technique:γ of the line from the NIST Multiline TRLZ0 of the line: from the load method

Load impedance: From the reference NIST multiline TRLFrom the ‘Mixed Technique’

Z modeledR* measuredZ* reconstructed [4]


Outline

Motivation



Implementation

Practical Results

Summary


Characterization of Standards

Line parameters, extracted from multiline TRL [6]

0 20 40 60 80 100 120FREQUENCY (GHz)

40

42

44

46

48

50

Rea

l(Zo)

(Ohm

)

-4

-3

-2

-1

0

1

Im(Z

o)

(Ohm

)

Real(Zo) (L)

Imag(Zo) (R)

0 20 40 60 80 100 120FREQUENCY (GHz)

0

2

4

6

8

Loss

(dB/c

m)

1

1.5

2

2.5

3

Rel

ativ

e Ph

ase

Const

ant

Loss (L)

Phase Constant (R)

Propagation constant Characteristic Impedance



Thru: measurement vs. simplified simulation [6]

0 20 40 60 80 100 120FREQUENCY (GHz)

-0.05

0

0.05

Mag

nitude

(dB)

-7.5

-5

-2.5

0

2.5

Phas

e (D

egre

e)

DB(|S[2,1]|) (L)Measured

DB(|S[2,1]|) (L)Simulated

Ang(S[2,1]) (R)Measured

Ang(S[2,1]) (R)Simulated



Load standard: fabrication tolerances within one test chip (mixed model vs. measurement) [6]

Mixed model agrees with measurement results

Mag

nitude

(dB)

0 20 40 60 80 100 120FREQUENCY (GHz)

-60

-50

-40

-30

-20

-10

0DB(|S[2,2]|)Load

DB(|S[2,2]|)Open-Resistor

DB(|S[2,2]|)Short-Resistor

DB(|S[2,2]|)Load Model

Return Loss of the Load


Calibration Accuracy Comparison: NIST Method

Calibration comparison technique for:Contact repeatability (on Si)Instrument drift* LRM+ accuracy

Reference calibration:NIST Multiline TRL

* Experimental time: 8 hours


Calibration Accuracy Comparison: NIST Method

0 20 40 60 80 100 120FREQUENCY (GHz)

0

0.05

0.1

0.15

0.2

0.25

0.3U

pper

bound for

|Sij'-

Sij|/

|Sij|

and |

Sii'

-Sii|

Sum of Contact and Instrument Drifts

Instrument Drift

LRMplus

LRM+ is in agreement with the reference multiline TRL

LRM+ vs. Multiline TRL [6]


Calibration Accuracy Comparison: DUT

Verification for FET: advanced 0.13 μm RF-CMOS NFET, [6]

20 40 60 80 100 12020

25

30

35

40

45

50

55

60

65

70Cgs

(fF)

FREQUENCY (GHz)

NIST Multiline TRL

Off-wafer SOLT+ De-embedding

SUSS LRM+


Calibration Accuracy Comparison: DUT

Verification for FET : advanced 0.13 μm RF-CMOS NFET, [6]

20 40 60 80 100 12010

12

14

16

18

20Cgd (

fF)

FREQUENCY (GHz)

NIST Multiline TRL

Off-wafer SOLT+ De-embedding

SUSS LRM+


Outline

Motivation



Implementation

Practical Results

Summary


Summary

Improved design of standards and a consistent reference plane increased on-wafer calibration accuracy

Simplified 3D EM simulation of standards demonstrated good results

Wafer-embedded NIST Multiline TRL and LRM+ significantly improve measurement accuracy at mm-wave frequencies


Conclusion

LRM+ and NIST Multiline (with 3 lines) are comparable for measurement accuracyLRM+ is more practical for implementation:

Requires fewer standards: 3 vs. 5 Saves test chip size by a factor of ~14xTwice as fast: 10 sweeps vs. 20 sweeps

LRM+ does not require motorized positioners (or operator):

Cheaper and faster


Acknowledgement

Susan L. Sweeney and Phillip L. Corsonfrom IBM Microelectronics

for their tremendous contribution


References

[1] R. B. Marks, "A multiline method of network analyzer calibration," Microwave Theory and Techniques, IEEE Transactions on, vol. 39, pp. 1205-1215, 1991.

[2] D. Williams, R. Marks, K. Phillips, and T. Miers, "Progress toward MMIC on-wafer standards," in ARFTG Microwave Measurements Conference-Fall, 36th, 1990, pp. 73-83.

[3] D. F. Williams, U. Arz, and H. Grabinski, "Accurate Characteristic Impedance Measurement on Silicon," in ARFTG Conference Digest-Spring, 51st, 1998, pp. 155-158.

[4] R. F. Scholz, F. Korndorfer, B. Senapati, and A. Rumiantsev, "Advanced technique for broadband on-wafer RF device characterization," in ARFTG Microwave Measurements Conference-Spring, 63rd, 2004, pp. 83-90.

[5] R. Doerner and A. Rumiantsev, "Verification of the wafer-level LRM+ calibration technique for GaAs applications up to 110 GHz," in ARFTG Microwave Measurements Conference-Spring, 65th, 2005, pp. 15-19.

[6] A. Rumiantsev, S. L. Sweeney, and P. L. Corson, "Comparison of on-wafer multiline TRL and LRM+ calibrations for RF CMOS applications," ARFTG Microwave Measurements Conference-Fall, 72nd, pp. 132-135, 2008.

[7] A. Rumiantsev, "A review of VNA calibration methods," in European Microwave Conference, 38th. Workshop WMO-3, Determining and Dealing with Errors in Microwave Measurements, 2008.

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A Practical Guide for Accurate Broadband On-Wafer ...mos-ak.org/sanfrancisco/papers/09_Rumiantsev_MOS-AK_SF08.pdf · A Practical Guide for Accurate Broadband On-Wafer Calibration