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Applied Mathematical Sciences, Vol. 7, 2013, no. 55, 2719 - 2734 HIKARI Ltd, www.m-hikari.com
A Pseudo Random Number Generator Based on
the Chaotic System of Chua’s Circuit,
and its Real Time FPGA Implementation
Lahcene Merah
1, Adda Ali-Pacha
2, Naima Hadj Said
3
and Mustafa Mamat4
1, 2
Department of Electronics 3Department of Computer Sciences
University of Science and Technology of Oran (USTO)
BP 1505 El M’Naouer Oran 31036, Algeria 4Department of Mathematics, Universiti Malaysia Terengganu
21300 K.Terengganu, Malaysia
Corresponding authors e-mails: [email protected], [email protected]
Copyright © 2013 Lahcene Merah et al. This is an open access article distributed under the
Creative Commons Attribution License, which permits unrestricted use, distribution, and
reproduction in any medium, provided the original work is properly cited.
Abstract
Due to its attractive proprieties for data encryption; chaotic systems becomes an
active research area in this last dedicate. Applying chaos proprieties in
cryptography has taken many ways and approaches, using chaotic systems as
pseudo random number generators is the most known technic. In this paper we
present a fitting way to generate a strong pseudo random number sequence (PRNS)
that satisfy the cryptography requirements from the chaotic system of Chua’s
circuit. The PRNS randomness then evaluated using the NIST-800-22 statistical
tests, and used to encrypt an image. A hardware implementation of the chaotic
system was done using a FPGA.
Keywords: Chaos, cryptography, PRNG, Chua’s circuit, FPGA, NIST
2720 Lahcene Merah et al
1. Introduction
Today, the massive revolution of media exchange and the increase of
computing speed make information security one of the major problems that worry
researchers of cryptographic field. Many Actual cryptographic algorithms that
considered as effective suffer now from the rise of the computing power of
computers and the advent of quantum computers could spell the end of these
algorithms.
Naturally, as an inseparable part of the secure systems, random number
generators (RNGs) have more prominently positioned into the focal point of
research [9]. Random numbers are extensively used in many cryptographic
operations: for key generation in both asymmetric and symmetric algorithms, as
challenges in authentication protocols, padding bytes, blinding values and in many
counter measures against side-channel attacks [8]. Since RNGs are implemented
on finite-state machines we call them pseudo random generators (PRNGs).
PRNGs are capable to generating sequences of numbers which appear
random-like from many aspects [17]. PRNGs, suitable for use in cryptographic
applications may need to meet stronger requirements than for other applications
[18], a perfect randomly generated key leads to the highest system security [19].
The randomness requirements in cryptographic applications are not very rigorous,
since PRNGs possess periodicity and can be mathematically predictable [12].
Since the discovery of chaos synchronization there has been an increasing
interest in using chaotic signals to implement a level of security for
communication systems [4].Chaos is not a complete disorder, it is a disorder in a
deterministic dynamic system which is always foreseeable in a short-term [2].
Chaotic signals are derived from nonlinear dynamic systems, they are aperiodic,
uncorrelated, broadband and deterministic and appear random in the time domain
[1]; furthermore, cryptographic researchers prefer chaotic systems properties, such
as aperiodicity, sensitivity to initial conditions and system parameters [16] which
any small perturbation can grow exponentially in the system and can result in a
non-predictive chaotic behavior [7].
With the increasing demand for various services such as encrypted digital TV,
credit cards, etc., it became necessary to manufacture encryption systems (RNGs,
algorithms) on chips. The main drawback of chaos-based RNG integrated circuits
(ICs) is the system robustness [12].
FPGA technology is a growing area of research that has the potential to
provide the performance benefits of ASICs and the flexibility of processors [21],
FPGAs are a reconfigurable hardware, and there are potential advantages of
reconfigurable hardware in cryptographic applications: algorithm agility,
algorithm upload, architecture efficiency, resource efficiency, algorithm
modification, throughput, and cost efficiency [23].
Pseudo random number generator 2721
2. Random number generators
Random number generators (RNGs) are essential in statistical studies in several
fields. They may be based on physical noise sources or on mathematical
algorithms, but in both cases truly random numbers are not obtained because of
data acquisition systems in the first case or because machine precision in the
second case. Instead, any real implementation actually produces a pseudorandom
number generator (PRNG) [10]. The need for random and pseudorandom numbers
arises in many cryptographic applications. For example, common cryptosystems
employ keys that must be generated in a random fashion [18].
In many cryptographic schemes the compromise of the random number
generator leads to the collapse of the overall security. As the security of the
overall system rests on these secrets, it is natural to set high standards for random
number generators that produce them [22].
3. Chaos based cryptography
A chaotic system is a non-linear, dynamic system. A dynamic system is simply
a set of functions (rules, equations) that specify how variables change overtime. A
system is considered non-linear if one or more functions specifying the change in
variables are non-linear [20]. There are two kinds of chaotic systems; continuous
chaotic systems (CCS) and discrete chaotic systems (DCS); the first kind can be
represented by multi-dimensional differential equations systems and the second
one by iterative maps. Since the CCS loses its dynamical proprieties when it is
implemented on finite precision machines, the DCS have more interest by
researchers.
Since 1990s, many researchers have found that there exists some interesting
relationship between chaos and cryptography [4]. The possibility for
self-synchronization of chaotic oscillations has sparked an avalanche of works on
the application of chaos in cryptography. The random behavior and sensitivity to
initial conditions and parameter settings allows chaotic systems to fulfill the
classic Shannon requirements of confusion and diffusion [5].
The chaos-based secure communication has become an important and
significant research direction. Now various methods for chaos-based secure
transmission of private information signals have been proposed, some popular
methods are additive masking, chaotic switching, chaotic parameter modulation,
chaos shift keying and chaotic frequency modulation [14].
4. The Chaotic system of Chua’s circuit
Chua's circuit is a simple electronic circuit that exhibits a wide variety of
nonlinear dynamical phenomena such as bifurcations and chaos. Because of its
2722 Lahcene Merah et al
simplicity and universality, Chua's circuit has attracted much interest and has
become a standard primer on investigations of chaos [11]. It was introduced in
1983 by Leon O. Chua, who was a visitor at Waseda University in Japan at that
time.
Chua’s circuit is an autonomous third order nonlinear electronic circuit. To
obtain a chaotic behavior from a simple autonomous circuit that constructed from
standard components (resistors, capacitors, inductors)
4.1 Chaotic criteria
An autonomous circuit made from standard components (resistors, capacitors,
inductors) must satisfy three criteria before it can display chaotic behavior. It must
contain one or more nonlinear elements, one or more locally active resistors and
three or more energy-storage elements.
Chua's circuit is the simplest electronic circuit meeting these criteria. As shown
in the figure 1, the energy storage elements are two capacitors (labeled C1 and C2)
and an inductor (labeled L1). There is an active resistor (labeled R). There is a
nonlinear resistor made of two linear resistors and two diodes. At the far right is a
negative impedance converter made from three linear resistors and an operational
amplifier. The section to the right simulates Chua's diode, a component that is
currently not sold commercially [25].
Figure.1: A version of Chua's circuit without Chua's Diode.
4.2 Modeling Chua’s circuit
The Chua’s circuit can be modeled mathematically by a system of three
dimensions of nonlinear ordinary differential equations as follow:
(1)
Pseudo random number generator 2723
With
The variables x(t), y(t) and z(t)presents respectively the voltages across the
capacitors C1and C2 and the intensity of the current the inductor L1.The function
f(x) describes the electrical response of the nonlinear resistor and parameters α and
βare determined by the particular values of the circuit components.
It should be noted that the study of the behavior of Chua’s system is out of
scope of this paper, but the internet is rich with studies and documents about
Chua’s system, just put Chua’s circuit on Google browser and you get a lot of
pages and document about it.
5. Implementation of the Chua’s system
In this section we will implement the Chua’s system through two steps, in the
first step we simulate the system using Xilinx System Generator tool (XSG) and
Matlab/Simulink. After the evaluation of the system and using it for encrypting an
image we pass to the second step that consists of the hardware FPGA
implementation of Chua’s system.
5.1 Simulation of the Chua’s system
The Chua’s system was simulated using Xilinx System Generator (XSG). XSG
is a DSP design tool from Xilinx that enables the use of the Math Works
model-based Simulink design environment for FPGA design. Previous experience
with Xilinx FPGAs or RTL design methodologies are not required when using
System Generator. Designs are captured in the DSP friendly Simulink modeling
environment using a Xilinx specific block set. All of the downstream FPGA
implementation steps including synthesis and place and route are automatically
performed to generate an FPGA programming file [24], except, the user can
configure the appropriate timing of his design and specify the pins of the inputs
and outputs of the design on the target FPGA chip.
The following figure presents the design of Chua’s equations system of (1)
using XSG, each integrator x, y and z contain a register/adder multiplied by dt
(the system step). The blocks surrounded by framework presents the f(x) function.
2724 Lahcene Merah et al
The system parameters are fixed as follow:α =15.6, β =-36, m0= -9/7 and m1
=-4/7 . The initial conditions are chosen randomly as follow: x0=0.9654454, y0
=1.0029554 and z0=1.4597855. With these parameters the system has a chaotic
behavior and unpredictability in long term with a high sensitivity to the initial
parameters.
The different time evolutions of the XSG Chua’s system are presented on the
following figure:
Figure.3: Different XSG Chua’s system outputs
-3-2
-10
12
3
-1.5
-1
-0.5
0
0.5
1
1.5
-8
-6
-4
-2
0
2
4
6
8
-6 -4 -2 0 2 4 6-1.5
-1
-0.5
0
0.5
1
1.5
Y(t)
X(t
)
-1.5 -1 -0.5 0 0.5 1 1.5-15
-10
-5
0
5
10
15
-6 -4 -2 0 2 4 6-15
-10
-5
0
5
10
15
Z(t)
X(t
)
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000-6
-4
-2
0
2
4
6
Time
X(t
)
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000-1.5
-1
-0.5
0
0.5
1
1.5
Time
Y(t
)
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000-15
-10
-5
0
5
10
15
Time
Z(t
)
Figure.2: Chua’s system design using XSG.
Pseudo random number generator 2725
6. Chua’s system based PRNG
In fact, the desired quality of randomness may and do differ from one
application domain to another, pseudo random number generators (PRNGs)
intended for cryptographic applications must be strong and presents some
statistical characteristics, PRNGs in this case are called Cryptographically secure
PRNGs.
The most common method for testing random number generators is based on
the statistical analysis of their output. Statistical test suites play a very important
role in assessing the randomness quality of sequences produced by random
number generators. And while these sequences constitute an essential input for
applications requiring unpredictability, irreproducibility, uniform distribution or
other specific properties of random number sequences [13].
The most known statistical test suite is the NIST 800-22 (National Institute of
Standards and Technology). It contains 15 tests applicable to the output of the
PRNG, each test computes what known α (the level of significance), if α> 0.01
then the test is considered passed. For more information of the NIST test suite
please refer to [18]. If all the 15 tests are passed for a sequence, we can say that
this sequence is cryptographically secured.
6.1 Application of the NIST statistical tests to the Chua’s system outputs
The following table presents the NIST statistical tests application results to
each binary sequences of signal x(t), y(t) and z(t) of the Chua’s system (the taken
length of sequences was 2 million for each one):
Test Signal x(t) Signal y(t) Signal z(t)
p_value Status p_value Status p_value Status
Frequency 0.0000 Fail 0.0000 Fail 0.0000 Fail
Block Frequency (m = 256) 0.0000 Fail 0.0000 Fail 0.0000 Fail
Cusum-Forward 0.0000 Fail 0.0078 Fail 0.0004 Fail
Cusum-Reverse 0.0000 Fail 0.0018 Fail 0.0000 Fail
Runs 0.0000 Fail 0.0000 Fail 0.0000 Fail
Long Runs of Ones 0.0000 Fail 0.0000 Fail 0.0000 Fail
Rank 0.0000 Fail 0.0000 Fail 0.0000 Fail
Spectral DFT 0.0000 Fail 0.0000 Fail 0.0000 Fail
NonOverlapping Templates (m = 9, B = 000000001) 0.0001 Fail 0.1845 Pass 0.0247 Pass
Overlapping Templates (m = 9) 0.0000 Fail 0.0000 Fail 0.0000 Fail
Universal 0.0000 Fail 0.0000 Fail 0.0000 Fail
Linear Complexity (M = 500) 0.0000 Fail 0.7243 Pass 0.3287 Pass
Approximate Entropy (m = 10) 0.0000 Fail 0.0000 Fail 0.0000 Fail
Serial (m = 16, ∇ ) 0.0000 Fail 0.0000 Fail 0.0000 Fail
Random Excursions (x = +1) 0.0000 Fail 0.0000 Fail 0.0000 Fail
Random Excursions Variant (x = -1) 0.0000 Fail 0.5441 Pass 0.0000 Fail
Table.1: NIST statistical tests application results to the outputs of the Chua’s system
2726 Lahcene Merah et al
It is clear from the table that any sequence (x, y or z ) of the Chua’s system is
not qualified as cryptographically secured pseudo random sequence. This is may
be due to the fact that the integer part of these sequences is not ideally distributed,
and presents certain regularity as presented on the following figure:
Figure.4:Binary sequences of each signal x(t), y(t) and z(t).
6.2 The proposed idea for generating CSPRNG from the Chua’s system
The idea is very simple, instead of using the entire sequence; we take only the
fraction part of each signal, then assemble the three fraction parts to construct one
sequence as shown in
the following figure:
Figure.5: The proposed idea to generate CSPRNS from the Chua’s system
The Chua’s chaotic system
Signal x (32 bits) Signal y (32 bits)
22 LSBs of x 21 LSBs of y
Signal z (32 bits)
21 LSBs of z
Pseudo random sequence of 64 bits of length
Pseudo random number generator 2727
With this scheme, we can generate a sequence of 64 bits of size and can be
considered as CSPRNS because it can satisfy all the NIST statistical tests as
shown in the following table:
Table.2: NIST statistical tests application results of the proposed scheme.
7. Simulation and analyses
This section is attendedd for evaluating the performance of the proposed
scheme, in which we encrypt and decypt two diffents images, the same previous
parameters of the Chua’s system are used for encryption. As mentionned
previously, Chua’s system with the proposed scheme delivers one data of 64 bits
of size in each cycle; this means that 8 pixels can be encrypted in each cycle.
The encrypted image of figure.6 (b) is completely differentfrom the original
image and cannot be recognized. This can justify the effectiveness of the proposed
scheme for image encryption.
The image in figure.6 (c) is the decrypted version of the encrypted image; it is
clear that decrypted image is the same as the original image (figure.6 (a)).
7.1 Histogram analyses
To prevent the leakage of information to an opponent, it is also advantageous if
the cipher-image bears little or no statistical similarity to the plain-image. An
image histogram illustrates how pixels in an image are distributed by graphing the
number of pixels at each color intensity level [3].
Although the pixel permutation will make the content of image unrecognized,
the attacker will get some information by the histogram analysis to rebuild the
image. Therefore, doing only the pixel permutation is not enough. Therefore, the
pixel substitution is adapted to change the image histogram [6].
Statistical Test Status P_value
Frequency Pass 0.15036
Block Frequency (m = 256) Pass 0.57441
Cusum-Forward Pass 0.21229
Cusum-Reverse Pass 0.14769
Runs Pass 0.49962
Long Runs of Ones Pass 0.14303
Rank Pass 0.52539
Spectral DFT Pass 0.18775
NonOverlapping Templates (m = 9, B = 000000001) Pass 0.19331
Overlapping Templates (m = 9) Pass 0.46844
Universal Pass 0.36058
Approximate Entropy (m = 10) Pass 0.24749
Random Excursions (x = +1) Pass 0.55378
Random Excursions Variant (x = -1) Pass 0.45061
Linear Complexity (M = 500) Pass 0.45124
Serial (m = 16, ∇ ) Pass 0.36665
2728 Lahcene Merah et al
By looking to the histogram of the encrypted image (fig.6 (b)), it is clear that is
uniform and different completely to the original image histogram. This means that
there is no statistical similitude of the encrypted image and the original one.
Figure.6Simulation results of the proposed scheme: (a) the original image and its histogram;
(b) the encrypted image and its histogram; (c) the decrypted image and its histogram
7.2 Sensitivity to the initial parameters
In this section, the evaluation of the sensitivity of the proposed scheme to the
initial parameters is achieved in this section. The precision used for implementing
the Chua’s system was 32 bits (fixed precision); 1 bit for the sign, 6 bits for the
integer part and 25 bits for the fraction part.
The system key is constructed by all the control parameters and the initial
conditions; 25 bits mean that the system will be sensitive to a small variation of
2.98*10-8
on its key.
The following figure presents the encryption process of an image and its
decryption with different initial conditions and control parameters:
0
500
1000
1500
0 50 100 150 200 250
0
50
100
150
200
250
0 50 100 150 200 250
0
500
1000
1500
0 50 100 150 200 250
(a) (b) (c)
Pseudo random number generator 2729
000
Figure.7 Decryption of the image with different changes on the initial parameters and the histogram on
each image,
a) the original image, b) the encrypted image, c) decrypted image by changing of the value x0
by
2.98*10-8
, d) decrypted image by changing of the value y0 by 2.98*10-8
, e) decrypted image by changing
of the value z0 by 2.98*10-8
, , f) decrypted image by changing of the value m0 by 2.98*10-8
,
g) decrypted image by changing of the value α by 2.98*10-8
, h) decrypted image the same
parameters
used for encryption
8. FPGA hardware implementation
In this section, the FPGA hardware implementation of the proposed scheme is
achieved. One of recent families of FPGAs technology was used; it’s the
SPARTAN 6 XC6SLX45 chip from XILINX, embedded on ATLYS complete
circuit board from DIGILENT INC (fig.8).
0
50
100
150
200
250
300
0 50 100 150 200 250
0
100
200
300
400
500
600
0 50 100 150 200 250
0
50
100
150
200
250
300
0 50 100 150 200 250
0
50
100
150
200
250
300
0 50 100 150 200 250
0
50
100
150
200
250
300
0 50 100 150 200 250
0
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100
150
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300
0 50 100 150 200 250
0
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150
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300
0 50 100 150 200 250
0
100
200
300
400
500
600
0 50 100 150 200 250
(a) (b)(c) (d)
(e) (f)(g) (h)
2730 Lahcene Merah et al
Spartan-6 LX FPGAs are optimized for applications that require the absolute
lowest cost. Now with up to 42% less power consumption and a 12% increase in
performance [26].
The hardware implementation VHDL code was generated automatically from
the XSG blocks, then after certain steps using the ISE tool a bitstream file also
generated and targeted to the FPGA chip.
The Figure.9 presents the design and timing summary of the design FPGA
implementation, it is clear that the design has a low cost hardware implementation.
The XC6SLX45 chip with its low cost is still has enough space to implement
more additional designs if necessary; like communication protocols to make
connection with the outside [15].
In order to visualize the analog real time outputs of the Chua’s system FPGA
circuit; we use a DAC (digital to analog converter), in this case we used the
Pmod-DA1 chip that designed by DIGILENT INC and has 2 analog outputs.
The Pmod-DA1 chip contains two DAC121S101 12-bit D/A converter chips from
National Semiconductor INC (fig.8).
The maximum estimated frequency (fig.9) is f =30.02 MHz, since the Chua’s
system FPGA circuit gives 32 bits of data key per clock cycle, it is easy to
compute the throughput:
Throughput = output word length × f
= 64 bits × 30.02 MHz = 1921.28 Mbps = 1.9Gbps
This is a high throughput and may be covers the most actual cryptography
applications requirements.
Figure.8 the ATLYS complete circuit board (include the SPARTAN 6 XC6SLX45 FPGA chip)
used for implementation.
Pseudo random number generator 2731
Figure.9the design and timing summaries of the Chua’s system FPGA implementation.
(a) (b)
(c) (d) (e)
Figure.10 the different real time FPGA outputs of the Chua’s system; a) the real time x-z plane output,
b) the real time x-y plane output, c) the real time x signal output, d) the real time y signal output
and e) the real time z signal output.
The real time outputs of the FPGA; shows that all the signals obtained are
identical to those obtained by simulation of the Chua’s system.
9. Performance of the proposed scheme based on Chua’s system
Our proposed scheme offers the following advantages:
2732 Lahcene Merah et al
The length of the secret key: the system has 7 initial value, each value is
presented by 32 bits, so the length of the initial parameters is 2(32x7)
= 2224
,
this is a big size which can certainly resist the brute force attacks.
The pseudo random sequence (PRS) is constructed by the fractional part of
the 3 signals x, y and z, so the Known Plaintext attacks has no effect
because of the complexity of the PRS.
The binary output of the system is ideally distributed and passed all the
NIST statistical tests which confirm its effectiveness for cryptographic
purposes.
The high throughput of the hardware FPGA circuit can covers any actual
cryptographic requirements.
10. Conclusion
We proposed in this paper an appropriate way to generate a cryptographically
secured pseudo random sequence from a chaotic system. With this new scheme
the Chua’s system shows better chaotic performance by inheriting the high
sensitivity to the initial conditions and expanding the range of parameters. In
addition, the generated sequence passes all the NIST statistical tests which
confirm its effectiveness for cryptographic issues.
The FPGA implementation results show that the design has a low cost
implementation and a cheap FPGA circuit (Spartan6 LX45familly in our case) is
sufficient to implement our design. In addition the hardware implementation
offers a throughput of 1.9 Gbps which is sufficient for the most actual
cryptographic requirements.
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Received: March 12, 2013