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Lecture 19Real Semiconductor Switches and the Evolution

of Power MOSFETS

A.. Real Switches: I(D) through the switchand V(D) across the switch

1. Two quadrant switch implementationand device choice examplea. Current Bi-directional and onequadrant stand-off voltage switch case

B. MOSFET Evolution1. Lateral MOSFET of Low Power VLSI

Utility and Power MOSFET Curves2. MOSFET Capacitance’s3. Vertical MOSFET For Achieving Both

High Current and High Stand-offVoltages

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A.. Real Switches: I(D) through the switchand V(D) across the switchWe calculate from the circuit topology and switchpositions the voltage across the switch, V(D), andthe current through the switch, I(D), so that therequired quadrants of switch operation are known. Then we look at various switch combinations tochoose the best switch for the required needs at allduty cycles, D.

1. Two quadrant real switchesFrom our I(D) and V(D) analysis of the specific PWM converterthere will be some switches that are required handle + i but onlyone voltage. There are also switches that must handle + V butonly one current. We can construct the required switch fromseveral established switches or we can use a new switch that hasall the properties of the combination of older switches. Forexample, we will see that a bipolar transistor and a diode canreplace a MOSFET and so on. The decision of what switchimplementation to use is a tradeoff. We must consider:

• System power versus required operating frequencyas shown on the next page•Both the power device choice and the associated powerdevice driver requirements as shown on page 3• The available switches and power ratings available at thetime of design as shown on page 4• The devices you have available to you at the cost limits setby the product profitability

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Note the curious hyperbolic power versus frequency relationshipin application requirements for power electronic switches. Wemust also realize that at high power levels the switch driverequired may be 1-10 % of the power switched. At the MW levelthe switch driver is itself a high power device.

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We look below at the time evolution of some possible powerdevices that we could employ as switches and their power ratingsfor the case of IGBT, MOSFET and THYRISTORS. These curvesare a function of time and also operating frequency, but they are acrude guide to the choices we will have to make. Each powerdevice will require a specific drive circuit specially designed forthat switch and no other. Thus as part of our decision on theswitch choice we must also consider the associated drive circuits.

We will use circuit analysis to determine therequired quadrants of operation for a given switchand the absolute values of the voltages across, V(D),and currents through, I(D), the switch as a functionof duty cycle, D. Then the artistic choice of theprecise switch and what it is made of, in terms ofcombinations of other switches, begins.

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(a) Current bi-directional switch with only onestandoff voltage

Consider first, a two device bi-directional switch made solely ofbipolar transistors and diodes.

a)

C

1

0

i

+

-v v

ion

off

b)

on

(transistor conducts)

(diode conducts)

Current-bi-directional two-quadrantSPST switch: (a) implementationusing a transistor and antiparalleldiode. (b) idealized switchcharacteristics.

Note parallel diode around abipolar transistor insures withv negative i flows to achievea two quadrant currentswitch.

In lecture 22 we will look at bipolar diode and transistorcharacteristics in more detail when we cover thyristors but for nowwe just remind you of the of the I-V curves as shown below.

A K

iD

vD+ -

(a)

Vrated

I

VF(I)

Reverseblockingregion

vD vD

iD iD

(b)

(c)

I=I0(eV/VT-1)

Avalancherated diode

On the following page we place the bipolar transistorcharacteristics as well for your perusal and consideration.

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For moredetails –see lecture 22. Here in lecture 19 we will short changeBJT technology because MOS technology has replaced it sosuccessfully. Consider that we are able to replace this twocomponent, all bipolar, switch implementation with a single powerMOSFET device. The single MOSFET device, we will see, hasthe operating characteristics shown below, thereby replacing twobipolar devices.

v

ion

off

b)

on(reverseconduction)

+

-

v

i

B. MOSFET Evolution1. Lateral MOSFET of Low Power VLSIUtility

Consider the figure below for a low power VLSI type MOSFET andthe inversion layer current channel under the lateral gate. Thisalso shows, if the source is shorted to the body, the internalreverse p-n diode of a MOSFET. It also shows a big limitation. Toscale to higher current we need a wider gate width and a smallerchannel length. The latter is incompatible with high V DS voltage. That is gm ~ W/L, but small L means the MOSFET will not

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withstand high blocking voltages. Moreover, large W means wetake up a large amount of chip area and cannot get as large a cellpacking density of paralleled MOSFET’S. What to do???

Power MOSFET cross-section in p-type substrate body.

Parallel to the MOS channel there is a parasitic NPN bipolartransistor, with no circuit connection to the p-base. However,parasitic capacitive currents cause by high dv/dt in the off state. That is i = Cdv/dt, can create base current. To avoid thisunintended parasitic bipolar action possibility the four terminalpower n-channel MOSFET (gate, drain, source and body) has thebody shorted to source to create a three terminal device. For p-channel MOSFETs the n-type body is connected to the p-typesource. This short creates a p-n pair from source (via body) todrain called the reverse body diode. This diode allows for bi-directional current to flow with performance similar to theMOSFET.Unique to MOSFET’s is both the low Ron and the speed ofswitching because no bipolar storage time is present:10 < ∆tsw< 100 nsec. Switching speeds can be fast compared toTsw. Switching speed depends only on the gate current. MOSFET’s are voltage controlled devices.N-channel CMOS transconducts + i. This is explained as followson page 8 below.

8

v

ion

off

b)

on(reverseconduction)

+

-

v

i

v

ion

off

b)

on

(reverseconduction)

+

-

v

i

n-channel current flow is normalfrom source to drain. Sourceterminal is negative, drain isground. Blocks +V conducts +i downwards

MOSFET can operatebackwards. n-channel currentflow is opposite from drain tosource if drain terminal isnegative and source is ground. FET blocks -V conducts +i upwards

The static model for a VLSI MOSFET involves the following fourvalues.

DS

G

Rds(on)

Rleak

Static model for MOSFET. The leakageresistance Rleak is usually m .Ω

In comparison, a typical power MOSFET characteristic curve isshown schematically below on page 9 and an actual I-V curve onpage 10. The Iout - Vin characteristic for Vin > VT(threshold) is givenby the transconductance gm whose value for power MOSFET’s istypically,1-10 Siemans.

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As seen, VGS > VT (1-3V) the device turns on and I-V is linear upuntil saturation. For power MOSFET devices Ron reaches aminimum for VGS > 10V as compared to logic MOSFET’s.

For switching control or driver circuits, conventional analogop-amps provide sufficient gate drive for the low to intermediatepower switches. Special driver stages can supplement the op-amp. Fifty ohm Zout for an op-amp gives RC of 100ns for the gateturn-on as shown on the following page.

10

+

-

S

D

G

200 pF

50

Vq

Vq

+12 V, on

0 V, off

Voltage follower Op-amp driving the gate of apower MOSFET

Ω

The specifications of a typical low power MOSFET in forwardmode are given below and on the next page in reverse mode. Data sheets for IDS versus VDS with VGS as a parameter are showndirectly below. From analysis of these curves we can extract theDC MOSFET parameters for the model of page 8.

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For HW#4Estimate all values for the static model of the MOSFET shown onpage 8 from the above data sheets.

2. MOSFET Capacitances

Shown below are the various device capacitance’s for a MOSFET

S

D

G

Cgd

Cds

Cgs

Capacitance elements associated withMOSFET.

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Note that for a charged gate the capacitance isnearly twice the value for an uncharged gate. Thisfact is very crucial to proper design of MOSFET gate drive circuits.That is, the turn-on delay for a given gate drive circuit has severalregions in a plot of VGS and VDS versus total required gate chargeas shown on the following page. We arbitrarily divide the totalcharge on the gate into three parts that we represent with thevariable, Q , each is associated with a specific turn-on time. Thislevel of detail is way beyond the intentions of this introductorycourse. Nevertheless, the issues are real and you should at leastrealize that power device turn-on has a variety of meanings asdiscussed on page 13 below. One way to discuss this is viachanges in VGS and VDS versus the gate charge.

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Q1 is the gate charge to achieve a turn-on delay for a given gatedrive current. Note the charge Q1 for turn-on is smaller than Q2required for turn-off as described below

Q2 is the gate charge to achieve a turn-on time delay if weconsider the full Miller capacitance and associated charge. Thegate capacitance is twice as large, if the MOSFET is turned onrather than turned off. Hence, twice as much charge, Q2, isneeded to turn-on when this effect is included as for turn-on whenwe do not take this into consideration. Roughly, speaking Q2 =2 xQ1

Q3 is the value gate charge for turn-on and turn-off time includingload effects. It is only that part of the Miller charge essential tothe SWITCH LOSS calculations. Q3 lies in-between the low Q1

and high Q2 values.Qtotal which equals (Q1+ Q2 + a little more charge) is the totalcharge to drive the MOSFET, not only on, but into the I-V regionwhere the source-drain resistance is lowest.We will revisit this later For MOSFET’S we find the crude rule

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VDS

Co: )Vds(CDS . Incidentally for MOS devices, CDS is big when it

should be and small when you don’t need it. We will revisit this inlecture 21 where we will see that CDS is an ideal snubber capacitorfor inductive switching!In summary, power MOSFET gate capacitance is typically 2000 -8000 pF. These capacitances must be included in any realisticcircuit model using the device.

3. Vertical MOSFET For High Current andHigh Stand-off Voltagesa. Low RON advantages and a circuitexample

The old lateral MOSFET for low power VLSI doesn’t scale well aswe go to higher power levels. Neither the current throughnor the voltage across a lateral MOSFET can hold acandle to the vertical MOSFET structure we willcover below. Moreover, vertical structures allow for moreparallel devices per area and hence lower on-resistance. Nevertheless, some features will remain the same.

C

i

+

-

v

0

1(a)(b)

The power MOSFET inherentlycontains a built-in body diode: (a)equivalent circuit. (b) addition oftwo external diodes to prevent

V positive the reverse bodydiode will NOT conduct butTR may or may notdepending on controlvoltage. Bipolar conductsonly 1 way naturally.

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conduction of body diode.

One result of the above discussion is that one may use a reverseconnected FET to replace a diode in a PWM dc-dc converterprovided we actively turn on and off the MOSFET when desired. In that case reverse current conduction is allowed and the CCMmay prevail for all circuit conditions.

Vg

iAvA+ -

vB

iB+

-

Implementation of the SPSTswitches using a transistor anddiode.

Vg

iAvA+ -

vB

iB+

-

Buck converter implemented usinga synchronous rectifier by replacingthe diode with a MOSFET.

In computer chip power supplies, this done for 1.5/3.0 V convertersupplies because otherwise the diode loss is too big. That is weneed a low RON device and the MOSFET is the ticket.

b. Evolution of the Vertical StructureMOSFET1. Overview of Issues

To get to the condition that the FET resistance causes much lowerDC loss than, say a diode, we need to satisfy the relation below.To achieve this, we shall see that vertical rather than lateralMOSFET structures can be sufficiently paralleled in a givenpractical device area to reduce RON. In pages 15 –19 we will alsooutline the evolution of the vertical MOSFET from lateral DMOS tothe present highest density UMOS that utilizes vertical trenches toachieve the lowest possible RON yet still improve the stand-offvoltage that the device can handle.

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Don’t ever forget a successful power MOSFET requires both highcurrent through the device, low RON and a large voltage across it.

Below we first show that we could get a successful powerMOSFET from just a big scaled up lateral MOSFET withenormous gate width to achieve high current drive at stand-offvoltages up to 100 Volts but not beyond that. A big lateraltransistor might drive big currents but it would never stand-off thelarge (>100 Volts) voltages that are also required to be blockedacross the source-drain region of a practical power switch. Wealso give below a quick insight as to why we can indeed parallelMOSFETS as compared to bipolar transistors, which we cannoteasily parallel. Without this knowledge it would be foolhardy toeven invest the energy in trying.

rms2

ON rms2

D rmsI R (FET) < I R (ON) + I Vo

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The above two factoids, will act as motivation and guide for thenext five pages of text that culminate in the method and structuresto achieve millions of paralleled MOSFETS by employing verticalrather than lateral MOSFET designs. On the next page we tellwhy the old but big lateral MOSFET is inadequate for the task butthe vertical MOSFET, in contrast, is ideal.

2. Vertical MOSFET StructureShown below is the revolutionary vertical MOSFET structure. Toachieve a large distance between the source and drain and yetutilize minimum area on a silicon wafer we place the drain on thebottom of the wafer and the source on the top. In between weemploy low resistivity material which can more easily withstand therequired stand-off voltages, as there is lots of room for largedepletion regions from back biased junctions. The figure belowdepicts the off-state with no current flow from source to drain.The difficulty in DMOS is that the current flow is not confined inany way so that if we wish to place nearby other MOSFET’S, toachieve an array of parallel devices,we will have overlappingcurrent flows. This current flow overlap situation spoils anyattempt to achieve independent MOSFET action for paralleldevices.

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Notice that in the vertical MOSFET as compared to the lateralMOSFET the current flows vertically from source to drain andvice versa depending on whether or not it is a p or n typeMOSFET. What is shown above is the role of the deep trench andassociated vertical inversion channel to cause the current flow tobe spatially confined. The source and gate regions of the verticalMOSFET, on the top of the wafer, can still be patterned usingconventional lithography to very small dimensions allowing manyMOSFET’S per unit area of silicon. But vertical current flowthrough the bulk silicon, if it is not well spatially confined, limits thecloseness of neighboring MOSFET’S that we wish to parallel.

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This unacceptable situation was solved by employing aburied trench that had both a conducting gate inside the trenchand thin gate oxide sidewalls capable of creating a verticalinversion layer in the silicon next to the trench. The trench of “U”shape would be dug deep into the silicon so that vertical currentflow in the two inversion channels would initially be guided alongthe sidewalls in a confined manner from the top downwards. Theterm UMOS is given to this structure which is shown on page 18.

At the top of the vertical MOSFET the source and gateregions would still be defined by lateral lithography so ultra-smalldevice sizes could be manufactured next to each other to achievevery high device densities per unit area. Here the vertical currentflow easily spreads out laterally because there is no currentconfining structure. Moreover, the resistivity of the lightly dopedJFET region causes unacceptably high RON. Compare the current flow with a vertical trench structure shownabove. The vertical trench with associated inversion layersprovides four beneficial effects.

• Lower RON than the bulk silicon in the epi layer• Much more confinement of the lateral current spread aswell as improved uniformity of current density• A higher packing density via tighter cell pitch of paralleleddevices. The benefit of high-density is greatest at lower drainvoltages• Vertical current flow prevents snapback breakdown inMOSFET as well as in IGBT’s of lecture 20

To better visualize the vertical current path and associatedspatially resolved contributions to total resistance we show thecomponents of a single MOSFET resistance below on page 20.

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Clearly, with the trench, of variable depth and width, it is noweasier to optimize both the stand-off voltage and the on resistanceof a power MOSFET. Moreover, we are now able to pack millionsof cells into a given area. If each cell carries one milliamp, with amillion cells, we are able by paralleling to achieve KA levels ofswitch current. This situation is summarized on two graphs onpage 21.Hence, UMOS reaches the theoretical limit of onresistance as shown below and on page 21.

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On the next page we look at the device cross-section for thevertical MOSFET and realize that there are more devices therethan we designed for. In particular, we note the parasitic verticalBJT. This device is usually just a non-involved one in most formsof switch action. But, for positive dV DS /dt conditions experiencedduring MOSFET turn-off, we note we we cause a parasitic BJT toturn-on inadvertently. CGDx dVDS/ dt drives the BJT intoconduction. This situation is shown on the next page in moredetail. The vertical parasitic BJT is outlined and the parasiticcurrent path as well. The full MOS device model is also shownwith the BJT. THIS IS A CAUTIONARY WARNING on the properuse of MOSFET’s and is easily avoided by snubber circuits placedaround the MOSFET to avoid too large dV/dt conditions describedin lecture 21.

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Again, the way around this situation is to employ a snubber circuitto limit the dV/dt values placed across the MOSFET. The devicecapacitance itself will act as as first order snubber to limit dV/dt. We will cover this in detail in lecture 21