A robust SmartSilicon technology for a-Si:H heterojunction cells on

MG and UMG-Si with efficiencies in the 16 -18% range

Ashok K. Sinha, Joseph Bach, Surinder Bedi, Ki-Bum Kim**, Leiping Lai*, Bin Li*,

John Li*, Wen Ma, Scott McHugo, Frank Pham and Chenlei Wang

Sunpreme Inc, Sunnyvale, CA 94085, USA

*Sunpreme Jiaxing Ltd, Jiaxing, Zhejiang, China

**Department of Materials Science and Engineering, Seoul National University, Seoul, South Korea

Abstract – We have developed a manufacturing- and field-

worthy technology based on low cost p-type MG and n-type UMG active absorbers. By optimizing the casting process, we are able to achieve reasonable carrier mobility. The cell is then enabled with a-Si:H for the surface passivation, emitter, back surface field and back reflector. The efficiencies are close to mainstream diffused junction cells, but with a much lower thermal coefficient of efficiency and 70~75% lower energy budget. Moreover the emitter current distribution is largely independent of underlying defects in the MG-Si. Hence the cells can be scaled to larger wafer sizes with cost benefits previously seen for semiconductors and flat-panel LCD’s.

Index Terms — amorphous films, diffusion length, hetero-junction cells, metallurgical silicon, mobility, scalable cells

I. INTRODUCTION

It is widely agreed[1] that the solar photovoltaic (PV)

industry has yet to, but must deliver power plant installations

at an average selling price (ASP) in the US of $1/Watt, in

order to become competitive, without special incentives or

mandates. An approximate split of this ASP into major

components translates to an ASP of 40¢/W for PV panels,

40¢/W of EPC (Engineering, Procurement, Construction,

including Balance of System, BOS) and 20¢/W for

development costs. Notwithstanding current price reductions

of poly-silicon, cells and panels, our bottoms-up analysis

indicates that panel COGS (Cost of Good Sold) will level off

at around 50¢/W, significantly shy of what is required for a

40¢/W ASP.

At the present time, the most widely available PV cell

technology, with ~80% market share utilizes phosphorus

diffused junction on p-type multi-crystalline solar-grade (SG)

Si wafers, with efficiencies around 17% [2]. Successful Si cell

technologies on n-type single crystal Si offer higher efficiency

in 20-22% range, with a tradeoff of higher silicon material

cost and greater process complexity. The highest efficiencies

have been reported for HIT technology [3], again on n-type

mono-crystalline Si, but this technology has remained a

distant niche in the market, well behind CdTe thin-film on

glass product [4].

We have developed a grounds-up SmartSilicon® technology

aimed at a potential solution to this problem by introducing

material, device and engineering innovations at wafer, cell and

module level, respectively.

One of our major achievements has been to be able to

reliably enable an MG-Si absorbing layer with a thin-film

emitter on it, to make cells that use 75% less energy during

fabrication than traditional cells. We describe here our

production and field experience and indicate a new direction

for stepped cost reductions.

II. THE SMARTSILICON TECHNOLOGY

One of the distinguishing features of our process (Fig. 1(a)

and (b)) is that we can make production-worthy cells on both

p-type MG and n-type UMG wafers, sliced from appropriately

cast and doped ingots. The process equipment set remains the

same, but the sequence of thin film steps is changed.

Fig. 1. A schematic cross section of SmartSilicon cells: (a) p-type

MG and (b) n-type UMG Si absorbers, with Si:H thin-film emitters

on the passivated base. Fig. 1(c) shows a conventional cell with an n-

type junction diffused into the p- type solar grade Si base.

Also shown for comparison in Fig 1 (c) is a cross-section

of a conventional, mainstream cell on p-type multi-crystalline

solar grade Si absorber into which is diffused an n-type

emitter with a POCl3 source. As can be seen, the grain

boundary defects go right through the junction, hence the need

for ultra-high purity silicon to prevent leakage currents across

the junction.

(9) Ag print & fire

(8) SiN

(7) N- junction

(6) p- Base

(9,10) Ag-Al fired contact

(c) Diffused junction

Cell

In contrast our MG-Si casting process is designed not for a

hard diffused junction [5], but only for the best Hall mobility,

by optimizing the grain orientation. With commercially

available MG feedstock which contains B at around 2 ppm,

we slightly dope this material during casting to yield a

uniform p-type resistivity across 70% of the ingot; the

remainder is recycled. For UMG material, we can dope the

casting n-type with a heavily phosphorus doped Si dopant.

The surface of the absorbing layer is passivated on both

sides with a very thin-film (~100A) intrinsic a-Si:H layer. On

the front an appropriately doped film serves as an emitter (Fig.

1(a) and (b)) which is located on the absorbing layer rather

than in it as is the case with diffused junction cells.

With this arrangement, we are able to get surface passivated

lifetimes, diffusion lengths, Voc’s and Jsc’s consistent with

UMG-Si, respectively. Table 1 summarizes

some of the key parameters that have been achieved.

TABLE 1

SUMMARY OF KEY PROCESS AND DEVICE PARAMETERS

Parameter Symbol

(unit)

p-type MG

absorber

n-type UMG

absorber

Hall mobility (majority

carrier)

(cm2V

-1sec

-1) 200 590

Cast brick lifetime brick (sec) 3.5 – 4.5 TBD

Post-passivation wafer

lifetime

(sec) 30 ~ 80 90 ~ 195

Diffusion length Ln(m) 190 ~ 300 TBD

Open circuit voltage Voc (mV) 640 680

Saturation current density Jsc (mAcm-2) 34 35

Fill factor FF 74 75

PV Efficiency at

1KWm-2

irradiance

(mWcm-2) 16. 17.3

Thermal Coefficient of Eff TCE (%/oC) -0.33 -0.31

Applying the measured values, for p-type MG-Si

absorber, of mobility, e of ~600 cm2V-1sec-1 (~3x the hole

mobility) and a lifetime of 30~80 sec into (1), we find that

the diffusion length Ln 180~350 m, close to that seen from

EQE measurements.

√ √( ) (1)

Likewise, applying (2) with measured values of JL, we get a

Voc of around 660mV, again close to actual measurements.

(

) (

) . Where, (

)(

) (2)

In Fig 2, we show IV and EQE data for p-type MG-Si

absorber. We have been running this product in a

manufacturing plant for several months with a fairly tight

efficiency distribution centered around 16%, and an upward

vector due to continuous improvements being put into the

factory. The factory yield has also shown a rapid learning

curve; it is now running at ~90%.

Fig. 2. IV and EQE curves for SmartSi cells on p-type MG-Si

Fig 3 (a) p-MGSi efficiency distribution and

(b) Factory Yield for the months of Dec and Jan

Besides being able to process both p- and n-type MG

substrates with our present device structure, we found two

other remarkable benefits. First, LBIC image (Fig. 4) taken at

the Delaware University showed a very uniform light induced

current distribution, uninfluenced by various defects, grain

boundaries, and orientations in the absorbing layer.

Fig. 4 (a) LBIC photoresponse mapping on wafer with

HeNe 633nm, step size 0.1, 0.2mm, spot size 50m. (b) The

optical image showing grain boundaries in the absorbing

layer. [From Steven Hegedus, IEC, U. of Delaware]

(a) LBIC image (b) Optical image

50%

60%

70%

80%

90%

100%

De

c, 20

12

W1

30

1

W1

30

2

W1

30

3

W1

30

4

W1

30

5

Jan, 2013

(b) Factory Yield (a) Efficiency

This result coupled with our low thermal budget processing

has enabled us to seamlessly scale up the wafer size to

210mm, with no warping-induced breakage and no defect-

limited efficiency losses.

Moreover, by skipping the energy intensive polysilicon

gasification process, we achieve a significant reduction in the

carbon footprint for cell production compared to both

mainstream diffused junction cells on cast multi-crystalline Si

and even more so for traditional HIT cells on mono-crystalline

Si [Fig. 5].

Fig. 5. Energy consumption components for major process

steps in polysilicon gasification, Czochralski crystal pulling

and other high temperature process steps for (a) HIT, (b)

Diffused junction and (c) SmartSilicon cells

III. FIELD PERFORMANCE

Fig. 6. Carport in Sunnyvale, CA showing power output vs

expected for a five months period

The Sunpreme SmartSilicon cells are typically encased in

double-glass, frameless panels. This configuration provides

additional protection against humidity, when tested in

autoclaves. And lack of frames reduces installation cost by

eliminating grounding wires. These panels have passed

certification for both thin-film and multi-crystalline

performance and safety standards. Figures 6 and 7 show some

of the recent field installations and performance data.

In conclusion, we have developed a manufacturing- and

field- worthy technology based on a low cost MG and UMG

active absorbers. Without excessive and costly purification,

we are able to achieve reasonable mobility. The cell is enabled

with thin films to passivate, create the emitter, back surface

field and back reflector. The efficiencies are close to

mainstream diffused junction cells, but with a much lower

energy budget. Moreover the emitter current distribution is

largely independent of underlying defects in the absorber;

hence the cells can be scaled to larger wafer sizes on

appropriate commercial equipment, to provide clear

manufacturing cost benefits of the Moore’s law, previously

seen for semiconductor chips and flat panel LCD devices.

Fig. 7. A BIPV installation in China (left) and a flat roof top

commercial installation in India (right)

ACKNOWLEDGEMENTS

We wish to acknowledge with gratitude many people at all

stages of this development. At the concept stage, we benefited

from collaboration with Professors Neelkanth Dhere of

Florida Solar Energy Center at University of Central Florida,

Vikram Dalal of Iowa State University, Steven Hegedus of

Institute of Energy Conversion at University of Delaware. Ion Yadigaroglu of the Capricorn Investment Group provided

much valued advice and support. Dr Bruno Ceccaroli

consulted with us on the energy analysis of poly-silicon

gasification.

REFERENCES

[1] U.S. Department of Energy, “$1/W Photovoltaic Systems: White Paper to Explore A Grand Challenge for Electricity from Solar”, DOE Workshop, August 10-11, 2010.

[2] M.A. Green, K. Emery, Y. Hishikawa, W. Warta and E.D. Dunlop, “Solar cell efficiency tables, version 39”, Progress in Photovoltaics: Research and Applications, vol. 20, issue 1, pg. 12-20, January, 2012

[3] T. Kinoshita, D. Fujishima, A. Yano, A. Ogane, S. Toboda, K. Matsuyama, Y. Nakamura, N. Tokuoka, H. Kanno, H. Sakata, M. Taguchi and E. Maruyama, "The approaches for high efficiency HIT solar cell with thin (<100um) silicon wafer over 23%", in 26th European Photovoltaic Solar Energy Conference, 2011, p. 871-874.

[4] N. Strevel, L. Trippel and M. Gloeckler, “Performance characterization and superior energy yield of First Solar PV power plants in high-temperature conditions”, 17th Edition of Photovoltaics International, August 2012

[5] K. Peter, R. Kopecek, A. Soiland and E. Enebakk, "Future Potential for SOG-Si Feedstock from the Metallurgical Process Route", in 23rd European Photovoltaic Solar Energy Conference, 2008, p. 947-950.