A Routing Algorithm for Harvesting Multipipeline Arrays

ICCAD90, Pages 2-5 A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and

Pipeline Delays

Peter Koo, Fabrizio Lombardi Texas A&M University, Department of Computer Science, College Station Tx 77843-3112

Donatella Sciuto

Department of Industrial Automation, University of Brescia, Brescia, Italy ABSTRACT This paper analyzes a new approach for reconfiguring multipipeline arrays from two-dimensional arrays. The proposed approach is fully characterized and the conditions for switching and routing are given. A polynomial time complexity algorithm is proposed for the reconfiguration of multipipeline arrays. It is proved that 100% harvesting is possible using the proposed algorithm while achieving very small intercell and pipeline delays. REFERENCES. [1] Kung, H.T. "Why Systolic Architectures?" Computer, Vol. 15, No. 1, pp. 37-46, 1982. [2] Leighton, T. and C. E. Leiserson "Wafer Scale Integration of Systolic Arrays" IEEE Trans. on Comput., Vol. C34, No. 5, pp. 448-461, 1985. [3] Greene, W.J. and A. Gamal "Configuration of VLSI Arrays in the Presence of Defects" JACM, Vol. 41, No. 4, pp. 694-717, 1984. [4] Hasan, N. and C.L. Liu "Minimum Fault Coverage in Reconfigurable Arrays" Proc. IEEE FTCS 18, pp. 348-353, 1988. [5] Negrini, R., Sami, M.G. and R. Stefanelli "Restructuring and Reconfiguring DSP Multi-Pipeline Arrays" Proc. MSTS, Phoenix, 1987. [6] Negrini, R., Stefanelli, R. and M.G. Sami "Fault Tolerance Technique for Array Structures used in Supercomputing" IEEE Computer, Vol. 18, No. 2, pp. 78-87, 1986. [7] Stornetta, W. S., B. A. Huberman and T. Hogg "Scaling Theory for Fault Stealing Algorithms in Large Systolic Arrays" IEEE Trans. of CAD, Vol. CAD9, No. 3, pp. 290-298, 1990. [8] Sami, M.G. and R. Stefanelli "Fault Tolerance and Functional Reconfiguration in VLSI Arrays" Proc. IEEE ISCAS, pp. 643-648, 1986. [9] Lombardi, F., Negrini, R., Sami, M.G. and R. Stefanelli "Reconfiguration of VLSI Arrays: A Covering Approach" Proc. FTCS 17, pp. 251-256, 1987. [10] Gupta, R., Zorat, A. and I.V. Ramakrishna "A Fault Tolerant Multi Pipeline Architecture" Proc. FTCS 16, pp. 350-355, 1986.

ICCAD90, Pages 6-9

Topological Routing using Geometric Information

Shinichiro Haruyama, D.F. Wong, Don Fussell Department of Computer Sciences, The University of Texas at Austin, Austin, Texas 78712

Abstract We propose a new method for the two-layer topological channel routing problem. Our algorithm takes geometric information into consideration when a topological solution is obtained. Experimental results show that the algorithm generates very good solutions. For example, we have obtained a height of 41 for Deutsch's Difficult Example without any parallel overlaps of wires and simultaneously a via count of 219. References [1] Takeshi Yoshimura, Ernest S. Kuh "Efficient Algorithms for Channel Routing" IEEE Transactions on Computer-Aided Design, Vol. CAD-1, pp. 25-35, January 1982. [2] Ronald L. Rivest, Charles M. Fiduccia "A 'Greedy' Channel Router" Proceedings of 19th Design Automation Conference, pp. 418-424, 1982. [3] Michael Burstein, Richard Pelavin "Hierarchical Wire Routing" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-2, pp. 223-234, October 1983. [4] Malgorzata Marek-Sadowska "An Unconstrained Topological Via Minimization Problem for Two-Layer Routing" IEEE Transactions on Computer-Aided Design, Vol. CAD-3, No. 3, pp. 184-190, July 1984. [5] Chi-Ping Hsu. Signal Routing in Integrated Circuit Layout. UMI Research Press, 1986. [6] Shinichiro Haruyama, D. F. Wong, and Don Fussell "Topological Channel Routing" Proceedings of International Conference on Computer Aided Design, pp. 406-409, 1988. [7] David N. Deutsch "Compacted Channel Routing" Proceedings of International Conference on Computer Aided Design, pp. 223-225, 1985. [8] J. Royle, M. Palczewski, H. VerHeyen, N. Naccache, and J. Soukup "Geometrical Compaction in One Dimension for Channel Routing" Proceedings of 24th Design Automation Conference, pp. 140-145, 1987. [9] Chung-Kuan Cheng and David N. Deutsch "Improved Channel Routing by Via Minimization and Shifting" Proceedings of 25th Design Automation Conference, pp. 677-680, 1988.

ICCAD90, Pages 10-13

An Optimal Channel Pin Assignment Algorithm

Yang Cai, D. F. Wong Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712

Abstract We study in this paper the Channel Pin Assignment problem subject to both position and order constraints. We show that the problem is NP-hard in general and present a polynomial time optimal algorithm for an important case where the relative orderings of the terminals are completely fixed. We extend our algorithm to solve the problem in the case where there are also separation constraints between some pairs of consecutive terminals optimally in polynomial time. We also discuss how our algorithm can be incorporated into standard cell and building-block layout design systems. Experimental results indicate that by allowing movable terminals, substantial reduction in channel density can be obtained. References [1] M. Burstein and R. Pelavin "Hierarchical channel router" INTEGRATION, the VLSI journal, vol. 1(1), 21-38, 1983. [2] Y. Cai and D.F. Wong "Optimal channel pin assignment' Tech. Rep., Dept. of Comp. Sci., Univ. of Texas at Austin, 1990. [3] D.N. Deutsch "A dogleg channel router" DAC-76, 425-433, 1976. [4] C.M. Fiduccia and R.L. Rivest "A greedy channel router" DAC-82, 418-424, 1982. [5] M.R. Garey and D.S. Johnson Computers and intractability: a guide to the theory of NP-completeness W.H. Freeman & Co., San Francisco, 1979. [6] I.S. Gopal, D. Coppersmith and C.K. Wong "Optimal wiring of movable terminals" IEEE Trans. on Computers, vol. C-32(9), 845-858, 1983. [7] A.S. LaPaugh and R.Y. Pinter "On minimizing channel density by lateral shifting" ICCAD-83, 121-122, 183. [8] T. Yoshimura and E.S. Kuh "Efficient algorithms for channel routing" IEEE Trans. on CAD, vol. CAD-1, 25-35, 1982.


Constraint Identification for Timing Verification

Joel J. Grodstein, Jengwei Pan, Bill Grundmann, Bruce Gieseke, Y.T. Yen Digital Equipment Corporation, 77 Reed Road, HL02-2/H13, Hudson, Massachusetts 01749

Abstract We present a new set of algorithms to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a new class of constraints which, though vital for correct circuit function, has not been well treated in the CAD literature. These algorithms have been incorporated into a full-custom timing verifier, NTV. References [1] Jouppi, N. "Timing Verification and Performance Improvement of MOS VLSI Designs" Tech. Report 84-266, Stanford University, 1984. [2] Jouppi, N. "Timing Analysis and Performance Improvement of MOS VLSI Designs" IEEE Trans. on CAD, Vol CAD-6, No. 4, July 1987. [3] Vanden Meersch, E., L. Claesen, and H. De Man "Slocop: A Timing Verification Tool for Synchronous CMOS Logic" Proceedings ESSCIRC '86, 1986, pp.C4.1 - C4.3. [4] Ousterhout, J. "Switch-Level Delay Models for Digital MOS VLSI" Proceedings 21st ACM/IEEE DAC, 1984, pp. 542-8 [5] Szymanski, T. "Leadout: A Static Timing Analyzer for MOS Circuits" Proceedings ICCAD, 1986, pp. 130-133. [6] Cherry, J. "Pearl: A CMOS Timing Analyzer" Proceedings 25th ACM/IEEE DAC, 1988, pp. 148-153. [7] Wallace, D., and C. Sequin "ATV: An Abstract Timing Verifier" Proceedings 25th ACM/IEEE DAC, 1988, pp. 154-159. [8] Wallace, D. "Abstract Timing Verification for Synchronous Digital Systems" Report No. UCB/CSD 88/425, U.C. Berkeley, 1988. [9] Weiner, N., and A. Sangiovanni-Vincentelli, "Timing Analysis In A Logic Synthesis Environment" Proceedings 26th ACM/IEEE DAC, 1989, pp. 655-661. [10] Sakallah, K., T. Mudge, and O. Olukotun "A Timing Model of Synchronous Digital Circuits" Proceedings 27th ACM/IEEE DAC, 1990, pp. 111-117.


Race Detection for Two-phase Systems

Joel Grodstein, Jim Montanaro, Susanne Marino Digital Equipment Corporation, 77 Reed Road, HL02-2/H13, Hudson, Massachusetts 01749

Abstract We present RACE2, a tool to find latch race-through in two-phase, non-underlapped-clock systems. Though these systems can run at very high clock speeds, susceptibility to race-through has made them difficult to design. RACE2, by detecting all race-through violations, greatly reduces the design risk on these very fast systems. It combines the exhaustive search of a pattern-independent tool with a knowledge base of fundamental principles about when races are -- and are not -- important. References [1] Afghahi, M., and C. Svensson "A Unified Single-Phase Clocking Scheme for VLSI Systems" IEEE J. of Solid-State Circuits, Vol. 25, No. 1, Feb. 1990. [2] Yuan, J., and C. Svensson "High-speed CMOS Circuit technique" IEEE J. Solid-State Circuits, Vol. 24, pp. 62-71, 1989. [3] Seger, Carl-Johan "The Complexity of Race Detection in VLSI Circuits" in Adv. Research in VLSI, MIT Press, 1989, pp. 335-50. [4] Seger, Carl-Johan "A Bounded Race-Delay Model" Proc. ICCAD, 1989, pp. 130-133. [5] Krambeck, R., et. al. "High-speed Compact Circuits with CMOS" IEEE J. Solid-State Circuits, Vol SC-17, pp. 614-619, 1982. [6] Jouppi, N. "Timing Anal. & Perf. Improvement of MOS VLSI Designs" IEEE Trans. on CAD, Vol CAD-6, No. 4, July 1987. [7] Glasser, L., and D. Dobberpuhl, D. "The Design & Analysis of VLSI Circuits" Addison-Wesley, Reading, MA, 1985, pg 333.


Timing Constraints for Correct Performance

Habib Youssef, Eugene Shragowitz Computer Science Department, University of Minnesota, 200 Union Street S.E., Minneapolis, MN 55455

ABSTRACT With the advances in VLSI design, chip timing is becoming dominated by interconnect delays rather than macro performances. This fact requires a change in the methodology of timing analysis, verification and physical design. In this paper, we describe efficient algorithm to derive timing constraints on all the interconnects, which are consistent with the correct timing performance. Description of this algorithm is accompanied with experimental results, which demonstrate the effect of these constraints on the final layout. References [1] Ryotoro Kamikawai et al. "A critical path delay check system" In Proc. of the 18th Design Automation Conference, pp. 118-123, 1981 [3] Lionel C. Bening, Thomas A. Lane, and James E. Smith "Developments in logic network path delay analysis" in Proc. of the 19th Design Automation Conference, pp. 605-609, 1982 [2] Tohru Sasaki et al. "Hierarchical design verification for large digital systems" in Proc. of the 18th Design Automation Conference, pp. 105-112, 1981 [4] Robert B. Hitchcock, Sr., Gordon L. Smith, and David D. Cheng "Timing Analysis of Computer Hardware" in IBM J. RES. DEVELOP., Vol. 26, No. 1, pp. 100-116, 1982 [5] E. Tamura et al. "Path Delay Analysis for Hierarchical Building Block Layout System" in Proc. of the 20th Design Automation Conference, pp. 403-410, 1983 [6] R. Reddi and C. Chen "Hierarchical Timing Verification System" in CAD, vol. 18, no. 9, pp. 467-471, November 1986 [7] Siegfried Heinkele "A fast timing analysis tool for VLSI" in Proc., VLSI in COMPUTERS, pp. 193-197, 1987 [8] Electronic Design Interchange Format, Version 2 0 0, Electronic Industries Association, Washington, D. C., May, 1987. [9] A. E. Dunlop et al. "Chip layout optimization using critical path weighting" in Proc. of the 21st Design Automation Conference, pp. 133-136, 1984 [10] Michael Burstein and Mary N. Youssef "Timing influenced layout design" in Proc. of the 22nd Design Automation Conference, pp. 124-130, 1985 [11] Steven Teig, Randall L. Smith, and John Seaton "Timing Driven Layout of Cell-Based ICs" in Design Automation Guide, pp. 94-101, 1987 [12] Peter S. Hauge, Ravi Nair, and Ellen J. Yoffa "Circuit placement for predictable performance" in Proc. of ICCAD'87, pp. 88-91, 1987 [13] Ravi Nair et al. "Generation of Performance constraints for layout" in IEEE Transaction on CAD, Vol. CAD-8, No. 8, August 1989 [14] Michael A. B. Jackson and Ernest S. Kuh "Performance-driven Placement of Cell Based IC's" in Proc. of the 26th Design Automation Conference, pp. 370-375, 1989 [15] T. I. KirkpatricK, N. R. Clark "PERT as an aid to logic design" in IBM J. RES. DEVELOP., Vol. 10, No. 2, pp. 135-141, 1966 [16] Roy E. Marsten "The Design of the XMP Linear Programming Library" in Transactions on Mathematical Software, vol. 7, no. 4, December, 1981.


An Automata-Theoretic Approach to Behavioral Equivalence

Srinivas Devadas MIT, Cambridge, MA

Kurt Keutzer

AT&T Bell Labs, Murray Hill, NJ Abstract We address the problem of verifying the equivalence of a behavioral description against a logic-level implementation. One major hindrance toward a precise notion of behavioral verification has been that parallel, serial or pipelined implementations of the same behavioral description can be implemented in finite-state automata with different input/output behaviors. In this paper, we use nondeterminism to model the degree of freedom that is afforded by parallelism in a behavioral description that also contains complex control. Given some assumptions, we show how the set of finite automata derivable from a behavioral description can be represented compactly as an input-programmed automaton (p-Automaton), i.e. an automaton with programmed meta-input variables. The logic-level implementation is deemed to be equivalent to the behavioral description if and only if the p-Automaton is equivalent to the logic-level finite automaton under some assignment to the meta-input variables. The above method allows for extending the use of finite-state automata equivalence-checking algorithms to the problem of behavioral verification. References [1] R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984. [2] E. M. Clarke, J. R. Burch, and K. L. McMillan. Sequential circuit verification using symbolic model checking. In Proceedings, 27th Design Automation Conference, pages 46-51, June 1990. [3] S. Devadas. Approaches to Multi-level Sequential Logic Synthesis. In Proceedings of the 26th Design Automation Conference, pages 270-276, June 1989. [4] S. Devadas, H-K. T. Ma, and A. R. Newton. On the verification of sequential machines at differing levels of abstraction. In IEEE Transactions on Computer-Aided Design, pages 713-722, June 1988. [5] I. Gertner and R. P. Kurshan. Logical analysis of digital circuits. In M. Barbacci and C. J. Koomen, editors, Computer Hardware Descriptions Languages and Their Applications, pages 47-67, New York, 1987. Elsevier. [6] A. Ghosh, S. Devadas, and A. R. Newton. Verification of Interacting Sequential Circuits. In Proceedings of the 27th Design Automation Conference, pages 213-219, June 1990. [7] J. E. Hopcroft and J. D. Ullman. Introduction to automata theory, languages and computation. In Addison-Wesley. Reading, Mass., 1979. [8] M. C. McFarland and A. C. Parker. An Abstract Model of Behavior for Hardware Descriptions. In IEEE Transactions on Computers, volume C-32, pages 621-636, July 1983.


Tautology Checking Using Cross-Controllability and Cross-Observability Relations

E. Cerny, C. Mauras Dep. d'informatique et de recherche operationnelle Universite de Montreal, C.P. 6128, Succ. A Montreal,

Quebec, Canada H3C 3J7 Abstract We describe a new method for verifying the equivalence between a combinational circuit and its specification, when both are given in a modular (e.g., factored) form. It is based on the notion of cross-controllability and cross-observability relations that exist between the internal logic values across a cut of the joint composition of the circuit and the specification. It is proven that even after abstracting input and other internal variables the relations are sufficient to verify the equivalence. The abstraction allows to reduce the size of the relation, thus permitting to verify much larger circuits: We report the verification of an 8x8 parallel multiplier using at most 527 BDD cells of 21 variables. Extensions to sequential circuits are also discussed. References [1] S. B. Akers. "Binary Decision Diagrams" IEEE Transactions on Computers, 27(6): 509-516, June 1978. [2] J. P. Billon and J. C. Madre. "Originals concepts of PRIAM, an industrial tool for efficient formal verification of combinational circuits" in G.J. Milne, editor, Proceedings of the IFIP WG 10.2 International Conference on the fusion of Hardware Design and Verification, Glasgow, July 1988. IFIP, North-Holland. [3] C. Berthet and E. Cerny. "An algebraic model for asynchronous circuits verification" IEEE Transactions on Computers, 37(7):825-847, 1988. [4] L. Berman and L. Trevillyan. "Functional Comparison of Logic Design for VLSI chips" IBM Research Report 14137, October 1988. [5] R. E. Bryant. "Graph Based Algorithms for Boolean Function Manipulation" IEEE Transactions on Computers, 35(8):677-691, 1986. [6] E. Cerny. "An approach to unified methodology of combinational switching circuits" IEEE Transactions on Computers, 27(8), 1977. [7] O. Coudert, C. Berthet and J. C. Madre "Verification of Synchronous Sequential Machines using Symbolic Execution" in Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, June 1989. [8] D.L. Dietmeyer. Logic Design of Digital Systems. Alyn & Bacon Inc., 1978. [9] G. D. Hachtel and R. M. Jacoby. "Verification Algorithms for VLSI Synthesis" IEEE Transactions on CAD, 7(5), May 1988. [10] S. Minato, N. Ishiura and S. Yajima. "Fast Tautology Checking Using Shared Binary Decision Diagrams, Benchmark Results" in L. Claesen, editor, Proceedings of the IMEC-IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, Houthalen, Belgium, November 1989. [11] H. Simonis, H. N. Nguyen and M. Dincbas. "Verification of Digital Circuits Using CHIP" in G.J. Milne, editor, Proceedings of the IFIP WG 10.2 International Conference on the fusion of Hardware Design and Verification, Glasgow, July 1988. IFIP, North-Holland. [12] D. Verkest and L. Claesen. "Special Benchmark Session on Tautology Checking" in L. Claesen, editor, Proceedings of the IMEC-IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, Houthalen, Belgium, November 1989.


Automatic and semi-automatic verification of switch-level circuits with Temporal Logic and Binary Decision Diagrams

Masahiro Fujita, Yusuje Matsunaga, Taeko Kakuda

Artificial Intelligence Labs. Fujitsu Laboratories Ltd., 1015 Kamikodanaka, Nakahara-ku, Kawasaki 211, Japan

Abstract We present in this paper automatic and semi-automatic verification methods for switch-level circuits. Switch-level circuits with no delay (but with/without charge effects) are automatically verified using a new formalism with Binary Decision Diagrams (BDD) and temporal logic. Purely bidirectional transistors, such as those whose signal directions are dynamically determined in operations, are treated in the uniform way as non bidirectional transistors. In the case of switch-level circuits with arbitrary delays, based on the work by Leeser [5], we present a semi-automatic verification method which uses a propositional theorem prover using BDD. First some assignments of propositional variables to terms of temporal logic are manually given, and then the automatic theorem prover does verification. References [1] R.E. Bryant "Graph-based algorithms for boolean function manipulation" IEEE Trans. Computer, C-35(8):667-691, August 1986. [2] Shin-ichi Minato, Nagisa Ishiura, and Shuzo Yajima "Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation" 27th ACM/IEEE Design Automation Conference, June 1990. [3] M. Fujita, H. Fujisawa, and N. Kawato "Evaluations and Improvements of a Boolean Comparison Method Based on Binary Decision Diagrams" IEEE International Conference on Computer Aided Design '88, Santa Clara, November, 1988. [4] J.C. Madre and J.P. Billon "Proving Circuit Correctness using Formal Comparison Between Expected and Extracted Behavior" 25th ACM/IEEE Design Automation Conference, June 1987. [5] M.E. Leeser "Reasoning About the Function and Timing of Integrated Circuits with Interval Temporal Logic" IEEE Trans. Computer-Aided Design, Vol. CAD-8, No. 12, pp.1233-1246, December 1989. [6] D.A. Basin, G.M. Brown, and M.E. Leeser "Formally Verified Synthesis of Combinational CMOS Circuits" IMEC-IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, Lueven, Belgium, November 1989. [7] C. Pedron and A. Stauffer "Analysis and Synthesis of Combinational Pass Transistor Circuits" IEEE Trans. Computer-Aided Design, Vol. CAD-7, No. 7, pp.775-786, July 1988. [8] Moszkowski, B. C. A Temporal Logic for Multilevel Reasoning about Hardware. IEEE Computer Magazine, 18, 2, pp.10-19 (1985). [9] M. Fujita, H. Tanaka, and T. Moto-oka "Logic design assistance with temporal logic" IFIP 7th Computer Hardware Description Languages and their Application, Tokyo, August, 1985. [10] M. Fujita and S. Kono, H. Tanaka and T. Moto-oka "Assistance in Hierarchical and Structured Logic Design Using Temporal Logic and Prolog" IEE Proceedings. Pt. E, Vol. 133, No. 5, September, 1986. [11] D.L. Dill and E.M. Clarke "Automatic Verification of Asynchronous Circuit Using Temporal Logic" IEE Proceedings. Pt. E, Vol. 133, No. 5, September, 1986. [12] M.J.C. Gordon and J. Herbert "Formal Hardware Verification Methodology and its Application to a Network Interface Chip" IEE Proceedings. Pt. E, Vol. 133, No. 5, September, 1986.

[13] S. Muroga, Y. Kambayashi, H.C. Lai and J.N. Culliney "The Transduction Method - Design of Logic Networks based on Permissible Functions" IEEE Trans. Comput., Vol.C-38, No.10, pp.1404-1424, October 1989. [14] Y. Matsunaga and M. Fujita "Multi-level Logic Optimization Using Binary Decision Diagrams" IEEE International Conference on Computer Aided Design '89, Santa Clara, November 1989. [15] H. Sato, Y. Yasue, Y. Matsunaga, and M. Fujita "Boolean resubstitution with permissible functions and Binary Decision Diagrams" 27th ACM/IEEE Design Automation Conference, June 1990. [16] Masahiro Fujita and Hisanori Fujisawa "Specification, Verification, and Synthesis of Control Circuits with Propositional Temporal Logic" 9th IFIP Symposium on Computer Hardware Description Languages, pp.265-279, Elsevier Science Publishers, 1989. [17] R.E. Bryant "Algorithmic Aspects of Symbolic Switch Network Analysis" IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 4, pp.618-633, July 1987. [18] R.E. Bryant "Boolean Analysis of MOS Circuits" IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 4, pp.634-649, July 1987. [19] O. Coudert, C. Berthet, and J.C. Madre "Verification of synchronous sequential machines based on symbolic execution" International Workshop on Automatic Verification Methods for Finite State Systems, Lecture Notes in Computer Science, 407, Spriger-Verlag, June 1989. [20] J.R. Burch, E.M. Clarke, and K.L. McMillan "Sequential Circuit Verification Using Symbolic Model Checking" 27th ACM/IEEE Design Automation Conference, June 1990. [21] Z. Manna and A. Pnueli "Verification of Concurrent Programs, Part 1: The Temporal Framework" Dept. of Computer Science, Stanford Univ. Report STAN-CS-81-836, June 1981. [22] K. Cho and R.E. Bryant "Test pattern generation for sequential MOS circuits by symbolic fault simulation" 26th ACM/IEEE Design Automation Conference, pp.418-423, June 1989. [23] M.J.C. Gordon "HOL: A Proof Generating System for Higher-Order Logic" In G. Birwistle and P.A. Subrahmanyan, editors, VLSI Specification, Verification and Synthesis, Kluwer Academic Publishers, 1988.


A New Global Router Based on a Flow Model and Linear Assignment

G. Meixner, U. Lauther Siemens AG, ZFE IS EA REF Otto-Hahn-Ring 6, D-8000 Munich 83, West-Germany

Abstract We have developed a new heuristic for global routing in graphs. Based on a flow model it can handle many nets simultaneously, thus reducing the net ordering problem. To demonstrate the validity of our method we applied it to standard cell design style. For this application we combined the flow model approach with linear assignment to achieve a hierarchical global routing scheme. This procedure is for very complex designs about six times faster than our old flat net by net global router, while producing denser layouts for the majority of our testcases. We also achieved a good quality in comparison with the TimberwolfSC version 5.4 global router. References [BD80] R. E. Burkhard and U. Derigs "Assignment and Matching Problems: Solution Methods with Fortran Programs" Springer, 1980. [BJ77] M. S. Bazaraa and J. J.Jarvis "Linear Programming and Network Flows" New York 1977. [BP83] M. Burstein and R. Petavin "Hierarchical Wire Routing" IEEE Trans. CAD, vol. CAD-2, no. 4, pp.223-234, 1983. [KM86] E. S. Kuh and M. Marek-Sadowska "Global Routing" in Layout Design and Verification, ed. by T. Ohtsuki, Amsterdam: North-Holland, 1986. [Lau87] U. Lauther "Top Down Global Routing for Channelless Gate Arrays Based on Linear Assignment" Proc. of the IFIP Intern. Conf. on VLSI 1987, pp.141 - 151. [LS88] KW. Lee and C. Sechen "A New Global Router for Row-Based Layout" Proc. of the Int. Conf. on CAD, 1988, pp.180 - 183. [MS86] M. Marek-Sadowska "Route Planner for Custom Chip Design" IEEE Intern. Conf. on CAD, Nov. 1986, Santa Clara Digest of Technical Papers, pp.246 - 249. [Na87] R. Nair "A Simple Yet Effective Technique for Global Wiring" IEEE Trans. CAD, vol. CAD-6, no.5. [SK87] E. Shragowitz and S. Keel "A Global Router Based on a Multicommodity Flow Model" Integration, vol 5, 1987. [Tar83] R.E. Tarjan "Data Structures and Network Algorithms" Philadelphia, 1983.


A Timing-Driven Global Router for Custom Chip Design

Somchai Prasitjutrakul, William J. Kubitz Department of Computer Science, University of Illinois at Urbana-Champaign, 1304 W. Springfield

Avenue Urbana, Illinois, 61801, U.S.A. Abstract A timing-driven global router for custom chip design, with the objective of maximizing the minimum delay slack, is presented. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays are used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented here is experimentally shown to produce global routes achieving the objective. References [1] M. A.B. Jackson, E. S. Kuh, and M. Marek-Sadowska "Timing Driven Routing for Building Block Layout" Proc. ISCAS. (1987), pp. 518-519. [2] Y. Fujihara, Y. Sekiyama, and et. al. "DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions" Proc. 26th DAC., (1989), pp. 791-794. [3] A. E. Dunlop, V. D. Agrawal, and et.al. "Chip Layout Optimization Using Critical Path Weighting" Proc. 21st DAC., (1984), pp. 142-146. [4] M. Rose, M. Wiesel, D. Kirkpatrick, and N. Nettleton "Dense, Performance Directed, Auto Place and Route" Proc. CICC, (1988), pp. 11.1.1 - 11.1.4. [5] N. J. Nilsson "Problem-Solving Methods in Artificial Intelligence" Mcgraw-Hill (1971), Ch. 3, pp. 43-78. [6] T. Sakurai "Approximation of Wiring Delay in MOSFET LSI" IEEE Journal of Solid-State Circuits (1983), Vol. SC-18, No. 4, pp. 418-426. [7] E. Horneber, and W. Mathis "A Closed-Form Expression for Singal Delay in CMOS-Driven Branched Transmission lines" VLSI'87, C.H.Sequin (editor), pp. 353-362. [8] D. L. Carter, and D. F. Guise "Analysis of Signal Propagation Delays and Chip Level Performance Due to On-Chip Interconnections" Proc. ICCD. (1983), pp. 218-221. [9] T.M. Lin, and C.A. Mead "Signal Delay in General RC Networks" IEEE Trans. on CAD. (1984), Vol. CAD-3, No. 4, pp. 331-349. [10] H. B. Bakoglu "Circuits, Interconnections, and Packaging for VLSI" Addison-Wesley, 1990. [11] W. Dai, T. Asano, and E. S. Kuh "Routing Region Definition and Ordering Scheme for Building-Block Layout" IEEE Trans. on CAD. (1985), Vol. CAD-4, No. 3, pp. 189-197. [12] R. B. Hitchcock, G. L. Smith, and D. D. Cheng "Timing Analysis of Computer Hardware" IBM Journal of Research and Development, Vol.26, No.1, pp.100-105. [13] G. W. Clow "A Global Routing Algorithm for General Cells" Proc. 21th DAC., (1984), pp. 45-51.


Rubber Band Routing and Dynamic Data Representation

Wayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue Computer Engineering Board of Studies, University of California, Santa Cruz, CA 95064

Masao Sato

Department of Information Engineering, Takushoku University, Tokyo 193, Japan ABSTRACT The limiting factor for high performance systems is being set by interconnection delay rather than transistor switching speed. The most severe limitation comes from the use of single chip modules, one level of the packaging hierarchy. Multichip modules can significantly improve the system performance. We propose a new methodology and efficient algorithms for performance driven routing based on computational geometry. A dynamic data representation using constrained triangulation is the key to achieve the efficient routability testing and incremental updating of topological routing. Variable width, variable spacing, evenly distributed spacing and thermal via insertion are used to handle cross talk, switching noise, and thermal resistance problems. REFERENCES [1] R. Bruce, W. Meuli, and J. Ho "Multichip Modules - An Overview" in Proc. of the 26th Design Automation Conf., pp. 389-393, 1989. [2] L. P. Chew "Constrained Delaunay triangulations" in Algorithmica, vol. 4, pp. 97-108, 1989. [3] R. C. Frye and K. L. Tai "Interconnection Lines for Wafer-Scale-Integrated Assemblies" U. S. Patent 4,703,288, Oct. 27, 1987. [4] C. E. Leiserson and F. M. Maley "Algorithms for routing and testing routability of planar VLSI layouts" in Proc. of the 17th Annual ACM Symposium on Theory of Computing," pp. 69-78, 1985. [5] T. Ohsaki "VLSI Packaging Technologies for High Speed Electronic Systems" in Proc. of VLSI 89, pp. 255-264, 1989. [6] F. P. Preparata and M. I. Shamos. Computational Geometry - An Introduction. Springer-Verlag, 1985.


Touch and Cross Router

K. Kawamura, T. Shindo, T. Shibiya, H. Miwatari, Y. Ohki Fujitsu Laboratories Ltd., 1015, Kamikodanaka Nakahara-ku Kawasaki 211, Japan

Abstract This paper presents a new general routing algorithm. Each net is routed to minimize the cost function defined by a weighted sum of penalties. Two types of design rule violations, touches and crosses, are factors of the cost function. Using these violations enables the algorithm achieve 100% completion even when routing problems have nets which must be considered simultaneously. This type of problem could not be routed completely by conventional rip-up routers. The algorithm was implemented on a newly developed massively parallel computer. Experimental results on Burstein's difficult switch box problem and several small printed circuit boards show that the algorithm is as powerful as a human expert designer. References [1] F. Rubin "An Iterative Technique for Printed Wire Routing" Proc. 11th Design Automation Workshop, 1974, pp. 308-313. [2] R. Linsker "An iterative-improvement penalty-function-driven wire routing system" IBM J. Res. Develop. vol. 28, no 5, 1984, pp. 613-624. [3] Youn-Long Lin, Yu-Chin Hsu and Fur-Shing Tsai "A Detailed Router based on Simulated Evolution" Proc. Int. Conf. Computer-Aided Design, 1988, pp. 38-41. [4] E. Rosenberg "A New Iterative Supply/Demand Router with Rip-up Capability forPrinted Circuit Boards" Proc. 24th Design Automation Conf., 1987, pp. 721-726. [5] William A. Dees, Jr. and Robert J. Smith, II "Performance of Interconnection Rip-up and Reroute Strategies" Proc. 18th Design Automation Conf., 1981, pp. 382-390. [6] William A. Dees, Jr. and Patrick G. Karger "Automated Rip-up and Reroute Technique" Proc. 19th Design Automation Conf., 1982, pp. 432-439. [7] K. Kawamura, M. Umeda and H. Shiraishi "Hierarchical Dynamic Router" Proc. 23th Design Automation Conf., 1986, pp. 803-809. [8] Shiraishi, H., Ishii, M., Kurita, S. and Nagamine, M., "ICAD/PCB: Integrated Computer Aided Design System for Printed Circuit Boards" Proc. 19th Design Automation Conf., 1982, pp.727-732. [9] H. Shin and A. Sangiovanni-Vincentelli "A Detailed Router Based on Incremental Routing Modification: Mighty" IEEE Trans. on Computer-Aided Design, Vol. CAD-6, No. 6, 1987, pp. 942-955. [10] Joobani, R. and Siewiorec P. Daniel "WEAVER: A Knowledge-Based Routing Expert" IEEE DESIGN & TEST, 1986, pp. 12-23. [11] C.S., Ying, X.L., Hong and E.Q., Wang "DRAFT: An Efficient Area Router Based on Global Analysis" Proc. Int. Conf. Computer-Aided Design, 1987, pp. 386-389. [12] Shibuya, T., Kawamura, K., Shindo, T., Miwatari, H. and Oki, Y. "Application Specific Massively Parallel Machine" to be appeared in Frontier '90, 1990. [13] Nair, R., Hong, S.J., Liles, S. and Villani, R. "Global Wiring on a Wire Routing Machine" Proc. 19th Design Automation Conf., 1982, pp.224-231.


Exploitation of Periodicity in Logic Simulation of Synchronous Circuits

Rahul Razdan, Gabriel Bischoff, Ernst Ulrich Digital Equipment Corporation, 77 Reed Road, HLO2-2/H13 Hudson, Ma. 01749

Abstract An overwhelming majority of logic designers use synchronous logic design techniques to manage the complexity of their designs and rely on logic simulation techniques for design verification. Yet, logic simulators do not take advantage of the higher abstraction level provided by synchronous logic design techniques to improve their performance. In the context of time to market pressures, this performance is critical to the verification of large complex designs. In this paper, we shall present a general technique which takes advantage of the high degree of periodicity common in synchronous logic designs. We shall show a performance improvement of at least 200% when these techniques are applied within the COSMOS simulation system to simulate large digital systems. References [1] Ulrich "A Design Verification Methodology based on Concurrent Simulation and Clock Suppression" IEEE Design Automation Conference 1983. [2] Ulrich, et.al "Design Verification for Very Large Networks Based on Concurrent Simulation and Clock Suppression" IEEE International Conference on Computer Design (ICCD) 1983 [3] R. E. Bryant, D. Beatty, K. Brace, K. Cho, and T. Sheffler "COSMOS: a Compiled Simulator for MOS Circuits" 24th Design Automation Conference, 6-16, 1987. [4] R. E. Bryant "Boolean Analysis of MOS circuits" IEEE Transactions on Computer Aided Design, CAD-6(4), 634-649, 1987.


SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction

D. T. Blaauw, R. B. Mueller-Thuns, D. G. Saab, P. Banerjee Center for Reliable an High Performance Computing, University of Illinois at Urbana-Champaign, Urbana,

IL 61801, U.S.A.

J. A. Abraham Computer Engineering Research Center, University of Texas at Austin, Austin, TX 78758, U.S.A.

ABSTRACT: Switch-level simulation has become a common means for accurate modeling of MOS circuit behavior. The SNEL simulator is a novel switch-level simulator which uses functional abstraction in a preprocessing step. Its functional abstraction algorithms use static circuit analysis to determine the overall circuit operation. This way, the operation of the circuit, rather than the full functionality of each individual circuit component is modeled during the simulation. A more abstract and high-level model of the circuit is therefore used, which greatly increases the simulation speed. Since the full switch-level behavior is captured by the functional abstraction, the accuracy of the simulation is maintained. The functional abstraction is performed at four circuit grain sizes or levels: individual circuit nodes, individual transistors, single dc-connected components, and multiple dc-connected components. At the highest level, the abstraction algorithm generates high-level software models for arbitrarily large circuit blocks. The proposed algorithms were implemented and tested for commercial circuits. By using all levels of abstraction, the simulation speed was increased by an order of magnitude. REFERENCES [1] R.E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Trans. on Computers, pp. 160-177, 1984. [2] Z. Barzilai, D. K. Beece, L. M. Huisman, V. S. Iyengar, and G. M. Silberman "SLS – A Fast Switch-Level Simulator" IEEE Transactions on CAD, pp. 838-849, 1988. [3] S. A. Szygenda and A. A. Lekkos "Integrated Techniques for Functional and Gate-Level Digital Logic Simulation" Proc. IEEE International Design Automation Conference, pp. 159-172, 1973. [4] A. Brish, R. Keinan, and Y. Ravid "A Smart System that Compiles RTL Models from Schematics" VLSI System Design, pp. 32-35, Feb. 1988. [5] M. Boehner "LOGEX - An Automatic Logic Extractor from Transistor to Gate Level for CMOS technology" Proc. IEEE International Design Automation Conference, pp. 517-522, 1988. [6] V. E. Kelly and L. I. Steinberg "The Critter System: Analyzing Digital Circuits by Propagating Behaviors and Specifications" Proc. Conference on Artificial Intelligence, pp. 284-289, 1982. [7] I.N. Hajj and D.G. Saab "Symbolic Logic Simulation of MOS Circuits" Int. Symp. on Circuits and Systems, pp. 246-249, 1983. [8] G. Ditlow, W. Donath, and A. Ruehli "Logic equations for MOSFET circuits" Proc. IEEE International Symposium on Circuits and Systems, pp. 752-755, 1983. [9] R.E. Bryant, D. Beatty, K. Brace, K. Cho, and T. Scheffler "COSMOS: A Compiled Simulator for MOS Circuits" Proc. IEEE Int. Design Automation Conference, pp. 9-16, 1987. [10] D. T. Blaauw, P. Banerjee, and J. A. Abraham "Automatic Classification of Node Types in Switch-Level Descriptions" Proc. IEEE International Conference on Computer Design, 1990.

[11] D. T. Blaauw, D. G. Saab, J. Long, and J. A. Abraham "Derivation of Signal Flow for Switch-Level Simulation" Proc. European Design Automation Conference, pp. 301-305, 1990.


Optimization of the Parallel Techniwue For Compiled Unit-Delay Simulation

Peter M. Maurer Department of Computer Science and Engineering, University of South Florida, Tampa, FL 33620

Abstract The parallel technique is a purely compiled method for unit-delay simulation that is based on levelized compiled simulation and bit parallel simulation. The parallel technique provides rapid simulations with a reasonable amount of code, but there are opportunities for optimization. This paper presents two schemes which are called bit-field trimming and shift-elimination. Performance results are presented that demonstrate an average performance improvement of 47%. REFERENCES [1] Bryant, R. E., D. Beatty, K. Brace, K. Cho and T. Sheffler "COSMOS: A Compiled Simulator for MOS Circuits" Proceedings of the 24th Design Automation Conference, 1987, pp. 9-16. [2] Chiang, M., and R. Palkovic "LCC Simulators Speed Development of Synchronous Hardware" Computer Design, Mar. 1, 1986, pp. 87-91. [3] D. M. Lewis "Hierarchical Compiled Event-Driven Logic Simulation" proceeding of ICCAD-89. [4] P. Maurer, Z. Wang "Techniques for Unit-Delay Compiled Simulation" Proceedings of the 27th Design Automation Conference, to appear June 1990. [5] F. Brglez, P. Pownall, R. Hum "Accelerated ATPG and Fault Grading via Testability Analysis" Proc ISCAS-85, pp. 695-698.


Fast Switch-level Fault Simulation Using Functional Fault Modeling

E. Vandris, G. Sobelman Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455

Abstract A new switch-level fault simulation method for MOS circuits that combines compiled switch-level simulation techniques with functional fault modeling is presented. The simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. During compilation the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level and is shown to perform well, although it incurs a higher overhead due to the dynamic memory properties of MOS circuits. References [1] R. Wadsack "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits" Bell System Technical Journal, Vol. 57, May-June 1978, pp. 1449-1473. [2] M.D. Shuster, R.E. Bryant "Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator" 22nd Design Automation Conf., 1985, pp. 715-719. [3] S.L. Lusky and T. Shridhar "Detectable CMOS Faults in Switch-Level Simulation" Int'l Test Conf., 1985, pp. 875-883. [4] P. Banerjee and J.A. Abraham "A Multivalued Algebra for Modeling Physical Failures in MOS VLSI Circuits" IEEE Trans. on Computer-Aided Design, July 1985, pp. 312-321. [5] J.P. Caisso and B. Courtois "Fault Simulation and Test-Pattern Generation at the Multiple-Valued Switch-Level" Int'l Test Conf., 1988, pp. 94-101. [6] R. E. Bryant et al. "COSMOS: A Compiled Simulator for MOS Circuits" 24th Design Automation Conference, 1987, pp. 9-16. [7] K. Cho and R.E. Bryant "Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation" 26th Design Automation Conference, 1989, pp. 418-423. [8] P. Agrawal, S.H. Robinson and T.G. Szymanski "Automatic Modeling of Switch-Level Networks Using Partial Orders" IEEE Trans. on Computer-Aided Design, July 1990, pp. 696-707. [9] L.E. Bays, C.F. Chen, E.M. Fields, R.N. Gadenz, W.P. Hayes, H.S. Moskovitz, T.G. Szymanski "Post-Layout Verification of the WE DSP32 Digital Signal PRocessor" IEEE Design & Test of Computers, February 1989, pp. 56-66. [10] R.E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Trans. on Computers, February 1984, pp. 160-177. [11] P. Agrawal and L.W. Norohna "Modeling Circuits in the MARS Hardware Accelerator" Int'l Conf. on Computer-Aided Design, 1987, pp. 492-495. [12] P. Agrawal and V.D. Agrawal "Can Logic Simulators Handle Bidirectionality and Charge Sharing?" Int'l Symp. on Circuits and Systems, 1990, pp. 411-414. [13] V.J. Oklobdzija and P.G. Kovijanic "On Testability of CMOS-Domino Logic" 14th Int'l Fault Tolerant Computing Conf., 1984, pp. 50-55. [14] W.T. Cheng and M-L. Yu "Differential Fault Simulation - A Fast Method Using Minimal Memory" 26th Design Automation Conf., 1989, pp. 424-428. [15] S. B. Akers and B. Krishnamurthy "Test Counting: A Tool for VLSI Testing" IEEE Design & Test of Computers, October 1989, pp. 58-77.


An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine Networks

Wayne Wolf Department of Electrical Engineering. Princeton University

Abstract This paper presents an algorithm which simultaneously generates the Cartesian product of a network of finite-state machines and minimizes the resulting product machine. Our algorithm can can generate collapsed machines, removing a large set of redundant states on the fly, in CPU times comparable to the time required for simple Cartesian product collapsing. The algorithm makes it practical to generate and analyze a much larger class of collapsed FSM networks. References [1] Wayne Wolf. The FSM network model for behavioral synthesis of control-dominated machines. In Proceedings, 27[sup.th] Design Automation Conference, pages 692-697, ACM Press, June 1990. [2] P. J. G. Ramadge and W. M. Wonham. The control of discrete event systems. Proceedings of the IEEE, 77(1), January 1989. [3] Sudhir Aggarwal, Daniel Barbara, and Kalman Z. Meth. SPANNER: a tool for the specification, analysis, and evaluation of protocols. IEEE Transactions on Software Engineering, SE-13(12):1218-1237, December 1987. [4] E. M. Clarke, D. E. Long, and K. L. McMillan. A language for compositional specification and verification of finite state hardware controllers. In J. A. Darringer and F.J. Rammig, editors, Computer Hardware Description Languages and their Applications, pages 281-295, Elsevier Science Publishers B. V., 1990. [5] Krishhan K. Sabnani, Aleta M. Lapone, and M. Umit Uyar. An algorithmic procedure for checking safety properties of protocols. IEEE Transactions on Communications, 37(9):940-948, September 1989. [6] Zvi Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, second edition, 1978. [7] John E. Hopcroft and Jeffrey D. Ullman. Introduction to Automata Theory, Languages, and Computation. Addison-Wesley, 1979. [8] Robert Mayo. Behavioral Synthesis benchmarks. December 1988. Benchmarks for the Behavioral Synthesis Workshop. [9] Carver Mead and Lynn Conway. Introduction to VLSI Systems. Addison-Wesley, Reading MA, 1980.


Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test

Pranav Ashar, Abhijit Ghosh, Srinivas Devadas(**), A. Richard Newton

Department of Electrical Engineering and Computer Sciences, University of California, Berkeley (**)Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology,

Cambridge Abstract In this paper, implicit state enumeration is used in developing strategies to solve key problems in sequential logic synthesis and test. It is shown here that it is possible to extract implicit State Transition Graphs (ISTGs) from logic-gate and flip-flop descriptions of sequential circuits that allow equivalent states to be represented by cubes, and edges from different states to be coalesced into one, thereby decreasing significantly the CPU time and memory requirements of the extraction process. Coupled with the new enumeration technique, we propose synthesis strategies for FSMs described at the logic level. As is illustrated in the results section, these synthesis strategies allow us to optimize large FSMs. We apply an ISTG traversal algorithm for verifying equivalence and detecting redundancies in logic-level sequential circuits. This algorithm is more efficient than previously developed sequential test generation algorithms when used to detect equivalent-state redundancies present in some classes of circuits. References [1] P. Ashar, S. Devadas, and A. R. Newton. Optimum and Heuristic Algorithms for Finite State Machine Decomposition and Partitioning. In Proc. of Int'l Conference on Computer-Aided Design, November 1989. [2] P. Ashar, A. Ghosh, S. Devadas, and A. R. Newton. A Taxonomy and Characterization of Approaches to Sequential Logic Verification and Synthesis. Manuscript in preparation. [3] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: A Multiple-Level Logic Optimization System. In IEEE Transactions on Computer-Aided Design, pages 1062-1081, November 1987. [4] Olivier Coudert, Christian Berthet, and Jean C. Madre. Verification of Sequential Machines Using Functional Boolean Vectors. In IFIP Conference, November 1989. [5] S. Devadas. Approaches to Multi-level Sequential Logic Synthesis. In Proc. of 26th Design Automation Conference, pages 270-276, June 1989. [6] S. Devadas, H-K. T. Ma, and A. R. Newton. On the Verification of Sequential Machines at Differing Levels of Abstraction. In IEEE Transactions on Computer-Aided Design, pages 713-722, June 1988. [7] S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. MUSTANG: State Assignment of Finite State Machines Targeting Multi-Level Logic Implementations. In IEEE Transactions on Computer-Aided Design, pages 1290-1300, December 1988. [8] S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. Irredundant Sequential Machines Via Optimal Logic Synthesis. In IEEE Transactions on Computer-Aided Design, pages 8-18, January 1990. [9] A. Ghosh, S. Devadas, and A. R. Newton. Test Generation for Highly Sequential Circuits. In Proc. of Int'l Conference on Computer-Aided Design, pages 362-365, November 1989. [10] S. Malik, E. Sentovich, R. Brayton, and A. Sangiovanni-Vincentelli. Retiming and Resynthesis: Optimizing Sequential Circuits Using Combinational Techniques. In Proc. of 1989 MCNC Logic Synthesis Workshop, May 1989. [11] A. Stolzle. A VLSI Wordprocessing Subsystem for a Real Time Large Vocabulary Continuous Speech Recognition System. In MS Thesis, September 1989.

[12] T. Villa. Constrained Encoding in Hypercubes: Applications to State Assignment. In U. C. Berkeley, ERL Memo 86/44, May 1986.


Minimization of Symbolic Relations

Bill Lin University of California Berkeley, CA 94704

Fabio Somenzi

University of Colorado, Boulder, CO 80309 Abstract We address the problem of minimizing symbolic relations. The relevance of this problem in the field of optimal encoding is shown by giving examples of application. A binate covering formulation of the optimization problems involved is given, for which several algorithms are available. We propose a new method based on binary decision diagrams (BDDs) and we show how the covering problem can be solved in linear time in that case. References [1] K. L. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of the Design Automation Conference, pages 40-45, June 1990. [2] R. K. Brayton and F. Somenzi. An exact minimizer for boolean relations. In Proceedings of the International Conference on Computer-Aided Design, pages 316-319, November 1989. [3] S. Devadas and A. R. Newton. Exact algorithms for output encoding, state assignment and four-level boolean minimization. In Hawaii International Conference on System Sciences, pages 387-396, January 1990. [4] A. Grasselli and F. Luccio. A method for minimizing the number of internal states in incompletely specified sequential networks. IEEE Trans. Elec. Comp., EC-14:350-359, June 1965. [5] Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, second edition, 1978. [6] B. Lin and A.R. Newton. Restructuring state machines and state assignment: Relationship to minimizing logic across latch boundaries. In MCNC Logic Synthesis Workshop, May 1989. [7] B. Lin, G. S. Whitcomb, and A. R. Newton. Symbolic don't cares and equivalence in high-level synthesis. In IFIP International Working Conference on Logic and Architecture Synthesis, May 1990. [8] G. De Micheli, R. K. Brayton, and A. Sangiovanni-Vincentelli. Optimal state assignment of finite state machines. IEEE Transactions on Computer-Aided Design, pages 269-285, July 1985. [9] R. L. Rudell and A. Sangiovanni-Vincentelli. Multiple-valued minimization for PLA optimization. IEEE Transactions on Computer-Aided Design, 6:727-750, September 1987.


Algorithms for Discrete Function Manipulation

Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton Department of EECS, University of California, Berkeley

Abstract Many problems can be stated more naturally using variables that have multiple values (i.e. take their values from a discrete set). Functions defined on these variables can also take on values from a discrete set. In some cases the sets are ordered. Examples of such problems range from routing to graph problems to scheduling. In many cases these problems are NP-Complete or coNP-Complete; however in many practical examples it is possible to implicitly enumerate all solutions using a directed graph structure. Recent work on binary decision diagrams (BDD's) [BRB90] have greatly advanced our ability to do this for problems involving binary variables. In this paper we investigate the analogous graph structure for representing and manipulating discrete variable problems. We define the multi-valued decision diagram (MDD), analyze its properties (in particular prove a strong canonical form) and provide algorithms for combining and manipulating MDD's. We give a method for mapping an MDD into an equivalent BDD which allows us to provide a highly efficient implementation using the already developed efficient BDD packages available. A direct implementation of the MDD structure has also been done, but our initial implementation has not yet been tuned to the same extent as for BDD's to enable a reasonable comparison. We have used the mapping to BDD's to provide an initial understanding of the limits on the sizes of real problems that can be executed. The results are encouraging. References [BRB90] K. Brace, R. Rudell, and R. Bryant. Efficient implementation of a BDD package. Proc. 27th Design Automation Conference, pages 40-45, June 1990. [Bry86] R.E. Bryant. Graph based algorithms for Boolean function manipulation. IEEE Transactions on Computers, C-35:667-691, August 1986. [Dev89] S. Devadas. Optimal layout via Boolean satisfiability. Proc. Int. Conf. on CAD, 1989 (ICCAD-89), pages 294-297, November 1989.


Floorplanning with Pin Assignment

Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh Electronics Research Laboratory, University of California, Berkeley, CA 94720, USA

Abstract We present a hierarchical technique for floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, we determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for Xerox general cell benchmark are reported. References [1] N.L. Koren "Pin Assignment in Automated Printed Circuit Board" Proc. 9-th Design Automation Workshop, 1972, pp. 72-79. [2] H.N. Brady "An Approach to Topological Pin Assignment" IEEE Trans. on Computer Aided Design, vol CAD-3, 1984, pp.250-255. [3] X. Yao, M. Yamada and C.L. Liu "A New Approach to the Pin Assignment Problem" Proc. 25-th Design Automation Conference, 1988, pp. 566-572. [4] X. Yao and C.L. Liu "Pin Position Assignment for Movable Pins in Macro-Cells" to appear in Int'l Journal Computer Aided VLSI Design, 1990. [5] J. Cong "Pin Assignment with Global Routing" Proc. Int'l Conf. on Computer Aided Design, 1989, pp. 302-305. [6] M. Pedram and B.T. Preas "A Hierarchical Floorplanning Approach" to appear in Proc. Int'l Conf. on Computer Design 1990. [7] W.M. Dai, B. Eschermann, E.S. Kuh and M. Pedram "Hierarchical Placement and Floorplanning for BEAR" IEEE Trans. on Computer Aided Design, vol CAD-8, no 12, 1989, pp. 1335-1349. [8] Y. Ogawa, M. Pedram and E.S. Kuh "Timing-Driven Placement for General Cell Layouts" Proc. Int'l Symposium on Circuits And Systems, vol. 2, May 1990, pp. 872-875. [9] J.K. Ousterhout "Corner Stitching: A Data Structuring Technique for VLSI Layout Tools" IEEE Trans. on Computer Aided Design, vol CAD-3, 1984. [10] W.-M. Dai, H.H. Chen, R. Dutta, M. Jackson, E.S. Kuh, M. Marek-Sadowska, M. Sato, D. Wang, and X.M. Xiong "BEAR: A New Building-Block Layout System" Proc. Int'l Conf. on Computer Aided Design, 1987, pp. 34-37. [11] R.E. Burkhard and U. Lerigs "Assignment and Matching Problems: Solution Methods with Fortran Programs" Springer Verlag, 1980. [12] M. Marek-Sadowska "Route Planner for Custom Chip Design" Proc. Int'l. Conf. on Computer Aided Design, 1986, pp. 246-249. [13] "General Cell Floorplanning Benchmarks" MCNC Int'l Workshop on Layout Synthesis, Research Triangle Park, NC, 1990.


DIFFUSION - An Analytic Procedure Applied to Macro Cell Placement

Chong-Min Kyung Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, P.O. Box 150,

Cheongryang, Seoul, Korea

Peter V. Kraus, Dieter A. Mlynski Institut fur Theoretische Elektrotechnik und Messtechnik, Universitat Karlsruhe (TH), Kaiserstr. 12, D-

7500 Karlsruhe, Germany

Abstract This paper describes a new optimization procedure called Diffusion which can be used in global circuit placement for suppressing inter-module and module-to-chip boundary overlaps. A salient feature of the proposed Diffusion procedure is that multiple decisions on the moves of all variables (module positions) are simultaneously made such that a global, analytic objective function is minimized. Various strategies are discussed to speed up the convergence, and to prevent the solution from being stuck at local minima. Net force model is used with the Diffusion procedure to minimize the inter-module wire length besides reducing the inter-module and module-to-chip overlaps. Various experimental results are given. Further potential applications of the proposed procedure include multi-layer placement, and placement in arbitrarily-shaped region. References [1] M. A. Breuer "Min-cut placement" J. Design Automation and Fault Tolerant Computing, vol. 1, pp. 343-382, Oct. 1977. [2] A. E. Dunlop and B. W. Kernighan "A procedure for placement of standard-cell VLSI circuits" IEEE Trans. on CAD of IC's and Systems, vol. CAD-4, pp. 92-98, Jan. 1985. [3] N. R. Quinn and M. A. Breuer "A force-directed component placement procedure for printed circuit boards" IEEE Trans. on Circuits and System, vol. CAS-26, pp. 377-388, 1979. [4] R. S. Tsay, E. S. Kuh and C. P. Hsu "Module placement for large chips based on sparse linear equations" Int. J. Circuit Theory and Applications, vol. 16, pp. 416-423, 1988. [5] C. K. Cheng and E. S. Kuh "Module placement based on resistive network optimization" IEEE Trans. on CAD of IC's and Systems, vol. CAD-3, pp. 218-225, July 1984. [6] J. M. Kleinhans, G. Sigl and F. M. Johannes "GORDIAN : A new global optimization/rectangle dissection method for cell placement" Proc. ICCAD, pp. 506-509, 1988. [7] G. J. Wipfler, M. Wiesel and D. A. Mlynski "A combined force and cut algorithm for hierarchical VLSI layout" Proc. 19th DAC, pp. 671-676, 1982. [8] S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi "Optimization by simulated annealing" Science, vol. 220, pp. 671-680, May 1983. [9] C. Sechen and A. Sangiovanni-Vincentelli "TimberWolf 3.2 : A new standard cell placement and global routing package" Proc. 23rd DAC, pp. 432-439, June 1986. [10] R. H. J. M. Otten "Graphs in floor plan design" Int. J. Circuit Theory and Applications," vol. 16, pp. 622-629, 1988. [11] D. R. La Potin and S. W. Director "MASON : A global floorplanning approach for VLSI design" IEEE Trans. on CAD of IC's and systems, vol. CAD-5, pp. 477-489, 1986. [12] H. Onodera et. al. "Step by step placement strategies for building block layout" Proc. of ISCAS, pp. 921-926, 1989. [13] H. C. Ranke and F. M. Johannes "Macrocell placement by global optimization with uniform cell distribution" Proc. IFIP International Conference on VLSI, pp. 423-432, 1989.

[14] B. Preas "Benchmarks for cell-based layout systems" Proc. 24th DAC, pp. 319-320. 1987.


Floorplanning by Topological Constraint Reduction

G. Vijayan, R. S. Tsay IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY 10598

ABSTRACT We present a new approach to constraint-based floorplanning based on the removal of redundant constraints, and adjustment of aspect ratios of flexible blocks. References [1] A. V. Aho, J. E. Hopcroft, J. D. Ullman. Data Structures and Algorithms. Addison-Wesley, 1983. [2] S-K. Dong, J. Cong, and C. L. Liu "Constrained Floorplan Design for Flexible Blocks" Digest of International Conference on Computer-Aided Design, November 1989, pp. 488-491. [3] M. Mogaki, C. Miura, and H. Terai "Algorithm for Block Placement with Size Optimization Technique by the Linear Programming Method" Digest of International Conference on Computer-Aided Design, November 1987, pp. 80-83. [4] E. Rosenberg "Optimal Module Sizing in VLSI Floorplanning by Nonlinear Programming" Methods and Models of Operations Research, Vol. 33. pp. 131-143. [5] L. Stockmeyer "Optimal Orientations of Cells in Slicing Floorplan Designs" Information and Control, Vol. 57, pp. 91-101. [6] T-C. Wang, and D. F. Wong "An Optimal Algorithm for Floorplan Optimization" Proceedings of 27th ACM/IEEE Design Automation Conference, June 1990, pp. 180-186. [7] S. Wimer, I. Koren, and I. Cederbaum "Optimal Aspect Ratios of Building Blocks in VLSI" Proceedings of 25th ACM/IEEE Design Automation Conference, June 1988, pp. 66-72. [8] D. F. Wong, and C. L. Liu "A New Algorithm for Floorplan Design" Proceedings of 23th ACM/IEEE Design Automation Conference, June 1986, pp. 101-107.


Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi Approach

M.A. Styblinski Department of Electrical Engineering, Texas A&M University, College Station, TX 77843

ABSTRACT A relationship between yield optimization, deterministic minimax design, and the Taguchi "on-target" design with variability reduction is established. It is shown that all these and other design approaches can be combined into one coherent methodology, using the same statistical optimization algorithms and same generic gradient evaluation formulas. A specific choice is controlled by the selection of the generalized membership function w(·) of the acceptability region, and a sequence of the values of the smoothing parameter β. Moreover, any "intermediate" approach between the basic types introduced can be defined in a sense similar to the one used in Zadeh's fuzzy set theory. As a result, circuit quality can be optimized within the same basic methodology, using different design strategies and investigating different trade-offs, e.g., between the performance and yield. Test examples, as well as a practical CMOS circuit are investigated. Convolution smoothing techniques, and the Stochastic Approximation approach to statistical optimization are utilized. REFERENCES [1] J.J. Pignatiello, Jr. "An Overview of the Strategy and Tactics of Taguchi" IIE Transactions, vol. 20, Sept. 1988, pp. 247-254. [2] M.A. Styblinski "Statistical Design Centering Approach to Minimax Circuit Design" Proc. Int'l Symp. on Circuits and Systems, May 1989, Portland, Oregon, pp. 697-700. [3] R.Y. Rubinstein Simulation and the Monte Carlo Method. John Wiley & Sons, 1981. [4] L.A. Zadeh "Probability Measures of Fuzzy Events" J. Math. Anal. Appl., Vol. 23, pp. 421-427, 1968. [5] G. Taguchi and Y. Wu Introduction to Off-line Quality Control. Central Japan Quality Control Association, 1982. [6] R.N. Kackar "Off-line Quality Control, Parameter Design, and the Taguchi Method" Journal of Quality Technology, vol. 17, No.4, October 1985, pp. 176-221. [7] L.J. Opalski, M.A. Styblinski "Generalization of Yield Optimization Problem: Maximum Income Approach" IEEE Trans. on Comp. Aided Design of ICAS vol. CAD-5, No. 2, April 1986, pp. 346-360. [8] M.A. Styblinski and L.J. Opalski "Algorithms and Software Tools for IC yield Optimization Based on Fundamental Fabrication Parameters" IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 79-89, January 1986. [9] M.A. Styblinski and A. Ruszczynski "Stochastic Approximation Approach to Statistical Circuit Design" Electronics Letters, vol. 19, No. 8, pp. 300-302, 1983. [10] E. Wehrhahn and R. Spence "The Performance of Some Design Centering Methods" Proc. 1984 IEEE Int. Symp. Circuits Syst., Montreal, Canada, May 1984, pp. 1424-1438. [11] T.K. Yu, S.M. Kang, J. Sacks, and W.J. Welch "Parametric Yield Optimization of MOS Integrated Circuits by Statistical Modeling of Circuit Performances" Technical Report No. 27, Dept. of Statistics, University of Illinois, Champaign, Il 61820, July 1989.


Computing Parametric Yield Accurately and Efficiently

Linda Milor Department of EE, University of Maryland, College Park, MD 20742

Alberto Sangiovanni-Vincentelli

Department of EECS, University of California, Berkeley, CA 94720 An algorithm for computing parametric yield is presented. The algorithm uses statistical modeling techniques and takes advantage of incremental knowledge of the problem to reduce significantly the number of simulations needed. Polynomial regression is used to construct simple equations mapping parameters to measurements. These simple polynomial equations can then replace circuit simulations in the Monte Carlo algorithm for computing parametric yield. The algorithm differs from previous statistical modeling algorithms using polynomial regression for three major reasons. First, the random error that is postulated in polynomial regression equations is taken into account when computing parametric yield. Second, the variance of the yield is computed. And third, the algorithm is fully automated. Therefore a direct comparison with Monte Carlo methods can be made. Examples indicate that significant speed-ups can be attained over Monte Carlo methods for a large class of problems. References [1] W. Maly "Modeling of lithography related yield losses for CAD of VLSI circuits" IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 166-177, July 1985. [2] D.M.H. Walker. Yield simulation for integrated circuits. Kluwer Academic Publisher, Norwell, Massachusetts, 1987. [3] P. Yang, D. Hocevar, P. Cox, C. Machala, and P. Chatterjee "An integrated and efficient approach for MOS VLSI statistical circuit design" IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 5-14, Jan. 1986. [4] S. Liu and K. Singhal "A statistical model for MOSFETS" Proc. ICCAD, Santa Clara, pp. 78-80, 1985. [5] J.M. Hammersley and D.C. Handscomb Monte Carlo Methods. Methuen and Co. Ltd., London, 1964. [6] D.E. Hocevar, P.F. Cox, and P. Yang "Parametric yield optimization of MOS circuit blocks" IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 645-658, June 1988. [7] L. Milor and A. Sangiovanni-Vincentelli "Optimal test set design for analog circuits" Proc. ICCAD, 1990. [8] A.R. Alvarez, B.L. Abdi, D.L. Young, H.D. Weed, J. Teplik, and E.R. Herald "Application of statistical design and response surface methods to computer-aided VLSI device design" IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 272-288, Feb. 1988. [9] K.K. Low and S.W. Director "An efficient methodology for building macromodels of IC fabrication processes" IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 1299-1313, Dec. 1989. [10] T.K. Yu, S.M. Kang, I.N. Hajj, and T.N. Trick "Statistical performance modeling and parametric yield estimation of MOS VLSI" IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1013-1022, Nov. 1987. [11] T.K. Yu, S.M. Kang, J. Sacks, and W.J. Welch "Parametric yield optimization of MOS integrated circuits by statistical modeling of circuit performances" Technical Report No. 27, Dept. of Statistics, University of Illinois, Champaign, July 1989. [12] J. Sacks, W.J. Welch, T.J. Mitchell, and H.P. Wynn "Design and analysis of computer experiments" Statistical Science Nov. 1989. [13] G.E.P. Box, W.G. Hunter, and J.S. Hunter. Statistics for experimenters. John Wiley and Sons, New York, 1978.

[14] N.R. Draper and H. Smith. Applied Regression Analysis. John Wiley and Sons, New York, 1981. [15] H.Y. Koh, C.H. Sequin, and P.R. Gray "Automatic synthesis of operational amplifiers based on analytic circuit models" Proc. ICCAD, Santa Clara, pp. 502-505, 1987.


Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients

Peter Feldmann, Stephen W. Director Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania Abstract In this paper we describe a method for estimating the yield and yield gradient based on a priori geometric approximation of the acceptability region in the disturbance space. Circuit performance macromodeling is used to construct the acceptability region approximation. While yield evaluation can be carried out in either the performance space or parameter space, we show that for monolithic integrated circuits, the gradient of yield can only be estimated accurately in the disturbance space. References [1] K. Singhal and J.F. Pinel. Statistical design centering and tolerancing using parametric sampling. IEEE Transactions on Circuits and Systems, CAS-28(7):692-701, July 1981. [2] S.R. Nassif, A.J. Strojwas, and S.W. Director. A methodology for worst-case analysis of integrated circuits. IEEE Transactions on Computer-Aided Design, CAD-5(1):104-113, January 1986. [3] M.A. Styblinski and L.J. Opalski. Algorithms and software tools of IC yield optimization based on fundamental fabrication parameters. IEEE Transaction on Computer-Aided Design, CAD-5(1):79-89, January 1986. [4] P. Cox, P. Yang, S.S. Mahant-Shetti, and P. Chatterjee. Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits. IEEE Transactions on Electron Devices, ED-32(2):471-478, February 1985. [5] K.J. Antreich and R.K. Koblitz. Design centering by yield prediction. IEEE Transactions on Circuits and Systems, CAS-29(2):88-96, February 1982. [6] D.E. Hocevar, P.F. Cox, and P. Yang. Parametric yield optimization for MOS circuit blocks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7(6):645-58, June 1988. [7] M.A. Styblinski and J.C. Zhang. Orthogonal array approach to gradient based yield optimization. In 1990 IEEE International Symposium on Circuits and Systems. Proceedings, 1990. [8] W.J. Welch, Tat-Kwan Yu, Sung Mo Kang, and J. Sacks. Computer experiments for quality control by parameter design. Journal of Quality Technology, 22(1):15-22, January 1990.


A Unified Framework for the Formal Verification of Sequential Circuits

Olivier Coudert, Jean Christophe Madre Bull Research Center, 68, Route de Versailles 78430 Louveciennes FRANCE

Introduction Hardware description languages (HDLs) dramatically change the way circuit designers work. These languages can be used to describe circuits at a very high level of abstraction, which allows the designers to specify the behavior of a circuit before realizing it. The validation of these specifications is currently done by executing them, which is very costly [2]. This cost motivates the research [3] [5] [7] [10] done on the automatic verification of temporal properties of finite state machines. Once the design of the circuit is done, the problem is to verify that the resulting circuit is correct with respect to its specification. Until recently, this verification was done by simulating the circuit and its specification on the same input sequences and by comparing their output sequences. This verification method is very costly and incomplete because of the large number of input sequences to consider [2]. This paper presents a unified framework for the verification of synchronous circuits. Within this framework the two verification tasks presented above can be automatically performed using algorithms based on the same concepts. The first idea is to manipulate sets of states and ets of transitions instead of individual states and individual transitions. The second idea is to represent these sets by Boolean functions and to replace operations on sets with operations on Boolean functions. Part 2 of the paper defines the two problems addressed here, and then it presents the verification algorithms. It shows that these algorithms use the standard set operations in addition to two specific operations called "Pre" and "Img". Part 3 briefly explains why the basic set operations are very efficiently performed when sets are denoted by the typed decision graphs of their characteristic functions. Part 4 presents the new Boolean operators "Constrain" and "Restrict", and the function "Expand" that support efficiently the "Img" and "Pre" operations. Part 5 gives experimental results and discusses them. References [1] J. P. Billon "Perfect Normal Forms for Discrete Functions" BULL Research Report No87019, March 1987. [2] J. P. Billon, J. C. Madre "Original Concepts of PRIAM, an Industrial Tool for Efficient Formal Verification of Combinational Circuits" in The Fusion of Hardware Design and Verification, G. J. Milne Editor, North Holland, 1988. [3] S. Bose, A. Fisher "Automatic Verification of Synchronous Circuits Using Symbolic Logic Simulation and Temporal Logic" in Proc. of the IFIP International Workshop, Applied Formal Methods for Correct VLSI Design, Leuven, November 1989. [4] R. E. Bryant "Graph-based Algorithms for Boolean Functions Manipulation" IEEE Transactions on Computers, Vol C35, 1986.

[5] S. Burch, E. M. Clarke, K. L. McMillan "Symbolic Model Checking: 10[sup.20] States and Beyond" in Proc. of LICS, 1990. [6] H. Cho, G. Hachtel, S. W. Jeong, B. Plessier, E. Schwarz, F. Somenzi "ATPG Aspect of FSM Verification" in Proc. of ICCAD, Santa-Clara, U.S.A., June 1990. [7] E. M. Clarke, O. Grumbreg "Research on Automatic Verification of Finite-State Concurrent Systems" Annual Revue Computing Science, vol. 2, pp 269-290, 1987. [8] O. Coudert, C. Berthet, J. C. Madre "Verification of Synchronous Sequential Machines Based on Symbolic Execution" in Proc. of the Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France, June 1989. [9] O. Coudert, C. Berthet, J. C. Madre "Verification of Sequential Machines Using Boolean Functional Vectors" in Proc. of the IFIP International Workshop, Applied formal Methods for Correct VLSI Design, Leuven, November 1989. [10] O. Coudert, J. C. Madre, C. Berthet "Verifying Temporal Properties of Sequential Machines without Building their State Diagrams" to appear in Proc. of the Workshop on Computer Aided Verification, Rutgers, U.S.A., June 1990.


Implicit State Enumeration of Finite State Machines using BDD's

Herve J. Touati, Hamid Savoj, Bill Lin Robert K. Brayton, Alberto Sangiovanni-Vincentelli

Electrical Engineering and Computer Sciences, Department University of California, Berkeley, CA 94720, USA

Abstract Coudert et al. have proposed in [4] an efficient method to compute the set of reachable states of a sequential finite state machine using BDD's. This technique can handle larger finite state machines than previously possible and has a wide range of applications in sequential synthesis, testing and verification. At the heart of this method is an algorithm that computes the range of a set of Boolean functions under a restricted domain. Coudert et al. originally proposed a simpler and more general algorithm for range computation that was based on relations, but dismissed it as impractical for all but the simplest examples. We propose a new approach based on relations that outperforms Coudert's algorithm with the additional advantage of simplicity and wider applicability. References [1] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: Multiple-Level Logic Optimization System. In IEEE Transactions on Computer Aided Design of Circuit and System, pages 1062-1081, November 1987. [2] R. E. Bryant. Graph Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677-691, August 1986. [3] J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential Circuit Verification Using Symbolic Model Checking. In 27th ACM/IEEE Design Automation Conference, Orlando, June 1990. [4] O. Coudert, C. Berthet, and J. C. Madre. Verification of Sequential Machines Based on Symbolic Execution. In Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, Grenoble, France, 1989. [5] O. Coudert, J. C. Madre, and C. Berthet. Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams. In Workshop on Computer-Aided Verification, Rutgers, June 1990. [6] A. Ghosh, S. Devadas, and A. R. Newton. Test Generation for Highly Sequential Circuits. In IEEE International Conference on Computer-Aided Design, pages 362-365, November 1989. [7] S. Malik, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic Verification Using Binary Decision diagrams in a Logic Synthesis Environments. In IEEE International Conference on Computer-Aided Design, pages 6-9, November 1988. [8] P. McGeer. On the Interaction of Functional and Timing Behavior of Combinational Logic Circuits. PhD thesis, U.C. Berkeley, November 1989. [9] R. Rudell. private communication, 1990.


ATPG Aspects of FSM Verification

Hyunwoo Cho, Gary Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric Schwarz, Fabio Somenzi

University of Colorado at Boulder, Department of Electrical and Computer Engineering, Boulder, Colorado 80309

Abstract We present algorithms for FSM verification and image computation which improve on [3], giving 1-4 orders of magnitude speedup. New features include: Primary input splitting—this PODEM feature enlarges the search space but shortens search due to implications. Identical subtree recombination--effective for iterative networks (e.g., serial multiplers). Free-variable recognition--prevents unbalanced bipartitioning tree in tautological subspaces. Reached set pruning--significant when the image contains large numbers of previously reached states. References [1] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of the 27th Design Automation Conference, pages 40-45, June 1990. [2] F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In Proceedings of the 1989 International Symposium on Circuits and Systems, pages 1929-1934, Portland, OR, May 1989. [3] O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines using boolean functional vectors. In L. Claesen, editor, Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, Leuven, Belgium, November 1989. [4] O. Coudert, C. Berthet, and J. C. Madre. Formal boolean manipulations for the verification of sequential machines. In Proceedings of the 1st European Design Automation Conference, pages 57-61, March 1990. [5] A. Ghosh, S. Devadas, and A. R. Newton. Test generation for highly sequential circuits. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 362-365, November 1989. [6] P. Goel. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Transactions on Computers, C-30(3):215-222, 1981. [7] P. N. Lowenstein. Formal verification of state-machines using higher-order logic. In IEEE Internatinal Conference on Computer Design, pages 204-207, Cambridge, MA, October 1989. [8] H.-K. T. Ma, S. Devadas, and A. R. Newton. On the verification of finite state machines at differing levels of abstraction. IEEE Transactions on CAD, Vol-7:713-722, June 1988. [9] H.-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli. Test generation for sequential circuits. IEEE Transactions on CAD, Vol-7:1081-1093, October 1988. [10] C. Pixley. A computational theory and implementation of sequential hardware equivalence. IN R. Kurshan and E. Clarke, editors, Proc. CAV Workshop (also DIMACS Tech. Report 90-31), Rutgers University, NJ, June 1990.


FOLM-planner : A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-Of-Gates) Type Gate Arrays

Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi ULSI Research Center, Toshiba Corporation, Kawasaki 210, JAPAN

Abstract A new floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM-planner is based on a "Frame Over-Lapping floorplan Model" (FOLM), which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. To accomplish these objectives, FOLM-planner uses a newly developed force directed method for frame reshaping as well as moving. Experimental results have shown that FOLM layout can shorten the net length inside a frame without the total net length becoming longer than by conventional layout models. References [1] A. Hui, A. Wong, C. Dell'oca, D. Wong and R. Szero "A 4.1k gates double metal HCMOS sea of gates array" IEEE Proc. of CICC, pp 15-17. 1985. [2] N. R. Quinn, Jr. and M. A. Breuer "A force directed component placement procedure for printed circuit boards" IEEE Trans. Circuits and Syst., CAS-26, pp 377-388. Jun. 1979. [3] W. Dai and E. S. Kuh "Hierarchical floor planning for building block layout" Proc. of ICCAD-86, pp. 454-457. 1986. [4] W. Dai, B. Eschermann, E. S. Kuh, M. Pedram "Hierarchical placement and floorplanning in BEAR" IEEE Trans. Computer-Aided Design, pp 1335-1349. Dec. 1989. [5] G.J. Wipfler, M. Wiesel and D.A. Mlynski "A combined force and cut algorithm for hierarchical VLSI layout" Proc. of 19th DAC, pp. 671-677. 1982. [6] R.H.J.M. Otten "Automatic floorplan design" Proc. of 19th DAC, pp 261-267. 1983. [7] R.H.J.M. Otten "Efficient floorplan optimization" IEEE ICCD, pp. 499-502. 1983. [8] D. F. Wong and C. L. Liu "A new algorithm for floorplan design" Proc. of 23rd DAC, pp 101-107. 1986. [9] M. Murakata, K. Koura, M. Igarashi and T. Mitsuhashi "A placement algorithm for sea-of-gate gate array by the goal programming method" Research Report of Design Automation Study Group, Information Processing Society of Japan, 90-DA-51. 1990, in Japanese.


Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists

Allen C. H. Wu, Daniel D. Gajski Dept. of Information and Computer Science University of California at Irvine, Irvine, CA. 92717

Abstract Most of today's integrated circuits are described and documented using hierarchical netlists. In addition to gates, latches, and flip-flops, these netlists include sliceable register-transfer components such as registers, counters, adders, ALUs, shifters, register files, and multiplexers. In this paper, we present a new sliced-layout architecture to alleviate the problems of the general bit-sliced layouts. We also describe partitioning algorithms that are used to generate the floorplan for this new layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between logic blocks. This approach improves the overall area utilization and minimizes the total wire length. References [1] Wu, A. C. H. and Gajski, D. "A New Partitioning Approach for Layout Synthesis from Register-Transfer Netlists" Technical Report \#90-10, University of California at Irvine, 1990. [2] Dirkes Lagnese, E., and Thomas, D. E. "Architectural Partitioning for System Level Design" Proc. 26th DAC, pp. 62-67, 1989. [3] Kernighan, B. W. and Lin, S. "An Efficient Heuristic Procedure for Partitioning Graphs" Bell System Technical Journal, Vol. 49, pp. 291-308, (2), 1970. [4] Dunlop, A. E. and Kernighan, B. W. "A procedure for Placement of Standard-Cell VLSI Circuits" IEEE Trans. Computer-Aided Design Vol. CAD-4, No. 1, pp. 92-98, 1985. [5] Wu, A. C. H., Chen, G. D. and Gajski, D. "Silicon Compilation from Register-Transfer Schematics" Proc. ISCAS, pp. 2576-2579, 1990. [6] Armstrong, J. Chip Level Modeling with VHDL. Prentice-Hall, 1989. [7] Siewiorek, D. P., Bell, C. G., and Newell, A. Computer Structures: Principles and Examples McGraw-Hill, 1982. [8] Lis, J. S. and Gajski, D. "Synthesis from VHDL" Proc. ICCD, pp. 378-381, 1988.


A Robust Framework For Hierarchical Floorplanning With Integrated Global Wiring

Thomas Lengauer, Rolf Muller

University of Paderborn, Paderborn, West Germany Abstract Recently, floorplanning procedures that are based on circuit partitioning have become quite popular. Their main advantages are that they are able to handle flexible cells easily and that they allow for a straightforward incorporation of global wiring. At Paderborn, we have implemented a floorplanning system that is based on circuit partitioning and incorporates hierarchical global wiring. Besides unifying several existing ideas in floorplanning, the system introduces the following new components: (1) A novel and more accurate estimate of wiring area during the floorplan sizing process and (2) a systematic optimization procedure during the selection of suitable floorplan patterns in the top-down phase that integrates floorplanning and hierarchical wiring. Experiments with the system prove the feasibility of the approach. References [1] M. Burstein and S. J. Hong. Hierarchical VLSI layout: Simultaneous wiring and placement. In F. Anceau and E. J. Aas, editors, Proceedings of VLSI'83, pages 45-60. Elsevier Science Publishers B.V., Amsterdam, The Netherlands, 1983. [2] M. Burstein and R. Pelavin. Hierarchical wire routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-2(4):223-234, 1983. [3] W. W.-M. Dai, B. Eschermann, E. S. Kuh, and M. Pedram. Hierarchical placement and floorplanning in BEAR. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-8(12):1335-1349, 1989. [4] W. W.-M. Dai and E. S. Kuh. Simultaneous floorplanning and global routing for hierarchical building block layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(5):828-837, 1987. [5] J. Heistermann and T. Lengauer. The efficient solution of integer programs for hierarchical global routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. to appear. [6] M. A. B. Jackson and E. S. Kuh. Performance-driven placement of cell based IC's. In Proceedings of the 26th Design Automation Conference, pages 370-375. ACM/IEEE, 1989. [7] D. Kludzeweit. Vorplazierung von Moduln beim Floorplanning basierend auf Partitioning. Diploma Thesis, Department of Mathematics and Computer Science, University of Paderborn, Paderborn, West Germany, 1990. [8] D. P. La Potin and S. W. Director. Mason: A global floorplanning approach for VLSI design. IEEE Transactions on CAD of Integrated Circuits and Systems, CAD-5(4):477-489, 1986. [9] U. Lauther. Top down hierarchical global routing for channelless gate arrays based on linear assignment. In C. H. Sequin, editor, Proceedings of VLSI'87, pages 141-151. Elsevier Science Publishers B.V., Amsterdam, The Netherlands, 1987. [10] T. Lengauer. Combinatorial Algorithms for Integrated Circuit Layout. Teubner-Wiley Series of Applicable Theory in Computer Science. John Wiley & Sons, New York, 1990. [11] T. Lengauer and R. Muller. The complexity of floorplanning based on binary circuit partitions. Technical Report 46, Department of Mathematics and Computer Science, University of Paderborn, Paderborn, West Germany, 1988. [12] W. K. Luk, P. Sipila, M. Tamminen, D. Tang, L. S. Woo, and C. K. Wong. A hierarchical global wiring algorithm for custom chip design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(4):518-533, 1987.

[13] M. Marek-Sadowska. Route planner for custom chip design. In Proceedings of the International Conference on Computer-Aided Design, pages 246-249. IEEE, 1986. [14] M. Marek-Sadowska and P. S. Lin. Timing driven placement. In Proceedings of the International Conference on Computer-Aided Design, pages 94-97. IEEE, 1989. [15] R. Muller. Hierarchisches Floorplanning mit integrierter globaler Verdrahtung. PhD thesis, Department of Mathematics and Computer Science, University of Paderborn, 1990. [16] R. H. J. M. Otten. Efficient floorplan optimization. In Proceedings of the International Conference on Computer Design: VLSI in Computers, pages 499-502. IEEE, 1983. [17] C. Sechen. Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing. In Proceedings of the 25th Design Automation Conference, pages 73-80. ACM/IEEE, 1988. [18] L. Stockmeyer. Optimal orientations of cells in slicing floorplan design. Information and Control, 57:91-101, 1983. [19] T.-C. Wang and D. F. Wong. An optimal algorithm for floorplan area optimization. In Proceedings of the 27th Design Automation Conference, pages 180-186. ACM/IEEE, 1990. [20] E. Wanke. PLEXUS: a system for implementing hierarchical graph algorithms. In R. Cori and M. Wirsing, editors, Proceedings of the 5th Annual Symposium on Theoretical Aspects of Computing, pages 403-404, New York, 1988. Springer Lecture Notes in Computer Science, No. 294, Springer Verlag. [21] G. Zimmermann. Top-down design of digital systems. In E. Horbst, editor, Advances in CAD for VLSI, Volume 2: Logic Design and Simulation, pages 185-206. Nort-Holland, New York, 1986. [22] G. Zimmermann. A new area and shape function estimation technique for VLSI layouts. In Proceedings of the 25th Design Automation Conference, pages 60-65. ACM/IEEE, 1988.


GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design

Alexander Herrigel Hagelin-Cryptos Crypto AG, Staff Scientist, Research & Development, P.O. Box 474, CH-6301 Zug,

Switzerland Abstract A new floorplanning method for the macrocell layout style is presented. The floorplan state space is characterized by an equivalence relation to apply efficient solution techniques. A new pseudo-polynomial area optimization algorithm is proposed that derives from a given hierarchical floorplan tree the optimal slicing tree. The order of this floorplan tree is at least 2 and at most 5. Extensions of this approach to cover non-slicing floorplans are also described. Since floorplanning and routing are interdependent tasks, an improved dynamic updating scheme is proposed to consider interconnect space around each cell during the floorplan assembly. The method has been successfully applied to an industrial design with about 260000 transistors. References [1] A. Herrigel "GRCA: A Global Approach for Floorplanning Synthesis" in Intl. Workshop on Layout Synthesis, Research Triangle Park, NC, May 1990. [2] D. La Potin and S. Director "Mason: A global floorplanning approach for VLSI design" Trans. on CAD, vol. 5, pp. 477-489, 1986. [3] G. Zimmermann "A new area and shape function estimation Technique for VLSI Layouts" in DAC, vol. 25, pp. 60-65, 1988. [4] W. Dai, B. Eschermann, E. Kuh, and M. Pedram "Hierarchical placement and floorplanning in BEAR" Trans. on CAD, vol. 8, pp. 1335-1349, 1989. [5] R. Otten "Efficient floorplan optimization" in ICCD, pp. 499-502, 1984. [6] A. Herrigel New approaches to physical synthesis in VLSI macrocell design. PhD thesis, Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, 1990. [7] D. Wong and P. Sakhamuri "Efficient floorplan area optimization" in DAC, vol. 26, pp. 586-589, 1989. [8] M. Hanan "On Steiner's problem with rectilinear distance" SIAM J. on Applied Mathematics Analysis, vol. 14, pp. 255-265, 1966. [9] A. Herrigel and W. Fichtner "An analytic optimization technique for placement of macro-cells" in DAC, vol. 26, 1989. [10] H. Brady "An approach to topological pin assignment" in Trans. on CAD, vol. 3, pp. 250-255, 1984. [11] B. Eschermann, W. Dai, E. Kuh, and M. Pedram "Hierarchical placement for macrocells: A "meet in the middle" approach" in ICCAD, pp. 460-463, 1988. [12] N. Chen, C. Hsu, E. Kuh, C. Chen, and M. Takahshi "BBL: A building block layout system for custom chip design" in ICCAD, pp. 40-41, 1983. [13] M. Beardslee, J. Burns, A. Casotto, M. Igusa, F. Romeo, and A. Sangiovanni-Vincentelli "Mosaico: An integrated macrocell layout system" in International Workshop on Placement and Routing, Research Triangle Park, North Carolina, 1988. [14] D. Smith, R. Putatunda, M. Stebnisky, and P. Patent "Vital: A macro, standard cell and gate array chip compiler" in International Workshop on Placement and Routing, Research Triangle Park, North Carolina, 1988. [15] P. Groeneveld and H. Cai "The Delft placement and routing system" in International Workshop on Placement and Routing, Research Triangle Park, North Carolina, 1988. [16] L. Sha and T. Blank "ATLAS: A technique for layout using analytic shapes" in ICCAD, pp. 84-87, 1987.

[17] P. Beadle "Integrating VLSI design synthesis tools" Tech. Rep. 88/22, Integrated Systems Laboratory, 1988. [18] N. Wehn, M. Glaser, H. Ebert, and C. Thieleke "A floorplanner for hierarchical macrocell design based on simulated annealing" tech. rep., FG Halbleiterschaltungstechnik, Technische Hochschule Darmstadt, 1988. [19] J. Kleinhans, G. Sigl, and F. Johannes "GORDIAN: A new global optimization / rectangle dissection method for cell placement" in ICCAD, pp. 506-509, 1988.


Mixed-Mode Incremental Simulation and Concurrent Fault Simulation

Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801

ABSTRACT In this paper, we describe our efforts in applying mixed-mode simulation techniques to two other areas of research. In incremental simulation, we present techniques to perform fast incremental circuit simulation based on a modified incremental-in-space approach and event-driven techniques. In fault simulation, we present a mixed-mode fault simulator that allows the user to specify any type of electrical level fault at the transistor level, as opposed to one of the simple stuck-at faults used in logic simulators. The program performs fault simulation, using mixed-mode techniques, and provides the fault coverage of a set of input patterns. To improve efficiency, concurrent fault simulation with a table look-up scheme is used. We demonstrate the merits of both algorithms with simulation results that show significant speed-ups over standard approaches. REFERENCES [1] R. A. Saleh and A. R. Newton. Mixed-Mode Simulation. Kluwer Academic Publishers, June 1990. [2] E. L. Acuna, J. P. Dervenis, A. J. Pagones, F. L. Yang, and R. A. Saleh "Simulation Techniques for Mixed Analog/Digital Circuits" IEEE Journal of Solid-State Circ., April 1990. [3] S. Y. Hwang, T. Blank, and K. Choi "Fast Functional Simulation: An Incremental Approach" IEEE Trans. on CAD, July 1988. [4] K. Choi, S. Y. Hwang, and T. Blank "Incremental-in-Time Algorithm for Digital Simulation" Proc. of 25th Design Automation Conf., June 1988. [5] R. L. Wadsack "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits" Bell Sys. Tech. Journal, May-June 1978. [6] C.-Y. Lo, H. N. Nham, and A. K. Bose "Algorithms for an Advanced Fault Simulation System in MOTIS" IEEE Trans. on CAD, March 1987. [7] G. Choi, R. K. Iyer, and R. A. Saleh "A Fault Behavior Model for an Avionic Microprocessor: A Case Study" Int. Work Conf. on Dependable Computing for Critical Applications, Aug. 1989. [8] M. A. Breuer and A. D. Friedman. Diagnosis and Reliable Design of Digital Systems. Computer Science Press, 1976.


Incorporation of Inductors in Piecewise Approximate Circuit Simulation

Chandramouli Visweswariah IBM T. J. Watson Research Center, Yorktown Heights, NY 10598

Peter Feldmann, Ronald A. Rohrer

Department of ECE, Carnegie Mellon University, Pittsburgh, PA 15213 Abstract Piecewise approximate circuit simulation has proven to be an efficient method for the nonlinear transient simulation of integrated circuits. The technique assumes all branch voltages to be represented by functions that are piecewise linear in time and branch currents that are piecewise constant in time, an assumption that is well suited to capacitors but contradictory to the basic law of inductors. However, inductive effects are important at the board level and are becoming increasingly important even in integrated circuit simulation. This paper describes the theory and the implementation of the accommodation of inductors in such a piecewise approximate simulation scheme, based on the conservation of flux and energy. References [1] C-F. Chen, C-Y. Lo, H. N. Nham, and P. Subramaniam. The second generation MOTIS mixed-mode simulator. Proc. 21st Design Automation Conference, pages 10-16, 1984. [2] L. O. Chua and P. M. Lin. Computer-aided analysis of electronic circuits : algorithms and computational techniques. Prentice Hall, 1975. [3] M. Costa, T. K. Sarkar, and B. J. Strait. On radiation from printed circuit boards. IEEE International Symposium on Electromagnetic Compatibility, pages 246-249, 1981. [4] J. J. Ebers and J. L. Moll. Large signal behavior of junction transistors. Proceedings of IRE, 42, December 1954. [5] H. J. DeMan et al. DIANA: mixed mode simulator with a hardware description language for hierarchical design of VLSI. Proc. IEEE ICCD, October 1980. Rye, NY. [6] Y. H. Kim, J. E. Kleckner, R. A. Saleh, and A. R. Newton. Electrical-logic simulation. IEEE International Conference on Computer-Aided Design (ICCAD), pages 7-10, November 1984. [7] E. S. Kuh and R. A. Rohrer. The state variable approach to network analysis. Proc. IEEE, 53:672-686, July 1965. [8] A. E. Ruehli. Survey of computer-aided electrical analysis of integrated circuit interconnections. IBM Journal of Research and Development, 23(6):626-639, November 1979. [9] L. M. Vidigal, S. R. Nassif, and S. W. Director. CINNAMON: coupled integration and nodal analysis of MOS networks. Proc. 1986 Design Automation Conference, pages 179-185, June 1986. [10] C. Visweswariah. Piecewise approximate circuit simulation. Technical Report CMUCAD-89-28, Carnegie Mellon University, May 1989. [11] C. Visweswariah and R. A. Rohrer. SPECS2: an integrated circuit timing simulator. IEEE International Conference on Computer-Aided Design (ICCAD), pages 94-97, November 1987. [12] C. Visweswariah and R. A. Rohrer. Piecewise approximate circuit simulation. IEEE International Conference on Computer-Aided Design (ICCAD), November 1989.


Analysis of VLSI Multiconductor Systems by Bi-Level Waveform Relaxation

Rui Wang, Omar Wing Department of Electrical Engineering, Center for Telecommunication Researchs, Columbia University,

New York, NY 10027

Abstract A new algorithm to compute the transient response of a coupled, dispersive multiconductor system terminated in non-linear loads such as transistors is developed. The characterization of the multiconductor system is obtained from fullwave analysis based on the Spectral Domain Approach, and it is suitable for circuit simulation. The transient response of such a system is computed by a Bi-level Waveform Relaxation method. The solution process consists of two steps. One to obtain a time domain solution at the input and output interfaces by Local Waveform Relaxation, and second to transform the waveforms into the frequency domain and obtain the necessary updates for the next Global Relaxation step. The method allows the interconnects to be separated from the rest of the system so that both the nonlinear termination circuit and the multiconductor system can be analyzed in the most efficient way. The method has been applied to multiconductor systems terminated in MOS, ECL, and GaAs transistors and it is shown that reflections and couplings can create logic errors in the system. The program that implements the algorithm is written in C. References [1] F. H. Branin, Jr. "Transient analysis of lossless transmission lines" Proc. IEEE, Vol. 55, pp. 2012-2013, Nov. 1967. [2] F. Y., Chang "Transient analysis of lossless transmission lines in a nonhomogeneous dielectric medium" IEEE Trans. Microwave Theory Tech., Vol. MTT-18, pp. 616-626, Sept. 1970. [3] A. R. Djordjevic, T. K. Sarkar, and R. F. Harrington "Analysis of lossy transmission lines with arbitrary nonlinear terminal networks" IEEE Trans. Microwave Theory Tech., Vol. MTT-34, pp. 660-666, June 1986. [4] J. E. Schutt-Aine and R. Mittra "Nonlinear transient analysis of coupled transmission lines" Trans. CAS, Vol. CAS-36, no. 7, pp. 959-967, July 1989. [5] F. Y. Chang "The generalized method of characteristic for waveform relaxation analysis of lossy coupled transmission lines" IEEE Trans. Microwave Theory Tech., Vol. MTT-37, no. 12, pp. 2028-2038, Dec. 1989. [6] T. Itoh and R. Mittra "Spectral-domain approach for calculating the dispersion characteristics of microstrip lines" IEEE Trans. Microwave Theory Tech., Vol. MTT-21, pp. 496-499, 1973. [7] R. Wang and O. Wing "Transient analysis of dispersive multiconductor systems by bi-level waveform relaxation" To be submitted to IEEE Trans. on CAD. [8] R. Wang "Computation of transient response of dispersive multiconductor systems by by-level waveform relaxation" Ph.D Thesis, Columbia University, New York, 1990. [9] J. K. White and A. L. Sangiovanni-Vincentelli Relaxation Technique for the Simulation of VLSI Circuits" Kluwer Academic Publishers, 1987.


Measuring Error Propagation in Waveform Relaxation Algorithms

Charles Zukowski, George Gristede Dept. of Elec. Eng., Columbia University, New York, NY 10027-6699

Albert Ruehli

IBM Watson Research Cen., P.O. Box 218 Yorktown Hgts., NY 10598 Abstract An analysis tool is introduced that measures subcircuit coupling and error attenuation in waveform relaxation (WR) circuit simulation algorithms with full dimensionality. Unlike current methods that use heuristics to calculate scalar "gains", this method captures all the effects of error attenuation over time and space. An example is provided of how this technique can be used to study the performance of various partitions, schedules, and WR algorithms on a wide range of technologies, including BiCMOS. References [1] E. Lelarasmee, A. E. Ruehli, A. L. Sangiovanni-Vincentelli "The Waveform Relaxation Method for Time-Domain Analysis of Large-Scale ICs" IEEE Trans. CAD, CAD-1(3), July 1982, pp. 131-145. [2] A. Vachoux, C.H. Carlin "Implementation of Decomposition and Scheduling Process for Waveform Relaxation Simulation" European Circuits Conf, ECCTD, Prague, Sept. 1985, pp. 54-57. [3] J. White, A. Sangiovanni-Vincentelli "Relax 2.1 - A WR Based Circuit Simulation Program" Proc. Int. Custom IC Conf., Rochester, NY, June 1984. [4] D. Dumlugol, P. Odent, J. Cocks, and H. DeMan "Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and its acceleration on Parallel Computers" IEEE Trans. on CAD, Vol. CAD-6, No. 6, Nov. 1987, pp. 992-1005. [5] B. Ingenbleek, B, Klassen, K-L Papp "SISAL: Ein Programm zur Transienten-analyse integrierter MOS-Schaltungen" GMD-Studie Nr. 110, Eis Workshop, Ges. Mathematik u. Datenverarbeitung MBH, Bonn, Germany, March, 1986. [6] T. Cockerill, H.Y. Hsieh, J. LeBlanc, D. Ostapko, A.E. Ruehli, J.K. White "Toggle: A circuit Analyzer for MOSFET VLSI" IEEE Proc. 1st Int. Conf. on VLSI & Comp, Comp Euro'87, May 87, pp. 224-8. [7] S. Mattison "CONCISE: A Concurrent Circuit Simulation Program" PhD Dissertation, Dept. of Appl. Elec., Univ. of Lund, Sweden, Aug. 1986. [8] P. Odent, L. Claesen, H. DeMan "Acceleration of Relaxation Based Circuit Simulation Using a Multi-processor System" to appear in IEEE Trans. on CAD. [9] J. K. White, A. Sangiovanni-Vincentelli. Relaxation Techniques for the Simulation of VLSI Circuits. Kluwer Pub., Boston, 1986. [10] P. Debefve, F. Odeh, A. Ruehli. Circuit Analysis, Simulation and Design. A. Ruehli, Ed., Elsevier, North Holland, Amsterdam, 1987. [11] A. E. Ruehli, A. Sangiovanni-Vincentelli, G. Rabbat "Time Analysis of Larger Scale Circuits Containing Oneway Macromodels" IEEE Trans. on CAS, Vol. CAS-29, March 1982, pp. 185-191. [12] R. E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Trans. on Comp., vol. C-33, Feb. 1984, pp. 160-177. [13] A. J.E. Kleckner. Advanced Mixed-Mode Simutation Techniques. ERL Rept., UC-Berkeley, No. UCB/ERL/M84/48, June 1984. [14] J. White and A. Sangiovanni-Vincentelli "Partitioning Algorithms and Parallel Implementations of Waveform Relaxation Algorithms for Circuit Simulation" IEEE Proc. Int. Symp. on Circuits and Systems, ISCAS, Kyoto, Japan, June 1985, pp. 1069-1072. [15] G. Marong and A. Sangiovanni-Vincentelli "Waveform Relaxation & Dynamic Partitioning for the Transient Simulation of Large Scale Bipolar Circuits" ICCAD85, pp. 32-34.

[16] P. Saviz & O. Wing "Dynamic Circuit Restructuring for Hierarchical Waveform Relaxation" ISCAS90, pp. 519-522. [17] Y. H. Kim, J. E. Kleckner, R. Saleh, A. R. Newton "Electrical-Logic Simulation" ICCAD84, pp. 7-9. [18] C. Zukowski. The Bounding Approach to VLSI Circuit Simulation. Kluwer Pub., Boston, 1986. [19] D. Erdman & D. Rose "A Newton Waveform Relaxation Algorithm for Circuit Simulation" CCAD89, pp. 404-407. [20] R. DeCarlo. Linear Systems: A State Variable Approach with Numerical Implementation. Prentice Hall, New Jersey, 1989.


Extraction of Functional Information from Combinational Circuits

M. Ohmura, H. Yasuura, K. Tamaru Department of Electronics, Kyoto University, Kyoto 606, JAPAN

ABSTRACT We propose a technique of functional information extraction, which is the transformation of design descriptions from logic circuit level to functional level. It will be an important technology for design verification as circuit extraction from layout design. We have developed functional information extraction system FINES, which can deal with both logic functions and arithmetic functions. Our technique has paid attention to characteristics of functions, so we can perform function extraction independent of circuit structures. References [1] T.G. Szymanski and C.J. Van Wyk "Layout Analysis and Verification" Edited by B.Preas and M. Lorenzetti: Physical Design Automation of VLSI Systems, The Benjamin/Cumming Publishing Company Inc. (1988). [2] M. Ohmura, J. Yasuura and K. Tamaru "On Functional Information Extraction of Combinational Circuits" Technical Report of IPSJ, DT-44-3, pp.17-24 [in Japanese] (Oct. 1988). [3] A.P. Kostelijk "VERA, a Rule-based Verification Assistant for VLSI Circuit Design" Proc. VLSI89, pp.89-98 (Aug. 1989). [4] D.T. Blaauw, D.G. Saab, R.B. Mueller-Thuns, J.A. Abraham and J.T. Rameh "Automatic Generation of Behavioral Models from Switch-Level Descriptions" Proc. 26th DAC, pp.179-184 (Jun. 1989). [5] R.E. Bryant "Graph-Based Algorithms for Boolean Function Manipulation" IEEE Trans. on Computers, Vol.C-35, No.8, pp.677-691 (Aug. 1986). [6] M. Kitajima, N. Takagi and S. Yajima "Symbolic Simulator Using a Graphical Representation of Boolean Functions" Technical Report of IEICE Japan, VLD87-113, pp.47-52 [in Japanese] (Dec. 1987). [7] Y. Matsunaga and M. Fujita "Multi-Level Logic Optimization Using Binary Decision Diagrams" Proc. ICCAD-89, pp.556-559 (Nov. 1989). [8] K. Cho and R.E. Bryant "Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation" Proc. 26th DAC, pp.418-423 (Jun. 1989). [9] S. Minato, N. Ishiura and S. Yajima "Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation" Proc. 27th DAC, pp.52-57 (Jun. 1990).


An O(n3logn)-Heuristic for Microcode Bit Optimization

Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung Department of Electrical Engineering, Korea Advanced Institute of Science & Technology, P.O. Box 150,

Cheongryang, Seoul, Korea

Abstract In this paper, we address the problem of minimizing the control ROM width which is very important in the design of microprogrammed processors, because it directly reduces the silicon area of the control unit. In earlier works, only exhaustive enumeration procedures could lead to optimal results as this problem is NP-complete. We propose a heuristic algorithm based on graph partitioning. This algorithm results in nearly optimal solutions with the time complexity of O(n3logn) where n denotes the number of distinct microoperations. Comparison of the results with earlier works has shown that the proposed heuristic performs better than earlier works [7] [8] in terms of cost and/or CPU time. References [1] T. Agerwala "Microprogram Optimization: A survey" IEEE Trans. on Comp., Vol. C-25, No. 10, pp. 962-973, Oct. 1976. [2] S. Dasgupta "The Organization of Microprogram Stores" Computing Surveys, Vol. 11, No. 1, pp. 39-65, March 1979. [3] S.J. Schwartz "An algorithm for minimizing read only memories for machine control" 1968 IEEE 10th Ann. Symp. on Switching and Automata Theory, pp. 28-33. [4] E.L. Robertson "Microcode Bit Optimization is NP-Complete" IEEE Trans. on Comp. C-28, No. 4, pp. 316-319, April 1979. [5] A. Grasselli and V. Montanari "On the minimization of read-only memories in microprogrammed digital computers" IEEE Trans. on Comp., C-19, pp. 1111-1114, Nov. 1970. [6] T. Jayasri and D. Basu "An approach to organizing microinstructions which minimizes the width of control store words" IEEE Trans. on Comp., C-25, No.5, pp. 514-521, May 1976. [7] J.L. Baer and B. Koyama "On the Minimization of the Width of the Control Memory of Microprogrammed Processor" IEEE Trans. on Comp., Vol. C-28, No. 4, pp. 310-316, April 1979. [8] A.W. Nagle, R. Cloutier and A.C. Parker "Synthesis of hardware for the control of digital systems" IEEE Trans. on CAD, Vol. CAD-1, No.4, pp. 201-212, Oct. 1982. [9] B.W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" Bell Sys. Tech. Journal, pp. 291-307, Feb. 1970. [10] J.P. Hayes "Computer Architecture and Organization" McGraw-Hill, 1978. [11] S. Davison et al. "Some experiments in local microcode compaction for horizontal machines" IEEE Trans. on Comp., pp. 460-477, July 1981. [12] J.A. Fisher "Trace scheduling: A technique for global microcode compaction" IEEE Trans. on Comp., pp. 478-490, July 1981. [13] S. Isoda et al. "Global compaction of horizontal microprograms based on the generalized data dependency graphs" IEEE Trans. on Comp., pp. 922-932, Oct. 1983.


Optimized Synthesis of Asynchronous Control Circuits from Graph-theoretic Specifications.

Peter Vanbekbergen, Francky Catthoor, Gert Goossens

IMEC Laboratory, Kapeldreef 75, B-3030 Leuven, Belgium

Hugo De Man ESAT Laboratory, Katholieke Universiteit, K. Mercierlaan 94, B-3030 Leuven, Belgium

Abstract Asynchronous circuits offer particular advantages in comparison with synchronous circuits, but a fault-free and efficient asynchronous design is difficult to achieve. Therefore, synthesis support for the design of asynchronous circuits is crucial. The synthesis method proposed in this paper starts from a graph-theoretic specification called a Signal Transition Graph (STG). This paper deals with the theoretical foundations of a method to transform a given STG into an STG that satisfies the original timing behavior and that in addition obeys the unique state coding requirement. It will be shown that in general, many valid solutions to this problem are possible. Therefore we attempt to find a transformed STG that can be realized in a circuit with optimized speed and area. References [1] Tadao Murata "Petri nets: Properties, Analysis and Applications" Proc. of the IEEE, Vol. 77, No. 4, April 1989 [2] Tam-Anh Chu "Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications." M.I.T. Computer Science, PhD June 1987. [3] T.H.-Y. Meng, R.W. Brodersen, D.G. Messerschmitt "Automatic Synthesis of Asynchronous Circuits from High Level Specifications." IEEE Trans. on CAD. Vol.8. No. 11, Nov. 1989. [4] Cho Wo Moon. "Private Communications." U.C. Berkeley 1989. [5] P. Vanbekbergen et. al. "Time & Area Performant Synthesis of Asynchronous Control Circuits." "1990 ACM Int. Workshop on Timing Issues in the Spec. and Synthesis of Digital Systems". [6] P. Vanbekbergen. "A Matrix Equation and a Timing Analysis Algorithm for Signal Transition Graphs" Report ESPRIT 2260 project: B1.3/IMEC/Y1-M12/1 Available on request.


High-Level Delay Estimation for Technology-Independent Logic Equations

David E. Wallace, Mandalagiri S. Chandrasekhar Hewlett-Packard Company / Design Technology Laboratory, 3172 Porter Drive, Palo Alto, CA 94304

ABSTRACT In this paper, we present a simple model for estimating the delay of a multi-level combinational logic description prior to a technology-dependent mapping phase. The model proposes that delay through a node varies logarithmically with both the complexity and the fanout of the node's logic equation. This is a consequence of the observation that in high performance circuits, both the fan-in and fan-out of cells are bounded by small numbers. We derive model parameters for three different CMOS ASIC libraries, and show how the predicted delays compare with the actual delays for three different industrial designs in each library. This model can serve as a proxy for delay during technology-independent logic optimization, much as literal counts serve as proxies for area. References [1] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. R. Wang "MIS: A multiple-level logic optimization system" IEEE Transactions on Computer-aided design, (6):1062-1081, November 1987. [2] K. J. Singh, A. R. Wang, R. K. Brayton, A. Sangiovanni-Vincentelli "Timing Optimization of Combinational Logic" Proceedings of IEEE International Conference on Computer-Aided Design, ICCAD-88, pp. 282-285. [3] E. Horowitz and S. Sahni. Fundamentals of Computer Algorithms. Chapter 5, Computer Science Press, 1978. [4] D. E. Wallace and C. H. Sequin "ATV: An Abstract Timing Verifier" Proceedings of the 25th ACM/IEEE Design Automation Conference, June 1988, pp. 154-159.


A High-Packing Density Module Generator for Bipolar Analog LSIs

Yoichi Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino Hitachi, Ltd., 1-280 Higashi-Koigakubo Kokubunji Tokyo, 185 JAPAN

Miki Seriuchi, Manabu Kusaoke

Hitachi VLSI Engineering, Corp., 1-280 Higashi-Koigakubo Kokubunji Tokyo, 185 JAPAN ABSTRACT This paper presents efficient placement and routing algorithms for the modules of a bipolar analog LSI. In the layout of an analog module, a grid-free technique is required to minimize the module area and geometric constraint observance is necessary for the circuit performance optimization. The new placement algorithm determines cell positions observing the geometric constraints by vertex-grouping of the constraint graph representing the relative device positions in the input circuit diagram. The routing algorithm, based on the characteristic fine-grid maze router, allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition. These algorithms are applied to the design of the analog modules. An automatically designed modules are compact and the required performances are met. REFERENCES [1] K.Ueda, et al. "Layout Strategy, Standardization and CAD Tools" Layout and Verifications, edited by T.Ohtsuki, Elsevier, 1986 pp. 1-54 [2] G.Serhan "Automated Design of Analog LSI" in Proc. CICC, 1985 pp. 79-82 [3] M.Kayal, et al. "SALIM: A Layout Generation Tool for Analog ICs" in Proc. CICC, 1988 [4] L.R.Carley, et al. "ACACIA: The CMU Analog Design System" in Proc. CICC, 1989 [5] T.Watanabe, et al. "A Layout Design System for Analog Custom LSIs" in Digest Tech. Papers of ESSCIRC '87, 1987 pp.209-212 [6] T.Kambe, et al. "Automatic Layout System for Analog LSI" in Proc. CAS Karuizawa Workshop, 1989 pp. 168-175 (in Japanese) [7] T.Akiyama, et al. "Analog LSI CAD Dynamic Router" Research Reports on Circuits and Systems, IEICE, CAS86-213, 1986 pp.73-79 (in Japanese) [8] Y.Shiraishi, et al. "A High-Packing Density Module Generator for CMOS Logic Cells" in Proc. 25th Design Automation Conference, 1988 pp.439-445 [9] M.Mogaki, et al. "LADIES : An Automatic Layout System for Analog LSI's" in Proc. ICCAD '89, 1989 pp.450-453 [10] M.Burstein, et al. "Channel Routing" Layout and Verifications, edited by T.Ohtsuki, Elsevier, 1986 pp. 133-167 [11] J.Xiong, et al. "A Gridless Maze Router : DBM" in Proc. ICCAD '86, 1986 pp.192-195


Constraint-Based Channel Routing for Analog and Mixed Analog/Digital Circuits

Umakanta Choudhury, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, UC Berkeley, CA 94720

Abstract In this paper, algorithms for mapping a set of constraints on critical coupling capacitances into constraints in the vertical-constraint graph of a channel are presented. For differential analog circuits, a technique to perform symmetrical routing in a channel is proposed. References [1] C.D. Kimble et al. "Autorouted Analog VLSI" Proc. IEEE Custom Integrated Circuits Conference, 1985, pp. 72-78. [2] R.S. Gyurcsik and J.-C. Jeen "A Generalized Approach to Routing Mixed Analog and Digital Signal Nets in a Channel" IEEE Journal of Solid-State Circuits, Vol 24, No. 2, Apr. 1989, pp. 436-442. [3] J. Rijmenants et al. "ILAC: An Automated Layout Tool for Analog CMOS Circuits" Proc. IEEE Custom Integrated Circuits Conference, May 1988, pp. 761-764. [4] D. Garrod, R.A. Rutenbar and L.R. Carley "Automatic Layout of Custom Integrated Circuits in ANAGRAM" Proc. IEEE ICCAD, Nov. 1988, pp. 544-547. [5] U. Choudhury and A. Sangiovanni-Vincentelli "Constraint Generation for Routing Analog Circuits" Proc. Design Automation Conference, June 1990, pp. 561-566. [6] U. Choudhury and A. Sangiovanni-Vincentelli "Use of Performance Sensitivities in Routing of Analog Circuits" Proc. International Symposium on Circuits and Systems, May 1990, pp.348-351. [7] H.H. Chen and E.S. Kuh "Glitter: A Gridless Variable-Width Channel Router" IEEE Trans. on CAD Vol. CAD-5, No. 4, Oct. 1986 [8] H. Yaghutiel, A. Sangiovanni-Vincentelli, and P.R. Gray "A Methodology for Automated Layout of Switched-Capacitor Filters" Proc. IEEE ICCAD, pp. 444-447, 1986 [9] E. Malavasi, U. Choudhury and A. Sangiovanni-Vincentelli "A Routing Methodology for Analog Integrated Circuits" in Proc. IEEE ICCAD, Nov. 1990


A Routing Methodology for Analog Integrated Circuits

Enrico Malavasi, Umakanta Choudhury, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, UC Berkeley, CA 94720

Abstract A general methodology for the design of the interconnections of analog circuits respecting high-level constraints on performances is described in this work. In our approach, sensitivities of performances to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a new cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performances are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated to the parasitics which violated the constraints, and the circuit rerouted. Results are reported validating the effectiveness of this approach for layout-design automation of analog circuits. References [1] C.D. Kimble et al. "Autorouted Analog VLSI". Proc. CICC, 1985. [2] R.S. Gyurcsik and J.-C. Jeen. "A Generalized Approach to Routing Mixed Analog and Digital Signal Nets in a Channel". IEEE JSSC, 24, N.2:436-442, April 1989. [3] J. Rijmenants et al. "ILAC: An Automated Layout Tool for Analog CMOS Circuits". Proc. IEEE CICC, pages 761-764, May 1988. [4] H. Y. Koh, C. H. Sequin, and P. R. Gray "Automatic Layout Generation for CMOS Operational Amplifiers". Proc. IEEE ICCAD, pages 548-551, November 1988. [5] H. Shin and A. Sangiovanni-Vincentelli "A Detailed Router Based on Incremental Routing Modifications: Mighty". IEEE Trans. on CAD, CAD-6, N.6:942-955, November 1987. [6] D. J. Garrod, R. A. Rutenbar, and L. R. Carley "Automatic Layout of Custom Analog Cells in ANAGRAM". Proc. IEEE ICCAD, pages 544-547, November 1988. [7] U. Choudhury and A. Sangiovanni-Vincentelli "Constraint Generation for Routing Analog Circuits". Proc. DAC, June 1990. [8] E. Malavasi, M. Chilanti, and R. Guerrieri "A General Router for Analog Layout". Proc. COMPEURO '89, Hamburg, pages 549-551, May 1989. [9] C. Lee "An algorithm for path connections and applications". IRE Trans. Electron. Computer, EC-10:346-365, September 1961. [10] T. Ohtsuki "Maze-Running and Line-Search Algorithms". Layout Design and Verification, chapter 3, pages 99-131. T. Ohtsuki Ed.North Holland, 1986. [11] N.J. Nilsson Problem-Solving Methods in Artificial Intelligence. McGraw-Hill, 1971. [12] G.W. Clow "A Global Routing Algorithm for General Cells". Proc. 21st DAC, pages 45-51, 1984. [13] J. Pearl Heuristics: intelligent search strategies for computer problem solving. Addison Wesley, 1984.


The Component Synthesis Algorithm: Technology Mapping for Register Transfer Descriptions

Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic

Department of Information and Computer Science, University of California, Irvine, 92717 Abstract Designers use functional models more frequently than behavioral or gate-level models. In functional modeling, one or more micro-architecture components are described as separate concurrent blocks. We present an algorithm, called Component Synthesis Algorithm, that automatically synthesizes micro-architecture components for a functional description. Experimental results show that automated functional synthesis is comparable to human designers. References [1] Dutt, N. GENUS: A Generic Component Library for High Level Synthesis, Tech. Report 9, Univ. of Cal., Irvine, 1989. [2] Gajski, D., et al Synthesis from VHDL: Rockwell-Counter Case Study, Tech. Rep. 9, Univ. of Cal., Irvine, 1990. [3] Keutzer, K. DAGON: Technology Binding and Local Optimization by DAG Matching, DAC, pp. 617-623, 1987. [4] Leive, G. W., & D. E. Thomas. A Technology Relative Logic Synthesis and Module Selection System. DAC, pp. 479-485, 1981. [5] Lis, J. S., & D. D. Gajski. Synthesis from VHDL. ICCD, 1988. [6] Mano, M. M. Computer Engineering Hardware Design. Prentice Hall, 1988. [7] McFarland, M. C., Parker, A. C., & Camposano, R. Tutorial on High Level Synthesis, DAC, 1988. [8] Paulin, G. P., & Knight, J. P. Scheduling and Binding Algorithms for High-Level Synthesis. DAC, pp. 1-6, 1989. [9] Rundensteiner, E. A., Gajski, D., & Bic, L. Technology Mapping for Register Transfer Descriptions. Tech. Rep. 42, Univ. of Cal., Irvine, 1989. [10] Tseng, C. & Siewiorek, D. P. Automated Synthesis of Data Paths in Digital Systems, IEEE Trans. on CAD of Integrated Circuits and Systems, CAD-5, 3, pp. 379 - 395, July, 1986. [11] The TTL Data Book for Design Engineers, Texas Instr., 2nd Ed., 1967.


MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations

Rajiv Jain Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI 53706

Abstract Selection of appropriate module types from a design library which will be used in the final implementation is called module selection. In this paper we give a solution to the module selection problem for pipelined designs with multi-cycle operations. The proposed solution technique is based on an area-delay analysis of an RTL design and produces optimal results in milliseconds. References [1] R. E. Bixby. Matroids and Operations Research. Advanced Techniques in the Practice of Operations Research. North-Holland Publishers, New York, 1982. [2] D. C. Fogg. Operator Selection: Two Approaches. Fourth High-Level Synthesis Workshop, October 1989. [3] Y-P. S. Foo and H. Kobayashi. A Knowledge-Based System for VLSI Module Selection. ICCAD, 1986. [4] L. Hafer and A. Parker. A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic. IEEE Trans. CAD, January 1983. [5] R. Jain, A. C. Parker, and N. Park. Module Selection for Pipelined Designs. DAC, 1988. [6] J-H. Lee, Y-C. Hsu, and Y-L. Lin. A New Integer Linear Programming Formulation for the Scheduling Problem in Data Path Synthesis. ICCAD, 1989. [7] G. W. Leive. The Design, Implementation, and Analysis of an Automated Logic Synthesis and Module Selection System. PhD thesis, Carnegie-Mellon University, January 1981. [8] M. C. McFarland. Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions. DAC, 1986. [9] M. J. Mlinar. System Level Tradeoffs in VLSI Design. PhD thesis, University of Southern California, 1990. (In preparation) [10] C. H. Papadimitriou and K. Steiglitz. Combinatorial Optimization: Algorithms and Complexity. Prentice-Hall Inc., New Jersey, 1982. [11] N. Park and A. C. Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Trans. CAD, March 1988. [12] P.G. Paulin and J. P. Knight. Force-Directed Scheduling for the Behavioral Synthesis of ASIC's. IEEE Trans. CAD, June 1989.


Partitioning of Functional Models of Synchronous Digital Systems

Rajesh Gupta, Giovanni De Micheli Center for Integrated Systems, Stanford University, Stanford, CA 94305

Abstract We present a partitioning technique of functional models that is used in conjunction with high-level synthesis of digital synchronous circuits. The partitioning goal is to synthesize multi-chip systems from one behavioral description, that satisfy both chip area constraints and an overall latency timing constraint. There are three major advantages of using partitioning techniques at the functional abstraction level. First, scheduling techniques can be applied concurrently to partitioning. Therefore, partitioning under timing constraints, and in particular under latency constraints, can be performed. Second, the functional model captures large hardware systems with fewer objects (than at the logic netlist abstraction level), making the partitioning algorithm more efficient. Third, hardware sharing trade-offs can be considered. In this paper, hardware partitioning is formulated as a hypergraph partitioning problem. Algorithms for hardware partitioning are presented and experimental results are reported. References [1] M. Beardslee, C. Kring, R. Murgai, H. Savoj, R. K. Brayton, A. R. Newton "SLIP: A Software Environment for System Level Interactive Partitioning" Proc. ICCAD'89, Santa Clara, Nov 1989. [2] W. E. Donath "Logic Partitioning" in B. Preas, M. Lorenzetti (ed), Physical Design Automation of VLSI Systems, Chapter 3, Benjamin-Cummings Publishing Company, 1988. [3] D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn "The Systems Architect Workbench" Kluwer Academic Press, 1989. [4] M. C. McFarland, A. C. Parker, R. Camposano "Tutorial on High-Level Synthesis" Proc. 25th DAC, 1988, pp. 330-336. [5] E. Dirkes LAgnese, D. E. Thomas "Architectural Partitioning for System Level Design" Proc. 26th DAC, pp. 62-67, June 1989. [6] M. C. McFarland, S.J. "Computer-Aided Partitioning of Behavioral Hardware Descriptions" Proc. 20th DAC, pp. 472-478, 1983. [7] R. Camposano, R. K. Brayton "Partitioning Before Logic Synthesis" Proc. 22nd DAC, pp. 324-326, November 1987. [8] S. Kirkpatrick, D. Gelatt and M. Vecchi "Optimization by Simulated Annealing" Science, 220, N.4598, pp. 45-54, May 1983. [9] B. W. Kemighan, S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" The Bell System Technical Journal, 49(2) Feb 1970. [10] G. De Micheli, D. Ku, F. Mailhot, T. Truong "The Olympus Synthesis System" IEEE Design and Test of Computers, Oct 1990. [11] C. Berge "Graphs and Hypergraphs" North-Holland, 1973. [12] E. L. Lawler "Cutsets and Partitions of Hypergraphs" Networks, no. 3, pp. 275-285. [13] P. J. M. van Laarhoven, E. H. L. Aarts "Simulated Annealing: Theory and Applications" D. Reidel Publishing Company, 1987. [14] P. DeWilde, E. Deprettere, R. Nouta "Parallel and Pipelined VLSI Implementation and Signal Processing Algorithms" In S. Y. Kung, H. J. Whitehouse, and T. Kailath (ed), VLSI and Modern Signal Processing, pp. 257-264, Prentice-Hall, 1985. [15] E. Dirkes Lagnese Private Communication.


CONTEST: A Fast ATPG Tool for Very Large Combinational Circuits

Udo Mahlstedt, Torsten Gruning, Cengiz Ozcan, Wilfried Daehn Institut fur Theoretische Elektrotechnik, Universitat Hannover, Appelstr. 9A, D-3000 Hannover 1,

Germany Abstract In this paper CONTEST (CONe-oriented TEST pattern generator), a new ATPG tool for very large combinational digital circuits is presented. CONTEST is based on four major ideas. Cone-oriented circuit partitioning reduces the circuit complexity and increases the number of dominators. The propagation graph is a dynamic data structure that keeps track of all paths from the fault location to a primary output. The new multiple backtrace procedure reduces contradictory node assignments by examination of fanout nodes and dynamic implications. The new pattern parallel fault dropping technique is based on Hamming distance variations of generated test patterns. Experimental results for the ISCAS'85 and ISCAS'89 benchmark circuits containing up to 40.000 nodes illustrate the superiority of the ATPG system. For these circuits a 100 percent fault coverage for all detectable stuck-at faults and a 100 percent redundancy identification is achieved. References [1] Williams, M.J.Y., Angell, J.B.: "Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic" IEEE Trans. Comput., C-22 (1), pp. 46-60, 1973 [2] Kobayashi, T., Matsue, T., Shibo, H.: "Flip-flop Circuit with FLT, Capability" Proc. IECEO, p. 692, 1968 [3] Eichelberger, E.B., Williams, T.W.: "A Logic Design Structure for LSI Testability" Proc. 14th Design Automation Conference, pp. 462-468, 1977 [4] Roth, J.P.: "Diagnosis of Automata Failures: A calculus and a method" IBM Journal Res. Dev. 10, pp. 278-281, 1966 [5] Goel, P.: "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic" IEEE Trans. Comput., Vol. C-30 (3), pp. 215-222, 1981 [6] Fujiwara, H., Shimono, T.: "On the Acceleration of Test Generation Algorithms" Proc. 13th Int. Symp. Fault-Tolerant Computing, pp. 98-105, 1983 [7] Kirkland, T., Mercer, M.R.: "A Topological Search Algorithm for ATPG" Proc. 24th Design Automation Conference, pp. 502-508, 1987 [8] Schulz, M.H., Auth, E.: "Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques" Proc. 18th Int. Symp. Fault-Tolerant Computing, pp. 30-35, 1988 [9] Gruning, T., Mahlstedt, U., Daehn, W., Ozcan, C.: "Accelerated Test Pattern Generation by Cone-Oriented Circuit Partitioning" IEEE Proc. 1th European Design Automation Conference, pp. 418-421, 1990 [10] Tarjan, R.: "Finding Dominators in Directed Graphs" SIAM Journal of Computing, Vol. 3, pp. 62-89, 1974 [11] Church, A.: "Introduction to Mathematical Logic" Princeton, New Jersey, Princeton University Press, 1956 [12] Muth, P.: "A Nine-Valued Logic Model for Test Generation" IEEE Trans. Comput., Vol. C-25, pp. 630-636, 1976 [13] Koppe, S., Starke, C.W.: "Logiksimulation komplexer Schaltungen fur sehr groβe Testlangen" NTG-Fachberichte Groβintegration, pp. 73-80, Marz 1985 [14] Goldstein, L.H.: "Controllability/Observability Analysis of Digital Circuits" IEEE Trans. on Circuits and Systems, Vol. CAS-26, No. 9, pp. 685-693, Sept. 1979

[15] Brglez, F., Fujiwara, H.: "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran" special session on ATPG and fault Simulation, Proc. 1985 IEEE Int. Symp. on Circuits and Systems, Kyoto (Japan), 1985 [16] Brglez, F., Bryan, D., Kozminski, K.: "Combinational Profiles of Sequential Benchmark Circuits" IEEE Int. Symp. on Circuits and Systems, 1989


Single-State-Transition Fault Model for Sequential Machines

Kwang-Ting Cheng, Jing-Yang Jou AT&T Bell Laboratories, Murray Hill, NJ 07974

ABSTRACT In this paper, a fault model in the state transition level for finite state machine is studied. In this model, called single-state-transition (SST) fault model, a fault causes a state transition to a wrong destination state while retains its input/output label. The effectiveness of this model is shown by both analysis and experimental results. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. Since any defective sequential machine may be viewed as one in which a multiple-state-transition fault of some arbitrary multiplicity is present, the high coverage of multiple-state-transition faults implies that the quality of the test set generated for SST faults is close to the sequences derived from checking experiment. It is shown that, for a N-state M-transition machine, the length of the SST fault test set is upper-bounded by 2·M·N2. while the length is exponential in terms of N for checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multi-level implementation of the machine. The achieved transistor fault coverage is considerably higher than that of the test set generated for the single-stuck-at faults. References [1] F. C. Hennie "Fault-detecting experiments for sequential circuits" Proc. 5th Ann. symp. on Switching Circuit Theory and Logical Design, pp. 95-110, November 1964. [2] E. P. Hsieh "Checkig Experiments for Sequential Machines" IEEE Trans. Computers, vol. C-20, pp. 1152-1166, October 1971. [3] K. Sabnani and A. Dahbura "A Protocol Test Generation Procedure" Computer Networks, vol. 15, pp. 285-297, 1988. [4] K.-T. Cheng and V. D. Agrawal "A Partial Scan Method for Sequential Circuits With Feedback" Trans. Computers, vol. 39-4, pp. 544-548, April 1990. [5] K.-T. Cheng and V. D. Agrawal "Design of Sequential Machines for Efficient Test Generation" Proc. Int'l Conf. Computer-Aided Design, pp. 358-361, November 1989. [6] K.-T. Cheng and J.-Y. Jou "Functional Test Generation for Finite State Machines" Int'l Test Conf., Sept. 1990. [7] W.-T. Cheng "The BACK Algorithm for Sequential Test Generation" Proc. Int. Conf. Computer Design (ICCD-88), pp. 66-69, October 1988. [8] D. G. Saab et al. "Hierarchical Multi-Level Fault Simulation of Large Systems" Journal Elec. Testing theory and Applications (JETTA), pp. 139-149, May 1990.


Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm

Chun-Hung Chen, Jacob A. Abraham Computer Engineering Research Center, The University of Texas at Austin, Austin, Texas 78758

Abstract This paper presents a powerful automatic test generation system using a novel Nine-Valued Relaxation Algorithm. This algorithm, which brings together the relaxation technique from circuit simulation and a nine-valued algebra from sequential circuit test generation, is applied to the strongly connected DC coupling components so that for every possible choice of node values a stable state could be achieved through relaxation. Circuits which use bi-directional transistors and depend on the transistor strengths for correct operation are properly handled by this algorithm. A method called DC path sensitization is used to detect the stuck-at, stuck-on, stuck-open and bridging faults for CMOS transistors. The algorithm has been implemented in C++ and preliminary results are very promising. The algorithm can easily be extended to different circuit models and other technologies, or be incorporated into a higher level test generation system. References [1] R. A. Marlett "An Effective Test Generation System for Sequential Circuits" 23th Design Automation Conference, June 1986, pp. 250-256. [2] A. Ghosh, S. Devadas, and A. Newton "Test Generation for Highly Sequential Circuits"International Conference on Computer-Aided Design, 1989, pp. 362-365. [3] S. Jain, V. D. Agrawal "Test Generation for MOS circuits Using D-Algorithm" 20th Design Automation Conference, 1983, pp. 64-70. [4] H. Shih, J. A. Abraham "Transistor-Level Test Generation for Physical Failures in CMOS Circuits" 23th Design Automation Conference, 1986, pp. 243-249. [5] K. Cho, R. Bryant "Test Pattern Generation for Sequential MOS circuits by Symbolic Fault Simulation" 26th Design Automation Conference, 1989, pp. 418-423. [6] A. E. Ruehli Circuit Analysis, Simulation and Design. Elsevier Science Publishing Company, 1987. June 1976, pp. 630-636. [7] P. Muth "A Nine-Valued Circuit Model for Test Generation" IEEE Transaction on Computers, Vol. C-25, No. 6, June 1976, pp. 630-636. [8] R. A. Marlett "EBT, A Comprehensive Test Generation technique for Highly Sequential Circuits" 17th Design Automation Conference, June 1978, pp. 332-339. [9] K. Roy, J. A. Abraham "High Level Test Generation Using Data Flow Description" Proceedings, European Design Automation Conference 1990, pp. 480-484. [10] L. Goldstein "Controllability/Observability Analysis of Digital Circuits" IEEE Transaction on Circuits and Systems, Vol. CAS-26, No. 9, Sept. 1979, pp. 685-693. [11] S. B. Lippman C++ Primer. Addison-Wesley Publishing Company, 1989. [12] P. Denyer and D. Renshaw VLSI Signal Processing: A bit-serial approach Addison-Wesley Publishing Company, 1985. [13] T. Ogihara, S. Saruyama, and S. Murai "Test Generation for Sequential Circuits Using Individual Initial Value Propagation" 25th Design Automation Conference, 1988, pp. 424-427.


A Parallel Algorithm for Hierarchical Circuit Extraction

Krishna P. Belkhale, Prithviraj Banerjee Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of

Illinois, Urbana, IL-61801 ABSTRACT In ICCAD88, 89, we proposed efficient parallel algorithms to speed up the task of VLSI circuit extraction on distributed memory multiprocessors. The input to the algorithms is a flat description of the circuit, in terms of the rectangles in different layers. In this paper, we describe an algorithm that combines the benefits of hierarchical analysis and parallelism. The input is a hierarchical description of the circuit. Towards this goal, we formulate and solve a general problem in scheduling. The parallel algorithm for hierarchical circuit extraction has been implemented on an Encore shared memory multiprocessor. REFERENCES [1] R. Hon and A. Gupta HEXT: A Hierchical Circuit Extractor. Computer Science Press, 1983. pp. 18-34. [2] G.M. Tarolli and W.J. Herman "Hierarchical circuit extraction with detailed parasitic capacitance" Proc. 20th Design Automation Conf. pp. 337-345, 1983. [3] S. Levitin A Multiprocessing Approach to Circuit Extraction. MIT, 1986, Master's Thesis. [4] K. P. Belkhale and P. Banerjee "PACE2: An Improved Parallel VLSI Extractor with Parameter Extraction" Proc. Int. Conf. on Computer-Aided Design, pp. 526-529, Nov. 1989. [5] B. A. Tonkin "Circuit Extraction on a Message-Based Multiprocessor" 27th Design Automation Conf., pp. 260-265, June 1990. [6] R. L. Graham "Bounds on Multiprocessing Timing Anomalies" SIAM J. Appl. Math., vol. 17, pp. 263-269, 1969. [7] K. P. Belkhale and P. Banerjee "Approximate Algorithms for the Partitionable Independent Task Scheduling Problem" Proc. Int. Conf. on Parallel Processing, Aug. 1990 (to appear).


A Hierarchical Circuit Extractor Based on New Cell Overlap Analysis

Hirotoshi Sawada NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa, 243-01, Japan

Abstract This paper presents a new algorithm for cell overlap analysis. Introducing a new hierarchical operations set, any type of cell overlap can be mapped into each subcell. Cell abstract is automatically defined without any technology dependent descriptions and hierarchical structure can be preserved. This algorithm is implemented in a hierarchical circuit extractor called HIPAS. This system can be used for a full chip with more than 200,000 transistors. References [1] Todd J. W. "Hierarchical Layout Verification" Proc. 21th Design Automation Conference, 1984, pp.484-489. [2] Keller K.H. "A Symbolic Design System for Integrated Circuits" Proc. 19th Design Automation Conference, 1982, pp.460-466. [3] Louis K., et al. "Hierarchical analysis of IC artwork with User Defined Abstraction" Proc. 22nd Design Automation Conference, 1985, pp. 293-298. [4] Henkel V., et al. "RICE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification" Proc. 25th Design Automation Conference, 1988, pp.465-470. [5] Gupta A., et al. "HEXT: Hierarchical Circuit Extractor" Journal of VLSI and Computer Systems, 1983, vol. 1, pp23-39. [6] B. Ahsan, et al. "A Technology Independent Approach Hierarchical IC Layout Extraction" Proc. 23rd Design Automation Conference, 1986, pp.425-431.


XREF/COUPLING: capacitive coupling error checker

Bill Grundmann, Y.T. Yen Digital Equipment Corporation, 77 Reed Road, HL02-2/H13, Hudson, Massachusetts 01749

Abstract Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect the global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. We present a new pattern-independent circuit verification tool XREF which can detect and report all possible failures in a design due to capacitive coupling effect. References [1] L. Glasser and D. Dobberpuhl "The design and analysis of VLSI circuits" Addison-Wesley Publishing Company, 1986, pp. 231-233. [2] B. Grundmann, Y. Yen, J. Grodstein, and J. Pan "Context recognition for static circuit verification tasks" (to be published) [3] B. Grundmann "GENMODEL: a behavior model extractor"(to be published).


Preform: a process independent symbolic layout system

Jean-Claude Dufourd, Jean-Francois Naviner Francis Jutand TELECOM Paris University, Dept. Elec, 46, rue Barrault, 75013 Paris, France

Abstract Preform stick is a symbolic design method for CMOS VLSI cells. It is an alternative to hand-crafted mask design allowing good density and electrical performances while designing very quickly and simply process independent cells. Its principle lies between Gate-Matrix layout and virtual grid sticks. This paper introduces the notion of process independent stick syntax and presents two compilers that enable the Preform tool to be independent of both process and design strategy. Preform has been used for the design of three chips up to 300.000 transistors. References [Art88] A. ARTIERI, S. KRITTER, F. JUTAND & N. DEMASSIEUX "A One Chip VLSI for Real Time Two-Dimensional Discrete Cosine Transform" Proc. ISCAS 88. [Dun80] A. DUNLOP "SLIM --The Translation of Symbolic Layouts Into Mask Data" Proc. DAC 80. [Gou90] C. GOUDET, Y. MATHIEU, G. CONCORDEL & N. DEMASSIEUX "A Real Time Multi-kernel Picture Convolver" Proc. CICC 90. [Lop80] A.D. LOPEZ & H.S. LAW "A Dense Gate Matrix Layout Method for MOS VLSI" IEEE Trans. on Electron Devices, Vol. ED-27, No 8, Aug. 1980. [Mea80] C. MEAD & L. CONWAY Introduction to VLSI Systems, Addison-Wesley, 1980. [Nai87] R. NAIR "MLG - A Case for Virtual Grid Symbolic Layout without Compaction" Proc. ICCAD 87. [STV89] Preliminary data sheet for the motion estimation processor STV3220, SGS-Thomson Microelectronics, May 89. [Wes81] N.H. WESTE "MULGA - An Interactive Symbolic Layout System for the Design of Integrated Circuits" The Bell Syst. Techn. Journal, Vol. 60, July-August 81. [Wil78] J. WILLIAMS "STICKS --A Graphical Compiler for High Level LSI Design" Proc. NCC, May 78.


Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis

D.L. Springer, D.E. Thomas

Carnegie Mellon University, Pittsburgh PA 15213 Abstract Coloring of conflict graphs, and clique partitioning of compatibility graphs have been used in high-level synthesis to map operators, values and data transfers onto shared resources. Existing high-level synthesis systems take advantage of two special conflict graphs, interval and circular-arc graphs, during register allocation to guarantee a minimum number of registers. This paper will present two types of graphs, chordal and comparability graphs. Chordal graphs will allow us to guarantee a minimum number of registers on a larger number of designs. Comparability graphs will allow us to reduce the complexity and improve clique portioning algorithms used in high-level synthesis. References [1] G. Borriello and E. Detjens. High-level synthesis: Current status and future directions. In Proceedings of the 25th DAC, pages 477-482, 1988. [2] R. Camposano. Design process model in the yorktown silicon compiler. In Proceedings of the 25th Design Automation Conference, pages 489-494, Anaheim CA., June 1988. ACM/IEEE. [3] D. E. Thomas et. al. Algorithmic annd Regisetter Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, 1990. [4] M. C. Golumbic. Algorithmic Graph Theory and Perfect Graphs. Academic Press, 1980. [5] B. S. Haroun and M. I. Emasry. Automatic synthesis of a multi-bus architecture for dsp. In Proceedings of ICCAD-88, pages 44-47, Santa Clara, CA, November 1988. IEEE. [6] F. J. Kurdahi and A. C. Parker. Real: A program for register allocation. In Proceedings, 24th DAC, pages 210-215, Miami Beach, Fla., June 1987. ACM/IEEE. [7] P. G. Paulin and J. P. Knight. Force-directed scheduling for the behavioral synthesis of asic's. IEEE Transactions On CAD, 8:661-679, July 1989. [8] J. V. Rajan. Automatic Synthesis of Microprocessors. PhD thesis, Carnegie Mellon University, Dec 1988. [9] Chia-Jeng Tseng. Automated Synthesis of Data Paths in Digital Systems. PhD thesis, Carnegie-Mellon University, April 1984. [10] Y-S. Chen Y-L. Lin, C-Y Huang and Y-C Hsu. Data path allocation basedon bipartite weighted matching. In Proceedings of the 27th DAC, 1990.


A Global Optimization Approach for Architectural Synthesis

Catherine H. Gebotys, Mohamed I. Elmasry Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario. N2L 3G1

Canada A relaxed LP model, which simultaneously schedules and allocates functional units and registers, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing exploration of optimal synthesized architectures since it is well known that early architectural decisions have the greatest impact on the final design. A mathematical integer programming formulation of the architectural synthesis problem was transformed into the node packing problem. Some integral facets of this polytope were extracted and generalized to produce integral solutions using the simplex algorithm without the need to branch and bound. Execution times are faster by an order of magnitude than previous research which makes use of heuristic techniques. This research breaks new ground by 1. simultaneously scheduling and allocating in practical execution times, 2. guaranteeing globally optimal solutions for a specific objective function, and 3. providing a polynomial run time algorithm for solving this NP-complete problem. References [1] M. McFarland, A. Parker, and R. Camposano "Tutorial on High-Level Synthesis" Design Automation Conference, pp. 330-336 (1988.). [2] S. Devadas and A. R. Newton "Algorithms for Hardware Allocation in Data Path Synthesis" IEEE Transactions on CAD, (1989). [3] Garey and Johnson "," in Computers and Intractability, Freeman and Co. (1979). [4] L. Hafer and A. Parker "A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic" IEEE Transactions on CAD, (1983). [5] Nemhauser and Wolsey "," in Integer and Combinatorial Optimization, (1989). [6] J. Lee, Y. Hsu, and Y. Lin "A New Integer Linear Programming Formulation for the Scheduling Problem in Data Path Synthesis" ICCAD, (1989). [7] A. Brooke, D. Kendricke, and A. Meeraus GAMS/MINOS Users Manual, Scientific Press (1988). [8] C. H. Gebotys and M. I. Elmasry "IP Techniques for Architectural synthesis" UW/ICR TechRept/90, (1990). [9] M.W. Padberg "On the Facial Structure of Set Packing Polyhedra" Mathematical Programming, 5(1973). [10] P. G. Paulin "Force Directed Scheduling" IEEE Transactions on CAD, pp. 661-679 (1989). [11] N. Karmarkar "A new polynomial-time algorithm for linear programming" Combinatorica, 4 pp. 373-395 (1984).


SALSA: A New Approach to Scheduling with Timing Constraints

John A. Nestor, Ganesh Krishnamoorthy Department of Electrical and Computer Engineering, Illinois Institute of Technology,

Chicago, Illinois 60616 Abstract This paper presents a new approach to the problem of scheduling with timing constraints. First, an initial schedule that satisfies all timing constraints is generated using algorithms adapted from layout compaction. This schedule is then improved with respect to resource usage using simulated annealing. A new schedule representation called SALSA provides for efficient exploration of alternative schedules while supporting timing constraints, conditionals, loops, and subroutines. References [1] M. C. McFarland, A. C. Parker, and R. Camposano "The High-Level Synthesis of Digital Systems" Proc. IEEE, Vol. 78, No. 2, Feb. 1990. [2] J. A. Nestor and D. E. Thomas "Behavioral Synthesis with Interfaces" Proc. ICCAD-86, pp. 112-115, Nov. 1986. [3] R. Camposano and A. Kunzmann "Considering Timing Constraints in Synthesis from a Behavioral Description" Proc. ICCD, pp. 6-9, Oct. 1986. [4] E. F. Girczyc and J. P. Knight "An ADA to standard cell hardware compiler based on graph grammars and scheduling" in Proc. ICCD, Oct. 1984, pp. 726-731. [5] S. Hayati and A. C. Parker "Automatic Production of Controller Specifications From Control and Timing Behavioral Descriptions" Proc. 26th DAC, June 1989, pp. 75-80. [6] D. E. Thomas, et. al. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, 1990. [7] A. C. Parker, J. Pizarro, and M. Mlinar "MAHA: A program for datapath synthesis" Proc. 22nd DAC, July 1986, pp. 461-466. [8] B. M. Pangrle and D. D. Gajski "Slicer: A state synthesizer for intelligent silicon compilation" Proc. ICCD-87, Oct. 1987. [9] P. G. Paulin and J. P. Knight "Force-directed scheduling for behavioral synthesis of ASIC's" IEEE Trans. on CAD, Vol. 8. No. 6, June 1989, pp.661-678. [10] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi "Optimization by Simulated Annealing" Science, vol. 220, no. 4598, pp. 671-680, May 1983. [11] A. R. Newton "Symbolic Layout and Procedural Design" in Design Systems for VLSI Circuits, pp. 65-112, Martinus Nijhoff, 1987. [12] D. Ku and G. De Micheli "Relative Scheduling Under Timing Constraints" Proc. 27th DAC, pp. 59-64, June 1990. [13] S. Devadas and A. R. Newton "Algorithms for Hardware Allocation in Data Path Synthesis" IEEE Trans. CAD, Vol. 8, No. 7, July 1989, pp.768-781. [14] M. Quayle and L. Grover "Pipelined and Non-Pipelined Data Path Synthesis using Simulated Annealing" Progress in Computer Aided VLSI Design, Vol. 4, Feb. 1990. [15] C. Tseng et. al. "Bridge: a Versatile Behavioral Synthesis System" Proc. 25th DAC, June 1988, pp. 415-420. [16] K. Wakabayashi and T. Yoshimura "A Resource Sharing and Control Synthesis Method for Conditional Branches" Proc. ICCAD-89, pp. 62-65, Nov. 1989. [17] M. D. Huang et al. "An Efficient General Cooling Schedule for Simulated Annealing" Proc. ICCAD-86, pp. 381-384, Nov. 1986. [18] G. Borriello and E. Detjens "High-Level Synthesis: Current Status and Future Directions" Proc. 25th DAC, pp. 477-482, June 1988.


A Hierarchical Approach for Testing Large Circuits

Susana Stoica Control Data Corporation, Minneapolis, MN

ABSTRACT The paper presents a method and circuit for implementing hierarchical scan. Hierarchical Scan (HScan, for further reference) has two parts : on one hand is a methodology of adding scan type circuits to very large electronic designs in a novel fashion, such that the timing and real estate impact of scan is reduced; and on the other hand is a scan circuit which serves the above methodology. The advantage of the HScan is that it can analyze and improve testability on subunits of the very large design such that the testability solution remains valid for the full scale design.


On the Efficiency of the Transition Fault Model for Delay Faults

Manfred Geilert, Jurgen Alt, Michael Zimmermann Institut fur Theoretische Elektrotechnik, Universitat Hannover, Appelstr. 9A, D-3000

Hannover 1, Germany Abstract In this paper we present a study about the efficiency of test pattern sets generated with the transition fault model applied to fine grained delay fault models. To this purpose we have developed the delay fault simulator DELFI - a program which is capable to simulate timing failures of combinational circuits using different delay fault models. For the computer experiements we selected transition fault test pattern sets because they are very cost-effective to generate. The simulations of benchmark circuits demonstrate that the transition fault test patterns detect gross delay faults even at nodes with redundant stuck-at faults. Furthermore the results show that the transition fault test patterns are not sufficient for small delay faults in the range of a few gate delays. In order to receive a satisfactory fault coverage for these delay faults the transition fault test sets must be extended. References [1] R.D. Eldred "Test Routines Based on Symbolic Logical Statements" Journal ACM, Vol. 6, Jan 59, pp.33-36. [2] T. Hayashi et.al. "A Delay Test Generator for Logic LSI" Proc. 14th Int. Conf. Fault Tolerant Computing, 1984, pp.146-149. [3] T.M. Storey, J.W. Barry "Delay Test Simulation" Proc. 14th Design Automation Conf., 1977, pp.492-494. [4] J.D. Lesser, J.J. Shedletsky "An experimental Delay Test Generator for Logic LSI" IEEE Trans. Computers, MAR. 1980, pp.235-248. [5] Z. Barzilai, B.K. Rosen "Comparison of AC Self-Testing Procedures" Proc. Int. Test Conf., 1983, pp.89-94. [6] Y.M. Elziq "Automatic Test Generation for Stuck-Open Faults in CMOS VLSI" IEEE 18th Design Automation Conference, 1981, pp.347-354. [7] S. Koeppe "Modeling and Simulation of Delay Faults in CMOS Logic Circuits" Proc. Int. Test Conf., 1986, pp.530-536. [8] S.M. Reddy, M.K. Reddy, V. Agrawal "Robust tests for Stuck-Open Faults in CMOS Combinational Logic" 14th Int. FTCS, 1984, pp.20-22. [9] G.L. Smith "Model for Delay Faults Based upon Paths" Proc. Int. Test Conf, 1985, pp.342-349. [10] J.A. Waicukauski, E. Lindbloom, B.K. Rosen, V.S. Iyengar "Transition Fault Simulation" IEEE Design and Test, April 1987. [11] M. Geilert "High-Speed Compiled-Code Simulation of Transition Faults" Proc. ICCAD 89, pp.478-481. [12] M.H. Schulz, F. Brglez "Accelerated Transition Fault Simulation" 24th Design Automation Conf., 1987, pp.237-243. [13] E.P. Hsieh, R.A. Rasmussen, L.J. Vidunas, W.T. Davis "Delay Test Generation" Proc. 14th Design Automation Conf., 1977, pp.486-491. [14] Y.K. Malaiya, R. Narayanswamy "Testing for Timing Faults in Synchronous Sequential Circuits" Proc. Int. Test Conf., 1983, pp.560-571. [15] K.D. Wagner "The Error Latency of Delay Faults in Combinational and Sequential Circuits" Proc. Int. Test Conf., 1985, pp.334-341.

[16] J.L. Carter, V.S. Iyengar, B.K. Rosen "Efficient Test Coverage Determination for Delay Faults" Proc. Int. Test Conf., 1987, pp.418-427. [17] A.K. Pramanick, S.M. Reddy "On the Detection of Delay Faults" Proc. Int. Test Conf., 1988, pp.845-856. [18] V.S. Iyengar, B.K. Rosen, I. Spillinger "Delay Test Generation 1 - Concepts and Coverage Metrics" Proc. Int. Test Conf., 1988, pp.845-856. [19] V.S. Iyengar, B.K. Rosen, I. Spillinger "Delay Test Generation 2 - Algebra and Algorithms" Proc. Int. Test Conf., 1988, pp.867-876. [20] P. Goel "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits" IEEE Trans. on Computers, Mar.1981, vol.C-30, no.3, pp. 215-222. [21] H. Fujiwara, T. Shimono "On the Acceleration of Test Generation Algorithms" IEEE Trans. on Computers, Dec. 1983, vol.C-32, no.12, pp.1137-1144. [22] M.H. Schulz, E. Trischler, T.M. Sarfert "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System" Proc. Int. Test Conf., 1987, pp. 1016-1026. [23] F. Brglez, H. Fujiwara "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN" Int. Symp. Circuits and Systems, 1985. [24] S.M. Reddy, C.J. Lin, S. Patil "An Automatic Test Pattern Generator for the Detection of Path Delay Faults" Proc. ICCAD 87, pp.284-287. [25] H. Youssef, E. Shragowitz, L.C. Bening "Critical Path Issue in VLSI Design" Proc. ICCAD 89, pp. 520-523. [26] J.Savir, W.H. McAnney "Random Pattern Testability of Delay Faults" Proc. Int. Test Conf., 1986, pp.263-273. [27] S.M. Reddy, C.J. Lin "Validatable Non-robust Tests for Delay Faults" 10th Annual IEEE Design for Testability Workshop, 1987. [28] C.J. Lin, S.M. Reddy "On Delay Fault Testing in Logic Circuits" IEEE Trans. on CAD, Sept. 1987, pp.694-703. [29] E.S. Park, M.R. Mercer "Robust and Nonrobust Test for Path Delay Faults in a combinational Circuit" Proc. Int. Test Conf., Sept. 1987, pp.1027-1034. [30] C.J. Terman "Simulation Tools for Digital LSI Design" Massachusetts Institute of Technology, 1983.


Evaluation and Synthesis of Self-Monitoring State Machines

Scott H. Robinson, John P. Shen SRC-CMU Research Center for CAD, Electrical & Computer Engineering Department, Carnegie Mellon

University, Pittsburgh, PA 15213 Abstract Signature monitoring has proven to be an effective method for concurrent detection of control-flow errors in processors. A recent proposal adapts signature monitoring to the concurrent checking of dedicated controllers or state machines. While initial results seem promising, the proposed approach and its associated techniques are ad hoc. This paper extends this approach and presents theoretical results, including existence-of-solution guarantees, as well as new, efficient synthesis algorithms. The algorithms have been implemented and successfully applied to a variety of machines including all of the machines in the MCNC benchmark set. For most examples, the evaluation and synthesis algorithms exhibit negligible running times and the resulting optimized machines exhibit reasonable overheads. There is strong indication that the efficient synthesis of self-monitoring, and possibly self-testing, state machines is feasible using this approach. References [1] A.V. Aho, J.E. Hopcroft, and J.D. Ullman. The Design and Analysis of Computer Algorithms. Addison-Wesley, 1974. [2] M.R. Garey and D.S. Johnson. Computers and Intractability - A Guide to the Theory of NP-Completeness. W.H. Freeman, 1979. [3] Z. Kohavi. Switching and Finite Automata Theory, volume Second Edition. McGraw-Hill Book Company, 1978. [4] R. Leveugle and G. Saucier. "Concurrent Checking in Dedicated Controllers." In Proc. ICCD, IEEE, October 1989, pages 124-127. [5] R. Leveugle and G. Saucier. "Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities." In Proc. 19th IEEE ITC, IEEE, August 1989, pages 355-363. [6] R. Leveugle and G. Saucier. "Optimized Synthesis of Concurrently Checked Controllers" IEEE Trans. Computers, 39(4):419-425, April 1990. [7] A. Mahmood and E.J. McCluskey. "Concurrent Error Detection Using Watchdog Processors - A Survey" IEEE Trans. Computers, 37(2):160-174, February 1988. [8] S.H. Robinson and J.P. Shen. "Theory and Algorithms for Self-Monitoring State Machines" TechReport CMUCAD-90-31, Carnegie Mellon University, August 1990. ECE Department. [9] K. Wilken and J.P. Shen. "Continuous Signature Monitoring: Low-Cost Concurrent-Detection of Processor Control Errors" IEEE Trans. Computer-Aided Design, 9(6):629-641, June 1990.


QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults

Weiwei Mao, Ravi K. Gulati, Deepak K. Goel

Ford Microelectronics, Inc, 9965 Federal Drive Colorado Springs, CO 80921

Michael D. Ciletti Dept. of Electrical and Computer Engg., University of Colorado, Colorado Springs, CO 80933

Abstract A hierarchical leakage fault analysis methodology is proposed for IDDQ testing of VLSI CMOS circuits. A software system QUIETEST has been developed on the basis of our methodology. The software can select a small number of test vectors for IDDQ testing from the provided functional test set. Therefore, the total test time for IDDQ measurements can be reduced significantly to make IDDQ testing of VLSI CMOS circuits feasible in production test environment. For two VLSI circuits QUIETEST was able to select less than 1% of functional test vectors from the full test set for covering as many leakage faults as would be covered if IDDQ was measured upon the application of 100% of the vectors. References [1] P. Nigh, W. Maly "Test Generation for Current Testing" IEEE Design & Test, pp. 26-38, Feb. 1990. [2] J.M. Soden, R.K. Treece, M.R. Taylor, C.F. Hawkins "CMOS IC Stuck-open Fault Electrical Effects and Design Considerations" Proc. International Test Conf., pp. 423-430, 1989 [3] J.M. Soden, C.F. Hawkins "Test Considerations for Gate Oxide Shorts in CMOS ICs" IEEE Design & Test, pp. 56-64, Aug. 1986. [4] L.K. Horning, J.M. Soden, R.R. Fritzemeier, C.F. Hawkins "Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing" Proc. International Test Conf., pp. 300-308, 1987. [5] Y.K. Malaiya, S.Y.H. Su "A New Fault Model and Testing Technique for CMOS Devices" Proc. International Test Conf., pp. 25-34, 1982. [6] M. Keating, D. Meyer "A New Approach to Dynamic IDD Testing" Proc. International Test Conf., pp. 316-321, 1987 [7] C. Crapuchettes "Testing CMOS IDD on Large Devices" Proc. International Test Conf., pp. 310-315, 1987. [8] W. Maly, P. Nigh "Built-in Current Testing: Feasibility Study" Proc. ICCAD, pp. 340-343, 1988. [9] C.F. Hawkins, J.M. Soden "Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs" Proc. International Test Conf., pp. 443-451, 1986. [10] C.F. Hawkins, J.M. Soden "Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs" Proc. International Test Conf., pp. 544-555, 1985.


CADICS - Cyclic Analog-To-Digital Converter Synthesis

Gani Jusuf, Paul R. Gray, Alberto L. Sangiovanni-Vincentelli Department of Electrical Engineering & Computer Sciences, University of California, Berkeley, California

94720 Abstract CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), silicon area, and performance comparable with manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically. References [1] W. Check, E. Cheng, G. Hill, M. Holler, and J. Miller "Microcontroller Includes A-D Converter for Lowest-Cost Analog Interfacing" Electronics, May 1978. [2] M. Townsend, M. E. Hoff, Jr. and R. E. Holm "An NMOS Microprocessor for Analog Signal Processing" IEEE Journal of Solid-State Circuits, February 1980. [3] H. Ohara, H. Ngho, M. Amstrong, C. Rahim, and P.R. Gray "A CMOS Programmable Self-Calibrating 13-bit 8-channel Data Acquisition Peripheral" IEEE Journal of Solid-State Circuits, December 1987. [4] P.E. Allen and P.R. Barton "A Silicon Compiler For Successive Approximation A/D And D/A Converters" 1986 IEEE Custom Integrated Circuits Conference pp.552-555 [5] W.J. Helms and B.E. Byrkett "Compiler Generation of A to D Converters" 1987 IEEE Custom Integrated Circuits Conference pp.161-164 [6] D. Lucas "Analog Silicon Compiler For Switched Capacitor Filters" Proc. of IEEE ICCAD, pp. 506-513, 1987. [7] P.W. Li "Ratio-independent Algorithmic Analog To Digital Converter Techniques" University of California at Berkeley, August 1984. Ph. D. Thesis. [8] G. Jusuf, and P. R. Gray "An Improved 1-Bit/Cycle Algorithmic A/D Converter" Electronic Research Laboratory Memo, University of California at Berkeley, May 1990. [9] M. Degrauwe, E. Vittoz, and I. Verbauwhede "A Micropower CMOS Instrumentation Amplifier" IEEE Journal of Solid-State Circuits, June 1985. [10] H.Y. Koh, C.H. Sequin, and P.R. Gray "Automatic Synthesis of Operational Amplifiers based on Analytic Circuit Models" 1987 International Conference on Computer-Aided Design, Santa Clara, CA, November 1987. [11] H. H. Chen, and E. S. Kuh "GLITTER: A Gridless Variable-Width Channel Router" IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 4, pp. 459-465, October 1986. [12] H. Yaguthiel, A.L. Sangiovanni-Vincentelli, and P.R. Gray "MEthodology for Automated Layout of Switch-Capacitor Filters" Proc. ICCAD 1986, pp. 444-447, Santa Clara, November 1986. [13] D. Harrison, P. Moore, R.L. Spickelmier, and A.R. Newton "Data Management and Graphic Editing in the Berkeley Design Environment" Proc. ICCAD 1986, Santa Clara, November 1986.


A Usable Circuit Optimizer for Designers

Dale E. Hocevar Technology CAD Branch, Texas Instruments, Dallas, Texas

Rajeev Arora, Uttiya Dasgupta, Sattam Dasgupta,

Nagaraj Subramanyam, Sham Kashyap Design Automation Department, Texas Instruments, Bangalore, India

ABSTRACT A new system for circuit optimization and performance characterization which is flexible and efficient is presented. This system has been successful in being accepted in an industrial design environment. Past circuit optimization systems have had difficulties becoming accepted by designers. A uniqueness of this system is the utilizing of distributed computing resources to reduce the computation time. A structured problem specification methodology was developed which is novel in providing the user with much flexibility yet allows simplification through libraries. A User-Interface and management system has been built which allows multiple jobs to be run and dynamically monitored and altered. This system has received considerable usage industrially. References [Shy88] J. Shyu and A. Sangiovanni-Vincentelli "ECSTASY: A New Environment for IC Design Optimization" Proc. IEEE ICCAD, pp. 484-487, Nov. 1988. [Nye88] W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli and A. L. Tits. "DELIGHT.SPICE: An Optimization-Based System for the Design of Integrated Circuits" IEEE Trans. Computer-Aided Design, vol. 7, pp. 501-519, April 1988. [Hoc85] D.E. Hocevar, P. Yang, T.N. Trick and B.D. Epler "Transient Sensitivity Computation For Mosfet Circuits" IEEE Trans on Electron Devices, vol. ED-32, pp. 2165-2176, Oct. 1985. [Ran89] P.J. Rankin and J.M. Siemenama "Analogue Circuit Optimization in a Graphical Environment" Proc. IEEE ICCAD, pp. 372-375, Nov. 1989. [Bra81] R.K. Brayton, G.D. Hachtel, and A.L. Sangiovanni-Vincentelli "A Survey of Optimization Techniques for Integrated-Circuit Design" Proc. of the IEEE, vol. 69, pp. 1334-1362, Oct. 1981. [Hac80] G.D. Hachtel, T.R. Scott, and R.P. Zug "An Interactive Linear Programming Approach to Model Parameter Fitting and Worst Case Circuit Design" IEEE Trans. on CAS, vol. CAS-27, pp. 871-881, Oct. 1980. [Mad75] K. Madsen, H. Schjaer-Jacobsen, and J. Voldby "Automated minimax design of networks" IEEE Trans. on CAS, vol. CAS-22, pp. 791-796, Oct. 1975. [Sch79] H. Schjaer-Jacobsen and K. Madsen "Algorithms for worst-case tolerance optimization" IEEE Trans. on CAS, vol. CAS-26, pp. 775-783, Sept. 1979. [Aro90] R. Arora, U. Dasgupta, D. Hocevar, and L. Goff "OASYS: A Tool for Aiding in Design of High Performance Circuits" Proc. IEEE ISCAS, May 1990. [Das89] U. Dasgupta and D.E. Hocevar "AC Sensitivity Computation for Integrated Circuits Using SPICE2" TI Tech. Conference, Nice, France, Nov. 1989.


Optimal Test Set Design for Analog Circuits

Linda Milor Department of EE, University of Maryland, College Park, MD 20742

Alberto Sangiovanni-Vincentelli

Department of EECS, University of California, Berkeley, CA 94720 Analog testing is a difficult task carried out by means of cut-and-try heuristics. Analog circuits are tested for functionality. Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. References [1] L. Milor and V. Visvanathan "Detection of Catastrophic Faults in Analog Integrated Circuits" IEEE Trans. computer-Aided Design, vol. CAD-8, no. 2, pp. 114-130, Feb. 1989. [2] P. Yang, D. Hocevar, P. Cox, C. Machala, and P. Chatterjee "An integrated and efficient approach for MOS VLSI statistical circuit design" IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 5-14, Jan. 1986. [3] S. Liu and K. Singhal "A statistical model for MOSFETS" Proc. ICCAD, Santa Clara, pp. 78-80, 1985. [4] H.Y. Koh, C.H. Sequin, and P.R. Gray "Automatic synthesis of operational amplifiers based on analytic circuit models" Proc. ICCAD, Santa Clara, pp. 502-505, 1987. [5] J.M. Hammersley and D.C. Handscomb Monte Carlo Methods Methuen and Co. Ltd., London, 1964. [6] L. Milor and A. Sangiovanni-Vincentelli "Computing Parametric Yield Accurately and Efficiently" ICCAD, 1990.


Feedback-Driven Datapath Optimization in Fasolt

David W. Knapp University of Illinois, 1304 W. Springfield Ave. Urbana, IL 61801

Abstract Fasolt is a program that optimizes a register-level datapath design. Fasolt is unique in that it uses layout information to drive the choice of optimizing transformations; hence it is feedback-driven, because it uses low-level information to drive high-level decision making. Fasolt 1.0 uses critical path and channel density to select pairs of wire bundles to be merged, which may necessitate retiming. Hence scheduling and allocation can take wiring into account in a novel way, which has been sufficient to give between ten and fifty percent area reductions in naive initial designs. References [1] M. A. Breuer. Min-cut placement. Design Automation and Fault-Tolerant Computing, 2, Oct. 1977. [2] F. Brewer and D. Gajski. Knowledge based control in micro-architecture design. In 24th Design Automation Conference, IEEE, 1987. [3] J. A. Darringer, W. H. Joyner, C. L. Berman, and L. Trevillyan. Logic Synthesis through Local Transformations. Technical Report RC 8748, IBM Thomas J. Watson Center, 1981. [4] A. E. Dunlop and B. W. Kernighan. A procedure for layout of standard-cell VLSI circuits. IEEE Transactions on CAD, CAD-4(1), Jan. 1985. [5] D. W. Knapp. An interactive tool for register level structure optimization. In 26th Design Automation Conference, pages 598-601, IEEE, 1989. [6] D. W. Knapp. Manual rescheduling and incremental repair of register-level datapaths. In ICCAD 89, pages 58-61, IEEE, 1989. [7] D. W. Knapp. Synthesis from partial structure. In D. A. Edwards, editor, Design Methodologies for VLSI and Computer Architecture, Elsevier, 1989. [8] D. W. Knapp and A. C. Parker. A design utility manager: the ADAM planning engine. In 23rd Design Automation Conference, IEEE, 1986. [9] D. W. Knapp and M. Winslett. A Formalization of Correctness for Linked Representations of Datapath Hardware. Elsevier, 1990. [10] T. Kowalski and D. Thomas. The VLSI design automation assistant: what's in a knowledge base. In 22nd Design Automation Conference, pages 252-258, IEEE, 1985. [11] M. C. McFarland, SJ. Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions. In 23rd Design Automation Conference, IEEE, 1986. [12] M. C. McFarland. On proving the correctness of optimizing transformations in a digital system design automation system. In 18th Design Automation Conference, IEEE, 1981. [13] R. Vemuri. A Formal Model for Register Transfer Level Structures and its Applications in Verification and Synthesis. Elsevier, 1990. [14] X. Yao and C. L. Liu. Solution of a module orientation and rotation problem. In European Design Automation Conference, pages 584-588, IEEE, 1990.


Automatic High Level Synthesis of Partitioned Busses

Christian Ewering University of Paderborn, 4790 Paderborn, West-Germany

Abstract A high level synthesis system maps operations of the behaviour specification to functional units minimizing the number of registers, multiplexers and wires. Arranging the results by a floorplanner often leads to a rather large amount of space for interconnections. This situation can be drastically improved if partitioned busses are generated instead of individual connections. For this purpose a parameterized and powerful target architecture is defined. In this paper we present a method which partitions a data flow graph towards a bus oriented design. A new allocation method is introduced for this purpose. First experiments with this approach were successful and lead to very small designs. References [1] G. BORRIELLO AND E. DETJENS High-Level Synthesis: Current Status and Future Directions. Proc. 25th ACM/IEEE Design Automation Conference 25 (1988), pp. 477-482. [2] R. CAMPOSANO AND R. K. BRAYTON Partitioning before Logic Synthesis. IEEE Int. Conf. on Computer Aided Design, (1987), pp. 324-326. [3] R. CAMPOSANO AND W. ROSENSTIEL Synthesizing Circuits from Behavioral Descriptions. IEEE Trans. on Comp., 8 (February 1989), pp. 171-180. [4] N. CHRISTOFIDES Graph Theory: An Algorithmic Approach. Academic Press, 1975. [5] B. S. HAROUN AND M. I. ELMASRY Automatic Synthesis of a Multi-Bus Architecture for DSP. IEEE Int. Conf. on Computer Aided Design, 1988. [6] S.C. JOHNSON Hierarchical Clustering Schemes. Psychometrika, 3 (September 1967), pp. 241-254. [7] S. Y. KUNG, H. J. WHITEHOUSE AND T. KAILATH VLSI and Modern Signal Processing. Prentice Hall, (1985), pp. 256-264. [8] E. D. LAGNESE AND D. E. THOMAS Architectural Partitioning for System Level Design. Proc. 26th ACM/IEEE Design Automation Conference, 26(25-29 June 1989), pp. 62-67. [9] T. LENGAUER AND R. MULLER A Robust Framework for Hierarchical Floorplanning With Integrated Global Wiring. Int. Conf. on Computer Aided Design, 1990. [10] H. D. MAN, J. RABAEY, J. VANHOOF, G. GOOSSENS, P. SIX AND L. CLAESEN CATHEDRAL-II - a computer-aided synthesis system for digital signal processing VLSI systems. Computer-Aided Engineering Journal, (April 1988), pp. 55-66. [11] P. MARWEDEL The Mimola Design System: A Design System which spans several levels. IFIP Methologies for Computer System Design, (1985), pp. 223-237. [12] M. C. MCFARLAND Computer-Aided Partitioning of Behavioral Hardware Descriptions. 20th Design Automation Conference, (1983), pp. 472-478. [13] M. C. MCFARLAND Using Bottom-Up Design Techniques in the Synthesis of igital Hardware from Abstract Behavioral Descriptions. Proc. 23rd Design Automation Conference, 1986. [14] M. C. MCFARLAND Reevaluating the Design Space for Register-Transfer Hardware Synthesis. IEEE Int. Conf. on Computer Aided Design, 1987. [15] B. M. PANGRLE Splicer: A Heuristic Approach to Connectivity Binding. Proc. 25th ACM/IEEE Design Automation Conference, 1988. [16] N. PARK AND A. PARKER SEHWA: A Program for Synthesis of Pipelines. Proc. 23rd ACM/IEEE Design Automation Conference, 23(1986), pp. 454-460. [17] A. C. PARKER, J. T. PIZARRO AND M. MLINAR, MAHA: A Program for Datapath Synthesis. Proc. 23rd ACM/IEEE Design Automation Conference, 23(1986), pp. 461-466.

[18] P. G. PAULIN AND J. P. KNIGHT Force-Directed Scheduling for the Behavioral Synthesis of ASIC's. IEEE Trans. on CAD, 6(June 1989), pp. 661-679. [19] P. PFAHLER Automated Datapath Synthesis: A Compilation Approach. Microprocessing and Microprogramming, 21(1987), pp. 577-584. [20] D. E. THOMAS, E. M. DIRKES, R. A. WALKER, J. V. RAJAN, J. A. NESTOR AND R. L. BLACKBURN The System Architect's Workbench. Proc. 25th ACM/IEEE Design Automation Conference, 25(1988), pp. 337-343. [21] C-J. TSENG AND D. P. SIEWIOREK Automated Synthesis of Data Paths in Digital Systems. IEEE Trans. on CAD, 5(July 1986), pp. 379-395.


Data Path Construction and Refinement

Fur-Shing Tsai, Yu-Chin Hsu Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C.

ABSTRACT This paper describes a system for the data path allocation problem in digital signal processor synthesis. The system, STAR, consists of three phases -- preprocessing, data path construction (DPC), and data path refinement (DPR). The data structures are created in the preprocessing phase. In the DPC phase, data transfers are first bound to busses, followed by variable binding and operation assignment. The objects of interest (variables, operations, and data transfers) are divided into clusters of manageable size and a branch-and-bound search is performed in each cluster for each sub-task. In the DPR phase, the binding quality of the objects is evaluated, a cluster of mixed types of objects (variables, operations, and data transfers) is ripped up according to a relation network, and reallocated using a branch-and-bound method. Our contributions include: 1) theorems for the lower bound of the number of interconnections; 2) In the DPR phase, we take a more global view of the allocation problem by ripping up and reallocating different types of objects simultaneously; 3) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources which the object uses; 4) a method to judge the potential for upgrading a data path; and 5) an iterative improvement technique based on the idea of a relation network. The system currently supports the synthesis of architecture in linear topology and random topology. Parameters can be specified to explore different design alternatives and design space. Experiments on benchmarks show promising results. REFERENCES [1] D. E. Thomas, C. Y. Hitchcock, T. J. Kowalski, J. V. Rajan and R. A. Walker "Automated Data Path Synthesis" IEEE Computer, Vol. 21, pp. 59-70, Dec. 1983. [2] C. Tseng and D.P. Siewiorek "Automated Synthesis of Data Paths in Digital Systems" IEEE Trans. on CAD, pp. 379-395, July 1986. [3] B. M. Pangrle "Splicer: A Heuristic Approach to Connectivity Binding" Proc. of 25th Design Automation Conference, pp. 536-641, June 1988. [4] P.G. Paulin and J.P. Knight "Scheduling and Binding Algorithm for High Level Synthesis" Proc. of 26th Design Automation Conference, pp. 1-6, June 1989. [5] A.C. Parker, J. Pizarro and M.J. Mlinarr "MAHA: A Program for Data path Synthesis" Proc. of the 23rd Design Automation Conference, pp. 461-466, July 1986. [6] S. Devadas and A. R. Newton "Algorithms for Hardware Allocation in Data Path Synthesis" IEEE Trans. on CAD, pp. 768-781, July 1989. [7] B.S. Haroun and M.I. Elmasry "Architectural Synthesis for DSP Silicon Compiler" IEEE T-CAD, pp. 431-447, April 1989. [8] C. Y. Huang, Y. S. Chen, Y. L. Lin and Y. C. Hsu "Data Path Allocation Based on Bipartite Weighted Matching" Proc. of the 27th Design Automation Conference, June 1990. [9] H. DeMan, J. Rabaey, P. Six and L. Claesen "Cathedral-II: A Silicon Compiler for Digital Signal Processing" IEEE Design and Test, pp. 13-25, December 1986. Proc. of the 25th Design Automation Conference, pp. 337-343, June 1988.

[10] D. E. Thomas, E. M. Dirks, R. A. Walker, J. V. Rajan, J. A. Nester and R. L. Blackburn "The System Architect's Workbench" Proc. of the 25th Design Automation Conference, pp. 337-343, June 1988. [11] R. Jain, K. Kucukcakar, A. J. Mlinar and A. C. Parker "Experience with the ADAM Synthesis System" Proc. of the 26th Design Automation Conference, pp. 56-61, June 1989. [12] J. T. Hwang, J. H. Lee and Y. C.Hsu "A Formal Approach to the Scheduling Problem in High Level Synthesis" IEEE T-CAD April 1991. (to be appear)


Partial Scan by Use of Empirical Testability

Kee S. Kim, Charles R. Kime Dept. of Electrical and Computer Engineering, University of Wisconsin, Madison, Wisconsin 53706

Abstract Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan method proposed here is to obtain maximum fault coverage for the number of scan elements selected. Empirical Testability Difference (ETD), a measure of the potential improvement in the overall testability of the circuit, is used to successively select storage elements for scan. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the actual test sequence generator. In addition, ETD focuses on the hard-to-detect faults rather than all faults once such faults are known. The method has been extensively tested with ten of the ISCAS89 sequential circuits [1] using FASTEST [2]. The results of these tests indicate that ETD yields on average either 27 % of the number of uncovered faults for the same number of scan elements or 21 % fewer scan elements for the same fault coverage compared to the other methods studied. References [1] Brglez, F., D. Bryan, and K. Kozminski "Combinational Profiles of Sequential Benchmark Circuits" Proc. Int. Sym. Circuits and Systems, pp. 1929-1934, 1989. [2] Kelsey, T., and K. Saluja "Fast Test Generation for Sequential Circuits" Proc. Int. Conf. on Computer-Aided Design, pp. 354-357, 1989. [3] Seshu, S., and D. Freeman "The Diagnosis of Asynchronous Switching Systems" IRE Trans. of Elec. Computers, vol. EC-11, pp. 459-465, August 1962. [4] Williams, T., and K. Parker "Design for Testability - A Survey" Proc. IEEE, vol. 71, pp. 46-60, January 1973. [5] Trischler, E. "Incomplete Scan Path with an Automatic Test Generation Methodology" Proc. IEEE Test Conf., pp. 153-162, 1980. [6] Chen, T-H., and M. Breuer "Automatic Design for Testability Via Testability Measures" IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 3-11, January 1985. [7] Agrawal, V., and K-T. Cheng "An Economical Scan Design for Sequential Logic Test Generation" Dig. Int. Sym. Fault-Tolerant Computing, pp. 28-35, 1989. [8] Gupta, R., R. Gupta, and M. Breuer "BALLAST: A Methodology for Partial Scan Design" Dig. Int. Sym. Fault-Tolerant Computing, pp. 118-125, 1989. [9] Wunderlich, H. and A. Kunzmann "An Analytical Approach to the Partial Scan Problem" J. of Electronic Testing: Theory and Appl., vol. 1, pp. 163-174, May 1990. [10] Marlett, R., and S. Pollock "Guaranteeing ASIC Testability" VLSI Systems Design, pp. 70-73, 76, August 1988. [11] Ma, H-K., S. Devadas, A. Newton, and A. Sangiovanni-Vincentelli "An Incomplete Scan Design Approach to Test Generation for Sequential Machines" Proc. Int. Test Conf., pp. 730-734, 1988. [12] Goldstein, L., and E. Thigpen "SCOAP: Sandia Controllability/Observability Analysis Program" Proc. Design Automation Conf., pp. 190-196, 1980. [13] Jain, S., and V. Agrawal "Statistical Fault Analysis" IEEE Design & Test of Computers, vol. 2, pp. 38-44, February 1985.


Test Vector Minimization during Logic Synthesis

Tsu-Wei Ku (*), Wei-Kong Chia (*) Data General Corporation, Sunnyvale Division, 433 N. Mathilda Av. Sunnyvale, CA 94086-4299

(*)Currently with Hitachi Micro System, Inc Abstract This paper presents a new approach to minimize the 100% single-stuck (SS) fault test vector set of a synthesized circuit during the logic synthesis process. In the synthesis process for any given two-level primary and irredundant (PI) network, we first define a specific SS fault test vector set of the two-level network, and prove that it is a superset of the 100% SS fault test vector set for the synthesized circuit. Instead of generating all the vectors in this superset, we develop an algorithm to minimize this superset during the logic optimization and technology mapping process. Then, we generate the test vectors by using a two-level test generator. Our experimental data demonstrates that the resulted number of test vectors can be up to 40% less than that of the conventional method such as PODEM in many cases, while the additional CPU time used for test vector generation is about 5% of the conventional method in average. References [1] K.A. Bartlett, R.K. Brayton, G.D. Hatchel, R.M. Jocoby, A. Sangiovanni Vincentelli and A. Wang "Multilevel Logic Minimization Using Implicit Don't Cares" IEEE Trans. on CAD/ICAS, June. 1988 [2] G.D. Hachtel, R. Jacoby, K. Keutzer and C. Morrison "On Properties of Algebraic Transformations and the Multifault Testability of Multilevel Logic" Proc. International Conference on Computer-Aided Design, Nov, 1989. [3] R.K. Brayton, R. Rudell, A. Sangiovanni Vincentelli and A. Wang "MIS: A Multiple-Level Logic Optimization System" IEEE Trans. on CAD, Vol. CAD-6, No. 6, Nov. 1987. pp. 582-596. [4] S. Devadas, H.T. Ma, A.R. Newton and A. Sangiovanni-Vincentelli "Optimal Logic Synthesis and Testability: Two faces of the Same Coin" Proc. International Test Conference 1988, pp. 4-12. [5] R.K. Brayton, G.D. Hachtel, C. McMullen and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic publisher, 1984. [6] R.S. Wei and A.L. Sangiovanni-Vincentelli "New Front-End and Line Justification Algorithm for Automatic Test Generation" Proc International Test Conference 1986.


On Determining Scan Flip-Flops in Partial-Scan Designs

D. H. Lee, S. M. Reddy University of Iowa, Iowa City, IA 52242

Abstract In this paper we report on procedures investigated to determine flip-flops to be scanned in partial-scan designs for sequential circuits. The main idea pursued is to derive a minimal feedback vertex set of the so-called S-graphs. Results of applying optimal and heuristic procedures on a set of benchmark circuits indicate that heuristic methods give fast and near minimal solutions. References [1] F. Brglez, D. Bryan, and K. Kozminski. Combinational Profiles of Sequential Benchmark Circuits. Proc. of International Symposium on Circuits and Systems, pp. 1929-1934, May, 1989 [2] K. T. Cheng and V. D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, Vol. 39, No. 4, pp 544-548, April 1990 [3] R. Gupta, R. Gupta and M.A. Breuer. BALLAST: A Methodology for Partial Scan Design. Digest of Papers of the 9th International Symposium on Fault-Tolerant Computing, June 1989, pp 118-125 [4] R. M. Karp. Reducibility between combinatorial problems. Complexity of Computer Computations, R. E. Miller and J. W. Thatcher, Eds. New York: Plenum Press (1972), pp 85-103 [5] D. H. Lee and S. M. Reddy. On Determining Scan Flip-Flops in Partial-Scan Designs. Technical Report, Department of Electrical and Computer Engineering, University of Iowa [6] H. Levy and D. W. Low. A Contraction Algorithm for Finding Small Cycle Cutsets. Journal of Algorithm 9, 470-493 (1988) [7] E. L. Lloyd and M. L. Soffa. On Locating Minimum Feedback Vertex Sets. Journal of Computer and System Science 37, 292-311 (1988) [8] A. Miczo. Digital Logic Testing and Simulator. pp 98-115, 1986, Harper & Row, Publishers, Inc. [9] S. Patil, P. Banerjee. TGEN: An Automatic Test Pattern Generator for Sequential Circuits. CRHC Technical Report, University of Illinois, April 1990 [10] B. K. Rosen. Robust Linear Algorithm for Cutsets. Journal of Algorithms 3, 205-217 (1982) [11] S. Sahni University of Minnesota, Private Communication [12] A. Shamir. A Linear Time Algorithm for Finding Minimum Cutsets in Reducible Graphs. SIAM J. Computing Vol. 8, No. 4, November 1979, pp 645-655 [13] G. W. Smith and R. B. Walford. The Identification of a Minimal Feedback Vertex Set of a Directed Graph. IEEE Transactions on Circuits and Systems, Vol CAS-22, No. 1, January 1975 [14] C. Wang, E. L. Lloyd, and M. L. Soffa. Feedback Vertex Sets and Cyclically Reducible Graphs. Journal of the Association for Computing Machinery, Vol. 32, No. 2, April 1985, pp 296-313


A Fast Algorithm for Performance-Driven Placement

Michael A.B. Jackson, Arvind Srinivasan, E. S. Kuh Electronics Research Lab, University of California, Berkeley, C A 94720

Abstract We have developed an algorithm for the placement of small-cell ICs subject to performance constraints that is efficient in terms of speed and memory usage. The approach models wirelength using a nonlinear cost function like that of [TKH88] and a timing model which uses a block-oriented representation of paths like that of [JK89]. The timing constraints are implicitly represented using a network and nonlinear programming techniques are used to solve the wirelength minimization problem while satisfying the constraints. This allows critical paths to dynamically adjust while the placement changes to minimize wirelength. The solution of the nonlinear programming problem yields an initial placement of cells that may violate slot constraints. We propose hierarchical solution techniques to resolve the slot constraints. By exploiting structure inherent in the formulation, a large reduction is achieved in the number of variables that represent the problem. Additionally, developing special techniques to take advantage of the interaction between the timing model and the physical position of the cells enabled us to achieve a speed-up of 10-15 times over [JK89] even with a crude implementation of the algorithm. References [Hal70] K. M. Hall. An r-dimensional quadratic placement program. Management Science, 17(3):219-229, November 1970. [JK89] M. A. B. Jackson and E. S. Kuh. Performance-driven placement of cell-based ic's. In IEEE Proceedings of the 26th Design Automation Conference, pages 370-375, 1989. [Lue84] David G. Luenberger. Linear and Nonlinear Programming. Addison Wesley, Reading, Massachusetts, 1984. [SJK90] Arvind Srinivasan, Michael A.B. Jackson, and E.S. Kuh. A fast algorithm for performance driven placement. UCB ERL Memo, Electronics Research Laboratory, University of California, Berkeley., 1990. [TKH88] R. S. Tsay, E. S. Kuh, and C. P. Hsu. Proud: A sea-of-gates placement algorithm.IEEE Design and Test of Computers, pages 318-323, December 1988.


Congestion-Driven Placement Using a New Multi-Partitioning Heuristic

S. Mayrhofer, U. Lauther Corporate Research and Development, Siemens AG, Munich

Abstract We present a new hierarchical top down placement technique for circuits implemented in sea-of-gates design style. It is based on a new hypergraph multi-partitioning algorithm, whose time complexity is linear in the number of pins of a circuit. The partitioning algorithm uses Steiner trees for the modeling of net topologies, which allows taking wiring congestion into account during placement. This leads to a more sophisticated balance criterion compared to conventionel min-cut algorithms and consequently to a better distribution of active elements and wiring over the chip area. Experimental results show that the application of the new method improves the wireability of designs considerably. References [DuKe85] A.E. Dunlop, B.W. Kernighan. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. CAD, Vol. 4, No. 1, Jan. 1985, pp. 92-98. [FM82] C.M. Fiduccia, R.M. Mattheyses. A linear time heuristic for improving network partitions. Proc. 19th DAC, 1982, pp. 175 - 181. [Han66] M. Hanan. On Steiner's problem with rectilinear distance. SIAM Journal on applied Math., Vol. 14, 1966, pp. 255-265. [KL70] B.W. Kernighan, S. Lin. An efficient heuristic procedure for partitioning graphs. Bell Syst. Techn. J., Vol. 49, Feb 1970, pp. 291-307. [Kr84] B. Krishnamurthy. An improved min-cut algorithm for partitioning VLSI networks. IEEE Trans. on Comp., Vol. C-33, No. 5, May 1984, pp. 438-448. [KSJ89] J.M. Kleinhans, G. Sigl, F.M. Johannes. Sea-of-Gates placement by simultaneous quadratic programming combined with improved partitioning. Proc. of the Int. Conf. on Very Large Scale Integration, VLSI '89, 1989, pp. 445-454. [Lau79] U. P. Lauther. A Min-cut placement algorithm for general cell assemblies based on a graph representation. Proc. 16th DAC, 1979, pp. 1-10. [San89] L.A. Sanchis. Multiple-way network partitioning. IEEE Trans. on Comp., Vol. 38, No. 1, Jan 1989, pp. 62-81. [SK88] P.R. Suaris, G. Kedem. An Algorithm for Quadrisection and its application to standard cell placement. IEEE Trans. on CAS, Vol. 35, No. 3, March 1988, pp. 294-303. [SK89] P.R. Suaris, G. Kedem. A quadrisection-based combined place and route scheme for standard cells. IEEE Trans. on CAD, Vol. 8, No. 3, March 1989, pp. 234-244. [SaRa89] Y. Saab, V. Rao. An evolution-based approach to partitioning ASIC systems. Proc. 26th DAC, 1989, pp. 767-770. [Vij89] G. Vijayan Min-Cost partitioning on a Tree Structure and Applications. Proc. 26th DAC, 1989, pp. 771-774. [Vij90] G. Vijayan. Partitioning Logic to Optimize Routability on Graph Structures. Proc. of the Int. Symposium on Circuits and Systems ISCAS 1990, pp. 2638-2641.


New Algorithms for the Placement and Routing of Macro Cells

William Swartz, Carl Sechen Department of Electrical Engineering, Yale University

ABSTRACT This paper describes new algorithms for timing driven placement and routing of rectilinearly shaped macro cells. We present new algorithms for the implementation of simulated annealing, based on a theoretically derived statistical annealing schedule. We describe a negative feedback scheme that optimizes the relative weighting between the primary objective term and the penalty function terms in the cost function. A new placement refinement method has been developed for rectilinear cells which spaces the cells at density avoiding the need for post-routing compaction. In addition, a detailed routing method has been developed which avoids the classically difficult problem of defining channels for detailed routing. Our result for the ami33 benchmark circuit is better than the previously published results. REFERENCES [CRS87] A. Casotto, F. Romeo, and A. Sangiovanni-Vincentelli "A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells." IEEE Trans. on Computer-Aided Design of ICs and Systems 6/5 (1987): 838-847. [CS90] D. Chen and C. Sechen "Mickey: a Macro Cell Global Router." Int. Workshop on Layout Synthesis, May 8-11, 1990, MCNC, Research Triangle Park, NC. [dFZ87] Ph. de Forcrand, and H. Zimmermann "Timing-Driven Auto-Placement" Proc. Int. Conf on Comp. Design (1987): 518-521. [Gro89] P. Groeneveld "On Global Wire Ordering for Macro-Cell Routing." Proc. 26th Design Automation Conference (1989): 155-160. [HNY86] P. Hauge, R. Nair, and E. Yoffa "Circuit Placement for Predictable Performance." Proc. Int. Conf. on Computed-Aided Design (1987): 88-91. [JG83] D. Jepsen and C. Gelatt, Jr. "Macro placement by Monte Carlo annealing." Proc. Int. Conf on Comp. Design (1983): 495-498. [Lam88] J. Lam, J. M. Delosme, and C. Sechen "An Efficient Simulated Annealing Schedule for Row-Based Placement" accepted: Int. J. Computer-Aided VLSI Design. [Lam88b] J. Lam and J. M. Delosme "Performance of a New Annealing Schedule." Proc. 25th Design Automation Conf. (1988): 306-311. [ML89] M. Marek-Sadowska and S. Lin "Timing Driven Placement." Proc. Int. Conf. on Computed-Aided Design (1989): 94-97. [OI86] O. Yasushi, T. Ishii, et al. "Efficient Placement Algorithms Optimizing Delay for High-Speed ECL Masterslice LSI's." Proc. 23rd Design Automation Conference (1986): 404-410. [RP87] C.P. RaviKumar and L.M. Patnaik "Parallel Placement by Simulated Annealing" Proc. Int. Conf on Comp. Design (1987): 91-94 [SBD87] P. Siarry, L. Bergonzi, and G. Dreyfus "Thermodynamic Optimization of Block Placement." IEEE Trans. on Computer-Aided Design of ICs and Systems 6/2 (1987): 211-221. [SBS85] C. Sechen, D. Braun, and A. Sangiovanni-Vincentelli. "ThunderBird: A Complete Standard Cell Layout Package." IEEE J. of Solid-State Circuits 23/2 (1985): 410-420. [Sec88] C. Sechen "Chip-Planning, Placement, and Global Routing of Macro-Cell Integrated Circuits Using Simulated Annealing." Int. J. of Comp. Aided VLSI Design 2, (1990): 127-158. [Sec88b] C. Sechen. VLSI Placement and Global Routing Using Simulated Annealing. Kluwer Academic Publishers (1988).

[Shi87] H. Shin and A. Sangiovanni-Vincentelli "A Detailed Router Based on Incremental Routing Modifications: Mighty." IEEE Trans. Computer-Aided Design 6/6 (1987): 942-955. [SL87] C. Sechen and K. W. Lee "An Improved Simulated Annealing Algorithm for Row-Based Placement." Proc. Int. Conf. on Computed-Aided Design (1987): 478-481. [SS84] C. Sechen and A. Sangiovanni-Vincentelli "The TimberWolf Placement and Routing Package." Proc. Custom Integrated Circuits Conference (1984). [UCB90] A. Sangiovanni-Vincentelli, et al. "Mosaico: A Macro-Cell Layout System." To appear in: Int. J. of Computer Aided VLSI Design (1990). [WL86] D.F. Wong and C.L. Liu "A New Algorithm for Floorplan Design." Proc. 23rd Design Automation Conference (1986): 101-105. [WL87] D.F. Wong and C.L. Liu "Floorplan Design for Rectangular and L-Shaped Modules." Proc. Int. Conf. on Computed-Aided Design (1987): 520-523.


VLSI Placement using Uncertain Costs

Cheryl L. Harkness, Daniel P. Lopresti Department of Computer Science, Brown University, Providence, RI 02912

Abstract Many objective functions used to evaluate placement quality contain uncertain parameters (e.g., channel width, wire length). While these values can be estimated, they cannot be precisely known until the layout is finished. As a result, current automatic placement algorithms use "expected" values in their objective functions and return one possible estimate of placement quality. An algorithm that uses the full range of potential values when computing placement cost can yield a more credible prediction of placement quality and reveal more about the structure of optimal configurations. In this paper, we propose an interval-based approach to modeling uncertainty in automatic placement and illustrate our methods by implementing an interval branch and bound placement algorithm. References [1] B. Preas and P. Karger. Automatic placement: A review of current techniques. In 23rd IEEE Design Automation Conference, pages 622-629, 1986. [2] B. Preas and W. van Cleemput. Placement algorithms for arbitrarily shaped blocks. In 16th IEEE Design Automation Conference, pages 474-480, 1979. [3] M. Ciesielski and E. Kinnen. Digraph relaxation for CAD layouts of cell based integrated circuits. In 1983-84 Computer Science and Computer Engineering Research Review. University of Rochester, 1983-84. [4] R. Moore. Methods and Applications of Interval Analysis. SIAM, Philadelphia, 1979.


Distributed Methodology Management for Design-in-the-Large

Wayne Allen, Douglas Rosenthal, Kenneth Fiduk MCC, 3500 W. Balcones Center Dr. Austin, TX 78759

Abstract The MCC CAD Framework Methodology Management System (MMS) is used to describe and control distributed engineering activities in terms of a unified design methodology. Methodologies describe the interactions among design tools and design team members necessary to manage the concurrent design activities associated with design-in-the-large (DITL). A distributed Process Control Server (PCS) provides general process control, load balancing, and interprocess communication (IPC) services to effectively support methodology management activities using networked computing resources. References [1] Cooke, D., et al "Design Management In a Workstation Environment" Proc. 22nd Hawaii Int'l. Conf. on System Sciences. [2] Harrison, D., P. Moore, R. Spickelmier, and A. Newton "Data Management and Graphics Editing in the Berkeley Design Environment" Proceedings of ICCAD-86, November, 1986. [3] Daniell, James, and S. W. Director "An Object-Oriented Approach to CAD Tool Control Within a Design Framework" Proceedings 26th DAC, June, 1989, pp. 197-202. [4] Bushnell, Michael, and Stephen W. Director "Automated Design Tool Execution in the ULYSSES Design Environment" IEEE Trans. on Computer-Aided Design, Vol. 8, No. 3, March, 1989, pp. 279-287. [5] Vidovic, N., et al "Towards a Consistent View of the Design Tools and Process in a Distributed Problem Solving Environment" Proc. 22nd Hawaii Int'l Conf. on System Sciences. [6] Di Janni, Alberto "A Monitor for complex CAD systems" Proceedings 23th DAC, June, 1986, pp. 145-151. [7] Bershad, Brian "Load Balancing with Maitre'd" Technical Report UCB/CSD-85/276, Computer Science Department, University of California at Berkeley, December, 1985. [8] "HP Task Broker" HP Design and Automation, November, 1989. [9] Segall, Z, and Rudolph, L. "PIE - A Programming and Instrumentation Environment for Parallel Processing" Technical Report CMU-CS-85-128, Department of Computer Science, Carnegie-Mellon University, April, 1985. [10] Eager, D.L., Lazowska, E.D., and Zahorjan, J. "Adaptive Load Sharing in Homogeneous Distributed Systems" IEEE Trans. Software Eng., Vol. SE-12, No. 5, May, 1986. [11] Theimer, M.M., and Lantz, K. "Finding Idle Machines in a Workstation-Based Distributed System" IEEE Trans. Software Eng., Vol. 15, No. 11, November, 1989. [12] Su, W., Fuacette, R., and Seitz, C. "C Programmer's Guide to the COSMIC CUBE" CalTech Technical Report 5203:TR:85, 29 July, 1986.


Knowledge Based Design Flow Management

Felix Bretschneider, Christa Kopf, Helmut Lagger Siemens Central Research and Development, Otto-Hahn-Ring 6, D-8000 Munich 83, FRG

Arding Hsu, Elizabeth Wei

Siemens Corporate Research, Inc., 755 College Road East, Princeton, NJ, 08540, USA Abstract Due to the increasing complexity of electronic systems, system engineers and designers are confronted with a constantly increasing variety of highly specialized tools, which have to be integrated and executed under common supervision. Although, considerable efforts have been invested in the development of frameworks, most of them are concentrated on the issues regarding design data management and tool integration. A rather important part of a CAD framework, design flow management (tool executions), has often been neglected. In this paper, the knowledge regarding design flow management is described and modeled by Predicate-Transition Petri nets and production rules. The approach offers a clear and flexible tool control mechanism within a CAD framework such that both static and dynamic behavior of a design flow are supported. We also demonstrate how different forms of knowledge can be implemented by a rule based system OPS83 and be integrated in the existing CAD framework HILDA to guide the users through the design process. References [1] D. Harrison et al. Electronic CAD Frameworks. Department of Electrical Engineering and Computer Sciences, University of California, Berkley. [2] M. L. Bushnell. Automated Full-Custom VLSI Layout Using the ULYSSES Design Environment. Academic Press, 1988. [3] M. L. Bushnell, S. W. Director. Automated Design Tool Execution in the ULYSSES Design Environment. IEEE Transaction on Computer Aided Design, Vol. 8, No. 3, 1989, pp. 279-287. [4] J. Daniell, S. W. Director. An Object Oriented Approach to CAD Tool Control within a Design Framework. Proc. of 26th DAC, 1989, pp. 197-202 [5] M. Treffers et al. An Object-Oriented Modular Approach to Design Management. Proc. of IFIP VLSI 89 (Supplement). [6] F. Bretschneider, H. Lagger, B. Schulz. Infrastructure of Complex Systems – CAD Frameworks. Proc. of EUROCAST, 1989. [7] A. Hsu, L. Hsu. HILDA: An Integrated System Design Environment. Proc. of ICCD, 1987, pp. 398-402. [8] G. Rozenberg, P.S. Thiagrajan. Petri Nets: Basic Notations, Structure and Behavior. Lecture Notes of Computer Science 224, Springer Publishing Company, 1986, pp. 585-668. [9] G. Genrich. Predicate / Transition Nets. Lecture Notes in Computer Science 254, Springer Publishing Company, 1987, pp. 207-247. [10] N. Vidovic et al. Towards a Consistent View of the Design Tools and Process in Distributed Problem Solving Environments. 22nd Hawaii Int'l Conf. on System Sciences, 1989. [11] M. Yoo, A. Hsu. DEBBIE: A Configurable User Interface for CAD Frameworks. Proc. of ICCD, 1990. [12] C. Forgy. OPS83 User's Manual and Report. Production Systems Technologies, Inc.


A CAD Process Scheduling Technique

Toshiaki Miyazaki (Tanaka) (1), Tamio Hoshino, Makoto Endo NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-Shi Kanagawa Pref., 243-01

JAPAN (1)He changed his family name from 'Tanaka' to 'Miyazaki'.

Abstract This paper describes an integration system for VLSI design tools and their human-interface builder. The main advantage of this system is its unique process control mechanism. Once VLSI designers specify their tasks by using a flow-chart based graphic editor, the system can handle the design process and maintain the design data produced by each tool. References [1] D. Harrison et al. "Data Management and Graphics Editing in the Berkeley Design Environment" Proc. ICCAD Conference, pp. 240-27, Santa Clara, CA, November 1986. [2] M. Bushnell and S. W. Director "Automated Design Tool Execution in the Ulysses Design Environment" IEEE Trans. on Computer-Aided Design, Vol.8, No.3, March 1989. [3] J. Daniell and S. W. Director "An Object Oriented Approach to CAD Tool Control Within a Design Framework" Proc. 26th Design Automation Conference, pp. 197-202, Las Vegas, NV, June 1989. [4] "Design Framework manual" Cadence Design Systems Inc. [5] "DECframe/Electronics manual" Digital Equipment Corp. [6] "TekWave manual" Tektronics Corp. [7] "CFI Newsline" CAD Framework Initiative, Inc. Vol.1, Issue 3, November 1989. [8] S. I. Feldman "MAKE - A Program for Maintaining Computer Programs" Software Practice and Experience, Vol.9, No.4, pp.255-265, April 1979.


A History Model for Managing The VLSI Design Process

Tzi-cker Chiueh, Randy Katz Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720 Abstract A history model is proposed to support the dynamic aspects of VLSI design, i.e., the controlled and disciplined sequencing of CAD tool invocations. This model is based on a task specification language, for encapsulating CAD tool invocations, and a novel activity thread, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. A prototype has been implementation built on tope of the OCT CAD framework. References [BUSH89] M. Bushnell, S.W. Director "Automated design tool execution in the Ulysses design environment" IEEE Transactions on CAD", Vol.8, No.3, (March 1989). [CKV89] T.F. Chiueh, R.H. Katz, V. King "Managing the VLSI Design Process" UCB/CSD 89/538, University of California, Berkeley, Computer Science Division, (November 1989). [CK90] T.F. Chiueh, R.H. Katz "The Design Flow Management System : A Survey and A Synthesis" in preparation. [CASO90] A. Casotto, R. Newton, A. Sangiovanni-Vincentelli "Design Management based on Design Traces" 27th Design Automation Conference, Orlando, FL., June, 1990. [DANI89] J. Daniell, S.W. Director "An object-oriented approach to distributed CAD tool control" in IEEE Proc. 26th Design Automation Conference, Las Vegas, NV, (June 1989). [HARR90] Harrison, D.S., Newton, R.A., Spickelmier, R.L., Barnes, T.J. "Electronic CAD Framework" Proceedings of The IEEE, Vol. 78, No. 2, Feb. 1990, p393-417. [KATZ87] Katz, R. H., R. Bhateja, E. Chang, D. Gedye, V. Trijanto "Design Version Management" IEEE Design and Test, V 4, N 1, (February 1987). [King89] Valerie King "Task Specification and Management in the VLSI Design Process" UCB/CSD 89/533, Computer Science Division, U.C. Berkeley, September 1989. [OCT89] OCT Manual. U. C. Berkeley EECS Department Technical Report


On the Diagnostic Resolution of Signature Analysis

Janusz Rajski, Jerzy Tyszer, Babak Salimi VLSI Design Laboratory. Department of Electrical Engineering. McGill University, 3480 University Street.

Montreal, Canada H3A 2A7 Abstract In order to use linear feedback shift registers (LFSR's) efficiently and reliably in fault diagnosis, it is important to understand the relation between the length of the LFSR, the size of the circuit, which defines the size of the fault list, and the quality of diagnostic resolution. In this paper we develop an analytical model, verified experimentally, that determines the fraction of faults that are uniquely diagnosed for a given size of the circuit and the length of the LFSR. References [1] R.C. Aitken and V.K. Agarwal "A diagnosis method using pseudorandom vectors without intermediate signatures" Proc. ICCAD. 89, Santa Clara, USA, pp. 574-577, Nov. 1989. [2] P.H. Bardell, W.H. McAnney, and J. Savin. Built-In Self Test for VLSI: Pseudorandom Technique. New York: Wiley, Interscience, 1987. [3] E.J. McCluskey "Built-in self test techniques" IEEE Design and Test Magazine, vol. 2, No. 2, pp. 21-28, April 1985. [4] J.E. Smith "Measures of the effectiveness of fault signature analysis" IEEE Trans. Comput., vol. C-29, No. 6, pp. 510-514, June 1980. [5] J.A. Waicukauski, V.P. Gupta, and S.T. Patel "Diagnosis of BIST failures by PPSFP simulation" Proc. ITC 1987, Washington, DC, pp. 480-484, Sept. 1987. [6] T.W. Williams, W. Daehn, M. Gruetzner, and C.W. Starke "Comparison of aliasing errors for primitive and non-primitive polynomials" Proc. ITC 1986, Washington, DC, pp. 282-288, Sept. 1986.


Computing the Error Escape Probability in Count-Based Compaction Schemes

Andre Ivanov Dept. of Electrical Engineering, University of British Columbia, 2356 Main Mall, Vancouver British

Columbia, V6T 1W5, Canada

Yervant Zorian AT&T Bell Laboratories Engineering Research Center, P.O. Box 900, Princeton NJ 08540, U.S.A.

Abstract Two major types of response compactors proposed for Built-In Self-Test (BIST) are polynomial-division-based compactors, e.g., signature analysis, and count-based compactors, e.g., ones count. Compaction implies a possible loss of information that introduces the possibility that errors in the tested circuit response escape detection, this phenomenon being known as error escape, or aliasing. Much work has recently been performed toward establishing the performance of polynomial-division-based compactors with respect to error escape. Comparatively very few efforts have been aimed at count-based compaction. This paper presents a unified probabilistic model of count-based compaction that relates the probability of occurrence of the "counted" events to a circuit's fault detection probabilities. This model enables an identical treatment of all the different count-based techniques proposed to date, e.g., ones, transitions, edges, spectral coefficients. Based on this model, we propose a computation technique for determining the error escape associated with these specific, as well as more general count-based compaction techniques, under various error models. References [1] R. C. Aitken and V. K. Agarwal "Aliasing Probability of Non-Exhaustive Randomized Syndrome Tests" Proc. ICCAD, Nov. 1988, pp. 232-235. [2] R.A. Frohwerk "Signature Analysis: A New Digital Field Service method" Hewlett-Packard Journal, May 1977, pp. 2-8. [3] H. Fujiwara and K. Kinoshita "Testing logic Circuits with Compressed Data" Proc. FTCS-8, June 1978, pp. 108-113. [4] S. K. Gupta and D. K. Pradhan "A Framework for Designing & Analyzing BIST Techniques" Proc. ITC, Sept. 1988, pp. 329-342. [5] J. P. Hayes "Transition Count Testing of Combinational Logic Circuits" IEEE Trans. Comput., Vol. 25, No. 6, June 1976, pp. 613-620. [6] A. Ivanov and Y. Zorian "Aliasing in Output Data Modification under Unequally Likely Errors" AT&T Technical Memorandum, Dec. 1989. [7] J. C. Muzio, F. Ruskey, R.C. Aitken, and M. Serra "Aliasing Probabilities for Some Data Compression Techniques" Developments in IC Testing, D.M. Miller, ed., Academic Press, London, 1987. [8] K. P. Parker and E. J. McCluskey "Probabilistic Treatment of Combinational Networks" IEEE Trans. Comput., Vol. 24, No. 6, June 1975, pp. 668-670. [9] D. K. Pradhan, S. K. Gupta, and M. G. Karpovsky "Aliasing Probability for Multiple-Input Signature Analyzer" IEEE Trans. Comput., Vol. 39, No. 4, Apr. 1990, pp. 586-591. [10] J. P. Robinson and N. R. Saxena "Simultaneous Signature and Syndrome Compression" IEEE Trans. CAD, Vol. 7, No. 5, May 1988, pp. 584-589. [11] J. Savir "Syndrome-testable Design of Combinational Circuits" IEEE Trans. Comput., Vol. 29, No. 6, June 1980, pp. 442-451.

[12] N. R. Saxena and E. J. McCluskey "Arithmetic and Galois Checksums" Proc. ICCAD, Nov. 1989, pp. 570-573. [13] A. K. Susskind "Testing by Verifying Walsh Coefficients" IEEE Trans. Comput., Vol. 32, No. 2, Feb. 1983, pp. 198-201. [14] T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, "Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials" Proc. ITC, Sept. 1986, pp. 282-288. [15] H-J. Wunderlich "On Computing Optimized Input Probabilities for Random Tests" Proc. 24th ACM/IEEE DAC, June 1987, pp. 392-398. [16] D. Xavier, R. C. Aitken, A. Ivanov, V. K. Agarwal "Experiments on Aliasing in Signature Analysis" Proc. ITC, Aug. 1989, pp. 344-354. [17] Y. Zorian and V. K. Agarwal "A General Scheme to Optimize Error Masking in Built-In Self-Testing" Proc. FTCS-16, July 1986, pp. 410-415. [18] Y. Zorian and V. K. Agarwal "Optimizing Error Masking in BIST by Output Data Modification" Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 1, No. 1, Feb. 1990, pp. 59-71.


Partial Detectability Profiles

Paul G. Ryan, W. Kent Fuchs Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of

Illinois at Urbana-Champaign, Urbana, IL 61801

Abstract Partial detectability profiles are formed by randomly sampling each fault's detectability and are used in estimating the fault coverage of random input test vectors on combinational circuits. Partial detectability profiles are particularly useful for predicting fault coverage for large circuits with a large number of inputs. Predictions made using full and partial detectability profiles are compared. References [1] Y. Malaiya and S. Yang "The coverage problem for random testing" Proc. of the 1984 International Test Conf., pp. 237-242, Oct. 1984. [2] E. McCluskey, S. Makar, S. Mourad and K. D. Wagner "Probability models for pseudorandom test sequences" Proc. of the 1987 International Test Conf., pp. 471-479, Sept. 1987. [3] P. Bardell, W. McCanny, and J. Savir Built-In Test for VLSI: Pseudorandom Techniques. New York: J. Wiley and Sons, 1987. [4] J. Savir, G. Ditlow, and P. Bardell "Random pattern testability" IEEE Trans. on Computers, vol. C-33, pp. 79-90, Jan. 1984. [5] J. Savir and P. Bardell "On random pattern test length" IEEE Transactions on Computers, vol. C-33, pp. 467-474, June 1984. [6] V. Agrawal "Statistical Testing" in Testing and Diagnosis of VLSI and ULSI. F. Lombardi and M. Sami, Eds. New York: Kluwer Academic Publishers, pp. 33-47, 1988. [7] V. D. Agrawal and H. Kato "Fault sampling revisited" IEEE Design and Test of Computers, pp. 32-35, Aug. 1990. [8] C. Chin and E. McCluskey "Test length for pseudo random testing" IEEE Trans. on Computers, vol. C-36, pp. 252-256, Feb. 1987. [9] K. Wagner, C. Chin, and E. McCluskey "Pseudorandom testing" IEEE Transactions on Computers, vol. C-36, pp. 332-343, March 1987. [10] R. Hogg and E. Tanis Probability and Statistical Inference. New York: Macmillan Publishing Company, 1988. p. 613, 371-378. [11] F. Brglex and H. Fujiwara "Neutral netlist of ten combinational benchmark circuits and target translator in FORTRAN" Proc. of the IEEE International Symp. on Circuits and Systems, June 1985. [12] M. Schulz, E. Trischler and T. Sarfert "Socrates: a highly efficient automatic test pattern generation system" IEEE Trans. on Computer-Aided Design, vol. 7, pp. 126-136, Jan. 1988.


A Routing System for Mixed A/D Standard Cell LSI's

Ikuo Harada, Hitoshi Kitazawa, Takao Kaneko LSI Design Systems Laboratory, NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi Kanagawa

Pref., 243-01 Japan Abstract Global and detailed routing algorithms that minimize crosstalk noise between signal lines are described. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in the independent area of the digital nets as much as possible. Both the global and detailed routers minimize the number of signal-line crossovers, especially for analog nets, as these crossovers are dominant in crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. The experimental results show that the proposed algorithms are effective in reducing the number of crossover and redundant vias. References [1] C. D. Kimble, G. F. G. A. E. Dunlop, V. L. Hein, K. J. S. M. Y. Luong and E. J. Swanson "AUTOROUTED ANALOG VLSI" Proc. CICC'85, pp. 72-78(1985). [2] G. Winner, T. A. Nguyen and C. Slemaker "Analog Macrocell Assembler" VLSI SYSTEMS DESIGN, pp. 68-71(1987). [3] H. Yaghutiel, A. Sangiovanni-Vicentelli and P. R. Gray "A Methodology for Automated Layout of Switched-Capacitor Filters" Proc. IEEE ICCAD-86, pp. 444-447(1986). [4] A. Barlow, K. Takasuka, Y. Nambu, T. Adachi and J. Konno "AN INTEGRATED SWITCHED CAPACITOR FILTER DESIGN SYSTEM" Proc. IEEE CICC, pp. 4.5.1-4.5.5(1989). [5] J. Rijmenants, J. B. Litsios, T. R. Schwarz and M. G. R. Degrauwe "ILAC: An Automated Layout Tool for Analog CMOS Circuits" IEEE J. Solid-State Circuits, SC-24, 2, pp. 436-442(1989). [6] M. Kayal, S. Piguet, M. Declercq and B. Hochet "SALIM: A Layout Generation Tool For Analog ICs" Proc. IEEE CICC, pp. 7.5.1-7.5.4(1988). [7] D. J. Garrod, R. A. Rutenbar and L. R. Carley "Automatic Layout of Custom Analog Cells in ANAGRAM" Proc. IEEE ICCAD-88, pp. 544-547(1988). [8] M. Mogaki, N. Kato, Y. Chikami, N. Yamada and Y. Kobayashi "LADIES: An Automatic Layout system for Analog LSI's" Proc. IEEE ICCAD-89, pp. 450-453(1989). [9] R. S. Gyurcsik and J. Jeen "A Generalized Approach to Routing Mixed Analog and Digital Signal Nets in a Channel" IEEE J. Solid-State Circuits, SC-24, 2, pp. 436-442(1989). [10] K. Ueda, H. Kitazawa and I. Harada "Top-Down Layout for Hierarchical Custom Design" IEEE Design and Test of Computers, 4, 6, pp. 22-29(1987). [11] S. Tsukiyama, I. Harada, M. Fukui and I. Shirakawa "A New Global Router for Gate Array LSI" IEEE Trans. on CAD, CAD-2, 4, pp. 313-321(1983). [12] B. W. Kemighan, D. G. Scweikert and G. Persky "An Optimum Channel Routing Algorithm for Polycell Layouts of Integrated Circuits" Proc. of 10th DA Workshop, pp. 50-59(1973).


A Detailed Router for Field-Programmable Gate Arrays

Stephen Brown, Jonathan Rose, Zvonko Vranesic Dept. of Electrical Engineering, University of Toronto, Ontario, Canada M5S 1A4

Abstract The detailed routing of Field-Programmable Gate Arrays (FPGAs) is a new and difficult problem because the wiring segments available for routing can only be connected together in a limited number of ways. This paper presents the Coarse Graph Expansion (CGE) detailed routing algorithm for FPGAs. The algorithm has the ability to resolve routing conflicts by considering the side-effects of one connection on another, and can be used over a wide range of FPGA interconnection architectures. CGE has been used to obtain excellent routing results for several industrial circuits with various FPGA routing architectures. The results show that CGE is able to route relatively large FPGAs in the absolute minimum number of tracks as determined by global routing, and that CGE has a linear run-time over circuit size. References [Cart86] W. Carter et. al "A User Programmable Reconfigurable Gate Array" Proc. 1986 CICC, May 1986, pp. 233-235. [ElGa89] A. El Gamal, et. al "An Architecture for Electrically Configurable Gate Arrays" IEEE JSSC Vol. 24, No. 2, April 1989, pp. 394-398. [Gree90] J. Greene, V. Roychowdhury, S. Kaptanoglu, and A. El Gamal "Segmented Channel Routing" Proc. 27th DAC, pp. 567-572, June 1990. [Has71] A. Hashimoto, and J. Stevens "Wire routing by optimizing channel assignment within large apertures" Proc. 8th DAC, pp. 155-163, 1971. [Lee61] C. Lee "An algorithm for path connections and its applications" IRE Trans. on Electronic Computers, VEC-10, pp. 346-365, Sept. 1961. [Rose89] J.S. Rose, R.J. Francis, P. Chow, and D. Lewis "The Effect of Logic Block Complexity on Area of Programmable Gate Arrays" Proc. 1989 CICC, May 1989, pp. 5.3.1-5.3.5. [Rose90a] J. Rose, and S. Brown "The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays" Proc. 1990 CICC, pp. 27.5.1-27.5.4, May 1990. [Rose90b] J. Rose "Parallel Global Routing for Standard Cells" IEEE Transactions on CAD Vol. 9, No. 9, September 1990. [Wong89] S.C. Wong, H.C. So, J.H. Ou, J. Costello "A 5000-Gate CMOS EPLD with Multiple Logic and Interconnect Arrays" Proc. 1989 CICC, May 1989, pp. 5.8.1 - 5.8.4. [Xil89] The Programmable Gate Array Data Book, Xilinx Co., 1989.


Three-Dimensional Routing for Multilayer Ceramic Printed Circuit Boards

Akihiko Hanafusa, Yasuhiro Yamashita, Mitsuru Yasuda DA Development Department, Fujitsu Limited

Abstract This paper describes an efficient three-dimensional (3-D) routing technique for multiplayer ceramic printed circuit (PC) boards. The router can take account of via length as well as pattern length. In the first of the two steps involved, it searches in the direction of via depth from start and end points only. This is called two-and-a-half-dimension (2.5-D) routing. Step 2 combines 2-D and 3-D routing for wiring not covered in step 1. This enables tens of thousands of wires to be routed at 99% effectiveness in less than four hours of CPU time, with all delay conditions satisfied. References [1] M. Oda and T. Hamaguchi Oblique Routing System for FACOM M-780 SSC. Fujitsu Sci. Tech J., Vol. 23, No. 4, pp. 236-242 (1987). [2] N. Kuwahara et al. A Routing System for High-Performance Computer Systems. Proc. ICCAD-86, pp. 250-253 (1986). [3] Y. Fujihara et al. DYNAJUST: An Efficient Routing Technique Optimizing Delay Conditions. Proc. ACM IEEE 26th Design Autom. Conf., pp. 791-794 (1989). [4] M. Mikami and K. Tabuchi. A Computer Program for Optimal Routing of Printed Circuit Conductors. IFIP. Congress, pp. 1475-1478 (1968). [5] D.W. Hightower A Solution for Line-Routing Problem on the Continuous Plane. Proc. Design Autom. Workshop, pp. 1-24 (1969). [6] T. Tada and A. Hanafusa Router System for Printed Wiring Boards of Very High-Speed, Very-Large-Scale Computers. Proc. ACM IEEE 23rd Design Autom. Conf., pp. 791-797 (1986). [7] A. Hanafusa and T. Tada Router System for High-Density Multi-Layer Printed Wiring Boards. Proc. Printed Circuit World Convention IV, 3 (1987).


Simulating Electromagnetic Radiation of Printed Circuit Boards

H. Heeb, A. Ruehli, J. Janak, S. Daijavad IBM T. J. Watson Research Center, P. O. Box 218 Yorktown Heights, NY 10598

Abstract A realistic approach is introduced in this paper for the computation of the Electromagnetic radiation Interference (EMI) from printed circuit boards. In previous work the radiation from a single trace was investigated. Here, we give an approach which is suitable for large problems such that real circuit boards can be investigated. Each trace and its source and loads are represented as electrical circuits and a conventional time-domain circuit simulation is used to find the currents. The field is then calculated by applying the free-space Green's function to all currents including the polarization currents. This is, to our knowledge, the first CAD tool which can predict EMI from basic principles. References [1] M. Costa, T. K. Sarkar and B. J. Strait. On radiation from printed circuit boards. In IEEE Int. Symp. on EMC, pages 246-249, 1981. [2] S. Daijavad, J. Janak, H. Heeb, A. Ruehli and D. McBride. A fast method for computing radiation from printed circuit boards. In IEEE Int. Symp. on EMC, August 1990. [3] H. Heeb and A. Ruehli. Approximate time-domain models of three-dimensional interconnects. In ICCD, September 1990. [4] J. F. Janak, D. D. Ling and H.-M. Huang. C3DSTAR: a 3D wiring capacitance calculator. In ICCAD, pages 530-533, 1989. [5] R. F. Milsom, K. J. Scott, G. Clark, J. C. McEntegart, S. Ahmed and F. N. Soper. FACET - a CAE system for RF analogue simulation including layout. In DAC, pages 622-625, 1989. [6] C. R. Paul and D. R. Bush. Radiated emissions from common-mode currents. In IEEE Int. Symp. on EMC, pages 197-203, 1987. [7] R. Raut. On the computation of electromagnetic field components from a practical printed circuit board. In IEEE Int. Symp. on EMC, pages 167-170, 1986. [8] B. J. Rubin and S. Daijavad. Radiation and scattering from structures involving finite-size dielectric regions. In IEEE APS Int. Symp., 1990. [9] A. E. Ruehli. Equivalent circuit models for three dimensional multiconductor systems. IEEE Transactions on Microwave Theory and Techniques, MTT-22(3):216-221, MArch 1974. [10] P. K. Wolff and A. E. Ruehli. Inductance computations for complex three dimensional geometries. In ISCAS, pages 16-19, 1981. [11] W. M. Zuberek, A. Konczykowska and H. Wang. Distributed transmission lines and time-domain analysis using spice-like circuit simulators. In ISCAS, 1989.


SIMCURRENT - An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits

Ulrich Jagau

Laboratorium fur Informationstechnologie, Universitat Hannover, Schneiderberg 32, D-3000 Hannover 1, Fed. Rep. of Germany

ABSTRACT A new method for an efficient estimation of the current waveforms of complex CMOS macro cells or modules at the gate level is presented. A prototype computer program - SIMCURRENT - based on this method runs about 5000 times faster than state of the art analog circuit simulators, e.g. Spice for this purpose (analysis of the C432 circuit). The accuracy of the current estimation is in the range of about 5% - mean and rms current values - founded on simulation results done on layouted circuits. The investigations are based upon actual double layer Al CMOS processes used in the industry. The SIMCURRENT program enables the proper layout of power rails which fulfill mean and peak current limits for electromigration. These limits are derived from reliability calculations for the given process. Supported by the determined current waveforms, analog simulations taking into account electromagnetic coupling can be introduced. The calculation of the analog current waveform is based upon an event table which has been generated by a logic simulator taking the switching behavior of the different gates of a circuit regarding their actual load into account. For maximum current flow - peak and mean value within a defined timing window - optimal input pattern sequences are generated with a controlled pseudo-random pattern generator. The pattern estimator takes the analog behavior of the gates (e.g. fan-out, peak switching current, or mean current consumption of a gate) into consideration. Simulation results for various circuits are presented. REFERENCES [BuNa88] R. Burch, F. Najm, P. Yang, D. Hocevar "Pattern-Independent Current Estimation for Reliable Analysis of CMOS Circuits" DAC 88, pp. 294 - 299, 1988. [FeNi88] D.B.I. Feltham, P.I. Night, L.R. Carly, W. Maly "Current Sensing for Built-In Testing of CMOS Circuits" ICCD 88, pp. 454 - 457, October 1988. [Ciri87] M.A. Cirit "Estimating Dynamic Power Consumption of CMOS Circuits" ICCAD 87, pp. 534 - 537, November 1987. [ChBa90] S. Chowdhury, J.S. Barkatullah "Estimation of maximum Current in MOS IC Logic Circuits" IEEE Trans. on CAD, Vol. 9, No. 6, pp. 642 - 654, June 1990. [DeSh88] A.C. Deng, Y.C. Shiau, K.H. Loh "Time Domain Current Waveform Simulation of CMOS Circuits" ICCAD 88, pp. 208 - 211, November 1988. [DyGr89] K.-P. Dyck, H. Grabinski "A Time Domain Simulation Technique for Lossy Transmission Lines in VLSI Circuit Simulation" European Simulation Multiconference ESM 89, June 1989. [GrMu85] H. Grabinski, J.P. Mucha "A Numerical Approach to the Analysis of Signal Propagation on VLSI Interconnect Systems" ICCD 85, pp. 683 - 687, October 1985. [HaHo87] J.E. Hall, D.E. Hocevar, P. Yang, M.J. McGraw "Spider - A CAD System for Modeling VLSI Metalization Patterns" IEEE Trans. on CAD, Vol. CAD-6, No. 6, pp. 1023 - 1031, November 1987.

[JaDy90] U. Jagau, K.P. Dyck, H. Grabinski, H.J. Iden, M. Kuboschek "Power Distribution Strategies Based on Current Estimation and Simulation of Lossy Transmission Lines in conjunction with Power Isolation Circuits" IEEE Int. Conf. on Wafer Scale Integration, pp. 288 - 297, January 1990. [NaBu88] F. Najm, R. Burch, P. Yang, I. Hajj "CREST - A Current Estimator for CMOS Circuits" ICCAD 88, pp. 204 - 207, November 1988. [StHo88] D. Stark, M. Horowitz "Analyzing CMOS Power Supply Networks Using Ariel" DAC 88, pp. 460 - 464, 1988. [Tyag87] A. Tyagi "Hercules: A Power Analyzer for MOS VLSI Circuits" ICCAD 87, pp. 530 - 533, November 1987. [Veen84] H.J.M. Veendrick "Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits" IEEE Jour. of SSC, Vol. SC-19, No. 4, pp. 468 - 477, August 1984.


An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis

Y. Leblebici, S.M. Kang Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University of

Illinois at Urbana-Champaign, 1101 W. Springfield Avenue Urbana, IL 61801 ABSTRACT A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model used in the proposed simulation tool includes both of the fundamental device degradation mechanisms, i.e. charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. The proposed simulation tool provides information on the evolution of device degradation during long-term operation, and on the performance characteristics of the damaged circuit. REFERENCES [1] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Terrill "hot-electron-induced MOSFET degradation - model, monitor and improvement" IEEE Trans. Electron Devices, vol. ED-32, pp. 375-384, February 1985. [2] M.M. Kuo, K. Seki, P.M. Lee, J.Y. Choi, P.K. Ko and C. Hu "Simulation of MOSFET lifetime under AC hot-electron stress" IEEE Trans. Electron Devices, vol. 35, pp. 1004-1011, July 1988. [3] S. Aur, D. Hocevar and P. Yang "HOTRON - A circuit hot electron effect simulator" Proc. 1987 IEEE International Conference on Computer Aided Design, pp. 256-259, November 1987. [4] A.T. Yang and S.M. Kang "iSMILE : A novel circuit simulation program with emphasis on new device model development" Proc. 26th Design Automation Conference, pp.630-633, June 1989. [5] Y. Leblebici, S.M. Kang, C.T. Sah and T. Nishida "Modeling and simulation of hot electron effects for VLSI reliability" Proc. 1987 IEEE International Conference on Computer Aided Design, pp. 252-255, November 1987. [6] Y. Leblebici and S.M. Kang "Simulation of MOS circuit performance degradation with emphasis in VLSI design-for-reliability" Proc. 1989 IEEE International Conference on Computer Design, pp. 492-495, October 1989. [7] Y. Leblebici and S.M. Kang "A one-dimensional MOSFET model for simulation of hot-carrier induced device and circuit degradation" Proc. 1990 IEEE International Symposium on Circuits and Systems, pp. 109-112, May 1990.


Multi-level logic minimization across latch boundaries

Yusuke Matsunaga, Masahiro Fujita, Taeko Kakuda Artificial Intelligence Labs. Fujitsu Laboratories Ltd., 1015 Kamikodanaka, Nakahara-ku, Kawasaki 211,

Japan Abstract In this paper, a method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient Binary Decision Diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to BDD. Circuits including latches can be efficiently minimized with the proposed method. References [1] S. Malik, E.M. Sentovich, R.K. Brayton, and A. Sangiovanni-Vincentelli "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques" MCNC International Workshop on Logic Synthesis, North Carolina, May 1989. [2] R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and A.R. Wang "MIS: Multi-level interactive logic Optimization system" IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 6, pp.1062-1081, November 1987. [3] K.C. Chen and S. Muroga "SYLON-DREAM: A Multi-Level Network Synthesizer" IEEE International Conference on Computer Aided Design '89, Santa Clara, November 1989. [4] X. Xiang and S. Muroga "Synthesis of Multilevel Networks with Simple Gates" MCNC International Workshop on Logic Synthesis, North Carolina, May 1989. [5] S. Muroga, Y. Kambayashi, H.C. Lai and J.N. Culliney "The Transduction Method - Design of Logic Networks based on Permissible Functions" IEEE Trans. Comput., Vol.C-38, No.10, pp.1404-1424, October 1989. [6] Y. Matsunaga and M. Fujita "Multi-level Logic Optimization Using Binary Decision Diagrams" IEEE International Conference on Computer Aided Design '89, Santa Clara, November 1989. [7] H. Sato, Y. Yasue, Y. Matsunaga, and M. Fujita "Boolean resubstitution with permissible functions and Binary Decision Diagrams" 27th ACM/IEEE Design Automation Conference, June 1990. [8] R.E. Bryant "Graph-based algorithms for boolean function manipulation" IEEE Trans. Computer, C-35(8):667-691, August 1986. [9] G. De Micheli "Synchronous Logic Synthesis" MCNC International Workshop on Logic Synthesis, North Carolina, May 1989.


Performance Optimization of Pipelined Circuits

Sharad Malik, Kanwar Jit Singh, R.K. Brayton, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Science, University of California, Berkeley

Abstract We consider the problem of minimizing the cycle time of a given pipelined circuit. Existing approaches are sub-optimal since they do not consider the possibility of simultaneously resynthesizing the combinational logic and moving the latches using retiming. In [7] the idea of simultaneous retiming and resynthesis was introduced. We use the concepts presented there to optimize a pipelined circuit to meet a given cycle time. Given an instance of the pipelined performance optimization problem we construct an instance of a combinational speedup problem. We then give a constructive proof that the pipelined problem has a solution if and only if the combinational problem has a solution. This result is significant since it shows it is enough to consider only the combinational speedup problem and all known techniques for that (e.g. [9] [10]) domain can be directly applied to generate a solution for the pipelined problem. References [1] K. A. Bartlett, G. Boriello, and S. Raju. Timing optimization of multi-phase sequential logic. In Proceedings of the Hawaii International Conference on System Sciences, 1990. [2] C. L. Berman, J. L. Carter, and K. F. Day. The Fanout Problem: From Theory to Practice. In C. L. Seitz, editor, Advanced Research in VLSI: Proceedings of the 1989 Decennial Caltech Conference, pages 69-99. MIT Press, March 1989. [3] G. DeMicheli. Performance-oriented synthesis of large-scale domino CMOS circuits. IEEE Transactions on CAD, CAD-6(5):751-765, September 1987. [4] E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Technology mapping in MIS. In Proceedings of the International Conference on Computer-Aided Design, pages 116-119, 1987. [5] C. E. Leiserson, F. M. Rose, and J. B. Saxe. Optimizing synchronous circuitry by retiming. In Proceedings of the Third Caltech Conference on VLSI, 1983. [6] C. E. Leiserson and J. B. Saxe. Optimizing synchronous systems. In Proceedings of the Twenty-Second Annual Symposium on Foundations of Computer Science, pages 23-26, 1981. [7] S. Malik, E. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli. Retiming and resynthesis: Optimizing sequential networks with combinational techniques. In Proceedings of the Hawaii International Conference on System Sciences, 1990. [8] P. G. Paulin and F. Poirot. Logic Decomposition Algorithms for the Timing Optimization of Multi-Level Logic. In Proceedings of the International Conference on Computer Design, pages 329-333, 1989. [9] K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Timing Optimization of Combinational Logic. In Proceedings of the International Conference on Computer-Aided Design, pages 282-285, 1988. [10] H. Touati, C. Moon, R. K. Brayton, and A. Wang. Performance-oriented Technology Mapping. In Advanced Research in VLSI: Proceedings of the sixth MIT Conference. MIT Press, April 1990.


Don't Care Minimization of Multi-Level Sequential Logic Networks

Bill Lin, Herve J. Touati, A. Richard Newton University of California, Berkeley, CA 94720

Abstract The use of don't cares in synthesis has been recognized to have a profound effect on area, testability, and performance. The problem of computing internal don't care sets for combinational networks have been extensively studied. However, when sequential networks are considered, many new possibilities exists. In this paper, we address the problem of computing sequential don't cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to our approach is the use of BDD-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described in this paper, exact sequential don't care sets for circuits with over 1068 states have been successfully computed. References [1] K. Barlett, R.K. Brayton, G.D. Hachtel, R.M. Jacoby, C.R. Morrison, R.L. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang Multi-level logic minimization using implicit don't cares. IEEE Transactions on Computer-aided design, June 1988. [2] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. Mis: A multiple-level logic optimization system. IEEE Transactions on Computer-aided design, CAD-6(6):1062-1081, November 1987. [3] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 1986. [4] J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential circuit verification using symbolic model checking. In Proceedings of the Design Automation Conference, June 1990. [5] O. Coudert, C. Berthet, adn J.C. Madre. Verification of sequential machines using function vectors. In L.J.M. Claesen, editor, Formal VLSI Correctness Verification. Elsevier Science Publishers B.V., North Holland Press, 1990. [6] O. Coudert, C. Berthet, and J.C. Madre. Verification of synchronous sequential machines based on symbolic execution. In J. Sifakis, editor, Automatic Verification Methods for Finite State Systems. Springer-Verlag, June 1990. [7] S. Devadas, H.K. Ma, A.R. Newton, and A. Sangiovanni-Vincentelli. Irredundant sequential machines via optimal logic synthesis. IEEE Transactions on Computer-aided design, pages 8-18, January 1990. [8] Z. Kohavi. Switching and Finite Automata Theory. McGraw Hill Publishing Company, 1978. [9] H. Savoj and R.K. Brayton. The use of observability and external don't cares for the simplification of multi-level networks. In Proceedings of the Design Automation Conference, June 1990.


A Clock Net Reassignment Algorithm Using Voronoi Diagram

Masato Edahiro C&C Systems Research Labs, NEC Corp., 4-1-1 Miyazaki Miyamae-ku, Kawasaki 213, JAPAN

Abstract This paper presents a new algorithm for the clock net reassignment problem in the semi-custom layout design. The clock net reassignment is used to shorten clock nets by reconnecting clock drivers and flip-flops so as to obtain high performance LSIs. The proposed algorithm, by using the Voronoi diagram in computational geometry, is quite efficient and gives better assignments than the existing techniques. The experimental results show that the new algorithm makes 10% reduction of net lengths in comparison with the existing algorithm. The proposed algorithm takes only 18 seconds to find an assignment for 167 drivers and 833 flip-flops. References [1] M. R. Garey and D. S. Johnson Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman & Company, San Francisco, (1979) [2] E. L. Lawler Combinatorial Optimization: Networks and Matroids. Holt, Rinehart and Winston, New York, New York, (1976) [3] T. Ohya, M. Iri and K. Murota A Fast Voronoi-Diagram Algorithm with Quaternary Tree Bucketing. Information Processing Letters, Vol. 18, No. 4, pp. 227-231, (1984) [4] F. P. Preparata and M. I. Shamos Computational Geometry: An Introduction. Springer-Verlag, New York, New York, (1985) [5] K. Sugihara and M. Iri Geometric Algorithms in Finite-Precision Arithmetic. Research Memorandum RMI 88-10, Department of Mathematical Engineering and Instrumentation Physics, Faculty of Engineering, University of Tokyo, (1988)


An Exact Algorithm for Single-Layer Wire-Length Minimization

J.-M. Ho Inst. of Information Sciences Academia Sinica, R. O. C.

M. Sarrafzadeh, A. Suzuki

Department of EE & CS Northwestern University, Evanston, IL 60208 Abstract Consider a given single-layer detailed routing a set of two-terminal nets. We present the necessary and sufficient condition for a layout to have minimum length under homotopic transformations (i.e., without changing the given global routing). Based on the proposed classification and the notion of line-segment visiblity, we present an exact algorithm that minimizes the total wire-length of in O(n2) time, where in is the number of bends in For the class of x-monotone layouts (i.e., each vertical line crosses each wire at most once) an O(n log n) time algorithm is proposed. References [1] B. S. Baker and R. Y. Pinter "An Algorithm for the Optimal Placement and Routing of a Circuit within a Ring of Pads" Proceedings of the 24th FOCS, pp. 360-370, 1983. [2] C. P. Hsu "General River Routing Algorithm" Proceedings of the 20th Design Automation Conference, 1983, pp. 578-583. [3] K. F. Liao and M. Sarrafzadeh "Boundary Single-Layer Routing with Movable Terminals" Workshop on Graph-theoretic Concepts in Computer Science, W. Berlin, Germany, June 1990. [4] M. Marek-Sadowska and T. T. K. Tarng "Single-layer IEEE Transactions on Computer-Aided Design of Integrated Circuits, CAD-2(4): 246-259, October 1983. [5] D. Richards "Complexity of Single-layer Routing" IEEE Transactions on Computers, C-33(3), March 1984. [6] M. Schlag, F. Luccio, P. Maestrini, D. T. Lee, and C. K. Wong "A Visibility Problem in VLSI Layout Compaction" In F. P. Preparata, editor, Advances in Computing Research (VLSI Theory), 1984, Vol. 2, pp. 259-282.


A New Class of Steiner Tree Heuristics with Good Performance: the Iterated 1-Steiner Approach

Andrew Kahng, Gabriel Robins

UCLA Department of Computer Science, Los Angeles, California 90024 Abstract Virtually all previous methods for the rectilinear Steiner tree problem begin with a minimum spanning tree topology and rearrange edges to induce Steiner points. This paper gives a more direct approach: we iteratively find optimal Steiner points to be added to the layout. Our method gives improved average-case performance, and also escapes the worst-case examples of existing approaches. Sophisticated computational geometry techniques allow efficient and practical implementation, and the method is naturally suited to real-world VLSI regimes where, e.g., via costs can be high. Extensive performance results show almost 3 percent wirelength reduction over the best existing methods. We describe a number of variants and extensions, and suggest directions for further research. References [1] M. W. Bern "Two Probabilistic Results on Rectilinear Steiner Trees" Algorithmica 3 (1988), pp. 191-204. [2] D. Eppstein, G. Italiano, R. Tamassia, R. E. Tarjan, J. Westbrook and M. Yung "Maintenance of a Minimum Spanning Forest in a Dynamic Planar Graph" Proc. ACM-SIAM Symp. on Discrete Algs., 1990, pp. 1-11. [3] M. Garey and D. S. Johnson "The Rectilinear Steiner Problem is NP-Complete" SIAM J. App. Math. 32(4) (1977), pp. 826-834. [4] G. Georgakopoulos and C. H. Papadimitriou "The 1-Steiner Tree Problem" J. Algorithms 8 (1987),pp. 122-130. [5] E. N. Gilbert and H.O. Pollak "Steiner Minimal Trees" SIAM J. App. Math. 16 (1968), pp. 1-29. [6] M. Hanan "On Steiner's Problem With Rectilinear Distance" SIAM J. App. Math. 14 (1966), pp. 255-265. [7] N. Hasan, G. Vijayan and C. K. Wong "A Neighborhood Improvement Algorithm for Rectilinear Steiner Trees" Proc. of ISCAS, 1990. [8] J.-M. Ho, G. Vijayan and C. K. Wong "New Algorithms for the Rectilinear Steiner Tree Problem" IEEE Trans. on Computer-Aided Design, 9(2), 1990, pp. 185-193. [9] F. K. Hwang "On Steiner Minimal Trees with Rectilinear Distance" SIAM J. App. Math. 30(1) (1976), pp. 104-114. [10] F. K. Hwang "The Rectilinear Steiner Problem" J. Design Automation and Fault-Tolerant Computing (1978), pp. 303-310. [11] A. Kahng and G. Robins "On Performance Bounds for Two Rectilinear Steiner Tree Heuristics in Arbitrary Dimension" 1990, submitted to IEEE Trans. on Computer-Assisted Design. [12] A. Kahng and G. Robins "A New Family of Steiner Tree Heuristics With Good Performance: The Iterated 1-Steiner Approach" Technical Report, UCLA CS Department, \#CSD-900014., April 1990. [13] F. P. Preparata and M. I. Shamos. Computational Geometry: An Introduction. New York, Springer-Verlag, 1985. [14] D. Richards "Fast Heuristic Algorithms for Rectilinear Steiner Trees" Algorithmica 4 (1989), pp. 191-207.

[15] M. Sarrafzadeh and C. K. Wong "Hierarchical Steiner Tree Construction in Uniform Orientations" draft, 1990. [16] J. M. Smith and J. S. Liebman "Steiner Trees, Steiner Circuits and the Interference Problem in Building Design" Engineering Optimization 4 (1979), pp. 15-36. [17] J. M. Smith, D. T. Lee and J. S. Liebman "An O(N log N) Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem" Engineering Optimization 4 (1980), pp. 179-192. [18] T. L. Snyder "A Simple and Faster Algorithm for the Rectilinear Steiner Problem in General Dimension" Proc. ACM Symp. on Comp. Geometry, 1990, to appear. [19] P. Winter "Steiner Problem in Networks: A Survey" Networks 17 (1987), pp. 129-167.


Rectilinear Steiner Tree Construction by Local and Global Refinement

Ting-Hai Chao1,2, Yu-Chin Hsu 1 1Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C.

2Computer and Communication Laboratory, Industrial Technology Research Institute, Hsinchu, Taiwan 31015, R.O.C.

Abstract This paper presents a new algorithm for constructing a rectilinear Steiner tree (RST) of a given set of points. The algorithm works by incrementally introducing Steiner points from a rectilinear minimum spanning tree (MST) and generating a refined Steiner tree. Steiner points are introduced in two stages according to their essentiality and cost. In the first stage, they are generated from the local structure of the tree; in the second stage, they are generated from the global structure using a loop detection method. The proposed algorithm outperforms most of other algorithms by the fact that the average cost improvement over the rectilinear minimum spanning tree is 10.6% and its time complexity is O(n2logn). References [1] M. R. Garey, and D. S. Johnson "The Rectilinear Steiner Tree Problem is NP-Complete" SIAM Journal of Applied Mathematics, Vol. 32, No. 4, 1977, pp. 37-58. [2] M. Hanan "On Steiner's Problem with Rectilinear Distance" SIAM Journal of Applied Mathematics, Vol. 14, No. 2, 1966, pp. 255-265. [3] A. V. Aho, M. R. Garey, and F. K. Hwang "Rectilinear Steiner trees,: Efficient special-case algorithms" Network, vol. 7, 1977, pp. 37-58. [4] J. P. Cohoon, D. S. Richard, and J. S. Salowe "An optimal Steiner Tree Algorithm for a Net Whose Terminals Lie on the Perimeter of a Rectangle" IEEE Transaction on Computer-Aided Design, Vol. 9, No. 4, April 1990, pp. 398-407. [5] Y. Y. Yang, and O. Wing "Suboptimal Algorithm for a Wire Routing Problem" IEEE Transaction on Circuits Theory, September 1972, pp. 508-511 [6] J. H. Lee, N. K. Base, and F. K. Hwang "Use of Steiner's Problem in Suboptimal Routing in Rectilinear Metric" IEEE Transaction on Circuit and System, Vol. CAS-23, No. 7, July 1976, pp. 470-476. [7] F. K. Hwang "An O(n log n) Algorithm for Suboptimal Rectilinear Steiner Trees" IEEE Transactions on Circuits and Systems, Vol. CAS-26, No. 1, January 1979, pp. 75-77. [8] K-W. Lee, and C. Sechen "A New Global Router for Row-based Layout" Digest of Technical Papers, ICCAD-88, November 1988, pp. 180-183. [9] J-M. Ho, G. Vijayan, C. K. Wong "New Algorithms for Rectilinear Steiner Trees" IEEE Transaction on Computer-Aided Design, Vol. 9, No. 2, February 1990, pp. 161-166. [10] F. K. Hwang "On Steiner Minimal Tree with Rectilinear Distance" SIAM Journal of Applied Mathematics, Vol. 330, No. 1, January 1976, pp. 104-114.


Circuit Simulation Algorithms on a Distributed Memory Multiprocessor System

John A. Trotter, Prathima Agrawal AT&T Bell Labs., Murray Hill, NJ, 07974.

Abstract Circuit simulation involves the repeated solution of circuit nodal equations. Direct methods using matrix factorization provide accurate and stable solutions. Because the factorization is repeated many times it takes up a large proportion of CPU time. However, the speed of factorization can be improved by using multiprocessor architectures and parallel algorithms. Shared memory multiprocessors have failed to achieve large speedups because of the processor to memory bottleneck, which gets worse as more processors are used. In this paper we match a distributed memory architecture to the problem to overcome the processor to memory bottleneck. We study parallel source row and target row directed matrix factorization algorithms where the operations are precompiled at the row level. Our contribution is in the formulation and analysis of these factorization algorithms for a distributed memory architecture. We evaluate the effectiveness of our approach for processor utilization, memory accesses and communication costs for large matrices corresponding to real VLSI circuits. We show quantitatively, using the above metrics, that the source row factorization scheme is the most effective. References [1] Duff I.S., Erisman A.M. and Reid J.K. "Direct Methods for Sparse Matrices" Oxford University Press, London, U.K. 1986. [2] Nagel, L.W. "SPICE2: A computer program to simulate semiconductor circuits" Memo No. ERL-M520, Electronics Research Lab. University of California, Berkeley, May 1975. [3] Nagel, L.W. "ADVICE for circuit simulation" Proc. IEEE ISCAS 80 Texas, 1980. [4] Dongarra J.J., Gustavson F.G. and Karp A. "Implementing Linear Algebra Algorithms for Dense Matrices on Vector Pipeline Machines" SIAM Rev. Vol. 26, No. 1, pp. 91-112, 1984. [5] Sadayappan P. and Visvanathan V. "Circuit Simulation on Shared-Memory Multiprocessors" IEEE Trans. Computers Vol. 37, No. 12. pp.1634-1642, Dec. 1988. [6] Weeks W., Jimenez A., Malroney G., Mehta D., Qassemzadeh H and Scott T. "Algorithms for ASTAP - A Network Analysis Program" IEEE Tans Circuit Theory, Vol. CT-20, pp. 628-634, Nov. 1973.


Parallel Simulation Algorithms for Grid-Based Analog Signal Processors

L. Miguel Silveira, Andrew Lumsdaine, Jacob K. White Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science,

Massachusetts Institute of Technology, Cambridge, MA 02139 ABSTRACT In this paper, specialized algorithms for circuit-level simulation of grid-based analog signal processing arrays on a massively parallel processor are described and implementation results presented. In our approach, the trapezoidal rule is used to discretize the differential equations that describe the analog array behavior, Newton's method is used to solve the nonlinear equations generated at each time-step, and a block conjugate-gradient squared algorithm is used to solve the linear equations generated by Netwon's method. Excellent parallel performance of the algorithm is achieved through the use of a novel, but very natural, mapping of the circuit data onto the massively parallel architecture. The mapping takes advantage of the underlying computer architecture and the structure of the analog array problem. Experimental results demonstrate that a full-size Connection Machine can provide a 1400 times speedup over a SUN-4/280 workstation. References [Burch89] R. Burch, K. Mayaram, J.-H. Chern, P. Yang, P. Cox "PGS and PLUCGS - Two New Matrix Solution Techniques for General Circuit Simulation" Proc. ICCAD-89, pp. 408 - 411, Nov. 1989. [Hillis85] W.D. Hillis The Connection Machine, MIT Press, Cambridge, MA, 1985. [Lumsdaine90] A. Lumsdaine, J. Wyatt, and I. Elfadel "Nonlinear Analog Networks for Image Smoothing and Segmentation" Proceedings of the International Symposium on Circuits and Systems, pp. 987 - 991, May, 1990. [Mead88] C. A. Mead Analog VLSI and Neural Systems, Addison-Wesley, Reading, MA, 1988. [Nagel75] L. W. Nagel "SPICE2: A Computer Program to Simulate Semiconductor Circuits" Electronics Research Lab Report, ERL M520, Univ. of Calif., Berkeley, May 1975. [Silveira90] L. M. Silveira "Circuit Simulation Algorithms for Massively Parallel Processors" S. M. Thesis, MIT, May 1990. [Simlab] A. Lumsdaine, M. Silveira, and J. White "Simlab Programmer's Guide" To be published as an MIT memo. [Sonneveld89] P. Sonneveid "CGS, A Fast Lanczos-type Solver for Nonsymmetric Linear Systems" SIAM J. Sci. Stat. Comp., 10(1989), pp. 36-52. [Tong 88] C. Tong "The Preconditioned Conjugate Gradient on the Connection Machine" Proceedings of the Conference on Scientific Applications on the CM, Horst D. Simon, ed., pp. 188-213, World Scientific, Singapore, 1988. [Webber87] D. M. Webber, A. Sangiovanni-Vincentelli "Circuit Simulation on the Connection Machine" 24th ACM/IEEE Design Automation Conf., pp. 108-113, June 1987. [Wyatt88] J. Wyatt, et al Smart Vision Sensors: Analog VLSI Systems for Integrated Image Acquisition and Early Vision Processing, Proposal, MIT, 1988.


A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations

K. Mayaram, P. Yang, J. Chern, R. Burch, L. Arledge, P. Cox

Semiconductor Process and Design Center, Texas Instruments Incorporated, Dallas, TX 75265 Abstract We present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The new solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and BJT circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a new matrix partitioning scheme. References [1] J. Deutsch and R. Newton "MSPLICE: A Multiprocessor Based Circuit Simulator" Proc. 1984 Int. Conf. Par. Proc., 1984. [2] J. White "The Multirate Integration Properties of Waveform Relaxation with Application to Circuit Simulation and Parallel Computation" Memo. No. UCB/ERL 85/90, Electronics Research Laboratory, University of California, Berkeley, Nov. 1985. [3] R. Saleh "Nonlinear Relaxation Algorithms for Circuit Simulation" Memo. No. M87/21, Electronics Research Laboratory, University of California, Berkeley, April 1987. [4] G. K. Jacob "Direct Methods in Circuit Simulation Using Multiprocessors" Memo. No. UCB/ERL 87/67, Electronics Research Laboratory, University of California, Berkeley, 1987. [5] P. Sadayappan and V. Visvanathan "Circuit Simulation on a Multiprocessor" Proc. IEEE 1987 CICC, May.1987 [6] C. Yuan, R. Lucas, P. Chan, and R. Dutton "Parallel Electronic Circuit Simulation on the iPSC System" Proc. IEEE 1988 CICC, May.1988 [7] P. Cox, R. Burch, D. Hocevar, and P. Yang "SUPPLE: Simulator utilizing parallel processing and latency exploitation" Proc. ICCAD-87, Nov. 1987. [8] D. M. Webber and A. Sangiovanni-Vincentelli "Circuit Simulation on the Connection Machine" Proc. 24th ACM/IEEE Design Automation Conf., June 1987. [9] D. Dumlugol, P. Odent, J. P. Cockx, and H. J. DeMan "Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and its Acceleration on Parallel Computers" IEEE Trans. CAD, vol. CAD-6, Nov. 1987. [10] D. W. Smart "Parallel Processing Techniques for the simulation of MOS VLSI Circuits using Waveform Relaxation" Tech. Report UILU-ENG-88-2237, University of Illinois, Urbana-Champaign, July 1988. [11] P. Saviz and O. Wing "Pyramid - A Hierarchical Waveform Relaxation Based Circuit Simulation Program" Proc. ICCAD-88, Nov. 1988. [12] R. Lucas "Solving Planar Systems of Equations on Distributed-Memory Multiprocessors" Ph. D. Dissertation, Stanford University, Stanford, Dec. 1987. [13] R. Guerrieri and A. Sangiovanni-Vincentelli "Three-Dimensional Capacitance Evaluation on a Connection Machine" IEEE Trans. CAD, vol. 7, Nov. 1988. [14] R. Guerrieri, A. Sangiovanni-Vincentelli, E. Tomacruz, T. Toyabe, D. Webber "Massively Parallel Algorithms for Three-Dimensional Device Simulation" NUPAD 1990, June 1990. [15] A. Yajima, F. Yamamoto, T. Morioka "Complete LU Decomposition Conjugate Residual Method and its Performance for Large-Scale Circuit Simulation" Proc. IEEE ISCAS, Helsinki, Finland, June 1988.

[16] R. Burch, K. Mayaram, J. H. Chern, P. Yang, and P. Cox "PGS and PLUCGS – Two New Matrix Solution Techniques for General Circuit Simulation" Proc. ICCAD-89, Nov. 1989. [17] J. H. Chern, J. T. Maeda, L. A. Arledge, and P. Yang "SIERRA: A 3-D Device Simulator for Reliability Modeling" IEEE Trans. CAD, vol. 8, May 1989. [18] M. Hestenes and E. Stiefel "Methods of Conjugate Gradients for Solving Linear Systems" J. Research Natl. Bureau of Standards, vol. 49, Dec. 1952. [19] H. C. Elman "Iterative Methods for Large, Sparse, Nonsymmetric Systems of Linear Equations" Report 229, Dept. of Computer Science, Yale University, April 1982. [20] C. den Heijer "Preconditioned Iterative Methods for Nonsymmetric Linear Systems" Proc. Intl. Conf. Simulation of Semiconductor Devices and Processes, Pineridge Press, Swansea, 1984. [21] J. Chern, K. Mayaram, L. Arledge, P. Yang, J. Maeda, P. Hagelstein "A Concurrent Conjugate-Gradient-Based 3-D Device Equation Solver Including Latency" NUPAD 1990, June 1990.


Fast Overlapped Scattered Array Storage Schemes for Sparse Matrices.

John A. Trotter, Prathima Agrawal AT&T Bell Labs., Murray Hill, NJ. 07974

Abstract The problem of manipulating a large number of linear equations occurs in many applications including circuit simulation. By storing only the non-zero elements of the matrix considerable memory space can be saved, allowing larger matrices to be processed. This requires efficient matrix storage and access schemes. Several schemes have been proposed to accomplish this but there appears to be a tradeoff between the achievable packing density and CPU time. This paper presents several new heuristic schemes for storing large sparse matrices in memory. These heuristics exploit the distribution of the zero and non-zero elements of the matrix rather than just the number of non-zeros. Their performance ranges from very high packing density and acceptable processing time to extremely fast but acceptable packing density. Our best packing density is comparable to the Ziegler scheme but at only 20% of the CPU time. The fastest scheme is about two orders of magnitude faster than the Ziegler method [3] but achieves only about 60% of its packing density. Example matrices from circuit simulation data illustrate the superiority of our schemes. References [1] Tarjan, R. and Yao, A. "Storing A Sparse Table" Comm ACM Nov 79, Vol22 No.11. pp. 606-611. [2] Sadayappan P. and Visvanathan V. "Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers" IEEE Trans. CAD Vol 8. No. 12, Dec 89, pp. 1276-1285. [3] Ziegler S. "Smaller Faster Table Driven Parser" Maddison Academic Computer Center, University Wisconsin, Maddison, WI 1977. Unpublished work. [4] Nagel, L.W. "SPICE2: A computer program to simulate semiconductor circuits" Memo No. ERL-M520, Electronics Research Lab. University of California, Berkeley, May 1975. [5] Nagel, L.W. "ADVICE for circuit simulation" Proc ISCS 80, Houston Texas, April 1980. [6] Sadayappan P. and Visvanathan V. "Circuit simulation on shared memory multiprocessors" IEEE Trans. Comp. Vol. 37, No. 12, Dec 88. [7] Eisenstat S.C., Gursky M.C. Schultz M.H. and Sherman A.H. "Yale Sparse Matrix Package II: The nonsymetric codes." Res. Rep. 114, Yale Univ. Comp. Sci. Dept., 1977. [8] Duff I.S. "MA28 - A Set of FORTRAN Subroutines for Sparse Unsymetric Linear Equations" AERE Rep. R 8730, HMSO London, U.K. 1977. [9] Duff I.S., Erisman A.M. and Reid J.K. "Direct Methods for Sparse Matrices" Oxford University Press, London, U.K. 1986. [10] Rao S., Ackland B., London T. and Hatamian M. "Perfect Hashing for Sparse Matrix Elimination" Private Communication. July 1988. [11] Trotter J. and Agrawal P. "Circuit Simulation Algorithms on a Distributed Memory Multiprocessor System" Proc. IEEE ICCAD, Nov. 1990.


Testability-Preserving Circuit Transformations

Michael J. Bryan, Srinivas Devadas MIT, Cambridge, MA

Kurt Keutzer

AT&T Bell Labs, Murray Hill, NJ Abstract We first consider the synthesis of robustly path-delay-fault testable circuits and show that a single property, ENF reducibility, allows us to unify previous results on robust delay fault testability and multifault testability as well as to prove new ones. We use the notion of ENF reducibility to show that a constrained version of a common area improving transformation, namely algebraic resubstitution with complement, retains robust path-delay-fault testability. Thus, a more efficient means of synthesizing fully robustly path-delay-fault testable networks is given. We use the same property of ENF reducibility to show that constrained algebraic resubstitution with complement retains multifault irredundancy. We next present necessary and sufficient conditions for transistor stuck-open fault testability in arbitrary, multilevel networks, and show that algeraic factorization, including the constrained use of the complement, can be used to synthesize fully stuck-open fault testable multilevel networks. Finally, we provide a comprehensive set of practical results. References [1] D. B. Armstrong. On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets. IEEE Transactions on Computers, EC-15(2):66-73, February 1966. [2] S. Devadas and K. Keutzer. Necessary and Sufficient Conditions for Robust Delay-Fault Testability of Logic Circuits. In Sixth MIT Conference on Advanced Research on VLSI, pages 221-238, April 1990. [3] S. Devadas and K. Keutzer. Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Logic Circuits. In Proceedings of the 27th Design Automation Conference, pages 221-227, June 1990. [4] G. D. Hachtel, R. M. Jacoby, K. Keutzer, and C. R. Morrison. On the Relationship Between Area Optimization and Multifault Testability of Multilevel Logic. In Int'l Conference on Computer-Aided Design, pages 422-425, November 1989. (Extended version submitted to IEEE TCAD). [5] N. K. Jha and S. Kundu. Testing and Reliable Design of CMOS Circuits. Kluwer Academic Publishers, 1990. [6] I. Kohavi and Z. Kohavi. Detection of multiple faults in combinational logic networks. IEEE Transactions on Computers, C21(6):556-568, June 1972. [7] S. Kundu, S. M. Reddy, and N. K. Jha. On the Design of Robust Multiple Fault Testable CMOS Combinational Logic Circuits. In Proceedings of the Int'l Conference on Computer-Aided Design, pages 240-243, November 1988. [8] A. Pramanick and S. Reddy. On the design of path delay fault testable combinational circuits. In Proceedings of the 20th Fault Tolerant Computing Symposium, June 1990. [9] S. M. Reddy, M. K. Reddy, and J. G. Kuhl. On Testable Design for CMOS Logic Circuits. In Proceedings of the Int'l Test Conference, pages 435-455, October 1983.


Timing Optimization with Testability Considerations

Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli University of California – Berkeley, CA

Kwang-Ting Cheng

AT&T Bell Laboratories, Murray Hill NJ Abstract Since redundancy is undesirable in high performance circuits, in this paper we explore timing optimization procedures to determine whether performance optimization may be achieved without introducing redundancy. We demonstrate the conditions under which timing optimization may introduce single stuck-fault redundancies into a given irredundant circuit and illustrate the difficulties in removing or preventing these redundancies. We then resolve the question of whether a testability criterion exists that may be retained or easily maintained as invariant during timing resynthesis. References [1] K. Bartlett, R. Brayton, G. Hachtel, R. Jacoby, C. Morrison, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Multi-level logic minimization using implicit don't cares. IEEE Transactions on Computer-Aided Design, 7(6): 723-740, June 1988. [2] S. Devadas and K. Keutzer. Necessary and sufficient conditions for robust delay-fault testability of combinational logic circuits. In The Proceedings of the 6th MIT Conference on Advanced Research in VLSI, April 1990. [3] G. Hachtel, R. Jacoby, K. Keutzer, and C. Morrison. On properties of algebraic transformations and the multifault testability of multilevel logic. In The Proceedings of the International Conference on Computer-Aided Design, November 1989. [4] K. Keutzer, S. Malik, and A. Saldanha. Is redundancy necessary to reduce delay? In The Proceedings of the Design Automation Conference, June 1990. [5] P.McGeer and R. Brayton. Provably correct critical paths. In The Proceedings of the Decennial Caltech VLSI Conference, 1989. [6] A. Pramanick and S. Reddy. On the design of path delay fault testable combinational circuits. In The Proceedings of the International Fault Tolerant Computing Conference, June 1990. [7] M. Schulz and E. Auth. Advanced automatic test pattern generation and redundancy identification techniques. In The Proceedings of the International Fault Tolerant Computing Conference, June 1988. [8] K. Singh, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Timing optimization of combinational logic. In The Proceedings of the International Conference on Computer-Aided Design, pages 282-285, 1988.


Efficient Automatic Diagnosis of Digital Circuits

Heh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin Department of Electrical Engineering National Taiwan University, Taipei, Taiwan, ROC

Abstract Diagnosis is a process to locate and correct design errors of an erroneous system. The problem of automatic diagnosis of digital circuits with efficiency is studied in this paper. Two improvements over the method of [1] are developed to enhance the efficiency of diagnosis. Specifically, the dominance relation in circuit topology is utilized to reduce the search space of possibly correctable gates. In our experiment, the search space is reduced to about 1/2. And a novel divide-and-conquer technique to determine the correct gate function is proposed. REFERENCES [1] J.C. Madre, O. Coudert, & J.P. Billon "Automating the Diagnosis and the rectification of Design Errors with PRIAM" ICCAD, pp. 30-33, 1989. [2] G. Odawara, M. Tomita, O. Okuzawa, T. Ohta, & Z. Zhuang "A logic Verifier Based on Boolean Comparison" Proc. 23th Design Automatic Conference, pp. 208-214, 1986. [3] R. Reiter "A Theory of Diagnosis from First Principles" Artificial Intelligence, No. 32, Elsevier Science Publishers, pp. 57-95, 1987. [4] S.C. Lee. Digital Circuit and Logic Design. Prentice-Hall, 1976 [5] H.T. Liaw, K.T. Tran, & C.S. Lin "VVDS: A Verification/Diagnosis System for VHDL" Proc. 26th Design Automatic Conference, pp. 435-440, 1989. [6] S. Rudeanu. Boolean Functions and Equations. North-Holland Publishing Co. Armsterdam, 1974. [7] A. V. Aho, J. D. Ullman. Principles of Compiler Design. Addison-Wesley, 1977. [8] D. Harel "A Linear Time Algorithm for Finding Dominators in Flow Graphs and Related Problems" Proc. of 17th Annual ACM Symposium on the Theory of Computing, pp. 185-194, 1985. [9] R. E. Bryant "Graph-based algorithm for boolean function manipulation" IEEE Trans. on Computers, vol. C-35, No. 8, pp. 677-691, August 1986.


An Algorithm for Locating Logic Design Errors

Masahiro Tomita Graduate School of Sci. and Tech. Kobe University, Nada, Kobe 657, Japan

Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi

Faculty of Engineering University of Tokyo, Bunkyo, Tokyo 113, Japan Abstract It is difficult to locate logic design errors in a gate level circuit automatically. In this paper, we discuss the problem of locating logic design errors, and propose an algorithm to solve it. Based on the results of logic verification, we introduce an input pattern for locating design errors. The pattern contains only one Boolean variable sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors. REFERENCES [1] G.L. Smith, et al. "Boolean Comparison of Hardware and Flowchart" IBM J. Res. Dev., Vol.26, No.1, pp.106-116, 1982. [2] Ruey-Sing Wei, et al. "PROTEUS: A Logic Verification System for Combinational Circuits" Proc. Int'l Test Conf., pp.350-359, 1986. [3] M.S. Abadir, et al. "Logic Design Verification via Test Generation" IEEE Trans. on CAD, Vol.7, No.1, pp.138-148, 1988. [4] G. Odawara, et al. "A Logic Verifier Based on Boolean Comparison" Proc. 23rd DAC, pp.208-214, 1986. [5] J.C. Madre et al. "Proving Circuit Correctness Using Formal Comparison between Expected and Extracted Behavior" Proc. 25th DAC, pp.205-210, 1988. [6] M. Fujita et al. "Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams" Proc. ICCAD'88, pp.2-5, 1988. [7] K.A. Tamura "Locating Functional Errors in Logic Circuits" Proc. 26th DAC, pp.185-191, 1989. [8] J.C. Madre et al. "Automating the Diagnosis and the Rectification of Design Errors with PRIAM" Proc. ICCAD'89, pp.30-33, 1989. [9] F. Brglez, et al. "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translation in Fortran" Special Session on ATPG and Fault Simulation, Proc. IEEE ISCAS'85, 1985.


Logic Compilation from Graphical Dependency Notation

Jukka Lahti, Jorma Kivela University of Oulu, Electronics Laboratory, SF-90570 Oulu, Finland

Abstract A graphical method for digital logic design based on the use of the IEC dependency notation logic symbol standard as a logic description language is presented. The method combines graphical specification of RTL-level logic functions, schematic capture and logic compilation. A procedure for finding a gate-level realization for the IEC logic symbols is presented. A CAD system called DEMET supporting the design method is also presented. The system can synthesize gate-level netlists from graphical descriptions expressed using the IEC standard. Netlists can be obtained in several widely used formats, including EDIF and VHDL. The system makes it possible to use the IEC logic symbol standard as an intelligent graphical front-end for tools like silicon compilers. References: [1] "IEEE Standard VHDL Language Reference Manual" IEEE, N.Y. 1988 [2] Drongowski, P.J. et al. "A graphical hardware design language" Proceedings of the 25th ACM/IEEE DAC, pp. 108-114, IEEE 1988 [3] Dutt, N.D. et al. "A Language for Interactive Behavioral Synthesis" Proc. CHDL 89, pp. 3-17, IFIP 1989 [4] International Electrotechnical Commission "IEC Publication 617 Part 12" 1984 [5] Kivela, J. et al. "The Dependency Notation as a Graphical Description Language for Logic Design and Silicon Compilation" Microprocessing and Microprogramming, Vol 18, pp. 631-636, North-Holland 1986 [6] EDIF Steering Commitee "Electronic Design Interchange Format Version 110" 985 [7] McCluskey, Edward "Computer Society has it backwards" IEEE Design & Test, pp. 6-7, IEEE February 1987 [8] Kampel, I. "A Practical Introduction to the New Logic Symbols" Butterworth, Stoneham, Mass. 1985 [9] ES2 "SOLO 1200 Reference Manual"


HS: A Hierarchical Search Package for CAD Data

Nishit P. Parikh AT&T Bell Laboratories, 1247 S. Cedar Crest Blvd,. Allentown, PA 18103

Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu

AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ 07974 ABSTRACT This paper presents a new algorithm that implicitly searches the entire VLSI CAD net list data space without first constructing it. While traditional methods construct the entire search space explicitly, which helps to achieve a fast 0(1) query time but requires Ω(n) space, the new method relies on the circuit hierarchy to prune the search effectively. We show that the hierarchical net list data space is smaller by a factor of 0(nε), where 0 ≤ ε ≤ 1 and a query can be executed in 0(1) amortized time. The above claims are validated by experimental results and other advantages of the new methods are discussed. REFERENCES [Katz85] R. Katz Information Management for Engineering Design (Computer Science Survey Series). Heidelberg, Germany: Springer-Verlag, 1985. [Ban85] J. Banerjee A clustering algorithm based on recursive traversal patterns in graph models of CAD" MCC, Internal Rep., Oct. 1985. [Ban88] J. Banerjee, W. Kim, S-J. Kim and J.F. Garza "Clustering a DAG for CAD database" IEEE Transactions on Software Engineering, Vol. 14, No. 11, pp. 1684-1699, November 1988. [Saab88] D.G. Saab, R.B. Mueller-Thuns, D. Blaauw, J.A. Abraham, "CHAMP: concurrent hierarchical and multilevel program for simulation" Proceedings ICCAD-88, pp.246-249, November 1988. [Sin89] A. Singhal, N. Parikh, et. al "Data Model and Architecture for VLSI CAD Data Bases" Proceedings ICCAD-89, pp.276-279, November 1989. [Nag80] L.W. Nagel "ADVICE for Circuit Simulation" Proc 1980 International Symp. on Circuits and Systems Houston, Texas April 28, 1980 [Str88] C. Stroud, R. Munoz, D. Pierce "Behavioral Model Synthesis with CONES" IEEE Proc. Design and Test of Computers pp.22-30 June, 1988 [Tarj85] R.E. Tarjan "Amortized Complexity Analysis" SIAM J. ALG. DISC. METH. Vol. 6, No. 2 pp.306-318, April 1985.


A Data Flow Based Architecture for CAD Frameworks

P. van den Hamer, M.A. Treffers PHILIPS CFT-Automation, Engineering Data Management Department, P.O. Box 218, 5600 MD

Eindhoven, The Netherlands A new approach to integrating multi-tool design environments is described which involves making a data flow model of the tools and design methodologies within the relevant design environment and storing this model in a database. This information about the design environment is subsequently used as the basis for organizing and accessing the sets of design data which are used and created within this environment. This approach thus provides a bridge between design process related functions (tool invocation, design process checking and auditing, history logging, design releasing) and functions related to the design data (data identification, data classification, version management, data browsing). The main advantages of this technique are its user- and system level simplicity, its ability to handle data in work-in-progress situations, its support for design methodology, its consistent handling of a wide range of data types and its flexibility with respect to changes in the design environment. References and Notes [Bek90] J.H. ter Bekke "Semantic Data Modeling" Prentice Hall, to be published in 1990; is based on a previous Dutch language book by J.H. ter Bekke (ISBN 902071659X) [CFI90] Within CFI, the IDEFIX modeling technique is used for both data exchange and framework standardisation activities. [Cor79] M. Cornish "The TI data flow architectures: the power of concurrency for avionics" proceedings 3rd Conference on digital avionics 1979 pp. 19-25. [DeM79] T. DeMarco "Structured Analysis and System Specification" Yourdon Press, New York 1979 [Ham90] P. van den Hamer "A flow-based approach to managing CAD data" internal Philips report, distributed with the April '90 minutes of CFI's DMM technical subcommittee. Copies can also be obtained from the author (UUCP [email protected]). Note that a patent application has been filed regarding this technology. [Kat86] R.H. Katz, E. Chang, R. Bhateja "Version Modeling Concepts for Computer-Aided Design Databases" ACM SIGMOD Conf., Washington DC, May 1986 [Rie88] B. Riemens, W. Reijntjens, H. Kok and A. Tommelein, Internal communications Philips Research Laboratories. [Smi76] J.M. Smith and D.C.P. Smith "Database abstractions: aggregation" CACM 20 (1977) 405-413 [Wol88] P. van der Wolf and T.G.R. van Leuken "Object type oriented data modelling for VLSI data management" Proc. 25th Design Automation Conference (1988), pp. 351-356.


An Algebra for Switch-Level Simulation

Ibrahim N. Hajj Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of

Illinois, 1101 West Springfield Avenue Urbana, Illinois 61801 Abstract This paper presents a new methodology for computing the steady-state solution of switch-level networks. The method is based on a matrix algebra similar in many respects to circuit nodal analysis in that the formulation steps are similar to the nodal equation formulation steps and the network matrix has the same dimension and structure as the nodal admittance matrix, except that logic operations (min and max operations) are employed in formulating and solving the network equations. Solution algorithms are then developed using the new algebra. The approach has been implemented as a part of a mixed-mode simulator which uses partitioning and sparse matrix solution techniques in analyzing the circuit. In its switch-level mode, the simulator can perform logic and concurrent fault simulation using realistic fault models, including bridging faults, and has been found to be competitive with existing switch-level simulators. References [1] R. E. Bryant "An Algorithm for MOS Logic Simulation" Lambda, 4th qtr. 1980, pp. 46-53. [2] R. E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Trans. Computers, February 1984, pp. 160-177. [3] J. P. Hayes "A Unified Switching Theory with Applications to VLSI Design" Proc. IEEE, 1982, pp. 1140-1151. [4] R. H. Byrd, G. D. Hachtel, M. R. Lightner, and M. H. Heydemann "Switch-Level Simulation: Models, Theory, and Algorithms" Computer-Aided Design of VLSI Circuits and Systems, Vol. 1, JAI Press, Greenwich, CT, 1986. [5] I. N. Hajj "A Path Algebra for Switch-Level Simulation" IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 153-155, November 1985. [6] R. E. Bryant "Algorithmic Aspects of Symbolic Switch Network Analysis" IEEE Trans. on Computer-Aided Design, Vol. CAD-6, no. 4, pp. 618-633, July 1987. [7] B. A. Carre Graphs and Networks. Clarenon Press, Oxford, England 1979. [8] R. E. Bryant "Switch-Level Algorithms" IEEE Design & Test of Computers, Vol. 4, no. 4, pp. 26-40, August 1987. [9] R. E. Bryant, D. Beatty, K. Brace, K. Cho, and T. Sheffler "COSMOS: A Compiled Simulator for MOS Circuits" Proc. 24th Design Automation Conference, pp. 9-16, June 1987.


A New Method for Assigning Signal Flow Directions to MOS Transistors

Kuen-Jong Lee, Rajiv Gupta , Melvin A. Breuer Department of Electrical Engineering-Systems University of Southern California, Los Angeles, CA 90089-

0781 Abstract Signal flow directions of MOS transistors have been used in many CAD tools. This paper presents a new graph theoretic approach for determining these directions. A MOS circuit is represented using several undirected graphs called ST-graphs. The direction assignment problem is modeled as a two paths problem in each ST-graph. Necessary and sufficient conditions under which all edges in an ST-graph are unidirectional are derived. A linear time algorithm is presented that assigns directions to all edges in an ST-graph if they are all unidirectional. If bidirectional edges exist, the algorithm assigns directions to most edges in the ST-graph, and the remaining edges are resolved by a sequence of additional algorithms. Experimental results validate the performance benefits of this new approach. References [1] N.P. Jouppi. Derivation of signal flow direction in MOS VLSL. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(3):480-490, May 1987. [2] M.A. Cirit. Switch level random pattern testability analysis. In Proc. Design Automation Conf., pages 587-590, 1988. [3] H.H. Chen, R.G. Mathews, and J.A. Newkirk. An algorithm to generate tests for MOS circuits at the at the swith level. In Proc. Int'l, Test Conf., pages 304-312, 1985. [4] Z. Barsilal, D.K. Breece, L.M. Huisman, V.S. Iyengar, and G.M. Silberman. SLS-A fast switch level simulator. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, CAD-7(8):838-849, Aug. 1988. [5] Y. Shiloach. A polynomial solution to the undirected two paths problem. Journal of the ACM, 27(3):445-456, July 1980. [6] P.D. Seymour. Disjoint paths in graphs. District Mathematics, 29(1980) 293-309. [7] N. Robertson and P.D. Seymour. Disjoint paths -- A survey. SIAM Jour. Alg. Disc. Math., pages 300-305, Apr. 1985. [8] K.J. Lee and M.A. Breuer. An algorithmic method for assigning signal flow directions to MOS transistors. Submitted to IEEE Trans. on Computer-Aided Design on Integrated Circuits and Systems, 1990. [9] K.J. Lee and M.A. Breuer. Assigning signal flow direction to MOS transistors. Technical Report CENG-90-09, Univ. of Southern California, Los Angeles, California, Feb. 1990. [10] R.E. Bryant. An algorithm for MOS LSI logic simulation. LAMBDA, pages 46-53, Fourth Quarter 1980. [11] M.K. Reddy, S.M. Reddy, and P. Agrawal. Transistor level test generation for MOS circuits. In Proc. Design Automotion Conf., pages 825-626, 1985. [12] N. Weste and K. Eahraghian. Principles of CMOS VLSI Design. Addison-Wesley, Mass., 1983. [13] A.V. Aho, J.E. Hopcroft, and J.D. Ullman. The Design and Analysis of Computer Algorithms. Addison-Wesley Publishing Company, 1926. [14] F. Bryles and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target transistor in Fortrar. In Proc. Int'l. Symposium on Circuits and Systems, 1985. [15] S.L. Lu. Internal memo of MOSIS project, 1988.


Logic Simulation and Parallel Processing

Vishwani D. Agrawal AT&T Bell Laboratories, Murray Hill, NJ 07974

Srimat T. Chakradhar

Department of Computer Science, Rutgers University, New Brunswick, NJ 08903 ABSTRACT In the parallelization of event-driven logic simulation, as more processors are added, the speedup gain diminishes. The actual speedup also appears to be dependent upon some characteristics of the circuit being simulated. In this paper, we present a new statistical model of parallel processing based upon circuit activity defined as the average number of gates evaluated at a time step. The number of active gates in a processor is assumed to be a random variable with binomial probability density function. The performance of the multiprocessor system is derived from the maximum order-statistic of these random variables. When the gates can be equally divided among the p processors, the lower bound on speedup is found to be a x p, where a is the average circuit activity. For unequal division of gates, the lower bound on speedup is less than a x p. Interestingly, for very low activity, speedups significantly higher than the lower bounds are possible. REFERENCES [1] P. Agrawal "Concurrency and Communication in Hardware Simulators" IEEE Transactions on Computer-Aided Design, vol. CAD-5, pp. 617-623, October 1986. [2] B. Ackland "MOS Timing Simulation on a Message-Based Multiprocessor" in Proceedings International Conference Computer Design (ICCD), pp. 446-450, October 1986. [3] E. P. DeBenedictis and B. Ackland "Circuit Simulation on Hypercube" Distributed Simulation, vol. 19, no. 3, pp. 89-93, 1988. [4] L. Soule and T. Blank "Statistics for Parallelism and Abstraction Level in Digital Simulation" in Proc. of the 24th ACM/IEEE Design Automation Conf., pp. 588-591, 1987. [5] K. Wong and M. A. Franklin "Performance Analysis of a Parallel Logic Simulation Machine" J. of Parallel and Distributed Computing, vol. 7, pp. 416-440, 1989. [6] K. Hwang and F. A. Briggs Computer Architecture and Parallel Processing. McGraw Hill, New York, 1986. [7] V. D. Agrawal and S. T. Chakradhar "Performance Estimation in a Massively Parallel System" in ACM/IEEE Supercomputing 90, November 1990. [8] K. T. Cheng and V. D. Agrawal Unified Methods for VLSI Simulation and Test Generation. Boston: Kluwer Academic Publishers, 1989. [9] K. S. Trivedi Probability and Statistics with Reliability, Queuing, and Computer Science Applications. Prentice-Hall, Englewood Cliffs, NJ, 1982. [10] S. S. Gupta "Selection and Ranking Procedures and Order Statistics for the Binomial Distribution" in Classical and Contagious Discrete Distributions (G. P. Patil, ed.), pp. 219-230, Statistical Publishing Society, Calcutta, 1965. [11] K. Signhal Personal communication.


Observability Don't Care Sets and Boolean Relations

Maurizio Damiani, Giovanni De Micheli Center for Integrated Systems Stanford University, Stanford, CA 94305

Abstract A new algorithm is presented that computes exact or approximate observability don't care (ODC) sets for multiple-level combinational network. The proposed algorithms are efficient because they use only local information. A method for deriving the equivalence classes of a Boolean relation from the observability don't care sets is then proposed. Experimental results on computing ODC sets are reported. References [1] K.A. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang "Multilevel Logic Minimization Using Implicit Don't Cares" IEEE Transactions on CAD/ICAS, vol. CAD-7, No. 6, pp. 723-739, June 1988. [2] G. D. Hachtel and M. R. Lightner "Top-Down Synthesis of Multilevel Logic Networks"Proc. ICCAD 1987, pp. 316-319, S. Clara, Nov. 1987. [3] S. Muroga, Y.Kambayashi, H.Lai and J.Culliney "The Transduction Method – Design of Logic Networks Based on Permissible Functions" IEEE Trans. Comp., vol. 38, No. 10, pp. 1404-1424, 1989. [4] D. Bostick, G. D. Hachtel, R. M. Jacoby, M. R. Lightner, P. Moceyunas, C. R. Morrison, and D. Ravenscroft "The Boulder Optimal Logic Design System" Proc. ICCAD 1987, pp. 62-65, S. Clara, Nov. 1987. [5] R. K. Brayton and F. Somenzi "Boolean Relations and the Incomplete Specification of Logic Networks" Proc. VLSI '89, pp. 231-240, Munich, August 1989. [6] H. Fujiwara. Logic Design and Design for Testability. MIT Press, Cambridge, 1985. [7] A. C. L. Chang, I. S. Reed, A. V. Banes "Path Sensitization, Partial Boolean Difference and Automated Fault Diagnosis" IEEE Transactions on Computers, C-21, pp. 189-194, Feb. 1972. [8] G. D. Hachtel, R. M. Jacoby, P. H. Moceyunas "On Computing and Approximating the Observability Don't Care Set" Proceedings on the International Workshop on Logic Synthesis, Research Triangle Park, May 1989. [9] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. Wang "MIS: A Multiple-Level Logic Optimization System" IEEE Transactions on CAD/ICAS, Vol. CAD-6, No. 6, pp. 1062-1081, November 1987. [10] R. K. Brayton, F. Somenzi "An Exact Minimizer for Boolean Relations" Proc. ICCAD 1989, pp. 316-319, S. Clara, Nov. 1989. [11] M.Damiani and G. De Micheli "Efficient Computation of the Exact and Approximate Observability Don't Care Sets in Multiple-Level Logic Synthesis" Proceedings of the IFIP working conference on Logic and Architecture Synthesis, Paris, May 1990, and Stanford CSL Report CSL-TR-90-424.


PHIFACT A Booelean Preprocessor for Multi-level Logic Synthesis

F. Crowet, M. Davio, C. Dierieck, J. Durieu, G. Louis C. Ykman-Couvreur Philips Research Laboratory Belgium, Louvain-la-Neuve

Abstract PHIFACT is a multi-level Boolean optimization program characterized by a controlled time-area trade-off. Its first phase, the Boolean phase uses Boolean techniques of decomposition and merging to carry out a structural analysis and, in particular, to detect shared circuit parts. Its second phase, the restructuring phase, carries out a systematic exploration of the area-time design space by applying a user controlled sequence of transformations minimizing a parameterized cost function. The obtained results show the feasibility of full Boolean computations and open the way to an important family of new structural analysis techniques. References [1] D. Bostick, G. D. Hachtel, R. Jacoby, M. R. Lightner, P. Moceyunas, C. R. Morrison, D. Ravenscroft. The Boulder Optimal Logic Design System. ICCAD, pp. 62-64, 1987. [2] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. Wang. MIS a Multiple Level Optimization system. International Workshop on Logic Synthesis, Research Triangle Park, North Carolina, May 12-15, 1987. [3] Ch. Ykman-Couvreur. Multilevel Boolean Optimization for Incompletely specified functions in PHIFACT, in "Logic and Architecture Synthesis for Silicon Compilers", (Ed. G. Saucier, P.M. McLellan), Noth-Holland Amsterdam, pp 127-154, 1988. [4] R. K. Brayton. Multilevel Logic Synthesis. Tutorial, ICCAD 1989. [5] S. Rudeanu. Boolean Functions and Equations, North Holland, Amsterdam, 1974. [6] S. Muroga, Y. Kambayashi, Hung Chi Lai, J. L. Culliney. The Transduction method. Design of Logic Networks Based on Permissible Functions. IEEE Transactions on Computers, C18, 10, pp. 1404-1424, Oct. 1989. [7] K. A. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R. L. Rudell, A. Sangivanni-Vicentelli, A. R. Wang. Multilevel Logic Minimization Using Implicit Don't Cares. IEEE Transactions on Computer Aided Design, CAD-7, 6, pp. 723-740, June 1988. [8] G. D. Hachtel, R. M. Jacoby, P. Moceyunas. On Computing and Approximating the Observability Don't Care Set. Proc. of the International Workshop on Logic synthesis, Research Triangle Park, May 1989. [9] M. Damiani, G. De Micheli. Efficient Computation of Exact and Simplified Observability Don't care Sets for Multiple-Level Combinational Networks. Center for Integrated Systems, Stanford University, 1990.

ICCAD90, Pages 510-513 A Method for Concurrent Decomposition and Factorization of Boolean Expressions

Jagadeesh Vasudevamurthy, Janusz Rajski

VLSI Design Laboratory, Department of Electrical Engineering, McGill University, 3480 University Street, Montreal, Canada H3A 2A7

Abstract This paper describes efficient algorithms for decomposition and factorization of Boolean expressions. The method uses only two-literal single-cube divisors and double-cube divisors considered concurrently with their complementary expressions. We demonstrate that these objects, despite their simplicity, provide a very good framework to reason about common algebraic divisors and the duality relations between expressions. The algorithm has been implemented and excellent results on several benchmark circuits illustrate its efficiency and effectiveness. References [1] K. Bartlett, W. Cohen, A. de Geus, and G. Hatchel "Synthesis and optimization of multilevel logic under timing constraints" IEEE Trans. on Computer-Aided Design, Vol. 5, no. 4, pp. 582-596, Oct. 1986. [2] D. Bostick and G. D. Hachtel. "The Boulder optimal logic design system" in Proc. of the Int. Conf. on Computer Aided Design, pp. 62-65, 1987. [3] R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-vincentelli "Logic Minimization Algorithms for VLSI Synthesis" Boston. MA: Kluwer Academic Publishers, 1984. [4] R. K. Brayton, N. Brenner, C. Chen, G. Hachtel, C. McMullen, and R. Otten "The Yorktown silicon compiler" in Proc. of the Int. Symp. on Circuits and systems, pp. 391-394, June 1985. [5] R. K. Brayton and C. McMullen "The decomposition and factorization of Boolean expressions" in Proc. of the Int. Symp. on Circuits and systems, pp. 49-54, May 1982. [6] R. K. Brayton, R. Rudell, A. Sangiovanni-vincentelli, and A. R. Wang "MIS:A multiple-level logic optimization system" IEEE Trans. on Computer-Aided Design, Vol. 6, no. 6, pp. 1062-1081, Nov. 1987. [7] D. L. Dietmeyer and Y. H. Su "Logic design automation of fan in limited NAND networks" IEEE Trans. on Computers, Vol. C-18, no. 1, pp. 11-22, Jan. 1969. [8] H. Mathony and U. G. Baitinger "CARLOS: An automated multilevel logic design system for CMOS semi-custom integrated circuits" IEEE Trans. on Computer-Aided Design, Vol. 7, no. 3, pp. 346-355, Mar. 1988. [9] J. Rajski and J. Vasudevamurthy "Testability preserving transformations in multi-level logic synthesis" in International Test Conference, 1990, accepted for publication. [10] "Introduction to Synthesis Benchmarks" in Second international workshop on logic synthesis, North Carolina, USA, May 23-26, 1989. [11] R. K. Brayton "Factoring logic function" I.B.M. Journal of Research and Development, pp. 187-198, March 1987.


A Two-Level Two-Way Partitioning Algorithm

Yen-Chuen Wei, Chung-Kuan Cheng Department of Computer Science and Engineering, Mail Code - C014, University of California, San Diego,

La Jolla, CA 92093 ABSTRACT In this paper, we present a two-way partitioning algorithm which significantly improves on the highly unstable results from the traditional Kernighan-Lin based algorithms. The algorithm groups strongly connected components into clusters, and rearranges the clusters into two final subsets with specified sizes. It is known that the grouping operations reduce the complexity and thus improve the results of partitioning very large circuits. However, if the grouping is inappropriate, the partitioning results may degenerate. To prevent degeneration, we use a ratio cut approach to do the grouping. By a series of experiments based on the tradeoff between cut capacity and CPU time, we determine an optimal value to control the resultant number of groups. Good experimental results have been observed in terms of cut capacity and CPU time. References [BH89] T. Bui, C. Heigham, C. Jones, and T. Leighton "Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms" Proc. 26th Design Automation Conference, 1989, pp.775-778. [Don88] W.E. Donath "Logic Partitioning" in Physical Design Automation of VLSI Systems, edited by B. Press and M. Lorenzetti, The Benjamin/Cummings Publishing Company, 1988, pp.65-86. [FK62] L.R. Ford and D.R. Fulkerson "Flows in Networks" Princeton University Press, 1962. [FM82] C.M. Fiduccia and R.M. Mattheyses "A Linear Time Heuristic for Improving Network Partitions" Proc. 19th Design Automation Conference, 1982, pp.175-181. [GJS76] M.R. Garey, D.S. Johnson and L. Stockmeyer "Some Simplified NP-Complete Graph Problems" Theoretical Computer Science, 1976, pp.237-267. [Kri84] B. Krishnamurthy "An Improved Min-cut Algorithm for Partitioning VLSI Networks" IEEE Trans. on Computers, Vol.C-33, May 1984, pp.438-446. [KL70] B.W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" Bell System Technical Journal, Vol. 49, No. 2, Feb. 1970, pp.291-307. [LR88] T. Leighton and S. Rao "An Approximate Max-Flow Min-cut Theorem for Uniform Multicommodity Flow Problems with Applications to Approximation Algorithms" FOCS, 1988, pp.422-431. [MS86] D.W. Matula and F. Shahrokhi "The Maximum Concurrent Flow Problem and Sparsest Cuts" Tech. Report, southern Methodist Univ., 1986. [NOP87] T. Ng, J. Oldfield, and V. Pitchumani "Improvements of a Mincut Partition Algorithm" Proc. Int. Conf. on Computer-Aided Design, 1987, pp.470-473. [San89] L.A. Sanchis "Multi-Way Network Partitioning" IEEE Trans. on Compputers, Vol.38, No.1, Jan., 1989, pp.62-81. [SC88] C. Sechen and D. Chen "An Improved Objective Function for Mincut Circuit Partitioning" Proc. Int. Conf. on Computer-Aided Design, 1988, pp.502-505. [SK72] D.G. Schweikert and B.W. Kernighan "A Proper Model for the Partitioning of Electrical Circuits" Proc. 9th Design automation workshop, 1972, pp.57-62. [WC89] Y.C. Wei and C.K. Cheng "Toward Efficient Hierarchical Designs by Ratio Cut Partitioning" Proc. Int. Conf. on Computer-Aided Design, 1989, pp.298-301. [WC90] Y.C. Wei and C.K. Cheng "Ratio Cut Partitioning for Hierarchical Designs" Tech. report CS90-164, U.C. San Diego, Jan., 1990.


Finding Clusters in VLSI Circuits

Jorn Garbers Dornier GmbH, 7990 Friedrichshafen, West Germany

Hans Jurgen Promel, Angelika Steger

Research Institute of Discrete Mathematics, Universitat Bonn, Nassestr. 2,5300 Bonn West Germany ABSTRACT Circuit partitioning plays a fundamental role in hierarchical layout systems. Identifying the strongly connected subcircuits, the clusters, of the logic can significantly reduce the delay of the circuit and the total interconnection length. Finding such a cluster partition, however, is NP-complete. In this paper we propose a fast heuristic algorithm based on a simple, local criterion. We are able to prove that for highly structured circuits the clusters found by this algorithm correspond with high probability to the "natural" clusters. An application to large scale real world circuits shows that by this method the number of nets cut is reduced by up to 46% compared to the standard mincut approach. References [1] B. Bollobas. Random Graphs. Academic Press, 1985. [2] W.E. Donath. Logic partitioning, in: Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti (eds.) The Benjamin/Cummings Publishing Company, 1988, 65-86. [3] C.M. Fiduccia and R.M. Mattheyses. A linear-time heuristic for improving network partitions. Proc. 19th Design Automation Conference, 1982, 175-181. [4] J. Garbers, H.J. Promel and A. Steger. Partitioning graphs into dense subgraphs. Report No. 89575-OR, Forschungsinstitut fur Diskrete Mathematik, Universitat Bonn. [5] J. Garbers, B. Korte, H.J. Promel, E. Schwietzke and A. Steger. VLSI-placement based on routing and timing information. Proc. European Design Automation Conf., 1990, 317-321. [6] B.W. Kernighan, and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J., vol. 49, 1970, 291-307. [7] B. Korte, H.J. Promel and A. Steger. Combining partitioning and global routing in sea-of-cells design. Proc. Int. Conf. Computer-Aided-Design, 1989, 98-101. [8] B. Krishnamurthy. An improved min-cut algorithm for partitioning VLSI circuits. IEEE Transactions on Computers 33, 1984, 438-446. [9] T.K. Ng, J. Oldfield and V. Pitchumani. Improvements of a mincut partition algorithm. Proc. Int. Conf. Computer-Aided-Design, 1987, 470-473. [10] B.T. Preas and P.G. Karger. Automatic placement. A review of current techniques. Proc. 23rd Design Automation Conf., 1986, 622-629. [11] D. Schweikert and B. Kernighan. A proper model for the partitioning of electrical circuits. Proc. 9th Design Automation Workshop, 1972, 57-62. [12] C. Sechen and D. Chen. An improved objective function for mincut circuit partitioning. Proc. Int. Conf. Computer-Aided-Design, 1988, 502-505. [13] Y.C. Wei and C.K. Cheng. Towards efficient hierarchical Designs by ratio cut partitioning. Proc. Int. Conf. Computer-Aided-Design, 1989, 298-301.


Optimal Orientations of Transistor Chains

T.W. Her, D.F. Wong Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712

T.H. Freeman

MCC, 3500 Balcones Center Drive Austin, Texas 78759

Abstract In the automatic generation of CMOS cell layout, transistors are usually grouped into chains, and the chains are then placed in rows. Reversing the order of any chain does not change the length of routing channel, but may change the channel density. In this paper we describe an O(NL+LlogL) time algorithm, where N is the total number of transistor chains and L is the channel length, to determine the orientation of each transistor chain such that the channel density is minimized. We also show that the problem of flipping chains and subchains to minimize channel density can also be solved optimally. Finally, we observe that our algorithm can be used to optimally solve a generalized channel routing problem. We have implemented our algorithm in the Custom Cell Synthesis System of the MCC Physical Satellite. For the cells selected from industry, our algorithm reduced channel density 18%. We also tested the algorithm on several channel routing problems and reductions up to 30% in channel density were obtained. REFERENCES [1] R. Nair and A. Stauffer "Optimal Transistor Orientation in CMOS cell layout" Research Report RC 13419, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, January 1988. [2] A. Stauffer and R. Nair "Optimal CMOS Cell Transistor Placement: A relaxation Approach" Proc. IEEE International Conference on Computer-Aided Design, Nov 1988. [3] T. Uehara, and W. vanCleemput "Optimal Layout of CMOS Functional Arrays" IEEE Transaction on Computers, Vol. C-30, No.5, 1981. [4] S. Wimer, R.Y. Pinter, and J.A. Feldman "Optimal Chaining of CMOS Transistors in a Functional Cell" IEEE Transaction on Computer-Aided Design of ICAS, Vol. CAD-30, No. 5, 1987. [5] Yoshimura, T. and E.S. Kuh "Efficient Algorithms for Channel Routing" IEEE Trans. on Computer-Aided Design of ICAS, Vol. CAD-1, (1982), 25-35.


A New Template Based Approach to Module Generation

John Conway, Gerard Beenker Philips Research Laboratories, P.O. Box 80.000, 5600 JA Eindhoven, The Netherlands

Abstract A new template-based approach to module generation is presented. This approach allows for the fast and efficient design of layout-rule independent, parametrisable layout generators. By virtue of the use of a true hierarchical compactor combined with a powerful module assembly technique, regular layout structures comparable in density to full custom layout can be generated. The procedural part of this approach has been implemented by creating a C++ object-oriented shell around the trapezoidal corner-stitched data structure of the Tailor layout system. A new verification technique has also been implemented which guarantees that generated modules are design rule correct when constructed. Results are given for a ROM and an SRAM matrix generator. References [1] J.D. Conway. New Concepts in Module Generation for VLSI Design. MSc thesis, Trinity College, Dublin, 1990. [2] David Marple, Michiel Smulders, Henk Hegen. Tailor: A Layout System Based on Trapezoidal Corner Stitching. IEEE Transactions on CAD, January 1990. [3] Cyrus S. Bamji, Charles E. Huack, Jonathan Allen. A Design By Example Regular Structure Generator. Proc. 22nd Design Automation Conf., 1985. [4] Robert N. Mayo. Mocha Chip: A System for the Graphical Design of VLSI Module Generators. IEEE International Conf. on Computer-Aided Design, 1986. [5] David Marple. A Hierarchy Preserving Hierarchical Compactor. Proc. 27th Design Automation Conf., 1990. [6] H.A.V. Janssen, M.A. Treffers, R.H.J. Segers, J.H. Huisken. GrapMG: Cost-effective module generation. Proc. European Solid-State Circuits Conf., 1989. [7] Bjarne Stroustrup. The C++ Programming Language. Addison-Wesley, 1986. [8] J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, G. Taylor. Magic: a VLSI layout system. Proc. 21st Design Automation Conf., 1984.


AWEsim: A Program for the Efficient Analysis of Linear(ized) Circuits

Xiaoli Huang, Vivek Raghavan, Ronald A. Rohrer Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

Abstract Asymptotic Waveform Evaluation (AWE) is a new method to analyze linear(ized) circuits. It employs a form of Pade approximation rather than numerical integration to approximate the behavior of linear(ized) circuits in either the time or the frequency domain. We present in this paper improvements on the theory of AWE to avoid some inherent limitations of Pade approximation. Then we will discuss some of the practical aspects that have arisen in our attempt to employ AWE in our simulation program AWEsim. We will also present some results of AWEsim that clearly demonstrate the advantage of AWE over traditional approaches to circuit simulation References [1] Larry T. Pillage and Ronald A. Rohrer. Asymptotic waveform evaluation for timing analysis. To appear in the IEEE Transactions on Computer-Aided Design, April, 1990. [2] M.J.Bosley, H.W.Kropholier, and F.P.Lees. On the relation between the truncated fraction expansion and moments matching methods of model reduction. International Journal on Control, 18(3):461-474, 1973. [3] Lawrence T. Pillage, Xiaoli Huang, and Ronald A. Rohrer. AWEsim: Asymptotic waveform evaluation for timing analysis. In 26th ACM/IEEE Design Automation Conference Proceedings, pages 634-637, 1989. [4] L.O. Chua and P.M. Lin. Computer-Aided Analysis of Electronic Circuits. Prentice-Hall, Englewood Cliffs, 1975.


Efficient Pole Zero Sensitivity Calculation in AWE

John Y. Lee, Xiaoli Huang, Ronald A. Rohrer Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

Abstract Asymptotic Waveform Evaluation (AWE) is a new method to approximate the behavior of linear(ized) circuits in either the time or the frequency domain in terms of a dominant pole/zero approximation. An efficient method for calculating the sensitivities of the poles and zeros found by AWE has been developed. Using the adjoint sensitivity method, it is possible to inexpensively compute the sensitivities of the poles and zeros with respect to all circuit parameters, as well as to circuit parasitics. The sensitivities of the poles and zeros show excellent correlation with the perturbation response, and can provide valuable feedback to the circuit designer. References [1] A. V. Oppenheim and A. S. Willsky. Signals and Systems. Prentice Hall, 1983. [2] Paul Gray and Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley and Sons, 1984. [3] Jiri Vlach and Kishore Singhal. Computer Methods for Circuit Analysis and Design. Electrical/Computer Science and Engineering Series. Van Nostrand Reinhold Company, 1983. [4] S. W. Director and R. A. Rohrer. The generalized adjoint network and network sensitivities. IEEE Transactions on Circuit Theory, 16:318-323, August 1969. [5] Larry T. Pillage and Ronald A. Rohrer. Asymptotic waveform estimation. IEEE Trans. Computer-Aided Design, 9(4):352-366, April 1990. [6] E. S. Kuh and R. A. Rohrer. The state-variable approach to network analysis.Proceedings of the IEEE, 53(7), July 1965. [7] Xiaoli, Huang, Vivek Raghavan, and Ronald A. Rohrer. Awesim: A program for the efficient analysis of linear(ized) circuits. In ICCAD90, elsewhere in these proceedings. [8] Paul M. Frank. Introduction to System Sensitivity Theory. Academic Press, 1978.


Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique

Tak K. Tang, Michel S. Nakhla Carleton University, Ottawa, Canada

ABSTRACT Generalization of the Asymptotic Waveform Evaluation method to handle interconnect models which contain distributed elements is described. As an example, analysis of lossy coupled transmission lines is considered. The method is useful for both delay and crosstalk estimation. REFERENCES [1] R. Sianati and T. Moravec "Estimating high speed interconnect performance" IEEE Trans. Circuits Syst., Vol. CAS-34, pp.533-541, Apr. 1989 [2] H. Hasegawa and S. Seki "Analysis of interconnection delay on very high-speed LSI/VLSI chips using an MIS microstrip line model" IEEE Trans. Electron Devices, Vol. ED-31, pp. 1954-1960, Dec. 1984. [3] M. Nakhla "Analysis of pulse propagation on high-speed VLSI chips" IEEE Journal of Solid-State Circuits, Special issue on Technologies for Custom IC's, pp. 490-494, Apr. 1990. [4] J. Rubenstein and P. Penfield "Signal delay in RC tree networks" IEEE Trans. Computer-aided Design, vol. 2, pp. 202-211, 1983. [5] T.M. Lin and C.A. Mead "Signal delay in general RC networks" IEEE Trans. Computer-aided Design, vol. 3, pp. 331-349, 1984. [6] J.L. Wyatt "Signal delay in RC models for interconnect" in Circuit Analysis, Simulation and design. Amsterdam, The Netherlands; North-Holand, 1987. [7] L.T. Pillage and R.A. Rohrer "Asymptotic waveform evaluation for timing analysis" IEEE Trans. Computer-aided Design, vol. 9, pp. 352-366, April 1990. [8] L.T. Pillage. Asymptotic Waveform Evaluation for Timing Analysis. Carnegie-Mellon University, Research Report No. CMUCAD-89-34. [9] R. Griffith and M. Nakhla "Time-domain analysis of lossy coupled Transmission lines" IEEE Trans. Microwave Theory Tech., Oct. 1990. [10] C.W. Ho, A.E. Ruehli and P.A. Brennan "The modified nodal approach to network analysis" IEEE Trans. Circuits Syst., vol. CAS-22, pp. 504-509, June 1975.


DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation

Douglas R. Holberg, Santanu Dutta, Lawrence Pillage

University of Texas, Austin Department of Electrical and Computer Engineering, Austin, Texas 78712 Abstract This paper describes an approach for piecewise modeling the non-linear devices incorporated in MOS and bipolar logic-stage delay models. Asymptotic Waveform Evaluation (AWE) is used to approximate the dominant time constants for each piecewise region. References [1] J. Rubenstein, P. Penfield, Jr. and M.A. Horowitz. "Signal Delay in RC Tree Networks" IEEE Trans. on Computer Aided Design, Vol. CAD-2, no. 3, pp. 202-211, July 1983. [2] W.C. Elmore. "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers" Journal of Applied Physics, Vol. 19, no. 1, pp. 55-63, January 1948. [3] J.K. Ousterhout. "CRYSTAL: A Timing Analyzer for NMOS VLSI Circuits" Proc. of the 3rd Caltech Conference on VLSI, March 1983. [4] L. Pillage and R. Rohrer. "Asymptotic Waveform Evaluation for Timing Analysis" IEEE Transactions on Computer-Aided Design, Vol. 9, no. 4, pp. 352-366, April 1990. [5] L.M. Brocco. "Macromodelling CMOS Circuits for Timing Simulation" M.S. thesis, Massachusetts Institute of Technology, June 1987. [6] M.A. Horowitz. "Timing Models for MOS Circuits" Ph.D. thesis, Stanford University, January 1984. [7] J.K. Ousterhout. "Switch-Level Delay Models for Digital MOS VLSI" Proc. of the 21st Design Automation Conference, 1984. [8] P. O'Brien and T. Savarino. "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation" International Conference on Computer-Aided Design, November 1989. [9] C.J. Terman. "Simulation Tools for Digital LSI Design" Ph.D. thesis, Massachusetts Institute of Technology, September 1983. [10] C. Chu and M. Horowitz. "Charge-Sharing Models for Switch-Level Simulation" IEEE Trans. on Computer-Aided Design, Vol. 6, no. 6, pp. 1053-1060, 1987.


checkTc and minTc : Timing Verification and Optimal Clocking of Synchronous Digital Circuits

Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun

Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109-2122

Abstract We introduce two CAD tools, checkTc and minTc, for timing verification and optimal clocking. Both tools are based on a new timing model of synchronous digital circuits which is: 1) general enough to handle arbitrary multiphase clocking; 2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; 3) extensible to make it relatively easy to incorporate "complex" latching structures; and 4) notationally simple to make it amenable to analytic treatment in some important special cases. We are currently using these tools to help in the design of a 4ns gallium arsenide micro-supercomputer. References [1] K. A. Sakallah, T. N. Mudge, and O. A. Olukotun "Analysis and Design of Latch-Controlled Synchronous Digital Circuits" in Proceedings of the 27th Design Automation Conference, 1990. [2] N. P. Jouppi. Timing Verification and Performance Improvement of MOS VLSI Designs. PhD thesis, Stanford University, Stanford, CA 94305-2192, October 1984. [3] T. G. Szymanski "LEADOUT : A Static timing Analyzer for MOS Cicuits" in ICCAD-86 Digest of Technical Papers, pp. 130-133, 1986. [4] J. J. Cherry "Pearl : A CMOS Timing Analyzer" in Proceedings of the 25th Design Automation Conference, pp. 148-153, 1988. [5] D. E. Wallace and C. H. Sequin "ATV: An Abstract Timing Verifier" in Proceedings of the 25th Design Automation Conference, pp. 154-159, 1988. [6] M. R. Dagenais and N. C. Rumin "On the Calculation of Optimal Clocking Parameters in Synchronous Circuits with Level-Sensitive Latches" IEEE Transactions on Computer-Aided Design, vol. 8, no. 3, pp. 268-278, March 1989. [7] K. A. Sakallah, T. N. Mudge, and O. A. Olukotun "A Timing Model of Synchronous Digital Circuits" Technical Report CSE-TR-47-90, University of Michigan, Dept of EECS, Ann Arbor, MI 48109-2122, 1990. [8] K. A. Sakallah, T. N. Mudge, and O. A. Olukotun "Optimal Clocking of Synchronous Systems" Technical Report CSE-TR-65-90, University of Michigan, Dept of EECS, Ann Arbor, MI 48109-2122, 1990. [9] D. T. Phillips, A. Ravindran, and J. J. Solberg. Operations Research: Principles and Practice. John Wiley and Sons, Inc., 1976. [10] R. B. Brown, J. A. Dyskstra, T. N. Mudge, and R. Milano "A GaAs Micro-Supercomputer: Rationale and Design" Technical Report CSE-TR-42-90, University of Michigan, Dept of EECS, Ann Arbor, MI 48109-2122, 1990.


A Framework Environment for Logic Design Support System

Kaname kuroki, Shigenobu Suzuki Nobuyoshi Nomizu, Kazutoshi Takahashi NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JAPAN

ABSTRACT A framework for an integrated logic design support system is presented. Owing to the use of this framework, it is easy to develop and add commands which have variable functions for automated logic design. ILOS (Integrated LOgic design System) has been developed using this framework. ILOS supports various design styles because these commands are flexibly combined on the framework. These commands are hierarchical circuit conversion, distributor synthesis, partitioned hierarchical design support, generation of schematic diagram and logic synthesis. ILOS is used in the design of supercomputers, large-scale computers and medium-scale computers. In large-scale computer design, ILOS reduced manpower costs by 70%. References [1] J.A. Darringer, D. Brand, J.V. Gerbi, W.H. Joyner, L.H. Trevillyan "LSS: A System for Production Logic Synthesis" IBM J. Res. Develop. 28, no. 5, pp. 537-545, 1984. [2] A.J. de Geus and W. Cohen "A Rule-Based System for Optimizing Combinational Logic" IEEE Design & Test of Computers, pp. 22-32 1985. [3] D. Gregory, K. Bartlett, A.J. de Geus, G.D. Hachtel "SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic" 23rd DAC, 1986. [4] K. Enomoto, S. Nalamura, T. Ogihara and S. Murai "LORES-2: A Logic Reorganization System" IEEE Design & Test of Computers, Vol. 2, No. 3, pp. 35-42 Oct. 1985. [5] S. Suzuki, T. Bitch, M. Kakimoto, K. Takahashi and T. Sugimoto "TRIP: An Automated Technology Mapping System" 24th DAC pp. 523-529, 1987. [6] Y. Tsuchiya, M. Morita, Y. Ikariya, E. Tsurumi, T. Mori and T. Yanagita, "Establishment of Higher Level Logic Design for Very Large Scale Computer" 23rd DAC pp. 366-371, 1986. [7] S. Kato and T. Sasaki "FDL: A Structural Behavior Description Language" 6th International Symposium on Computer Hardware Description Language pp. 137-152, 1983.


MIS-MV: Optimization of Multi-level Logic with Multiple-valued Inputs

Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto Sangiovanni-Vincentelli Dept. of EECS, University of California, Berkeley

Abstract We present techniques for the optimization of multi-level logic with multiple-valued input variables. The motivation for this is to tackle the input encoding problem in logic synthesis, where binary codes need to be found for the different values of a symbolic input variable. Multi-level multiple-valued optimization is used to generate constraints that are used to determine the codes. The state assignment problem in sequential logic synthesis can be approximated as an input encoding problem by ignoring the next state field, which is reasonable when the primary output logic dominates the next state logic. We present a novel technique for extracting common factors with multiple-valued variables and show how other multi-level optimization techniques are easily extended with multiple-valued variables. These ideas have been implemented as algorithms in the program MIS-MV. We present some practical issues in the implementation as well as some experimental results. References [1] K. Bartlett, R. Brayton, G. Hachtel, R. Jacoby, C. Morrison, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Multi-level logic minimization using implicit don't cares. IEEE Transactions on Computer-Aided Design, 7(6):723-740, June 1988. [2] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Multi-level logic optimization and the rectangular covering problem. In Proceedings of the International Conference on Computer-Aided Design, 1987. [3] R. K. Brayton and C. McMullen. The decomposition and factorization of Boolean expressions. In Proceedings of the International Symposium on Circuits and Systems, 1982. [4] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. MIS: A multiple-level logic optimization system. IEEE Transactions on Computer-Aided Design, (6):1062-1081, November 1987. [5] S. Devadas, H.-K. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. MUSTANG: State assignment of finite state machines targeting multi-level logic implementations. IEEE Transactions on Computer-Aided Design, (12):1290-1300, December 1988. [6] G. Hachtel, X. Du, and P. Moceyunas. Algorithms for state assignment based on multi-level representation. In Proceedings of the Hawaii International Conference on System Sciences, 1990. [7] G.D. Hachtel and R. M. Jacoby. Verification algorithms for VLSI synthesis. IEEE Transactions on Computer-Aided Design, CAD-7(5):616-640, May 1988. [8] L. Lavagno, S. Malik, R. K. Brayton, and A. Sangiovanni-Vincentelli. Optimization of multi-level logic with multiple-valued inputs. Technical report, Electronics Research Lab., U. C. Berkeley, August 1990. [9] B. Lin and A. R. Newton. Synthesis of multiple level logic from symbolic high-level description languages. In Proceedings of the International Conference on Very Large Scale Integration, Munich, 1989. [10] S. Malik, R. K. Brayton, and A. Sangiovanni-Vincentelli. Encoding symbolic inputs for multi-level logic implementation. In Proceedings of the International Conference on Very Large Scale Integration, Munich, 1989. [11] G. De Micheli, R. K. Brayton, and A. Sangiovanni-Vincentelli. Optimal state assignment for finite state machines. IEEE Transactions on Computer-Aided Design, (3):269-285, July 1985. [12] S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney. The transduction method - design of logic networks based on permissible functions. In IEEE Transactions on Computers, 1989.

[13] R. L. Rudell and A. Sangiovanni-Vincentelli. Multiple-valued minimization for PLA optimization. IEEE Transactions on Computer-Aided Design, (5):727-750, September 1987. [14] A. Srinivasan, T. Kam, S. Malik, and R. Brayton. Algorithms for discrete function manipulation. In Proceedings of the International Conference on Computer-Aided Design, 1990. [15] T. Villa and A. Sangiovanni-Vincentelli. NOVA: State assignment of finite state machines for optimal two-level logic implementations. In Proceedings of the Design Automation Conference, 1989.


Multi-Level Logic Optimization for Large Scale ASICs

Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura NTT Communications and Information Processing Laboratories, 1-2356 Take, Yokosuka-shi, Kanagawa

238-03, Japan Abstract In the synthesis of large-scale ASICs from high-level description language, such as behavioral description, all control logic should be synthesized and optimized with good quality and in practical CPU time, even when the logic circuit comprises thousands of inputs and outputs. Therefore, we developed an efficient high-level synthesis and optimization system for large-scale circuits, which reduces the total number of fan-ins in the technology-independent phase and adjusts speed and area after technology mapping is completed. This paper mainly describes multi-level logic optimization techniques based on refined weak division methods and additional functions for carrying out good optimization with only a slight overhead. It also describes technology mapping and local optimization techniques suitable for high-level CAD systems like ours. Our system has shown that multi-level logic optimization in VLSIs with more than 100,000 gates (that is, VLSIs whose control logic comprise more than 10,000 gate circuits) is possible in practical CPU time. References [1] Y. Nakamura, K. Oguri, H. Nakanishi, R. Nomura "An RTL Behavioral Description Based Logic Design CAD System with Synthesis Capability" IFIP CHDL-85, pp. 64-78, Aug. 1985. [2] K. Oguri, Y. Nakamura, R. Nomura "Evaluation of Behavior Description Based CAD System Used in Prolog Machine Logic Design" IEEE ICCAD-86, pp. 116-119, Nov. 1986. [3] Y. Nakamura "An Integrated Logic Design Environment Based on Behavioral Description" IEEE Trans. on CAD, Vol. CAD-6, No. 3, pp. 322-336, Mar. 1987. [4] Y. Nakamura, K. Oguri "An RTL Logic Design Aid for Parallel Control VLSI Processors" IFIP VLSI-87, pp. 13-28, Aug. 1987. [5] Y. Nakamura, K. Oguri, A. Nagoya, R. Nomura "A Hierarchical Behavioral Description based CAD System" EURO ASIC-90, pp. 282-287, May 1990. [6] S. Muroga, Y. Kambayashi, H. C. Lai, J. N. Culliney "The Transduction Method - Design of Logic Networks Based on Permissible Functions" IEEE Trans. on Comput, Vol C-38, No. 10, pp. 1404-1424, Oct. 1989. [7] K. A. Bartlett, R. K. Brayton, G. D. Hatchel, R. M. Jacoby, C. R. Morrison, R. L. Rudell, A. Sangiovanni-Vincetelli, A. R. Wang "Multilevel Logic Minimization Using Implicit Don't Cares" IEEE Trans. on CAD, Vol. CAD-7, No. 6, pp. 723-740, June 1988. [8] R. K. Brayton, C. McMullen "The decomposition and factorization of Boolean expressions" ISCAS-82, pp. 49-54, May 1982.

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