A Simple Bipolar Transistor-Based Bypass Approach for Photovoltaic Modules

IEEE JOURNAL OF PHOTOVOLTAICS, VOL. 4, NO. 1, JANUARY 2014 405

A Simple Bipolar Transistor-Based Bypass Approachfor Photovoltaic Modules

Vincenzo d’Alessandro, Pierluigi Guerriero, and Santolo Daliento

Abstract—This paper presents a novel bypass approach for pho-tovoltaic panels relying on a bipolar transistor operated in satura-tion, the activation of which is handled automatically by a circuitcomprising a pair of MOS transistors only. The functioning prin-ciple of the proposed system is explained and the improvementsin terms of reliability of the bypassed subpanel and power pro-duced by the string in comparison with a traditional diode-basedscheme are quantified. The analysis is corroborated by dc/transientmeasurements and tailored PSPICE simulations.

Index Terms—Active bypass, bypass diode, one-diode equivalentcircuit, hot spot, photovoltaic (PV) panel, shading.

I. INTRODUCTION

S ILICON p-n and Schottky bypass diodes are widely used inphotovoltaic (PV) fields to provide an alternative path for

the current flow when a group of cells belonging to a panel (alsodenoted as module) embedded in a series string is shaded ormalfunctioning. This allows overcoming various issues. First,as early stated in [1], the decrease in the current conducted bythe sunny cells [2]–[4] and the consequent collapse in the stringpower production are significantly reduced. Besides, the averagereverse voltage drop affecting the shaded cells is lowered, thusminimizing failure phenomena due to hot spots [5], [6] andimpact ionization; as a result, high reliability of the panels isensured throughout their lifetime.

In some works [7], [8], the integration of a bypass diodewithin each elementary cell was proposed. Although this solu-tion is suited to almost completely eliminate reliability issuesand minimize the power dissipation under shading conditions,the common approach is to provide commercial PV moduleswith a rear-mounted junction box containing 2 to 6 discretebypass diodes, which are antiparalleled to panel subsections(hereinafter referred to as subpanels) consisting of an assignednumber of individual cells connected in series (typically 12, 18,or 24) [2], [4]–[6], [9]–[17]; performance and reliability im-provements with respect to this conventional arrangement canbe achieved by adopting overlapped [6], [12], [13], [15] andeven multilevel [18] diode configurations.

A common mistake is to believe that traditional bypass diodesallow totally avoiding power consumption under shading condi-tions. In reality, if a subpanel is shaded, its voltage drop becomes

Manuscript received September 3, 2012; revised August 10, 2013; acceptedSeptember 16, 2013. Date of publication October 16, 2013; date of current ver-sion December 16, 2013.

The authors are with the Department of Electrical Engineering and In-formation Technology, University Federico II, Naples 80125, Italy (e-mail:[email protected]; [email protected]; [email protected]).

Digital Object Identifier 10.1109/JPHOTOV.2013.2282736

negative, thereby enabling the corresponding bypass diode toconduct the portion of the current imposed by the sunny cellsin the string that cannot flow through the subpanel (hereinafterdenoted as bypass current Ibypass); as a consequence, the sys-tem comprising the shaded subpanel and the bypass diode notonly does not contribute to the energy production any more, butalso dissipates a power given by the product of the string currentand the voltage drop across the forward-biased diode. Althoughthis loss is low compared with the case of a diode-less stringwith a shaded group of cells, it can grow to values worthy ofattention when (i) the number of shaded subpanels is high, and(ii) in new-generation PV fields that feature enlarged cell size,whose photogenerated currents can even reach 16 A [19]. More-over, in the latter case the diode reliability can be dramaticallyaffected by the high temperatures arising under critical shadingconditions.

Nowadays, considerable effort is being made to conceive andrealize low-drop “active” solutions for PV subpanels in order to(i) counteract the overheating of the bypass system by reducingits power consumption; (ii) minimize the occurrence of local-ized damages; and (iii) to a lesser extent, increase the energyyield of the string. Some topologies have been recently devel-oped, in which the bypass diode is replaced by an active device,i.e., a low-RDS MOS transistor (MOST), and a control circuitryis adopted to drive this device into linear mode when the sub-panel is shaded or malfunctioning, and keep it inactive whenthe subpanel is normally irradiated. In particular, an ingeniousmodularized system featuring a 50-mV drop (Ibypass = 10 A,TAMB = 85 ◦C) has been implemented by the Fraunhofer Insti-tute for Solar Energy [18]–[21] in Microsemi technology [22]with a connection system produced by Spelsberg [23], and asolution referred to as “cool bypass switch” [24], [25] ensuringa 270-mV drop (Ibypass = 8 A, TAMB = 125 ◦C) has beenjointly manufactured by STMicroelectronics [26] and the Sicil-ian University partners. Further diode-free bypass systems arecurrently under development (e.g., by OKE Services [27]).

In this paper, a simple approach is presented, in which thebypass task is delegated to a bipolar transistor operated in sat-uration mode. The circuit benefits from an automatic activa-tion/deactivation of the bypass element handled by two MOSTsonly, and can be used concurrently with the traditional diode toincrease both subpanel reliability and power production.

This work extends the preliminary treatment presented in[28] with a detailed procedure for the choice of componentsand an experimental analysis to support the theory and circuitsimulations. The paper is organized as follows. In Section II,the functioning principle of the proposed solution is explained.In Section III, the details of the design strategy are given. The

2156-3381 © 2013 IEEE

406 IEEE JOURNAL OF PHOTOVOLTAICS, VOL. 4, NO. 1, JANUARY 2014

Fig. 1. (a) Sketch of a module composed by 2 bypass-provided subsections,one of which is partially shaded; (b) traditional bypass scheme relying on adiode; proposed active bypass systems based on either (c) PNP or (d) NPNbipolar transistor as a bypass component; the solution (c) makes use of twoNMOSTs, while two PMOSTs are exploited in (d), respectively.

experimental setups and the simulation method are illustrated inSection IV. Section V is devoted to the discussion of results andexamination of the advantages and drawbacks of the approach.Conclusions are then drawn in Section VI.

II. ACTIVE BYPASS CIRCUIT

Let us consider a panel composed of two 20-cell subpanels,each equipped with a bypass circuit, and assume that one sub-panel is partially shaded (e.g., by a cloud), while the other isuniformly hit by the light, as schematically sketched in Fig. 1(a).The panel voltage and current are denoted by Vpanel and Ipanel ,

respectively. It is worth noting that Ipanel coincides with the cur-rent flowing through the irradiated subpanel, the bypass systemof which is not working.

A subpanel provided with the traditional antiparalleled bypassdiode is shown in Fig. 1(b). If the subpanel is evenly illuminated,the voltage drop Vsubpanel is positive, and the diode is reversebiased. If the subpanel is shaded, it can conduct only a lim-ited portion, designated as Ishadow , of the current Ipanel fed bythe sunny subpanel; under such conditions, Vsubpanel reverses itssign and pushes the diode into forward bias, thus enabling an ad-ditional path for the excess current Ibypass = Ipanel − Ishadow .

Fig. 1(c) and (d) depicts two “dual” variants of the proposedactive bypass system, which are indicated as PNP/NMOS andNPN/PMOS. The functioning principle of the approach and theimprovements in comparison with the diode scheme will beillustrated only for the PNP/NMOS topology without loss ofgenerality. As can be seen, the circuit includes: 1) a PNP bipo-lar transistor, which acts as a bypass component by offeringan alternative path for the current Ibypass when the subpanelis partially shaded; 2) two N -channel power MOS transistors(NMOSTs), denoted by A and B, which are devised to automat-ically turn on the PNP device as shading occurs, as well as tokeep it inactive when the subpanel is exposed to sunlight; and 3)an additional diode to partially support the bipolar transistor orfully bear the bypass current if the subpanel is broken or subjectto ideally dark conditions (Ishadow = 0 A), as will be clarifiedlater.

To simplify the description, a diode-less PNP/NMOS topol-ogy will be considered so that the sole bipolar transistor isdestined to carry out the bypass action (IC = Ibypass).

The basic behavior of the proposed circuit can be illustrativelyexplained as follows. From a simple inspection of Fig. 1(c), itcan be evinced that Vsubpanel = VGSA , and VDSA = VGSB . Ifthe subpanel is illuminated, the high (positive) Vsubpanel drivesNMOST A into linear mode; hence, VDSA is much lower thanthe threshold voltage VTHB of the NMOST B mounted in apass-transistor configuration, which is therefore inactive; con-sequently, the bipolar device is in turn kept dry since it is not fedwith a base current. As partial shading occurs, both Vsubpaneland IDA reduce (IDA tends to be almost equal to Ishadow ),whereas VDSA increases so that device A moves toward pinch-off; as VDSA exceeds VTHB , NMOST B turns on and startsextracting a current IB = IDB from the base terminal of thePNP transistor, which—if the system is properly designed—ispushed into saturation due to the circuit topology and exhibitsa low emitter–collector voltage drop VEC . In conclusion, a keyrole is played by VDSA , which is low when IDA is high (sunnyconditions), while becoming high when IDA decreases (shadingconditions).

It is worth noting that, contrarily to what happens in thestandard diode-based approach, Vsubpanel is still positive in spiteof the partial shading, since it must be higher than the thresholdvoltage VTHA not to inhibit the IDA conduction; this means thatthe subpanel keeps producing power, which is instead dissipatedby NMOST A. As a result, the possibility of localized damagesdue to hot-spot occurrences and avalanche breakdown withinthe subpanel is reduced.

D’ALESSANDRO et al.: SIMPLE BIPOLAR TRANSISTOR-BASED BYPASS APPROACH FOR PHOTOVOLTAIC MODULES 407

Fig. 2. Key (a) voltages and (b) currents corresponding to the shaded subpaneland to the associated bypass scheme vs. the whole panel voltage Vpanel ; (c)power produced by the panel as a function of Vpanel , as determined by the pro-posed system (solid line) and the conventional diode-based approach (dashed),along with the difference between the two (dotted).

Further information concerning the functioning principle canbe gained by (i) assuming that all cells of the illuminated sub-panel are characterized by a PV current Iph = 2 A, while thosebelonging to the shaded one share Ishadow = 0.5 A (uniformshading); (ii) sweeping the panel voltage Vpanel from 0 V tothe open-circuit value Voc (≈ 21.4 V); and (iii) monitoring thebehavior of all the key voltages [see Fig. 2(a)] and currents [seeFig. 2(b)] against Vpanel .

For low Vpanel values, Ipanel ≈ Iph > Ishadow so that thebipolar transistor associated with the shaded subpanel is auto-matically enabled to perform the bypass action and conducts acollector current IC = Ibypass ≈ 1.5 A, while the voltage dropVEC amounts to 253 mV only. Under such conditions, VDSA ≈

2.25 V (> VTHB ) and Vsubpanel ≈ 2 V (> VTHA ). It should benoted that

VEC = VDSA − Vsubpanel = VGSB − VGSA (1)

whence it can be concluded that VDSA is always higher thanVsubpanel during the bypass stage, since VEC > 0 V to allow theIbypass flow. The base current IB is equal to 5.7 mA.

By further increasing Vpanel , the inherent cell diodes of thesunny subpanel start conducting, and Ipanel decreases; as Vpanelreaches 10.7 V, Ipanel equates the shading-induced Ishadow ,and there is no need for the bypass action any longer: VDSAdrastically reduces (NMOST A is pushed into deep linear mode),thus turning off the pass-transistor B, and consequently, alsothe bipolar device; in this scenario, VEC becomes negative anddecreases with Vpanel .

Fig. 2(c) shows the power produced by the whole panel as afunction of voltage, as obtained by exploiting either the proposedapproach or a traditional P-N diode for the aforementioned con-ditions. It can be plainly seen that a significant increase in thepower peak is achieved with the active bypass circuit thanks tothe low voltage drop VEC across the PNP transistor operated insaturation mode.

The same considerations hold for the NPN/PMOS variant ofthe active bypass system shown in Fig. 1(d), the behavior ofwhich will not be described in detail here, since it can be easilyderived from that related to the PNP/NMOS version by simplyreplacing voltages VGS , VDS , VTH , VEC with VSG , VSD , |VTH |,VCE , respectively.

As shown in Fig. 1(c), an additional (backup) diode mountedin parallel to the bipolar device should be also employed with atwofold aim.

1) In the first place, the diode might support the bipolar tran-sistor action for high bypass currents so as to further re-duce the power loss. For this purpose, a low-drop Schottkydiode is suggested, as it will be clarified in Section V.

2) If the subpanel is broken or under ideally dark conditions(Ishadow = 0 A), both NMOSTs remain switched off,since they are not required to conduct current (Ishadow =0 A implies IDA = IDB = 0 A). As a consequence, thebypass action must be necessarily performed by the ad-ditional diode, which will entirely conduct the currentprovided by the sunny cells belonging to other subpanels.It is worth noting that, under such conditions, Vsubpanel =0 V and the voltage drop across the forward-biased diodeis equal to VDSA .

III. CIRCUIT DESIGN

For an assigned Ipanel , the voltage drop VEC increases byreducing Ishadow (which implies a growth in Ibypass) or in-crementing the difference VTHB − VTHA (which leads to alowering in the driving current IB ). In principle, one couldkeep VEC extremely low—regardless of the bypass currentvalue—by selecting the NMOS transistors A and B so asto ensure that VTHA − VTHB > 0; this would indeed pushthe PNP device into deep saturation mode [28]. However,a number of simulations and experiments performed on PV


strings have shown that in this case some bypass circuitsmight unexpectedly activate for low string voltages Vstringeven in the absence of shadow with the following scenario:Vstring is partitioned between the subpanels with inactivebypass, while the blocks including the subpanels with en-abled bypass are under short-circuit conditions with VEC ≈0 V (VDSA ≈ Vsubpanel), IC ≈ 0 A, and IB ≈ IE . By slightlyincreasing Vstring , the voltages across the subpanels with in-active bypass become high enough to make the intrinsic celldiodes conduct a significant current, which in turn counteractsIph , thereby reducing the current conducted by the string Istring ,and consequently, also the produced power. The Istring decreaseis not sustained by the subpanels with enabled bypass, whichstill conduct Iph due to the low Vsubpanel , but by the associatedPNP transistors that work in reverse mode with the current ICentering the terminal. By further incrementing Vstring , this un-desired mechanism eventually ends so that all the bypass circuitsare off, Vstring is equally partitioned between the subpanels, andIstring flows through the subpanels and the NMOSTs A (op-erated in deep linear region). It is to be highlighted that thiseffect occurs for Vstring values far lower than that correspond-ing to the power peak. Nevertheless, it introduces a drop in thepower–voltage characteristic, which in severe cases may turninto a local maximum and could in principle adversely affectthe maximum power point tracking (MPPT) task.

In order to prevent the aforementioned mechanism, the circuitneeds to be designed so as to inhibit the activation of the pass-transistor B when VEC = 0 V, i.e., when the block composedby subpanel and bypass circuit is under short-circuit conditions.This can be accomplished by satisfying the following relation:

VGSBsc = VDSAsc < VTHB (2)

where the subscript sc stands for short circuit. By observingthat VDSA = VGSA for VEC = 0 V, constraint (2) can be alsoexpressed as

VGSAsc < VTHB . (3)

Since VGSAsc > VTHA , it follows that VTHB must be nec-essarily higher than VTHA ; however, devices A and B cannotbe selected with a high difference VTHB − VTHA , which wouldraise the drop VEC = VGSB − VGSA to values close to thoseprovided by a conventional diode, thus restoring the canonicalpower loss.

On the aforementioned bases, one can proceed as follows.1) Device A must feature low threshold voltage VTHA and

on-resistance RDSA in order to minimize the dissipatedpower VDSA × IDA ≈ VDSA × Ishadow during the bypassstage for a given shading level; it is indeed to be recalledthat VDSA > VGSA > VTHA so that VTHA represents aminimum boundary for VDSA ; besides, for assigned val-ues of IDA and VTHA , the gap VGSA − VTHA (and thusVDSA − VTHA ) reduces with RDSA .

2) In a similar fashion, a low RDSA guarantees that undershort-circuit conditions the difference VGSAsc − VTHA ( =VDSAsc − VTHA ) is small. This allows avoiding a largediscrepancy between VTHB (that must be > VDSAsc) and

Fig. 3. Prototype of the PNP/NMOS version of the proposed bypass circuitadopted for the experimental validation.

VTHA . In principle, the choice of transistors A and Bshould be made to keep VTHB − VTHA around 0.2–0.3 V.

3) It is to be remarked that constraint (2), even if satisfied un-der standard conditions, might not hold any more for highpanel temperatures; nevertheless, an extensive simulationanalysis conducted according to the approach addressedin Section IV allowed demonstrating that in this case theimpact on the power–voltage characteristic is negligible.

A further RDSA reduction can be obtained by consideringsome paralleled NMOSTs A in the place of a single transistor;this would also imply a higher ruggedness due to the lowerpower dissipated by the individual devices A, which alleviatesthe overheating and minimizes the possibility of current flowinterruption due to transistor failure.

IV. EXPERIMENTAL SETUPS AND SIMULATION APPROACH

A. Experimental Setups

The proposed circuit was applied to two commercial PVmodules, which will be hereinafter denoted as #1 and #2. Inparticular,

1) panel #1 features Isc = 2.81 A, Voc = 24.6 V, Pmax =50 W under standard conditions, and it is partitioned intotwo 20-cell subpanels, each equipped with a 54050 P-Ndiode, and

2) panel #2 features Isc = 8.8 A, Voc = 37 V, Pmax = 240 Wunder standard conditions, and it is subdivided into three20-cell subpanels, each provided with a low-drop SB1240Schottky diode.

The diode-less prototype of the PNP/NMOS variant of theproposed active bypass system is shown in Fig. 3. The PNPbipolar junction transistor (BJT) 2SA2014 was employed asbypass element.

All diodes and transistors were experimentally characterizedby an HP4142B curve tracer equipped with a high-current sourceunit allowing pulsed measurements with minimum pulse widthequal to 100 μs.

The static I–V characteristics of the panels were measured byboth a commercial and an in-house setup. The first relies on (i)a custom version of the H&H ZS3060 electronic dc load [29]rated for 3 kW and 800 V devised to force the operating pointand (ii) a data acquisition section involving two PC-controlled


2000 Keithley multimeter units synchronized by a home-madeboard to improve the measurement accuracy. However, this so-lution operates in a fixed voltage/current/resistance step mode;as a consequence, an I–V characteristic can be accurately drawnonly at the price of a significant increase in the overall numberof points and thus in measurement time (tens of seconds). Thisis especially true under partial shading conditions, for whichthe curve exhibits regions with highly different slopes due tothe bypass activation. In order to overcome this limitation, analternative in-house curve tracer relying on BJTs connected ina Darlington topology [30] and rated up to 500 W was devel-oped. This tracer is equipped by a control logic to dynamicallytune the step during the measurement run according to the en-countered slope, thus ensuring an excellent description of theI–V curve in less than 1 s. Besides, it can be employed to carryout measurements on PV panels embedded in an installed fieldthanks to a disconnection system that preserves the current flowin the string and a Bluetooth wireless communication to transferdata to a PC station.

Another setup relying on a 300-MHz-bandwidth DPO3034Tektronix oscilloscope was adopted to investigate the dynamicbehavior of the proposed system under rapidly varying weatherconditions, which were emulated by applying a constant loadand manually perturbing the irradiance over a subpanel throughdifferent light filters (i.e., transparent plastic sheets with differ-ent opacity degree).

B. Simulation Approach

The widespread PSPICE program [31] was adopted to betterexplore the features and illustrate the advantages of the proposedapproach. High-granularity simulations were allowed by con-sidering a cell-level description so as to enable also the analysisof nonuniform shading conditions over module subsections. Theelementary cell was modeled through the equivalent one-diodelumped electrical circuit including: a current source of PV cur-rent, an ideal (i.e., resistance-free) diode, and the parasitic series(Rs) and shunt (Rsh) resistances, which were extracted accord-ing to the technique presented in [32]. The positive temperaturecoefficient (TC) of the PV currents due to bandgap shrinkingwas accounted for by resorting to the accepted linear modelgiven by

Iph = Iph (T0) + κ · (T − T0) (4)

where T is the actual temperature, T0 = 25 ◦C, and parameterκ was taken from the panel datasheets. The BJT model avail-able in PSPICE was enriched to include the positive TC of thecommon-emitter current gain βF due to the bandgap narrow-ing in the highly-doped emitter. The temperature dependences ofthe other parameters (e.g., threshold voltage of the MOS transis-tor, reverse saturation current of the diode) are intrinsically ac-counted for in PSPICE. The parameters of all devices, as well asthose associated with the PV cells, were suitably tailored thanksto the preliminary experimental characterization performed asdescribed in Section IV-A. In particular, the threshold voltagesVTH were extracted from the ID − VGS transcharacteristics byadopting the quadratic extrapolation method [33], [34]: if the

Fig. 4. Measured (dotted lines) and simulated (solid) panel current Ipanelvs. voltage Vpanel for various shading conditions, as obtained by applying thePNP/NMOS variant of the proposed bypass system to panel #1.

device operates in pinch-off, the drain current ID is proportionalto the square of the overdrive voltage VGS − VTH ; as a conse-quence, in this region the

√ID − VGS characteristic is a straight

line, the extrapolation of which crosses the VGS axis at VTH .

V. RESULTS AND DISCUSSION

The NMOS device A mounted on the prototype was selectedin accordance to the guidelines drawn in Section III; the tran-sistor features a threshold voltage experimentally determined tobe VTHA = 1.86 V at T = 25 ◦C, while the on-resistance RDSAis <4 mΩ.

For panel #1, the drop VDSAsc was measured to be 2.14 V forIsc ≈ 2.1 A (at an approximate temperature of 50 ◦C), while itwas extrapolated to be 2.19 V for the standard Isc at T = 25 ◦Cby PSPICE simulations. The NMOST B was chosen so as toobey constraint (2), being characterized by VTHB = 2.21 V atT = 25 ◦C.

As concerns panel #2, VDSAsc was measured to be about2.31 V for Isc ≈ 5 A, and extrapolated to be 2.45 V understandard conditions. Consequently, an NMOST B with VTHB =2.48 V was chosen to ensure safe operation.

Fig. 4 illustrates the comparison between experimental andsimulated I–V curves, as obtained by intentionally shading 4cells of a subpanel of module #1 with three different filters,along with the shadow-less characteristic. The absence of acurrent drop (induced by the undesired activation of a bypasscircuit) in the sunny curve at low Vpanel witnesses that a properchoice of NMOSTs A and B was made. It can be evinced thatthe PSPICE simulator is well calibrated, and can be in principleused for predictive analyses.

A PSPICE-based investigation was conducted to quantify theimprovement in power production provided by the proposedsystem in comparison with the approach based on the mereP-N diode. This analysis was performed by simulating a stringconsisting of 10 panels of type #1, with all subpanels equippedeither by a properly designed diode-less active bypass circuit orby a diode alone. It was assumed that Iph = 2 A and T = 50 ◦C,and the number of uniformly-shaded subpanels was varied. Forthe shaded subpanels, the PV current Ishadow common to all


Fig. 5. Parameter α defined as in (5) as a function of shading level by varyingthe number of shaded subpanels in a 10-panel string.

cells was swept so as to cover the entire range 0.1–1.9 A. Thepercentage increase in maximum power, defined as

α =Pmax (active) − Pmax (diode)

Pmax (diode)· 100 (5)

was then calculated and reported in Fig. 5. The results can besummarized as follows. As the number of shaded subpanelsincreases, (i) the Ishadow range within which the power peakoccurs during the bypass action shrinks; and (ii) in such a range,parameter α grows up; in particular, for the analyzed case study,the α increase can be estimated by 0.25 × Nβ ,N being thenumber of shaded subpanels, where β = 1.3 at low Ishadow andslightly higher as the shading level reduces.

An illustrative comparison between the active and traditionalapproaches was carried out by simulating the aforementioned10-panel string with 7 sunlight-exposed panels and 3 shadedones. The string was assumed to be at T = 50 ◦C with a PVcurrent Iph = 2 A for the sunny cells. The shading condi-tions were applied as follows: one panel with all cells sharingIshadow = 1.2 A, one panel whose subpanels exhibit 4 cellswith Ishadow = 1.2 A and 16 with Ishadow = 0.8 A, and onepanel whose subpanels include 10 cells with Ishadow = 0.5 Aand 10 with Ishadow = 0.2 A. The resulting power–voltage char-acteristics are shown in Fig. 6, which evidences that the max-ima increase due to the beneficial impact of the active bypassapproach.

The comparison between the proposed system and the com-mercial Schottky-based scheme for panel #2 is worthy of partic-ular attention for various reasons. First, the drop VEC across thePNP BJT is expected to grow (compared with type #1) due to (i)the larger difference VTHB − VTHA , which reduces the drivingcurrent IB , and (ii) the higher current Ibypass that the bipolardevice is destined to handle; in addition, the SB1240 Schottkydiode offers a very low voltage drop for high currents.

An analysis was carried out by simulating panel #2 at T =50 ◦C with Iph = 5 A for the sunny cells, and a shaded subpanelwith Ishadow spanning from 0.5 to 4.5 A. Three different bypassapproaches were considered, namely, the standard scheme withthe Schottky diode alone, the diode-less active circuit, and one in

Fig. 6. Produced power as a function of string voltage Vstring for the caseof three shaded panels belonging to a 10-panel string with modules of type #1.The curve obtained with the proposed approach (solid line) is compared withthe one corresponding to the traditional P-N bypass diode (dashed).

Fig. 7. Voltage drops versus current Ishadow for different bypass approachesapplied to panel #2 with a shaded subpanel. The behavior obtained with theSchottky diode alone (dashed line) is compared with those determined by thediode-less (solid) and the Schottky-equipped (dotted) variants of the activebypass circuit.

which both solutions coexist, i.e., the Schottky diode is mountedin antiparallel to the PNP device, as depicted in Fig. 1(c). Fig. 7shows the evaluated voltage drops across the bypass elements asa function of the shading-limited current for all the above cases.An inspection of the figure reveals that the Schottky-enrichedactive bypass architecture deserves to be preferred to the othertwo solutions, since it ensures a low voltage drop regardless ofthe shading level. In particular, the bypass task is effectivelyaccomplished by the Schottky diode when the current to handleis high. This device must therefore be added to the active bypassscheme in the place of a P-N diode for modules featuring ahigh photogenerated current since, besides the backup scope, itcontributes to keep the power loss within low bounds when thesubpanel is subject to critical shading conditions.

The experimental transient evolution of the voltage dropsacross the bypass devices for panels #1 (Isc ≈ 2.1 A) and #2(Isc ≈ 5 A) is illustrated in Fig. 8(a) and (b), respectively. Inboth cases, the diode-less PNP/NMOS circuit shown in Fig. 3was compared with the solutions relying on commercial diodes.Two different shading conditions were intentionally generated


Fig. 8. Measured transient evolution of the voltage drops over the bypassdiodes (dashed lines) and PNP BJTs (solid) for (a) panel #1 and (b) panel#2 at different shading levels. In both cases, only 4 cells of a subpanel wereintentionally obscured.

by using two filters placed over 4 cells of a subpanel, and thedrops across the bypass elements, as well as the bypass currents,were monitored by using the setup described in Section IV.The sunny operating conditions were restored by removing thefilter, after which the drops rapidly become negative. It is shownthat for the case of panel #1 the active circuit prevails over thetraditional approach independently of the shading level. Con-versely, for the case of module #2, it dominates only for lowbypass currents, while guaranteeing the same performance ofthe Schottky-based scheme for Ibypass amounting to 4 A.

PSPICE simulations were carried out to quantify the benefitsof the proposed circuit in terms of reliability of the individualcells in a shaded subpanel. In particular, a module #1 providedwith (i) a conventional diode, (ii) a diode-less variant of the pro-posed circuit, and (iii) a combination of the two, was analyzedat T = 50 ◦C. A subpanel was assumed partially shaded withan assigned number of ideally dark cells (Iph = 0 A); all othercells were considered sunny with Iph = 2.1 A. Fig. 9 shows thevoltage drop across one dark cell by incrementing the numberof obscured cells for the above cases. It is found that for theworst-case scenario of only one dark cell, the standard solutionrelying on a mere diode leads to a reverse drop amounting to11.4 V, which reduces to 8.71 V (25%) by exploiting both thevariants of the active bypass circuit. This improvement reducesby increasing the number of dark cells.

A weak point of the approach is the power dissipated byMOST A, which suffers from the burden to keep Vsubpanel

Fig. 9. Voltage drop across a chosen completely dark cell as a function ofnumber of obscured cells (all belonging to the same subpanel) for a module #1,corresponding to the cases of a conventional diode (dashed line), the diode-lessactive bypass circuit (solid), and a combination of the two (dotted).

positive, thus alleviating the hot-spot problem in the shadedsubpanel. This problem can be particularly acute when the PVcurrent is high and the shading level is low (which concurrentlyimply a large Ishadow value). In order to analyze this issue,PSPICE simulations were carried out at T = 75 ◦C on a 3-subpanel module of type #2 by assigning Iph = 8 A to all thesunny cells, and uniformly shading one subpanel with chosenvalues of Ishadow . The Schottky-equipped variant of the pro-posed active circuit was considered. The powers dissipated byall the individual elements (PDA , PDB , PDQ , and PDSchottky forthe NMOSTs A and B, the PNP BJT, and the Schottky diode,respectively), as well as the total power dissipated by the by-pass circuit (Ptotal , defined as PDA+PDB+PDQ + PDSchottky)were monitored. In particular, Fig. 10(a) reports the maximumPtotal versus Ishadow , along with all the individual power com-ponents evaluated at voltage Vpanel corresponding to the max-imum Ptotal . It is found that the price to pay to keep Vsubpanelpositive is a high Ptotal , which spans from about 5 W to 20 Wwith increasing Ishadow , being mostly attributed to the Schot-tky diode at low Ishadow (high Ibypass) and to NMOST A asIshadow becomes higher than 1 A. It is noteworthy that (i) forIshadow>2 A, the bypass current flows mainly in the BJT, whichtherefore dissipates more than the Schottky diode; and (ii) thepower dissipated by the pass-transistor NMOST B, which con-ducts the low base current of the BJT, is negligible.

Lastly, the improvement attained by considering 4 paralleledNMOSTs A in the place of a single transistor was exploredthrough PSPICE for a module of type #2. First, it was observedthat VDSAsc under standard conditions reduces to about 2.16 V(from 2.45 V corresponding to the case of only one device);this allowed adopting the NMOST B with VTHB = 2.21 V em-ployed for panel #1. The analysis was performed in the formerlyadopted conditions (Iph = 8 A, T = 75 ◦C). Results, illus-trated in Fig. 10(b), can be summarized as follows: (i) the max-imum Ptotal slightly reduces compared with the scheme withonly one NMOST A; (ii) the power dissipated by a single de-vice A drastically decreases, thereby alleviating the overheatingissue; (iii) the reduction of the difference VTHB − VTHA leadsto a VEC decrease for a given bypass current. As a consequence,


Fig. 10. Total power and its individual components dissipated by the Schottky-equipped bypass circuit as a function of the current Ishadow flowing in a shadedsubpanel of module #2 (Iph = 8 A, T = 75 ◦C) for the case of (a) 1 and(b) 4 NMOST(s) A.

for very low Ishadow , Ibypass is shared by BJT and Schottkydiode [and not only taken by the diode as in the case reportedin Fig. 10(a)]; when Ishadow grows, the bypass action is onlyperformed by the BJT.

VI. CONCLUSION

In this work, a simple-to-implement bypass system for sub-sections of PV panels has been presented, which relies on abipolar transistor driven into saturation mode in case of shad-ing or malfunction events. The circuit is based on the actionof only two NMOSTs to automatically enable/inhibit the bipo-lar device, and can be used concurrently with an antiparalleledSchottky diode to support the bipolar transistor under criticalshading conditions for panels with large cell size. As demon-strated by a large campaign of simulations and measurements,the proposed scheme allows enhanced subpanel reliability andhigher power production of the PV string compared with the tra-ditional diode-based approach. However, this is obtained at theprice of the power consumption of the MOST devised to keeppositive the voltage drop across the subpanel, which can becomesignificant for large cell size and low shading level; a solu-tion to counteract the resulting overheating has been examined,which involves the adoption of a chosen number of paralleledNMOSTs in the place of a single device.

ACKNOWLEDGMENTS

The authors would like to thank R. Carta (Vishay Semicon-ductors, Turin, Italy) for providing the power MOSTs adopted inthe experimental analysis, Dr. A. G. Metzger (Skyworks Solu-tions Inc., Newbury Park, CA, USA) for his effort in reviewingthe technical English, and the anonymous reviewers for theirhelpful and constructive comments.

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Vincenzo d’Alessandro received the Laurea andPh.D. degrees in electronics engineering from Uni-versity Federico II, Naples, Italy, in 1999 and 2003,respectively.

He is currently an Assistant Professor with theDepartment of Electrical Engineering and Informa-tion Technology, University Federico II, where heteaches semiconductor devices and digital circuits.He has co-authored more than 100 papers in refereedinternational journals and conference proceedings, aswell as a book chapter. His current research interests

include electrothermal and thermal modeling/simulation of semiconductor de-vices and circuits with particular emphasis on bipolar technology, and model-ing/simulation of photovoltaic modules and arrays.

Dr. d’Alessandro is a Reviewer for the IEEE ELECTRON DEVICE LETTERS,Solid-State Electronics, Microelectronics Reliability, and the International Jour-nal of Numerical Modeling, as well as international conferences.

Pierluigi Guerriero received the Laurea and Ph.D.degrees in electronics engineering from Univer-sity Federico II, Naples, Italy, in 2007 and 2012,respectively.

He was a Designer of automation control systemswith Avio Interiors, Latina, Italy, from 2007 to 2008.From 2009 to 2012, he was an R&D Project Head,working on photovoltaic applications with ISET Srl,Valle di Maddaloni, Italy. He is currently a Postdoc-toral Researcher with the Department of ElectricalEngineering and Information Technology, University

Federico II. He has co-authored 13 papers in refereed international journalsand conference proceedings. His research interests include monitoring systemsfor photovoltaic arrays, development of effective MPPT algorithms, as well asdc–ac converters.

Santolo Daliento received the Laurea and Ph.D. de-grees in electronics engineering from University Fed-erico II, Naples, Italy, in 1992 and 1996, respectively.

He is currently an Associate Professor with the De-partment of Electrical Engineering and InformationTechnology, University Federico II, where he teachesanalog electronics and photovoltaic devices and sys-tems. He has co-authored more than 70 papers inrefereed international journals and conference pro-ceedings. His research interests include modeling ofpower devices, lifetime engineering treatments, semi-

conductor characterization techniques, and innovative photovoltaic devices.

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A Simple Bipolar Transistor-Based Bypass Approach for Photovoltaic Modules