A sub-1µW, 16kHz Current-Mode SAR-ADC forSingle-Neuron Spike Recording

Bard Haaheim∗† and Timothy G. Constandinou∗†∗Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK

†Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UKEmail: bard@haaheim.org, t.constandinou@imperial.ac.uk

Abstract—This paper presents an ultra-low-power 8-bit asyn-chronous current-mode (CM) successive approximation (SAR)analogue-to-digital converter (ADC) for single-neuron spikerecording. The novel design exploits CM techniques to supportoperation at supply voltages down to 1.2V , consuming under500nA at 16kSamples/s. The design features easy scalability, andallows for a tuneable sampling frequency and dynamic range(DR). The circuit is designed in a commercially-available 0.18µmCMOS technology and occupies a chip area of 0.078mm2. Thesystem requires a single, post-fabrication current calibration sup-ported by on-chip circuitry to ensure robust operation throughprocess and mismatch variations.

Index Terms—ADC, current-mode, SAR, neural, low power,compact area

I. INTRODUCTION

With ever-advancing trends in microelectronics, researchersare now innovating analytical tools for the in-vivo measure-ment of neural activity. Next generation neural interfacesare being developed for totally-implantable devices that usewireless bio-telemetries for the transmission of both powerand data. Such links require digitised signals for efficient andreliable data transmission thus introducing the need for on-chip and ultra-low-power ADCs. These new platforms willneed to support 100s of channels monitoring single-neuronactivity that use DSPs for feature extraction and spike sortingto reduce the data requirements prior to data transmission. Thisis because for such high channel counts, the raw data rate is farhigher than the available bandwidth in the wireless telemetry[1], [2]. For this, Nyquist rate ADCs are required with a marginfor anti-aliasing filter roll-off, implying ∼16kSamples/s for the(0.3-5)kHz spike signal frequency range of interest.

Traditionally, such systems use single, multiplexed ADC’sthat are time-shared [3], whereas this paper introduces an ultra-low-power ADC for single-channel implementations allowingfor an efficient and easily-scalable system. This techniqueis implemented in [4], using charge redistribution voltage-mode SAR-ADCs. However, current-mode (CM) convertersare now demonstrating excellent characteristics and in par-ticular, high resource efficiency (power and area) [5]–[7].Such techniques are therefore highly desirable for single-neuron spike recording applications. This paper addresses thechallenge of a relatively high digital power consumption in[5] by applying analogue methods and exploiting a one-timecalibration to reduce the transistor area needed to ensure linearoperation over process and mismatch variations, maintaining

a 3σ production yield. A novel current comparator is alsopresented that balances speed with resolution by dynamicallyadjusting the feedback impedance of an inverting amplifier.

The paper is organised as follows: Section II presentsthe proposed system architecture, Section III describes thetransistor level design for the individual circuit blocks andSection IV presents the system performance and draws acomparison with other relevant work from the literature.

II. SYSTEM OVERVIEW

CM-SAR ADCs are based on the same fundamentals astheir voltage-mode counterparts (e.g. charge redistributionSAR ADC) which are generally low power, low speed, smallarea and medium precision. The CM-SAR ADC, in contrastto voltage mode, needs only MOSFET devices for numericaland logical operation and additionally has the potential tooperate down to a very low power supply. Therefore this canpotentially: (1) reduce the area requirements, (2) reduce powerconsumption and (3) achieve high speed operation.

iDAC

iIN Logic

andRegisters

CM-DAC

CurrentComparator Digital

output

Analogue input 1 N

Nb

Fig. 1. System level design for the proposed CM-SAR ADC.

This system is implemented following the conventional CM-SAR ADC architecture shown in Fig. 1. The digital output isgenerated by comparing the input current to a reference current(IDAC) in sequence for each bit in the selected resolution,adding up to N-cycles per conversion (i.e. a binary search).For each cycle, the current comparator feeds back to the logicadjusting the reference current closer to the input value. Thereference current is generated by a CM digital-to-analogueconverter (CM-DAC) calculated according to Eqn. (1) where(b) is an internal register loaded into the output register atthe End-of-Conversion (EOC). The conversion is started by anEnable signal, which together with the EOC signal providesthe handshake for asynchronous operation.

IDAC = Ibias ·N−1∑n=0

2nbn (1)

ifq

Po

siti

ve f

eed

ba

ck

loo

p

vdda

vcharge

reset turnOn

M1

M2

M3

M4

M5

M6

M7

M8 M9

v1

v2

vout

ifee

db

ack

W/L2W/L

Cfq

Fig. 2. Threshold detecting circuit with positive feedback used in the impulsegenerator to create ∼µs pulses in the driving of the SAR algorithm.

Ibias controls the input dynamic range (DR), which makes thepower consumption of the DAC module directly proportionalto the signal level and thus favourable for the low energyneural signals.

III. IMPLEMENTATION

A. Control Logic

The digital logic used to realise the SAR algorithm issimilar to what is demonstrated in [7] using an impulsegenerator and simple logic to generate the DAC control. Ingeneral, digital logic switching at low frequency, uses a smallamount of power as long as the drive signals are fast andthe output capacitances are small. Storage capacitors havetherefore been avoided to minimize capacitance and replacedby flip-flops. Furthermore, care has been taken in the designof the connections between the analogue and digital circuitsto ensure fast transitions for non-current starved logic. In theimpulse generator, a current charged capacitor (Cfq) has beenused to create relatively long delays (∼µs) required to ensurecircuit settling times are met. This implies a slowly varyingvoltage would consume significant power, if connected directlyto digital logic. However, the circuit shown in Fig. 2 has beenused to address this. When the inverter (M1-M2) begins tochange state, the current through it increases causing a voltagedrop across M3, thus turning on M5 [8]. This speeds up theswitching process and therefore ensures low power operationby reducing the transition time. M4 is used to turn off thecurrent feedback when it is idle. The sampling frequency ofthe ADC is given by Eq. 2 and is therefore proportional to theselected charging current.

fs =1

N

ifqCfqVth

(2)

B. Current Comparator

The current comparator uses a combination of capacitiveand resistive current detection [9], [10], shown in Fig. 3. Thenon-linear resistance formed by M5-M6 is used to providefeedback to the zero-adjusting inverting amplifier consistingof M1-M4. This resistance limits the voltage drop for large

vdda

out

Resistive feedback loop

M3

M1

M2

M4

v1v2

icic

M6

M5

Resistive feedback loop

CM

B1

BufferM7 M8

M9 M10

M11M12

M13

vdda

ibias

OTA stage 1OTA stage 2

Bias generation for feedback loop

M14M15 M16

M17

M18

M19 M20

v4vcm

vn

vp

v3

Fig. 3. Current comparator circuit with non-linear resistive feedback.

input currents (ic) whilst appearing as an open circuit forsmall voltages, effectively disconnecting the feedback loop.This ensures both a high resolution and fast response time inaddition to tying the input voltage to a common mode. Becausethe node voltage V2 only deviates from the common-modeby the voltage drop across M5-M6, the current comparatormodule needs further amplification to generate the digitaloutput. This is achieved by connecting a differential amplifier(M7 −M13) to the common mode voltage and V2. However,because the OTA requires a constant bias current it is vitalto keep this as small as possible to save power. Using smallbiases compromises the slew-rate introducing the need tospeed up the transitions before connecting to digital logic. Thisis implemented using a current starved inverter chain (Buffer).The biasing of the feedback transistors (M5-M6) is required tofollow Eq. 3-4. These voltages are generated using transistorsM15-M20. For the topology to work, it is also essential thatthe feedback amplifier (M1-M4) is able to source and sinkthe current levels provided at the input, the maximum givenby 2N−1ibias. The gain bandwidth product of the amplifieralso applies power constraints for a given sampling frequencyas it is approximately inversely proportional to the square ofthe settling time. Transistors M3 −M4 are used to limit thepower consumption of inverter M1 − M2 by reducing theavailable supply rail, effectively reducing VGS and VDS forthe inverter (given a sub-threshold operation), resulting in agreatly reduced power consumption.

Vn ≤ CM + Vtn (3)Vp ≥ CM − |Vtp| (4)

C. Current-Mode DAC

The CM-DAC circuit consists of a binary weighted currentsplitting array using cascoded current mirrors. By using thistopology, the module is optimized for DR and accuracy at theexpense of speed and mismatch (for a given area). However,current steering has been employed to avoid turning off thecurrent mirrors, thus also avoiding the speed issue. Because

iCalibX

vdda

. . .

S1 S2 SX

M1 M2 M3

iBias

iBias

iBias/21

iBias/22

. . .

iBias/2x

x . . .

M4 M5

M6 M7 M8

. . .

iBias/2x

CalibX

Fig. 4. Example circuit used for current calibration.

the input voltage of the proceeding current comparator isfixed, the CM-DAC can be connected directly without causingfurther non-linearities due to channel-length modulation. Atnano-ampere bias levels, mismatch will limit the linearity ofthe CM-DAC, thus limiting the resolution of the ADC [11].To achieve an 8-bit resolution for this technology requirescalibration. This is achieved by creating the calibration circuitshown in Fig. 4. A calibration circuit is attached to each ofthe current branches in the CM-DAC, between the cascodedcurrent mirror and the current steering switches such as toinfluence the DC current within each bit in the CM-DAC. Thismismatch correction requires a one-time calibration settingswitches sx to the required values, stored in non-volatilememory provided on-chip (or using a fuse block). The requirednumber of calibration bits depends on selected transistorsizes and process technology. For the circuit presented herein,this requires 4-bits calibration in each direction, using itsPMOS counterpart to generate the positive correction current.The number of calibration bits is derived from Monte-Carlosimulations given in the results section. Because of mismatchin the input current mirror, the exact DR cannot be predictedand thus a calibration circuit is added to the bias to ensurefull scale operation. A calibration current is also added to theinput of the comparator because of the inherent asymmetrybetween the NMOS and PMOS devices, thus to cancel outany offset. However, it is only the mismatch in the CM-DACmodule that causes non-linearities. To complete the calibrationcircuit, a similar module was also added to adjust the samplingfrequency (ifq).

IV. SIMULATION RESULTS

The design has been implemented in an IBM 0.18µmHV CMOS technology and simulated in Cadence Spectre IC5.1.41ISR3 with foundry-supplied BSIM 3v3.2 models. Thesimulation temperature is set to 37C representing an in-vivoenvironment. The design has however also been validated overthe range 20−40C to ensure reliable operation within a mar-gin for fluctuations and during test at room temperature. Theinput signal frequency is limited only by the input mirror stage,which for this design is set to the Nyquist criterion of FS

2 .Due to relatively large device sizing, the noise contributionsproved to be significant lower than 1 LSB. A comparison of

this design with other similar ADCs is given in table I.

TABLE ICOMPARISON OF LOW POWER ADCS

Parameter [5] [7] [6] [12] Thiswork

VDD 1V 0.6V 0.55V 1V 1.2Technology 0.13µm 0.18µm 0.18µm 0.35µm 0.18µmMode I-Mode I-Mode I-Mode V-Mode I-ModeResolution 8 8 8 12 8ENOB 7.6bit 8 8 10.2 8Area [mm2]† 0.005 0.004 0.009 1†† 0.078Sampling rate 1kS/s 100kS/s 250kS/s 1kS/s 16kS/sFOM (fJ/conv) 1314 16 9 435 132Power [nA] 255 667 1054 512 450

.†Estimated chip area ††Area include ECG circuit

0 10 20 30 40 50 6010

−7

10−6

10−5

10−4

10−3

Time [µs]

Pow

er

[nA

]

0 10 20 30 40 50 60−30

−20

−10

0

10

20

30

40

Time [µs]

I C [

nA

]

0 10 20 30 40 50 60

0

0.5

1

1.5

Time [µs]

Vcom

p a

nd V

1 [

V]

Fig. 5. The current consumption (top), the CM-DAC output current (middle)and the input and output voltages of the current comparator(bottom) of theADC applying iin=49nA, 0-256nA being the DR.

The typical operation of the ADC for a 49nA input currentis illustrated in Fig. 5. The top graph shows the overall powerconsumption where on average 60nA is required by the digitalcircuits. The middle graph shows the input current to thecomparator module and the bottom graph shows the input andoutput voltages. It can be observed that whenever the currentis negative, the output voltage goes high and the oppositeoccurs while the input voltage is stable. The minimum currentrequired by the comparator module is 128nA given a 1nAbias in addition to the OTA (logic driver) contribution raisingthe average power consumption to ∼250nA for the module.However, it is noted that the design of the OTA can be furtheroptimized for power efficiency or alternatively replaced with

0 50 100 150 200 250−0.05

0

0.05

0.1

0.15

Digital Input (Dec)

INL [

LS

B]

0 50 100 150 200 250−0.2

−0.1

0

0.1

0.2

Digital Input (Dec)

DN

L [

LS

B]

Fig. 6. INL and DNL of ADC using 1nA bias.

−10 −5 0 5 1010

1

102

103

104

105

106

Input current IC[nA]

Input

Resis

tance [

MΩ

]

Estimated

Measured

Fig. 7. Input impedance of the current comparator module.

another suitable topology (i.e. to provide sufficient amplifica-tion with a high slew-rate), but this has been left for futurework. The INL and DNL of the ADC are shown in Fig. 6.This has been tested using a full scale stepwise ramp signalover a 16ms duration. Fig. 7 shows the input impedance ofthe comparator module for input currents around zero togetherwith an estimated line being an ideal 0.2V voltage drop overthe feedback resistance. From this it can be seen that the circuithas a resolution well within nano-ampere range and followsclose to a ±0.2V logic output.

A. Monte-Carlo simulations

To ensure a reliable design, Monte-Carlo analysis of eachindividual current mirror has been performed, thus to ensurethe resolution of the calibration is sufficient for the expectedlevel of process variation and mismatch. Selecting the currentsplitting transistors to be L/W=2/20, the MSB current branchhas a typical σSD = 1.4LSB resulting in the requirementof a 4-bit calibration circuit in each direction (assumingeach branch uses the same calibration resolution). Offset andgain errors in addition to the sampling frequency bias werealso of a similar level and thus chosen to be of the same

calibration resolution for easy programmability, adding up toa requirement of 11-bytes (i.e. 88-bits) of non-volatile memoryon-chip. As the mismatch is transistor area dependent, anoptimal solution to reduce the number of calibration bits fora given area, leaves room for further design optimization.

V. CONCLUSION

This paper has presented an 8-bit CM-SAR ADC requiringa current consumption of 500nA at 16kSamples/s. The designfeatures good programmability as both the DR and Fs aredependent on selected bias. The power consumption is scaledwith the input current level making this ADC suitable forsignals of low energy content. The novel design using analoguetechniques achieves asynchronous operation making this ADCideal for single-neuron recording applications. The silicon areafootprint is under 0.078mm2 in a 0.18µm CMOS technology.

ACKNOWLEDGEMENT

This work was supported by the UK Engineering and Phys-ical Sciences Research Council (Grant ref: EP/I000569/1).

REFERENCES

[1] A. Eftekhar, S. E. Paraskevopoulou, and T. G. Constandinou, “Towardsa next generation neural interface: Optimizing power, bandwidth anddata quality,” Proc. IEEE BioCAS, pp. 122–125, 2010.

[2] R. Harrison, “The design of integrated circuits to observe brain activity,”Proc. IEEE, vol. 96, no. 7, pp. 1203 –1216, 2008.

[3] F. Shahrokhi, K. Abdelhalim, D. Serletis, P. Carlen, and R. Genov, “The128-channel fully differential digital integrated neural recording andstimulation interface,” IEEE Trans. Biomedical Circuits and Systems,vol. 4, no. 3, pp. 149–161, 2010.

[4] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black,B. Greger, and F. Solzbacher, “A low-power integrated circuit for awireless 100-electrode neural recording system,” IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 123 –133, 2007.

[5] S. Al-Ahdab, R. Lotfi, and W. Serdijn, “A 1-v 225-nw 1ks/s currentsuccessive approximation adc for pacemakers,” Proc. IEEE PRIME,pp. 1–4, 2010.

[6] R. Dlugosz and K. Iniewski, “Ultra low power current-mode algorithmicanalog-to-digital converter implemented in 0.18um cmos technology forwireless sensor network,” Proc. IEEE MIXDES, pp. 401–406, 2006.

[7] R. Dlugosz, V. Gaudet, and K. Iniewski, “Flexible ultra low powersuccessive approximation analog-to-digital converter with asynchronousclock generator,” Proc. IEEE CCECE, pp. 1649–1652, 2007.

[8] E. Culurciello, R. Etienne-Cummings, and K. Boahen, “A biomorphicdigital image sensor,” IEEE Journal of Solid-State Circuits, vol. 38,no. 2, pp. 281–294, 2003.

[9] R. del Rio-Fernandez, G. Linan-Cembrano, R. Dominguez-Castro, andA. Rodriguez-Vazquez, “A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage cmos,” Proc.IEEE Analog and Mixed IC Design, pp. 111–116, 1997.

[10] L. Chen, B. Shi, and C. Lu, “A high speed/power ratio continuous-timecmos current comparator,” vol. 2, pp. 883–886, 2000.

[11] B. Linares-Barranco and T. Serrano-Gotarredona, “On the design andcharacterization of femtoampere current-mode circuits,” IEEE Journalof Solid-State Circuits, vol. 38, no. 8, pp. 1353–1363, 2003.

[12] X. Zou, X. Xu, L. Yao, and Y. Lian, “A 1-v 450-nw fully integratedprogrammable biomedical sensor interface chip,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1067–1077, 2009.