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7/25/2019 A Top Down Approach to Mixed Signal SoC Verification
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S Bangalore, India
Insert CompanyLogo Here
Copyright 2011 Magma Design Automation, Inc.
A Top-Down Approach toMixed-Signal SoC Verification
Sudarshanam Kommanaboyina
Microchip Technology India Pvt. Ltd.
7/25/2019 A Top Down Approach to Mixed Signal SoC Verification
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2 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.
Agenda
Challenge Traditional flow to simulate analog, digital blocks
Mixed-signal simulation Co-Sim observations Feasibility of Finesim for Co-Sim
Example
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Challenge
Mixed-signal SoC design Polarity issues at the interface between
analog and digital blocks Functional issues at the interface Approach suggested to avoid re-spin
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Standalone Analog Simulations
en
reset_nstart
trim[4:0]
sel[2:0]
an_in1
an_in2
an_in3
control[4:0] an_out5
an_out1an_out2
an_out3
an_out4
dig_out3
dig_out1
dig_out2
ANA
LOG
NETLIST
SPICE
Stimulus from analog testbench
Stimulus from RTL simulations
or
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Observations
Analog stimulus generated from designers with human errors indesign can carry the same perception to analog testbench that mayresult in polarity issuesEg. Control signal polarity getting inverted at the analog-digitalinterfaceStimulus from RTL simulation has controllability and it is possibleto catch the polarity issues
It is tedious to check the results manually from the above twomethods
Almost no verification done after integration of standalone blocks (simulated in spice) causing possible functional failuresEg. missing level shifter in multi-supply designs
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Full-Chip RTL Simulations
en
reset_n
starttrim[4:0]
sel[2:0]
an_in1
an_in2
an_in3
control[4:0] an_out5
an_out1
an_out2an_out3
an_out4
dig_out3
dig_out1
dig_out2
RTL
BLOCK
1
BL
OCK
2
ANALOG
MODE
L
B
EHAVIO
RAL
R
TL
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Observations
Behavioral models of analog modules used(Verilog/VHDL)Uses full-chip testbench to simulate full-chip RTL +
analog behavioral modelsBehavioral model may not match with analog spicenetlist since it cannot capture spice device/modelcomplexityGenerates stimulus for standalone analog simulationswhich are then used to run block level spice simsNot possible to catch polarity issues, functional bugs
at the interface
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Full-Chip Spice Simulations
enreset_nstart
trim[4:0]
sel[2:0]
an_in1
an_in2
an_in3
control[4:0] an_out5
an_out1an_out2
an_out3
an_out4
dig_out3
dig_out1
dig_out2
NETLIS
T
BLOC
K
1 NE
TLIST
BLOCK
2
ANA
LOG
NETL
IST
SPI
CE
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Observations
Digital gates equivalent spice netlist + Analog spice netlist usedfor full-chip simulation
Takes weeks to run in true-spice and several days in fastSpice
Very few test cases are run at this stage, may not be possible tocatch the interface bugs
No standard verification methodology exists currently confirmingthe verification coverage/closure.
Bugs caught at this stage may postpone the tapeout
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Full-Chip Co-Sim Simulation
enreset_nstart
trim[4:0]
sel[2:0]
an_in1
an_in2
an_in3
control[4:0] an_out5
an_out1an_out2
an_out3
an_out4
dig_out3
dig_out1
dig_out2
BLOC
K
1
BLOCK
2
ANA
LOG
NETLIST
SPICE
RTL
RTL
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Full-Chip Co-Sim Simulation (Contd)
RTL + Analog Spice netlist simulationRTL simulation by QuestaSim
Analog spice simulation by Finesim
Digital-to-Analog (D2A) & Analog-to-Digital(A2D) interface
Logic D2A A2D
1 vdd >vdig1
0 gnd
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Observations
Start Co-Sim by plug-and-play analog blocks as and when theblock gets ready, without waiting for all the blocks to get ready
Compared to full-chip Spice simulation, Co-Sim takes very less
time to simulate the whole chip as the digital blocks are in RTLformEg. fastSpice Vs spice - ~10-30X
Cosim Vs spice ~100X
Functional bugs and polarity issues between analog and digitalblocks can be caught at the early stage of design
Uses the existing full-chip RTL test bench infrastructure to verifyanalog modules under real conditions
Feasibility to choose among analog Spice, fastSpice modes,verilogA models all spice or mixed spice+verilogA
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Feasibility of Finesim for Co-Sim
Features Magma (Finesim)Verilog support Yes
System Verilog support Yes
Changes to behavioral models Required/optional
VerilogA Yes
VerilogAMS Underdevelopment
Spice netlist Yes
All advanced features of Finesim can be used for Co-Sim( multi-cpu simulations, spice mode, fast mode etc)
Finesim supports all major RTL simulation tool vendors( Modelsim, Ncsim, VCS)
Finesim has a provision to specify the voltage levels to each pinseparately, supports multi-voltage domain
Also supports instance based replacement
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Co-Sim Example Using Finesimmodule top;// logic/reg/wire declaration
test1 inst_test1(.in1 (out1 ),.in2 (out2 ),.in3 (in3 ),.in4 (in4 ),.out1 (out1 ),
.out2 (out2 ),
.out3 (out3 ),
.inout1(inout1),
.inout2(inout2));
test2 inst_test2(.in1 (in1 ),.in2 (in2 ),.out1 (out1 ),.out2 (out2 ),.out3 (out3 )
);initialbegin//{
//testbench
end//}initial
$finesim_config(config.inc);endmodule
module test2(input logic in1 ,input logic in2 ,output logic out1 ,output logic out2 ,output logic out3);
assign out1 = in1 && in2;assign out2 = in1 || in2;assign out3 = in2;
endmodule
module test1(input logic in1 ,input logic in2 ,input logic in3 ,input logic [1:0] in4 ,output logic out1 ,output logic out2 ,output logic out3 ,
inout inout1,inout inout2
);parameter finesim_a2d=avdd";parameter finesim_d2a=dvdd";parameter finesim_d2a$in1="dvdd1";parameter finesim_d2a$in4[1]="dvdd1";parameter finesim_d2a$inout1="dvdd1";parameter finesim_a2d$inout1="avdd1";parameter finesim_a2d$out1="avdd1";initial $finesim_module;
endmodule
config.inc.a2d avdd vl=0.9 vh=0.9.d2a dvdd vl=0 vh=2.8 vx=1.4 tr=0.3n tf=0.3n.a2d avdd1 vl=1.4 vh=1.4.d2a dvdd1 vl=0 vh=1.8 vx=0.9 tr=0.3n tf=0.3n.finesim test1.sp.option dump_ie=1.option port_map_by_name=1 bus_format=[%d].option minimize_ie=1
test1.spvvdd VDD 0 dc 1.8vvss VSS 0 dc 0.global vss vdd.inc ./model.inc.inc finemix.sp*Default name of spice instance netlist file
.subckt test1 in1 in2 in3 in4[0] in4[1]+ out1 out2 out3 inout1 inout2*Spice netlist.ends test1
*can specify any number of subckt*or specify paths for other spice netlist
.option post
.tran 1p 100ns
.end
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Q&A
Note: The Microchip name and logo are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries.All other trademarks mentioned herein are property of their respective companies.