a Transmit Signal Processor (TSP) Four Channel, 65 MSPS ...db.zmitac.aei.polsl.pl/Electronics_Firm_Docs/... · SDFSD SCLKD CIC RCF Filter NCO I Q I SPort Q data DATa SDINA SDFSA SCLKA

REV. PrK Analog Devices Preliminary SpecificationInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility isassumed by Analog Devices for its use, nor for any infringement of patents or other rights of third parties which mayresult from its use. No license is granted by implication of otherwise under any patent or rights of Analog Devices.Revision Code:120799. AD6622 Marketing Administrator: (336)-605-4205

a Four Channel, 65 MSPS DigitalTransmit Signal Processor (TSP)

PRELIMINARY TECHNICAL DATA AD6622FEATURESWideband Digital IF OutputWideband Digital IF Input Allows Cascade of Chips for Additional ChannelsProgrammable IF and Modulation for each ChannelProgrammable Interpolating RAM Coefficient FilterHigh Speed CIC Interpolating FilterNCO Frequency Translation Worst Spur Better than –100dBc Tuning Resolution Better than 0.02Hz Real or Complex OutputsDigital Summation of Channels Clipped or Wrapped Over-Range 2’s Complement or Offset Binary OutputSeparate 3-wire Serial Data Input for each ChannelMicroprocessor ControlJTAG Boundary Scan

APPLICATIONSCellular/PCS BasestationsMicro/Pico Cell BasestationsWBCDMAWireless Local Loop BasestationsPhase Array Beam Forming Antennas

SPort RCF CICFilter

NCO

SPort RCFCICFilter NCO



JTAG uPort

Sum

mation

18

18

CH A

CH B

CH C

CH D

FUNCTIONAL BLOCK DIAGRAM

PRODUCT DESCRIPTIONThe AD6622 comprise four identical digital transmit signalprocessors (TSP) complete with synchronization circuitry andcascadable wideband channel summation. An external Digital-to-Analog Converter (DAC) is all that is required to complete a wideband digital up-converter. On-chip tuners allow the relativephase and frequency for each RF carrier to be independentlycontrolled.

Each TSP has three cascaded signal processing elements: a RAMprogrammable Coefficient interpolating Filter (RCF), aprogrammable Cascaded Integrator Comb (CIC) interpolating

filter, and a Numerically Controlled Oscillator/tuner (NCO). Theoutputs of the four TSPs are summed and scaled on-chip.

In multi-channel wideband transmitters, multiple AD6622s maybe combined using the chip’s cascadable output summation stage.Each channel provides independent serial data inputs that may beconnected directly to the serial port of DSP chips. Userprogrammable FIR filters can be used to filter linear inputs.

All control registers and coefficient values are programmedthrough a generic microprocessor interface. Two microprocessorbus modes are supported. All inputs and outputs are LVCMOScompatible. All outputs are LVCMOS and 5V TTL compatible.

AD6622 PRELIMINARY SPECIFICATION

REV. PrK 2 Analog Devices Preliminary Specification

OUT

Sum

mat

ion

MICROPORT

ALE

A[2

:0]

/CS

/DS

/DT

AC

K

R/W

D[7

:0]

OEN

SYNC

IN

[17:0]

[17:0]

JTAG

TDI

TDO

TM

S

TCK

CLK

I

Q

I

Qdata

SDINC

SDFSC

SCLKC

I

Q

I

Qdata DATb

SDINB

SDFSB

SCLKB

I

Q

I

Qdata DATd

SDIND

SDFSD

SCLKD

CICFilter NCORCF

I

Q

I

SPort Qdata DATa

SDINA

SDFSA

SCLKA

QIN

QOUT

/TR

ST

NCO

NCO

CICFilter

CICFilter

/RE

SE

T

RCF

RCF

SPort

SPort

NCOCICFilterRCFSPort

DATc

AD6622 FUNCTIONAL BLOCK DIAGRAM

THEORY OF OPERATIONAs Digital-to-Analog Converters (DACs) achieve higher samplingrates, analog bandwidth, and dynamic range, it becomesincreasingly attractive to accomplish the first IF stage of atransmitter in the digital domain. Digital IF signal processingprovides repeatable manufacturing, higher accuracy, and moreflexibility than comparable high dynamic range analog designs.

The AD6622 Four Channel Transmit Signal Processor (TSP) isdesigned to bridge the gap between DSPs and high speed DACs.The wide range of interpolation factors in each filter stage makesthe AD6622 useful for creating both narrowband and widebandcarriers in a high speed sample stream. The high resolution NCOallows flexibility in frequency planning and supports both digitaland analog air interface standards. The RAM-based architectureallows easy reconfiguration for multi-mode applications.

The interpolating filters remove unwanted images of signalssampled at a fraction of the wideband rate. When the channel ofinterest occupies far less bandwidth than the wideband outputsignal, rejecting out-of-band noise is called “processing gain”. Forlarge interpolation factors, this processing gain allows a 12-bitDAC to express the sum of multiple 16-bit signals sampled at alower rate without significantly increasing the noise floor abouteach carrier. In addition, the programmable RAM Coefficientstage allows anti-imaging, and static equalization functions to becombined in a single, cost-effective filter.

The high speed NCO can be used to tune a quadrature sampledsignal to an IF channel, or the NCO can be directly frequencymodulated at an IF channel. Multi-carrier phase synchronizationpins and phase offset registers allow intelligent management ofthe relative phase of the independent RF channels. Thiscapability supports the requirements for phased array antennaarchitectures and management of the wideband peak/power ratioto minimize clipping at the DAC.

The wideband input and output ports allow multiple AD6622s tobe cascaded into a single DAC. The master clock for the entiresystem is based on the DAC clock rate (up to 65 MSPS). Theexternal 18-bit resolution reduces summation of truncation noise.The wideband ports can be configured for real or quadratureoutputs. Quadrature sampled outputs (I&Q) is limited to half themaster clock rate on the shared output bus.



RECOMMENDED OPERATING CONDITIONS

ParameterTestLevel MIN

AD6622ASTyp Max Units

VDD IV 2.4 3.0 3.3 VTAMBIENT IV -40 +25 +70 °C

ELECTRICAL CHARACTERISTICS

Parameter (Conditions) TempTestLevel Min


LOGIC INPUTS (5V TOLERANT) 3.0V CMOS Logic Compatibility Full Logic “1” Voltage Full IV 2.0 VDD+0.3 V Logic “0” Voltage Full IV -0.3 0.8 V Logic “1” Current Full IV 1 10 uA Logic “0” Current Full IV 1 10 uA Input Capacitance +25°C V 4 pFLOGIC OUTPUTS Logic Compatibility Full Logic “1” Voltage (IOH=0.25mA) Full IV VDD-0.05 VDD-0.035 V Logic “0” Voltage (IOL=0.25mA) Full IV 0.02 0.05 VIDD SUPPLY CURRENT CLK=60MHz, 3.3V 1 Full IV 506 5661 mA CLK=GSM Example V 3502

CLK=IS-136 Example V Tbd CLK=WBCDMA Example V Tbd Sleep Mode Full IV 0.1 0.5 mAPOWER DISSIPATION CLK=60MHz, 3.3V 1 Full IV 1.77 1.87 W CLK=GSM Example V Tbd CLK=IS-136 Example V Tbd CLK=WBCDMA Example V Tbd Sleep Mode Full IV 0.33 1.65 mWNOTES1 This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimuminterpolation in both CIC stages, maximum switching of input data, and maximum VDD of 3.3V. In an actual application the power will beless, see the Thermal Management section of the data sheet for further details.



TIMING CHARACTERISTICS1 (CLOAD=40pF All Outputs Unless Specified)

Name Parameter (Conditions) TempTestLevel Min


CLK Timing Requirements:tCLK CLK Period Full IV 12.5 nstCLKL CLK Width Low Full IV 5.5 0.5 x tCLK nstCLKH CLK Width High Full IV 5.5 0.5 x tCLK ns

/RESET Timing Requirements:tRESL /RESET Width Low Full IV 30.0 ns

Input Wideband Data Timing RequirementstSI Input to CLK Setup Time Full IV 0.5 nstHI Input to CLK Hold Time Full IV 3.5 ns

Parallel Output Switching Characteristics:tSO CLK to Output Setup Time Full IV 12 nstHO CLK to Output Hold Time Full IV 4.1 nstZO Output Tri-state Time Full V 5 ns

SYNC Timing Requirements:tSS SYNC to CLK Setup Time Full IV 2.6 nstHS SYNC to CLK Hold Time Full IV 1.5 ns

Serial Port Timing Requirements:tDSCLK CLK to SCLK Delay Full V 8.5 nstDSDFS SCLK to SDFS Delay Full IV -1.2 2.4 nstSSI SDI to SCLK Setup Time Full IV 10.2 nstHSI SDI to SCLK Hold Time Full IV 13.7 ns

MICROPROCESSOR PORT, MODE INM(ALE=0) MODE INM Write Timing:

tHWR /WR(R/W) to RDY(/DTACK) Hold Time Full IV 0 nstSAM Address/Data to /WR(R/W) Setup Time Full IV 0 nstHAM Address/Data to RDY(/DTACK) Hold Time Full IV 0 nstDRDY /WR(R/W) to RDY(/DTACK) Delay Full IV 10.2 nstACCFAST /WR(R/W) to RDY(/DTACK) High Delay Full IV 2*tCLK 3* tCLK nstACCMEDIUM /WR(R/W) to RDY(/DTACK) High Delay Full IV 3* tCLK 4* tCLK nstACCSLOW /WR(R/W) to RDY(/DTACK) High Delay Full IV 4* tCLK 5* tCLK ns

MODE INM Read Timing:tSAM Address to /RD(/DS) Setup Time Full IV 0 nstHA Address to Data Hold Time Full IV 0 nstZD Data Tri-state Delay Full IV 3.4 7 10.5 nstDD RDY(/DTACK) to Data Delay Full IV tCLK-10ns nstDRDY /RD(/DS) to RDY(/DTACK) Delay Full IV 10.2 nstACCFAST /RD(/DS) to RDY(/DTACK) High Delay Full IV 2* tCLK 3* tCLK nstACCMEDIUM /RD(/DS) to RDY(/DTACK) High Delay Full IV 3* tCLK 4* tCLK nstACCSLOW /RD(/DS) to RDY(/DTACK) High Delay Full IV 4* tCLK 5* tCLK ns

MICROPROCESSOR PORT, MODE MNM(ALE=1)MODE MNM Write Timing:

tHDS /DS(/RD) to /DTACK(RDY) Hold Time Full IV 0 nstHRW R/W(/WR) to /DTACK(RDY) Hold Time Full IV 0 nstSAM Address/Data To R/W(/WR) Setup Time Full IV 0 nstHAM Address/Data to R/W(/WR) Hold Time Full IV 0 nstDDTACK /DS(/RD) to /DTACK(RDY) Delay Full IV 1* tCLK nstACCFAST R/W(/WR) to /DTACK(RDY) Low Delay Full IV 2* tCLK 3* tCLK nstACCMEDIUM R/W(/WR) to /DTACK(RDY) Low Delay Full IV 3* tCLK 4* tCLK ns



tACCSLOW R/W(/WR) to /DTACK(RDY) Low Delay Full IV 4* tCLK 5* tCLK nsMODE MNM Read Timing:

tSAM Address to /DS(/RD) Setup Time Full IV 0 nstHA Address to Data Hold Time Full IV 0 nstZD Data Tri-State Delay Full IV 0 nstDD /DTACK(RDY) to Data Delay Full IV tCLK-10ns nstDDTACK /DS(/RD) to /DTACK(RDY) Delay Full IV 1* tCLK nstACCFAST /DS(/RD) to /DTACK(RDY) Low Delay Full IV 2* tCLK 3* tCLK nstACCMEDIUM /DS(/RD) to /DTACK(RDY) Low Delay Full IV 3* tCLK 4* tCLK nstACCSLOW /DS(/RD) to /DTACK(RDY) Low Delay Full IV 4* tCLK 5* tCLK ns1All Timing Specifications valid over VDD range of 2.4V to 3.3V.



OUT[17:0],QOUT

CLK

tCLK

tCLKH

tCLKL

tHO

tSO

OEN

tZO tZO

Figure X. Parallel Output Switching Characteristics.

SDI

SDFS

CLK

SCLK

tDSCLK

tDSDFS tDSDFS

tSSI tHSI

CLKn

DATAn

Figure X. Serial Port Switching Characteristics.

IN[17:0],QIN

CLK

tSI tHI

Figure X. Wideband Input Timing.

SYNC

CLK

tSS tHS

Figure X. SYNC Timing Inputs.



tSAM

/RD (/DS)

/WR (R/W)

/CS

A[2:0]

D[7:0]

RDY(/DTACK)

Valid Address

Valid Data

tSAM tHAM

tHAM

tDRDY

tHWR

tACC

Notes:1. tACC Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY. tACCFAST requires a maximum of 3 CLK periods and applies to A[2:0]=7,6,5,3,2,1 tACCMEDIUM requires a maximum of 4 CLK periods and applies to A[2:0]=4 and 0 if the access is to a Control Register not a RAM Register. tACCSLOW requires a maximum of 5 CLK periods and applies to A[2:0]=0 when accessing RAM Registers.

Figure X. INM MicroPort Write Timing Requirements.

tSAM

/RD (/DS)

/WR (R/W)

/CS

A[2:0]

D[7:0]

RDY(/DTACK)

Valid Address

tZDtDD

tDRDY

tZD

tACC

Valid Data

tHA

Notes:1. tACC Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY. tACCFAST requires a maximum of 3 CLK periods and applies to A[2:0]=7,6,5,3,2,1 tACCMEDIUM requires a maximum of 4 CLK periods and applies to A[2:0]=4 and 0 if the access is to a Control Register not a RAM Register. tACCSLOW requires a maximum of 5 CLK periods and applies to A[2:0]=0 when accessing RAM Registers.

Figure X. INM MicroPort Read Timing Requirements.



tSAM

/DS (/RD)

R/W (/WR)

/CS

A[2:0]

D[7:0]

/DTACK(RDY)

Valid Address

Valid Data

tSAM tHAM

tHAM

tHRW

tACC

tHDS

tDDTACK

Notes:1. tACC Access time depends on the Address accessed. Access time is measured from the FE of /DS to the FE of /DTACK. tACCFAST requires a maximum of 4 CLK periods and applies to A[2:0]=7,6,3,2,1 tACCMEDIUM requires a maximum of 5 CLK periods and applies to A[2:0]=4,5 and 0 if the access is to a Control Register versus a RAM Register. tACCSLOW requires a maximum of 6 CLK periods and applies to A[2:0]=0 when accessing RAM Registers.

Figure X. MNM MicroPort Write Timing Requirements.

tSAM

/DS (/RD)

R/W (/WR)

/CS

A[2:0]

D[7:0]

/DTACK(RDY)

Valid Address

tZDtDD

tZD

tHDS

tACC

Valid Data

tHA

tDDTACK

Notes:1. tACC Access time depends on the Address accessed. Access time is measured from the FE of /DS to the FE of /DTACK. tACCFAST requires a maximum of 4 CLK periods and applies to A[2:0]=7,6,3,2,1 tACCMEDIUM requires a maximum of 5 CLK periods and applies to A[2:0]=4,5 and 0 if the access is to a Control Register versus a RAM Register. tACCSLOW requires a maximum of 6 CLK periods and applies to A[2:0]=0 when accessing RAM Registers.

Figure X. MNM MicroPort Read Timing Requirements.



ABSOLUTE MAXIMUM RATINGS*Supply Voltage……………….……..-0.3V to +4.5VInput Voltage….-0.3 to VDD+0.3V (not 5V Tolerant)IN[17:0], QIN, OENInput Voltage……………….-0.3 to 5V (5V Tolerant)CLK, /RESET, /DS, R/W, ALE, A[2:0], D[7:0], SYNC, /TRST,TCK, TMS, TDI, SDINA, SDINB, SDINC, SDINDOutput Voltage Swing………..-0.3V to VDD +0.3VLoad Capacitance…………………………….200pFJunction Temperature Under Bias………….+125°CStorage Temperature Range……...-65°C to +150°CLead Temperature (5 sec)…………………..+280°C

* Stresses greater than those listed above may cause permanentdamage to the device These are stress ratings only; functionaloperation of the devices at these or any other conditions greaterthan those indicated in the operational sections of thisspecification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect devicereliability.

THERMAL CHARACTERISTICS128-Lead MQFP:θJA=33°C/Watt, no airflowθJA=27°C/Watt, 200 lfpm airflowθJA=24°C/Watt, 400 lfpm airflowThermal measurements made in the horizontal position on a 2-layer board.

EXPLANATION OF TEST LEVELSI. 100% Production Tested.II. 100% Production Tested at +25°C, and Sample Tested atSpecified Temperatures.III. Sample Tested Only.IV. Parameter Guaranteed by Design and Analysis.V. Parameter is Typical Value Only.VI. 100% Production Tested at 25°C, and Sample Tested atTemperature Extremes.

ORDERING GUIDE

Model Temperature Range Package DescriptionPackageOption

AD6622AS -40°C to +70°C (Ambient) 128-Lead MQFP (Metric Quad Flatpack) S-128AAD6622S/PCB Evaluation Board with AD6622 and Software

CAUTION

ESD (Electrostatic Discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and testequipment and can discharge without detection. Although the AD6622 features proprietary ESD protection circuitry, permanent damagemay occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoidperformance degradation or loss of functionality.



GN

D

OE

N

GN

D

GN

D

GN

D

OU

T0

OU

T1

OU

T2

GN

D

OU

T3

OU

T4

OU

T5

OU

T6

VD

D

OU

T7

OU

T8

OU

T9

OU

T10

GN

D

GN

D

GN

D

OU

T11

OU

T12

OU

T13

OU

T14

VD

D

OU

T15

OU

T16

OU

T17

QO

UT

GN

D

GN

D

D7

GN

D

GN

D

GN

D

D6

GN

D

GND

VDD

GND

TMS

TDO

TDI

SCLKA

VDD

SDFSA

SDINA

SCLKB

SDFSB

GND

GND

GND

SDINB

SCLKC

SDFSC

SDINC

VDD

SCLKD

SDFSD

SDIND

GND

VDD

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

GND

GND

SYNC

/RESET

/CS

VDD

A0

A1

A2

ALE

GND

GND

GND

R/W(/WR)

/DTACK(RDY)

/DS(/RD)

D0

VDD

D1

D2

D3

D4

GND

VDD

D5

GND

6463626160595857565554535251504948474645444342414039

IN14

IN15

IN16

GN

D

GN

D

IN17

QIN

GN

D

GN

D

CL

K

VD

D

GN

D

TC

K

/TR

ST

GN

D

GN

D

IN0

GN

D

GN

D

IN1

IN2

IN3

IN4

VD

D

IN5

IN6

IN7

IN8

GN

D

GN

D

GN

D

IN9

IN10

IN11

IN12

VD

D

IN13

GN

D

102

101

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

103104105106107108109110111112113114115116117118119120121122123124125126127128

AD6622TOP VIEW

(Not to Scale)



PIN FUNCTION DESCRIPTIONSName Type DescriptionVDD P +3.0V SupplyGND P Ground ConnectionCLK I Input Clock (actively pulled down if not connected)/RESET I Active Low Reset Pin (actively pulled up if not connected)OEN I Active High Output Enable Pin (actively pulled down if not connected) (not 5V tolerant)OUT[17:0] O/T Wideband Output DataQOUT O/T Indicates Q Output Data (Complex Output Mode)D[7:0] I/O/T Microprocessor Interface Data/DS or /RD I INM Mode: Read Signal, MNM Mode: Data Strobe Signal/DTACK or RDY O Acknowledgment of a Completed Transaction (Signals when uP Port Is Ready for an Access) Open Drain,

must be pulled up externallyR/W or /WR I Read/Write Line (Write Signal)ALE I Sets MicroPort Mode: ALE = 1, MNM Mode ALE = 0, INM ModeA[2:0] I Microprocessor Interface Address/CS I Chip Select, Enable the Chip for uP AccessSYNC I SYNC Signal for Synchronizing Multiple AD6622 (actively pulled down if not connected)QIN I Indicates Q Input Data (Complex Input Mode) (actively pulled down if not connected) (not 5V tolerant)IN[17:0] I Wideband Input Data (Allows Cascade of Multiple AD6622 Chips in a System) (actively pulled down if

not connected) (not 5V tolerant)/TRST I Test Reset Pin (actively pulled up if not connected)TCK I Test Clock Input (actively pulled down if not connected)TMS I Test Mode Select (actively pulled up if not connected)TDO O Test Data OutputTDI I Test Data Input (actively pulled down if not connected)SCLKA O Serial Clock Output Channel ASDFSA O Serial Data Frame Sync Output Channel ASDINA I Serial Data Input Channel A (actively pulled down if not connected)SCLKB O Serial Clock Output Channel BSDFSB O Serial Data Frame Sync Output Channel BSDINB I Serial Data Input Channel B (actively pulled down if not connected)SCLKC O Serial Clock Output Channel CSDFSC O Serial Data Frame Sync Output Channel CSDINC I Serial Data Input Channel C (actively pulled down if not connected)SCLKD O Serial Clock Output Channel DSDFSD O Serial Data Frame Sync Output Channel DSDIND I Serial Data Input Channel D (actively pulled down if not connected)



Name Pin NumberVDD 14,26,41,47,59,66,78,90,104,110,122,127GND 1,3,4,5,9,19,20,21,31,32,34,35,36,38,39,42,52,53,54,63,64,65,68,69,72,73,83,84,85,95,96,98,99,102,103,105,115,116

,117,126,128CLK 67/RESET 61OEN 2OUT[17:0] 29,28,27,25,24,23,22,18,17,16,15,13,12,11,10,8,7,6QOUT 30D[7:0] 33,37,40,43,44,45,46,48/DS or /RD 49/DTACK or RDY 50R/W or /WR 51ALE 55A[2:0] 56,57,58/CS 60SYNC 62QIN 70IN[17:0] 71,74,75,76,77,79,80,81,82,86,87,88,89,91,92,93,94,97/TRST 100TCK 101TMS 106TDO 107TDI 108SCLKA 109SDFSA 111SDINA 112SCLKB 113SDFSB 114SDINB 118SCLKC 119SDFSC 120SDINC 121SCLKD 123SDFSD 124SDIND 125



FUNCTIONAL OVERVIEWThe following descriptions explain the functionality of each of thecore sections of the AD6622. Detailed timing, application, andspecifications are described in detail in their respective portionsof the data sheet.

SERIAL DATA PORTThe AD6622 has four independent Serial Ports (A, B, C, and D)that each accepts data to its own channel (1, 2, 3, or 4) of thedevice. Each Serial Port has 3 pins: SCLK, SDFS, and SDIN.The SCLK and SDFS pins are outputs that provide serial clockand framing. The SDIN pins are inputs that accept channel data.The Serial Ports do not accept configuration or control inputs.The Serial Ports do not accept external clock or framing signals,although it is possible to synchronize the AD6622 Serial Ports tomeet an external timing requirement.

The serial clock output, SCLK, is created by a programmableinternal counter that divides down the master clock. When thechannel is reset, SCLK is held low. SCLK starts on the firstrising edge of CLK after Channel Reset is removed (D0 throughD3 of external address 4). Once active, the SCLK frequency isdetermined by the master CLK frequency and the SCLK divider,according to the equation below. The SCLK divider is a 5-bitunsigned value located in Channel Register 0x0D. The user mustselect the SCLK divider to insure that SCLK is fast enough toaccept full input sample words at the input sample rate. See thedesign example at the end of this section. The maximum SCLKfrequency is 1/2 of the master clock frequency. The minimumSCLK frequency is 1/64 of the master clock frequency.

)1(2 +⋅=

rSCLKdividef

f CLKSCLK

The serial data frame sync output, SDFS, is pulsed high for oneSCLK cycle at the input sample rate. The input sample rate isdetermined by the master clock divided by channel interpolationfactor. If the SCLK rate is not an integer multiple of the inputsample rate, then the SDFS will continually adjust the period byone SCLK cycle in order to keep the average SDFS rate equal tothe input sample rate. When the channel is in sleep mode, SDFSis held low. The first SDFS is delayed by the channel resetlatency after the Channel Reset is removed. The channel resetlatency varies dependent on channel configuration.

The serial data input, SDIN, accepts 32-bit words as channelinput data. The 32-bit word is interpreted as two 16 bit 2’scomplement quadrature words, I followed by Q, MSB first. Thefirst bit is shifted into the serial port starting on the second risingedge of SCLK after SDFS goes high, as shown by the timingdiagram below.

SDI

SDFS

CLK

SCLK

tDSCLK

tDSDFS tDSDFS

tSSI tHSI

CLKn

DATAn

Figure X. Serial Port Switching Characteristics.

As an example of the Serial Port operation, consider a CLKfrequency of 62.208 MSPS and a channel interpolation of 2560.In that case, the input sample rate is 24.3 kSPS (62.208 MSPS /2560), which is also the SDFS rate. Substituting, fSCLK ≥32·fSDFS

into the equation below and solving for SCLKdivider, we find theminimum value for SCLKdivider according to the equation below.

164

−⋅

≤SDFS

clk

ff

rSCLKdivide

Evaluating this equation for our example, SCLKdivider must beless than or equal to 39. Since the SCLKdivider channel register isa 5-bit unsigned number it can only range from 0 to 31. Anyvalue in that range will be valid for this example, but if it isimportant that the SDFS period is constant, then there is anotherrestriction. For regular frames, the ratio fSCLK/fSDFS must be equalto an integer of 32 or larger. For this example, constant SDFSperiods can only be achieved with an SCLK divider of 19.

In conclusion, SDFS rate is determined by the AD6622 masterclock rate and the interpolation rate of the channel. The SDFSrate is equal to the channel input rate. The channel interpolationis equal to RCF interpolation times CIC5 interpolation, timesCIC2 interpolation

( 25 CICCICRCF LLLL ⋅⋅= ).

The SCLK rate is determined by the AD6622 master clock rateand SCLKdivider. The SCLK is a divided version of the AD6622master CLK. The SCLK divide ratio is determined bySCLKdivider as shown in the previous equation. The SCLKmust be fast enough to input 32 bits of data prior to the nextSDFS. Extra SCLKs are ignored by the serial port.



PROGRAMMABLE INTERPOLATING RAMCOEFFICIENT FILTER (RCF)Each channel has a fully independent RAM Coefficient Filter(RCF). The RCF accepts data from the Serial Port, filters it, andpasses the result to the CIC filter. The RCF implements a FIRfilter with optional interpolation. The FIR filter can produceimpulse responses up to 128 output samples long. The FIRresponse may be interpolated up to a factor of 128, although thebest filter performance is usually achieved if the RCFinterpolation factor is confined to 8 or below.

FIR Filter ImplementationThe RCF accepts quadrature samples from the serial port with afixed point resolution of 16 bits each, for I and Q.

DataMEM

CoefficientMEM

16

16

16

RCF CoarseScale

IQ ToCICFilter

SerialPort

SDFSSCLKSDIN

RCF

The AD6622 RCF realizes a sum-of-products filter using a poly-phase implementation. This mode is equivalent to an interpolatorfollowed by a FIR filter running at the interpolated rate. In thefunctional diagram below, the interpolating block increases therate by the RCF interpolation factor (LRCF) by inserting LRCF-1zero valued samples between every input sample. The next blockis a filter with a finite impulse response length (NRCF) and animpulse response of h[n], where n is an integer from 0 to NRCF-1.

↑ LRCF

NRCF TapFIR Filter

h[n]

fIN fIN * LRCF f IN * LRCF

a b c

The difference equation for the diagram above is written below,where h[n] is the RCF impulse response, b[n] is the interpolatedinput sample sequence at point ‘b’ in the diagram above, and c[n]is the output sample sequence at point ‘c’ in the diagram above.

∑−

=

−⋅=1

0

][][][RCFN

k

knbnhnc

This difference equation can be described by the transfer functionfrom point ‘b’ to ‘c’ as shown below.

∑−

=

−⋅=1

0

][)(RCFN

n

nbc znhzH

The actual implementation of this filter uses a poly-phasedecomposition to skip the multiply-accumulates whenb[n-k] is zero. Compared to the diagram above, thisimplementation has the benefits of reducing by a factor of LRCF

both the time needed to calculate an output and the required datamemory (DMEM). The price of these benefits is that the usermust place the coefficients into the coefficient memory (CMEM)indexed by the interpolation phase. The process of selecting thecoefficients and placing them into the CMEM is broken into threesteps shown below.

1. Select the Impulse Response Length (NRCF) and theInterpolation Factor (LRCF). The Impulse Response Length(NRCF) is limited in three ways: by the available calculationtime, by the data memory size (DMEM), and by thecoefficient memory size (CMEM). The equation belowshows that NRCF is limited to the minimum of these threeconditions.

)128,16,2

min( RCFRCF LL

N ⋅≤

TimeRestriction

DMEMRestriction

CMEMRestriction

where 25 CICCICRCF LLLL ⋅⋅=

2. The interpolation rate (LRCF) may be any integer of NRCF

ranging from 1 to 128, while meeting the above equation.Most filter designs can be optimized by choosing thesmallest LRCF that does not compromise the image rejectionof the subsequent CIC filter. The quality of an interpolatingfilter is a strong function of the NRCF/LRCF ratio and a weakerfunction of NRCF. The best filters are usually achieved bymaximizing NRCF/LRCF (no larger than 16) and then increasingboth NRCF and LRCF by the same ratio until the filter becomestime or CMEM limited.

3. Once NRCF and LRCF are selected, Channel Register 0x0A isprogrammed to NRCF – 1, and Channel Register 0x0C isprogrammed to NRCF/LRCF – 1.

4. Determine the Impulse Response. The impulse responserelative to the RCF output rate can be calculated usingordinary FIR design techniques. In most cases, it is desirableto pre-compensate the inband frequency roll-off of the CICfilter that follows. There are no symmetry requirements, sothe RCF can also be used for static phase equalization. Theimpulse response must be quantized to 16-bit 2’scomplement numbers for the CMEM. The channel centergain and worst case peak can be calculated for each of theLRCF phases (p) according to the equations below. A RCFcoarse scale factor (g) that ranges between 0 and 3 is



provided to limit the gain without excessive loss ofresolution in the CMEM. The coarse scale factor is locatedin Channel Register 0x0D.

∑−

=

− +⋅⋅=1

0

][2RCF

RCF

L

N

kRCF

gp pLkhterGainChannelCen

5. The channel center gain is the response to a constant fullscale input at every output phase. The summation is splitinto phases because the interpolation of the data insures thatonly NRCF/LRCF coefficients can be active for any singleoutput. For LRCF=1, there is only one phase and the channelcenter gain is the simple sum of all the coefficients, scaled by2-g. If the channel center gain is not the same for every valueof p, then some or all of the images of the channel center willbe imperfectly rejected by the RCF.

∑−

=

− +⋅⋅=1

0

][2RCF

RCF

L

N

kRCF

gp pLkheakWorstCaseP

6. The worst case peak is calculated similarly to the channelcenter gain, except the input sequence swings from full scalepositive to full scale negative to match the polarity of thecoefficient by which it will be multiplied, so that eachproduct is positive. This results in a maximal, which mustbe less than one to guarantee no possibility of wrapping.Note that when LRCF is greater than one, each phase mayproduce its worst case peak in response to a different inputsequence.

7. Programming DMEM and CMEM. The DMEM must beinitialized to all zeros to avoid any unpredictable startuptransients since a reset does not clear the memory. Theimpulse response h[n] must be reordered by phase for theCMEM as shown in the code below. Several filters withimpulse lengths that total less than 128 can be programmedinto the CMEM simultaneously and selected later using theRCF offset pointer (ORCF) which is set by Channel Register0x0D.

/* Reorder FIR Coefficients for AD6622CMEM */for (p=0; p<L_RCF; p++)for (k=0; k<N_RCF/L_RCF; k++)CMEM[O_RCF + p*N_RCF/L_RCF + k] =C[k*L_RCF +p];/* End of routine */

Applicable RCF Control Registers For FIR ModeChannelAddress

BitWidth DESCRIPTION

0x0A 8 7: Reserved (must be written to 0)6-0: NRCF-1

0x0B 8 7: Reserved (must be written to 0)6-0: ORCF

0x0C 8 7-6: Reserved5-4: Reserved (must be written to 0)3-0: NRCF/LRCF-1

0x0D 8 7-6: RCF Coarse Scale:00=0dB01=-6dB10=-12dB11=-18dB

5: Reserved (must be written to 0)4-0: Serial Clock Divider

0x0E 16 15-0: Reserved0x0F 16 15-0: Reserved0x10 16 15-0: Reserved (must be written 0)0x11 16 15-0: Reserved (must be written 0)0x20-0x3F

16 15-0: Data Memory (DMEM)

0x80-0xFF

16 15-0: Coefficient Memory (CMEM)



CASCASDED INTEGRATOR COMB (CIC)INTERPOLATING FILTERThe I and Q outputs of the RCF stage are interpolated in integerfactors by two cascaded integrator comb (CIC) filters. The CICsection is separated into three discrete blocks: a fifth order filter(CIC5), a second order filter (CIC2), and a scaling block (CICScaling). The CIC5 and CIC2 blocks each exhibit a gain thatincreases with respect to their interpolation factors, LCIC5 andLCIC2. The product of these gains must be compensated for in ashared CIC Scaling block.

CIC_Scale CIC2

LCIC5 LCIC22-CIC_Scale

CIC5

CIC ScalingThe CIC5 and CIC2 stages have a base-band gain of LCIC5

4·LCIC2.The CIC Scaling block is used to avoid numeric overflow in theCIC stages. The CIC Scale block reduces the signal level withouttruncation or loss of resolution. The overall gain of the CICsection is given by the equation below.

ScaleCICCICCIC LLGainCIC _

24

5 2_ −⋅⋅=

The value CIC_Scale may range from 0 to 25, and can beindependently programmed for each channel at Control Register0x06. CIC_Scale may be safely calculated according the equationbelow to insure the net gain through the CIC stages.

( )( )24

52log_ CICCIC LLceilScaleCIC ⋅=

The ‘ceil’ function is the next highest integer. While this normallyconstitutes a small loss, it can be recovered in the RCF scaling.Likewise, if the RCF output level is known to be less than fullscale, the CIC gain can be increased by reducing CIC_Scale.

CIC5The CIC5 is a fifth order interpolating cascaded integrator combwhose impulse response is completely defined by itsinterpolation factor, LCIC5. The value LCIC5-1 can beindependently programmed for each channel at location 0x09.While this control register is 8-bits wide, LCIC5 should be confinedto the range from 1 to 32 to avoid the possibility of internaloverflow for full scale inputs. The transfer function of the CIC5is given by the following equations with respect to the CIC5output sample rate, fsamp5.

5

111

)(55

−

−= −

−

zz

zCICCICL

This polynomial fraction can be completely reduced as followsdemonstrating a finite impulse response with perfect phaselinearity for all values of LCIC5.

∑∑−

=

−−

=

−

−=

=

1

1

52

1

51

0

55

5

)(5CIC

CICCIC L

k

L

kjL

k

k ezzzCICπ

The frequency response of the CIC5 can be expressed as follows.The initial 1/LCIC5 factor normalizes for the increased rate, whichis appropriate when the samples are destined for a DAC with azero order hold output. The maximum gain is (LCIC5)

4 atbaseband, but internal registers peak in response to variousdynamic inputs. As long as LCIC5 is confined to 32 or less, thereis no possibility of overflow at any register.

5

5

5

5

5 sin

sin1

)(5

⋅

=

CIC

CIC

CIC

CIC

ff

ffL

LfCIC

π

π

As an example, we will consider an input from the RCF whosebandwidth is 0.141 of the RCF output rate, centered at baseband.Interpolation by a factor of five reveals five images, as shownbelow.

2 1 0 1 2150

130

110

90

70

50

30

10

10

dB

The CIC5 rejects each of the undesired images while passing theimage at baseband. The images of a pure tone at channel center(DC) are nulled perfectly, but as the bandwidth increases therejection is diminished. The lower band edge of the first imagealways has the least rejection. In this example, the CIC5 isinterpolating by a factor of five and the input signal has abandwidth of 0.141 of the RCF output sample rate. The plotbelow shows –110 dBc rejection of the lower band edge of thefirst image. All other image frequencies have better rejection.



2 1 0 1 2150

130

110

90

70

50

30

10

10

dB

The table below lists maximum bandwidth that will be rejected tovarious levels for CIC5 interpolation factors from 1 to 32. Theexample above corresponds to the listing in the –110dB columnand the LCIC5=5 row. It is worth noting here that the rejection ofthe CIC5 improves as the interpolation factor increases.

-110dB -100dB -90dB -80dB -70dB

1 Full Full Full Full Full2 0.101 0.127 0.160 0.203 0.2563 0.126 0.159 0.198 0.246 0.3074 0.136 0.170 0.211 0.262 0.3255 0.141 0.175 0.217 0.269 0.3336 0.143 0.178 0.220 0.272 0.3377 0.144 0.179 0.222 0.275 0.348 0.145 0.180 0.224 0.276 0.3419 0.146 0.181 0.224 0.277 0.34210 0.146 0.182 0.225 0.278 0.34311 0.147 0.182 0.226 0.278 0.34412 0.147 0.182 0.226 0.279 0.34413 0.147 0.183 0.226 0.279 0.34514 0.147 0.183 0.226 0.279 0.34515 0.148 0.183 0.227 0.280 0.34516 0.148 0.183 0.227 0.280 0.34517 0.148 0.183 0.227 0.280 0.34618 0.148 0.183 0.227 0.280 0.34619 0.148 0.183 0.227 0.280 0.34620 0.148 0.184 0.227 0.280 0.34621 0.148 0.184 0.227 0.280 0.34622 0.148 0.184 0.227 0.280 0.34623 0.148 0.184 0.227 0.280 0.34624 0.148 0.184 0.227 0.280 0.34625 0.148 0.184 0.227 0.281 0.34626 0.148 0.184 0.227 0.281 0.34627 0.148 0.184 0.227 0.281 0.34628 0.148 0.184 0.227 0.281 0.34629 0.148 0.184 0.227 0.281 0.34630 0.148 0.184 0.227 0.281 0.34631 0.148 0.184 0.227 0.281 0.34632 0.148 0.184 0.228 0.281 0.346



CIC2The CIC2 is a second order interpolating cascaded integratorcomb whose impulse response is completely defined by itsinterpolation factor, LCIC2. The value LCIC2-1 can beindependently programmed for each channel at location 0x08.While this control register is 8-bits wide, LCIC2 should be confinedto the ranges shown by the table below according to theinterpolation factor of the CIC5. Exceeding the recommendedguidelines may result in overflow for input sequences at or nearfull scale. While relatively small values of LCIC5 allow for thelarger overall interpolation factors with minimal powerconsumption, LCIC5 should be maximized to achieve the bestoverall image rejection.

LCIC5 Max. LCIC2

1-19 25620 20921 17222 14323 11924 10125 8526 7327 6328 5429 4730 4131 3632 32

The transfer function of the CIC2 is given by the followingequations with respect to the CIC2 output sample rate, fout.

2

111

)(22

−

−= −

−

zz

zCICCICL

This polynomial fraction can be completely reduced as followsdemonstrating a finite impulse response with perfect phaselinearity for all values of LCIC2.

∑∑−

=

−−

=

−

−=

=

1

1

22

1

21

0

22

2

)(2CIC

CICCIC L

k

L

kjL

k

k ezzzCICπ

The frequency response of the CIC2 can be expressed as follows.The maximum gain is LCIC2 at baseband. The initial 1/LCIC2 factornormalizes for the increased rate, which is appropriate when thesamples are destined for a DAC with a zero order hold output.

2

2

2 sin

sin1

)(2

⋅

=

out

out

CIC

CIC

ff

ffL

LfCIC

π

π

As an example, we will consider an input from the CIC5 whosebandwidth is 0.0033 of the CIC5 rate, centered at baseband.Interpolation by a factor of five reveals five images, as shownbelow.

2 1 0 1 2150

130

110

90

70

50

30

10

10

dB

The CIC2 rejects each of the undesired images while passing theimage at baseband. The images of a pure tone at channel center(DC) are nulled perfectly, but as the bandwidth increases therejection is diminished. The lower band edge of the first imagealways has the least rejection. In this example, the CIC2 isinterpolating by a factor of five and the input signal has abandwidth of 0.0033 of the CIC5 output sample rate. The plotbelow shows –110 dBc rejection of the lower band edge of thefirst image. All other image frequencies have better rejection.

2 1 0 1 2150

130

110

90

70

50

30

10

10

dB

The table below lists maximum bandwidth that will be rejected tovarious levels for CIC2 interpolation factors from 1 to 32. Theexample above corresponds to the listing in the –110dB columnand the LCIC2=5 row. It is worth noting here that the rejection ofthe CIC2 improves as the interpolation factor increases.



-110dB -100dB -90dB -80dB -70dB

1 Full Full Full Full Full2 0.0023 0.0040 0.0072 0.0127 0.02263 0.0029 0.0052 0.0093 0.0165 0.02924 0.0032 0.0057 0.0101 0.0179 0.03165 0.0033 0.0059 0.0105 0.0186 0.03286 0.0034 0.0060 0.0107 0.0189 0.03347 0.0034 0.0061 0.0108 0.0192 0.03388 0.0035 0.0062 0.0109 0.0193 0.03419 0.0035 0.0062 0.0110 0.0194 0.034310 0.0035 0.0062 0.0110 0.0195 0.034411 0.0035 0.0062 0.0110 0.0195 0.034512 0.0035 0.0062 0.0111 0.0196 0.034613 0.0035 0.0062 0.0111 0.0196 0.034614 0.0035 0.0063 0.0111 0.0196 0.034715 0.0035 0.0063 0.0111 0.0197 0.034716 0.0035 0.0063 0.0111 0.0197 0.034717 0.0035 0.0063 0.0111 0.0197 0.034818 0.0035 0.0063 0.0111 0.0197 0.034819 0.0035 0.0063 0.0111 0.0197 0.034820 0.0035 0.0063 0.0111 0.0197 0.034821 0.0035 0.0063 0.0111 0.0197 0.034822 0.0035 0.0063 0.0111 0.0197 0.034823 0.0035 0.0063 0.0111 0.0197 0.034824 0.0035 0.0063 0.0112 0.0197 0.034825 0.0035 0.0063 0.0112 0.0198 0.034926 0.0035 0.0063 0.0112 0.0198 0.034927 0.0035 0.0063 0.0112 0.0198 0.034928 0.0035 0.0063 0.0112 0.0198 0.034929 0.0035 0.0063 0.0112 0.0198 0.034930 0.0035 0.0063 0.0112 0.0198 0.034931 0.0035 0.0063 0.0112 0.0198 0.034932 0.0035 0.0063 0.0112 0.0198 0.0349



NUMERICALLY CONTROLLED OSCILLATOR (NCO)TUNEREach channel has a fully independent tuner. The tuner acceptsdata from the CIC filter, tunes it to a digital IntermediateFrequency (IF), and passes the result to a shared Summationblock. The tuner consists of a 32-bit quadrature NCO and aQuadrature Amplitude Mixer (QAM). The NCO serves as alocal oscillator and the QAM translates the interpolated channeldata from baseband to the NCO frequency. The worst casespurious signal from the NCO is better than -100dBc for alloutput frequencies. The Tuner can produce real or complexoutputs as requested by the shared Summation block.

In the complex mode, the NCO serves as a quadrature localoscillator running at fCLK/2 capable of producing any frequencybetween –fCLK/4 and +fCLK/4 with a resolution of fCLK/233 (0.0076Hz for fCLK=65 MHz).

In the real mode, the NCO serves as a quadrature local oscillatorrunning at fCLK capable of producing any frequency between –fCLK/2 and +fCLK/2 with a resolution of fCLK/232 (0.015 Hz forfCLK=65 MHz). The quadrature portion of the output isdiscarded. Negative frequencies are distinguished from positivefrequencies solely by spectral inversion.

The digital IF is calculated using the equation below.

322_ frequencyNCO

ff NCOIF ⋅=

where:NCO_frequency is the value written to 0x02,fIF is the desired intermediate frequency, andfNCO is fCLK/2 for complex outputs and fCLK for real outputs.

16 16

PhaseOfffset

D Q

NCOFrequency

Word

32 32 32 32 32 32

CLK

Mic

ropr

oces

sor

Inte

rface

+ D Q +Angle to

CartesianConversion +

PNGen.

+PN

Gen.OnOff

OnOff

X

XI

Q

I, Q

I data fromCIC5

Q data fromCIC5

Phase DitherThe AD6622 provides a phase dither option for improving thespurious performance of the NCO. Phase dither is enabled bywriting a one to Bit 3 of Channel Register 0x01. When phasedither is enabled, spurs due to phase truncation in the NCO arerandomized. The choice of whether Phase Dither is used in asystem will ultimately be decided by the system goals and thechoice of IF frequency. The 18 most significant bits of the phaseaccumulator are used by the angle to Cartesian conversion. If theNCO frequency has all zeroes below the 18th bit, then phasedither has no effect. If the fraction below the 18th bit is near a 1/2or 1/3, etc. of the 18th bit, then spurs will accumulate separatedfrom the IF by 1/2 or 1/3, etc. of the CLK frequency. The smallerthe denominator of this residual fraction, the larger the spurs dueto phase truncation will be. If the phase truncation spurs areunacceptably high for a given frequency, then the phase dither canreduce these at the penalty of a slight elevation in total errorenergy. If the phase truncation spurs are small, then phase dither

will not be effective in reducing them further, but a slightelevation in total error energy will occur.

Amplitude DitherAmplitude dither can also be used to improve spuriousperformance of the NCO. Amplitude dither is enabled by writinga 1 to Bit 4 of Channel Register at 0x01. When enabled,amplitude dither can reduce spurs due to truncation at the inputto the QAM. If the entire frequency word is close to a fractionthat has a small denominator, the spurs due to amplitudetruncation will be large and amplitude dither will spread thesespurs effectively. Amplitude dither also will increase the totalerror energy by approximately 3 dB. For this reason amplitudedither should be used judiciously.

Phase OffsetThe phase offset (Channel Register 0x04) adds an offset to thephase accumulator of the NCO. This is a 16-bit register that isinterpreted as a 16-bit unsigned integer. Phase offset ranges from



0 to nearly 2π radians with a resolution of π/32768 radians. Thisregister allows multiple NCOs to be synchronized to producesine waves with a known phase relationship.

NCO Frequency Update and Phase Offset Update Hold OffCountersThe update of both the NCO Frequency and Phase Offset can besynchronized with internal hold off counters. Both of thesecounters are 16-bit unsigned integers and are clocked at the masterCLK rate. These hold off counters used in conjunction with thefrequency or phase offset registers, allow Beam Forming andFrequency Hopping. See the Synchronization section of the datasheet for additional details. The NCO phase can also be clearedon Sync (set to 0x0000) by setting Bit 2 of Channel Register 0x01high.

NCO Output ScaleThe output of the NCO can be scaled in four steps of 6dB eachvia Channel Register 0x01, Bits 1-0. Below is a table of thecontrol scale. The NCO always has loss to accommodate thepossibility that both the I and Q inputs may reach full-scalesimultaneously, resulting in a +3dB input magnitude.

0x01 Bit 1 0x01 Bit 0 NCO Output Level0 0 -6dB (no attenuation)0 1 -12dB attenuation1 0 -18dB attenuation1 1 -24dB attenuation



SUMMATION BLOCKThe Summation Block of the AD6622 serves to combine theoutputs of each channel to create a composite multi-carrier signal.The four channels are summed together and the result is thenadded with the 18-bit Wideband Input Bus (IN[17:0]). The finalsummation is then driven on the 18-bit Wideband Output Bus(OUT[17:0]) bus on the rising edge of the high speed clock. If theOEN input is high then this output bus is tri-stated. If the OENinput is low then this bus will be driven by the summed data.The OEN is active high to allow the Wideband Output Bus to beconnected to other busses without using extra logic. Most otherbusses (like 374 type registers) require a low output enable,which is opposite of the AD6622 OEN, thus eliminating extracircuitry.

The Wideband Output Bus may be interpreted as a 2’scomplement number or as an offset binary number as defined bybit 1 of the Summation Mode Control Register at address 0x000.When this bit is high then the Wideband Output is in 2’scomplement mode and when it is low it is configured for offsetbinary output data.

The MSB (bit 17) of the Wideband Output Bus is typically usedas a guard bit for the purpose of clipping the wideband outputbus when bit 0 of the Summation Mode Control Register ataddress 0x000 is high. If clip detection is enabled then bit 17 ofthe output bus is not used as a data bit. Instead, bit 16 willbecome the MSB and is connected to the MSB of the DAC.Configuring the DAC in this manner gives the summation block again of 0dB. When clip detection is not enabled and bit 17 is usedas a data bit then the Summation Block will have a gain of –6.02dB.

There are two data output modes. The first is offset binary.This mode is used only when driving offset binary DACs. 2’scomplement mode may be used in one of two circumstances. Thefirst is when driving a DAC that accepts 2’s complement data.The second is when driving another AD6622 in cascade mode.

When clipping is enabled, the 2’s complement mode output buswill clip to 0x2FFFF for output signals more positive than theoutput can express and it will clip to 0x3000 for signals morenegative than the output can express. In offset binary mode theoutput bus will clip to 0x3FFFF for output signals more positivethan the output can express and it will clip to 0x2000 for signalsmore negative than the output can express.

The Wideband Input is always interpreted as an 18-bit 2’scomplement number and is typically connected to the WidebandOutput Bus of another AD6622 in order to send more than 4carriers to a single DAC. The Output Bus of the proceedingAD6622 should be configured in 2’s complement mode and clipdetection disabled. The 18-bit resolution insures that the noiseand spur performance of the wideband data stream does notbecome the limiting factor as large numbers of carriers aresummed.

There is a two clock cycle latency from the Wideband Input Busto the Wideband Output Bus. This latency may be calibrated outof the system by use of the Start Hold-Off counter. Thepreceding AD6622 in a cascaded chain can be started two highspeed clock cycles before the following AD6622 is started andthe data from each AD6622 will arrive at the DAC on the sameclock cycle. In systems where the individual signals are notcorrelated, this is usually not necessary.

The AD6622 is capable of outputting both Real and ComplexData. When in Real mode the QIN input is tied low signaling thatall inputs on the Wideband Input Bus are real and that all outputson the Wideband Output Bus are real. The Wideband Input Buswill be pulled low and no data will be added to the compositesignal if this port is unused (not connected).

If Complex data is desired then there are two ways this can beobtained. The first method is to simply set the QIN input of theAD6622 high and to set the Wideband Input Bus low. Thisallows the AD6622 to output Complex Data on the WidebandOutput Bus. The I data samples would be identified whenQOUT is low and the Q data samples would be identified whenQOUT is high. The second method of obtaining complex data isto provide a QIN signal that toggles on every rising edge of thehigh speed clock. This could be obtained by connecting theQOUT of another AD6622 to QIN. In a cascaded system theQIN of the first AD6622 in the chain would typically be tied highand the QOUT of the first AD6622 would be connected to theQIN of the following part. All AD6622s will synchronizethemselves to the QIN input so that the proper samples arealways paired and the Wideband Output bus represents validComplex Data samples.

QINWideband InputIN[17:0]

Output Data TypeOUT[17:0], QOUT

Low Real RealHigh Zero ComplexPulsed Complex Complex

14-BitDAC

AD6622 AD6622

2’s Comp,Clipping Disabled

Offset Bin,Clipping Enabled

QINLogic1 QIN

IN[17:0]

OUT[16:3]

QOUT

OUT[17:0]

IN[17:0]Logic0

Figure XX. Cascade Operation of two AD6622s.



SYNCHRONIZATIONThree types of synchronization can be achieved with theAD6622. These are Start, Hop, and Beam. Each is described indetail below. The synchronization is accomplished with the useof a shadow register and a hold off counter. See Figure XX belowfor a simplistic schematic of the NCO shadow register and NCOFreq Hold Off counter to understand basic operation. Enablingthe clock (AD6622 CLK) for the hold off counter can occur witheither a Soft_Sync (via the micro port), or a Pin Sync (via theAD6622 Sync pin, pin 62). The functions that include shadowregisters to allow synchronization include:

1. Start2. Hop (NCO Frequency)3. Beam (NCO Phase Offset)

NCO ShadowRegister

NCO Register NCO PhaseAccumulator

32 32 32

16 16

HOPHoldoff

C=1

C=0

ENA

HoldoffCounter

ENA

PL

D Q D Q

D Q D

D Q

HOP Sync

C=1

C=0

ENA

PLD

Start Sync

StartHoldoff

StartCounter

CLR

SET

Q

ResetPin

SLEEP16 16

CLK

Mic

ropr

oces

sor I

nter

face

Figure XX. NCO Shadow Register and Hold Off Counter

Start refers to the start-up of an individual channel, chip, ormultiple chips. If a channel is not used, it should be put in theSleep Mode to reduce power dissipation. Following a hard reset(low pulse on the AD6622 /Reset pin), all channels are placed inthe Sleep Mode.

Start With No Sync

If no synchronization is needed to start multiple channels ormultiple AD6622s, the following method should be used toinitialize the device.

1. To program a channel, it must first be set to the ProgramMode (bit high) and Sleep Mode (bit high) (Ext Address 4).The Program Mode allows programming of data memory andcoefficient memory (all other registers are programmablewhether in Program Mode or not). Since no synchronizationis used all Sync bits are set low (External Address 5). Allappropriate control and memory registers (filter) are thenloaded. The Start Update Hold Off Counter (0x00) shouldbe set to 0.

2. Set the appropriate Program and Sleep bits low (Ext Address4). This enables the channel. The channel must haveProgram and Sleep Mode low to activate a channel.

Start With Soft SyncThe AD6622 includes the ability to synchronize channels orchips under microprocessor control. One action to synchronize isthe start of channels or chips. The Start Update Hold OffCounter (0x00) in conjunction with the Start bit and Sync bit (ExtAddress 5) allow this synchronization. Basically the StartUpdate Hold Off Counter delays the Start of a channel(s) by itsvalue (number of AD6622 CLKs). The following method is usedto synchronize the start of multiple channels via microprocessorcontrol.

1. Set the appropriate channels to sleep mode (a hard reset tothe AD6622 Reset pin brings all 4 channels up in sleepmode).

2. Write the Start Update Hold Off Counter(s) (0x00) to theappropriate value (greater than 1 and less than 2^16-1). Ifthe chip(s) is not initialized, all other registers should beloaded at this step.

3. Write the Start bit and the SyncX(s) bit high (Ext Address5).

4. This starts the Start Update Hold Off Counter countingdown. The counter is clocked with the AD6622 CLK signal.When it reaches a count of one the Sleep bit of theappropriate channel(s) is set low to activate the channel(s).

Start With Pin SyncA Sync pin is provided on the AD6622 to provide the mostaccurate synchronization, especially between multiple AD6622s.Synchronization of Start with an external signal is accomplishedwith the following method.

1. Set the appropriate channels to sleep mode (a hard reset tothe AD6622 Reset pin brings all 4 channels up in sleepmode).

2. Write the Start Update Hold Off Counter(s) (0x00) to theappropriate value (greater than 1 and less than 2^16-1). Ifthe chip(s) is not initialized, all other registers should beloaded at this step.

3. Set the Start on Pin Sync bit and the appropriate Sync PinEnable high (0x01).



4. When the Sync pin is sampled high by the AD6622 CLKthis enables the count down of the Start Update Hold OffCounter. The counter is clocked with the AD6622 CLKsignal. When it reaches a count of one the Sleep bit of theappropriate channel(s) is set low to activate the channel(s).

Hop is a jump from one NCO frequency to a new NCOfrequency. This change in frequency can be synchronized viamicroprocessor control or an external Sync signal as describedbelow.

To set the NCO frequency without synchronization the followingmethod should be used.

Set Freq No Hop1. Set the NCO Freq Hold Off counter to 0.2. Load the appropriate NCO frequency. The new frequency

will be immediately loaded to the NCO.

Hop With Soft SyncThe AD6622 includes the ability to synchronize a change in NCOfrequency of multiple channels or chips under microprocessorcontrol. The NCO Freq Hold Off counter (0x03) in conjunctionwith the Hop bit and the Sync bit (Ext Address 5) allow thissynchronization. Basically the NCO Freq Hold Off counterdelays the new frequency from being loaded into the NCO by itsvalue (number of AD6622 CLKs). The following method is usedto synchronize a hop in frequency of multiple channels viamicroprocessor control.

1. Write the NCO Freq Hold Off (0x03) counter to theappropriate value (greater than 1 and less then 2^16-1).

2. Write the NCO Frequency register(s) to the new desiredfrequency.

3. Write the Hop bit and the Sync(s) bit high (Ext Address 5).4. This starts the NCO Freq Hold Off counter counting down.

The counter is clocked with the AD6622 CLK signal. Whenit reaches a count of one the new frequency is loaded into theNCO.

Hop With Pin SyncA Sync pin is provided on the AD6622 to provide the mostaccurate synchronization, especially between multiple AD6622s.Synchronization of Hopping to a new NCO frequency with anexternal signal is accomplished with the following method.

1. Write the NCO Freq Hold Off counter(s) (0xX03) to theappropriate value (greater than 1 and less than 2^16-1).

2. Write the NCO Frequency register(s) to the new desiredfrequency.

3. Set the Hop on Pin Sync bit and the appropriate Sync PinEnable high (0x01).

4. When the Sync pin is sampled high by the AD6622 CLKthis enables the count down of the NCO Freq Hold Offcounter. The counter is clocked with the AD6622 CLKsignal. When it reaches a count of one the new frequency isloaded into the NCO.

Beam is a change in phase for a particular channel and can besynchronized with respect to other channels or AD6622s. Thischange in phase can be synchronized via microprocessor controlor an external Sync signal as described below.

To set the amplitude without synchronization the followingmethod should be used.

Set Phase No Beam1. Set the NCO Phase Offset Update Hold Off Counter (0x05)

to 0.2. Load the appropriate NCO Phase Offset (0x04). The NCO

Phase Offset will be immediately loaded.

Beam With Soft SyncThe AD6622 includes the ability to synchronize a change in NCOphase of multiple channels or chips under microprocessor control.The NCO Phase Offset Update Hold Off Counter in conjunctionwith the Beam bit and the Sync bit (Ext Address 5) allow thissynchronization. Basically the NCO Phase Offset Update HoldOff Counter delays the new phase from being loaded into theNCO/RCF by its value (number of AD6622 CLKs). Thefollowing method is used to synchronize a beam in phase ofmultiple channels via microprocessor control.

1. Write the NCO Phase offset Update Hold Off Counter(0x05) to the appropriate value (greater than 1 and less then2^16-1).

2. Write the NCO Phase Offset register(s) to the new desiredphase and amplitude.

3. Write the Beam bit and the Sync(s) bit high (Ext Address 5).4. This starts the NCO Phase Offset Update Hold Off counter

counting down. The counter is clocked with the AD6622CLK signal. When it reaches a count of one the new phase isloaded into the NCO.

Beam With Pin SyncA Sync pin is provided on the AD6622 to provide the mostaccurate synchronization, especially between multiple AD6622s.Synchronization of Beaming to a new NCO Phase Offset with anexternal signal is accomplished with the following method.

1. Write the NCO Phase Offset Hold Off (0x05) counter(s) tothe appropriate value (greater than 1 and less than 2^16-1).

2. Write the NCO Phase Offset register(s) to the new desiredphase and amplitude.

3. Set the Beam on Pin Sync bit and the appropriate Sync PinEnable high (0x01).

4. When the Sync pin is sampled high by the AD6622 CLKthis enables the count down of the NCO Phase Offset HoldOff counter. The counter is clocked with the AD6622 CLKsignal. When it reaches a count of one the new phase isloaded into the NCO registers.



JTAG INTERFACEThe AD6622 supports a subset of IEEE Standard 1149.1specification. For additional details of the standard, please see“IEEE Standard Test Access Port and Boundary-ScanArchitecture,” IEEE-1149 publication from IEEE.

The AD6622 has five pins associated with the JTAG interface.These pins are used to access the on-chip Test Access Port andare listed in the table below. Name Pin Number Description/TRST 100 Test Access Port ResetTCK 101 Test ClockTMS 106 Test Access Port Mode SelectTDI 108 Test Data InputTDO 107 Test Data Output

The AD6622 supports four op codes as shown below. Theseinstructions set the mode of the JTAG interface.Instruction Op CodeIDCODE 10BYPASS 11SAMPLE/PRELOAD 01EXTEST 00

The Vendor Identification Code can be accessed through theIDCODE instruction and has the following format.

MSBVersion

PartNumber

ManufacturingID #

LSBMandatory

000 0010011110000000

000 1110 0101 1

A BSDL file for this device will be available from Analog Devices,Inc. Contact Analog Devices Inc. for more information.



SCALINGProper scaling of the wideband output is critical to maximize thespurious and noise performance of the AD6622. A relativelysmall overflow anywhere in the data path can cause the spuriousfree dynamic range to drop precipitously. Scaling down theoutput levels also reduces dynamic range relative to anapproximately constant noise floor. A well-balanced scaling planat each point in the signal path will be rewarded with optimumperformance. The scaling plan can be separated into two parts:multi-carrier scaling and single-carrier scaling.

Multi-Carrier ScalingAn arbitrary number of AD6622s can be cascaded to create acomposite digital IF with many carriers. As the number ofcarriers increases, the peak to RMS ratio of the composite digitalIF will increase as well. It is possible and beneficial to limit thepeak to RMS ratio through careful frequency planning andcontrolled phase offsets. Nevertheless, in most cases with a largenumber of carriers, the worst case peak is an unlikely event.

The AD6622 immediately preceding the DAC can beprogrammed to clip rather than wrap around (see the SummationBlock description). For a large number of carriers, a rare but finitechance of clipping at the Ad6622 wideband output will result insuperior dynamic range compared to lowering each carrier leveluntil clipping is impossible. This will also be the case for mostDACs. Through analysis or experimentation, an optimal outputlevel of individual carriers can be determined for any particularDAC.

Single Carrier ScalingOnce the optimal power level is determined for each carrier, onemust determine the best way to achieve that level. The maximumSNR can be achieved by maximizing the intermediate power levelat each processing stage. This can be done by assuming theproper level at the output and working backwards along the signalpath: Summation, NCO, CIC, and finally, RCF.

The Summation Block is intended to combine multiple carriers,with each carrier at least 6 dB below full scale. For thisconfiguration, the AD6622 driving the DAC should have clipdetection enable. OUT17 becomes a clip indicator that reportsclipping in both polarities. If the DAC requires offset binaryoutputs, then the internal offset binary conversion should beenabled as well. Any preceding cascaded AD6622s shoulddisable clip detection and offset binary conversion. The IN17-IN0 of the first AD6622 in the cascade should be grounded. Seethe Summation Block section for details. In this configuration,intermediate OUT17s will serve as guard bits that allowintermediate sums to exceed full scale. As long as the final outputdoes not exceed 6 dB over full scale, the clip detector will performcorrectly.

If a single carrier needs to exceed –6 dB full scale, hardwiredscaling can be accomplished according to the table below. This is

most useful when the AD6622 is processing a Single WidebandCarrier such as UMTS or CDMA 2000.

Max. SingleCarrier Level

Connect toDAC MSB

ClipDetect

Offset BinaryCompensation

-12.04 dB OUT17 N/A Internal-6.02 dB OUT16 +/- Internal

0 dB OUT 15 +only 0x18000+6.02 dB OUT 14 +only 0x1C000+12.04 dB OUT 13 +only 0x1E000+18.06 dB OUT 12 +only 0x1F000+24.08 dB OUT 11 +only 0x1F800

The NCO/Tuner is equipped with an output scalar that rangesfrom –6.02 to –24.08 dB below full scale, in 6.02 dB steps. Seethe NCO/Tuner section for details. The best SNR will beachieved by maximizing the input level to the NCO and using thelargest possible NCO attenuation. For example, to achieve anoutput level –20 dB below full scale, one should set the CICoutput level to –1.94 dB below full scale and attenuate by –18.06dB in the NCO.

The CIC is equipped with an output scalar that ranges from 0 to–150.51 dB below full scale in 6.02 dB steps. This largeattenuation is necessary to compensate for the potentially largegains associated with CIC interpolation. See the CIC section fordetails. For example to achieve an output level of –1.94 dBbelow full scale, with a CIC5 interpolation of 27 (114.51 dB gain)and a CIC2 interpolation of 3 (9.54 dB gain), one should set theCIC_Scale to 20 and the RCF output level to –5.59 dB below fullscale.

59.502.62051.11454.994.1 −=⋅+−−−

The RCF is equipped with an output scalar that ranges from 0 to–18.06 dB below full scale in 6.02 dB steps. This attenuation canbe used to compensate for filter gain in the RCF. For example, ifthe desired RCF output is –5.59 dB and the maxim gain of theRCF coefficients is 11.04dB, then the RCF_Coarse_Scale shouldbe set to 2 and the coefficients should be scaled so that the largestcoefficient is –4.59 dB below full scale. The largest possible gainof the RCF coefficients is when the largest coefficient of theimpulse response is normalized to one. This means that all of thecoefficients are as large as possible so the sum of the coefficientsare as large as possible. This maximum gain will determine theRCF_Coarse_Scale, which should be used to make the total RCFgain between 0 and –6.02dB. After the RCF_Coarse_Scale ischosen then the Coefficients can be re-scaled, as in the example,to set the total RCF gain to a desired level. See the RCF sectionfor additional information.

59.402.6204.1159.5 −=⋅+−−

Finally, as described in the RCF section, there may be a worstcase peak of a phase that is larger than the channel center gain. Inthe preceding example, if the worst case to channel center ratio is



larger than 4.59 dB (potentially overflowing the RCF), then theRCF_Coarse_Scale should be reduced by one and the CIC_Scaleshould be increased by one. In the preceding example, if the worstcase to channel center ratio is larger than 5.59 dB (potentiallyoverflowing the RCF and CIC), then the RCF_Coarse_Scaleshould be reduced by one and the NCO_Output_Scale should beincreased by one.



MICROPORT INTERFACEThe MicroPort interface is the communications port between theAD6622 and the host controller. There are two modes of busoperation: Intel non-multiplexed mode (INM), and Motorola non-multiplexed mode (MNM) which is set by hard wiring the ALEpin to either ground or supply. The mode is selected based onthe use of the MicroPort control lines (/DS or /RD, DTACK orRDY, R/W or /WR) and the capabilities of the host processor.See the timing diagrams for details on the operation of bothmodes.

The External Memory Map provides data and address registers toread and write the extensive control registers in the InternalMemory Map. The control registers access global chip functionsand multiple control functions for each independent channel.

MicroPort ControlAll accesses to the internal registers and memory of the AD6622are accomplished indirectly through the use of the microprocessorport external registers shown in Table x below. Accesses to theExternal Registers are accomplished through the 3 bit address bus(A[2:0]) and the 8 bit data bus (D[7:0]) of the AD6622(MicroPort). External Address [3:0] provides access to data readfrom or written to the internal memory (up to 32 bits). ExternalAddress [0] is the least significant byte and External Address [3]is the most significant byte. External Address [4] controls theresets of each channel. External Address [5] controls the syncstatus of each channel. External Address [7:6] determines theInternal Address selected and whether this address is incrementedafter subsequent reads and/or writes to the internal registers.

EXTERNAL MEMORY MAPThe External Memory Map is used to gain access to the InternalMemory Map described below. External Address [7:6] sets theInternal Address to which subsequent reads or writes will beperformed. The top two bits of External Address [7] allow theuser to set the address to auto increment after reads, writes, orboth. All internal data words have widths that are less than orequal to 32 bits. Accesses to External Address [0] triggeraccesses to the AD6622’s internal memory map. Thus duringwrites to the internal registers, External Address [0] must bewritten last to insure all data is transferred. Reads are theopposite in that External Address [0] must be the first dataregister read (after setting the appropriate internal address) toinitiate an internal access.

External Address [5:4] reads and writes are transferredimmediately to internal control registers. External Address [4] isthe reset register. The reset bits can be set collectively by theaddress. The reset bits can be cleared by operation of start syncs(described below).

External Address [5] is the sync register. These bits are writeonly. There are three types of syncs: start, hop, and beam. Eachof these can be sent to any or all of the four channels. Forexample, a write of X0010100 would issue a start sync to

channel C only. A write of X1101111 would issue a beamsync and a hop sync to all channels.

The internal address bus is 11 bits wide and the internal data busis 32 bits wide. External address 7 is the Chan (Channel ) andstores the upper three bits of the address space in Chan[2:0].Chan[7:6] define the auto-increment feature. If bit 6 is high, theinternal address in incremented after an internal read. If bit 7 ishigh, the internal address is incremented after an internal write. Ifboth bits are high, the internal address in incremented after eithera write or a read. This feature is designed for sequential access tointernal locations. External address 6 is the Addr (Address) andstores the lower 8 bits of the internal address. External addresses3 through 0 store the 32 bits of the internal data. All internalaccesses are 2 clock cycles long.

Writing to an internal location with a data width of 16 bits isachieved by first writing the upper three bits of the address tobits 2 through 0 of the Chan (bits 7 and 6 of the Chan arewritten to determine whether or not the auto increment feature isenabled). The Addr is then written with the lower eight bits ofthe internal address (it doesn’t matter if the Addr is writtenbefore the Chan as long as both are written before the internalaccess). Since the data width of the internal address is 16 bits,only data register 1 and data register 0 are needed. Data register 1must be written first because the write to data register 0 triggersthe internal access. Data register 0 must always be the lastregister written to initiate the internal write.

Reading from the MicroPort is accomplished in a similar manner.The internal address is first written. A read from data register 0activates the internal read, thus register 0 must always be readfirst to initiate an internal read. This provides the 8 LSBs of theinternal read through the MicroPort (D[7:0]). Additional bytesare then read by changing the external address (A[2:0]) andperforming additional reads. If data register 3 (or any other) isread before data register 0, incorrect data will be read. Dataregister 0 must be read first in order to transfer data from the corememory to the external memory locations. Once data register isread, the remaining locations may be examined in any order.

The MicroPort of the AD6622 allows for multiple accesses while/CS is held low (/CS can be tied permanently low if the MicroPortis not shared with additional devices). The user can accessmultiple locations by pulsing the /WR or /RD line and changingthe contents of the external three bit address bus. Access to theexternal registers of Table 2 is accomplished in one of two modesusing the /CS, /RD, /WR, and ALE inputs. The access modes areIntel Non-Multiplexed mode and Motorola Non-Multiplexedmode. These modes are controlled by the ALE input (ALE=0 forINM, ALE=1 for MNM). /CS, /RD, and /WR control the accesstype for each mode.



Intel Non-Multiplexed Mode (INM)ALE must be tied low to operate the AD6622 MicroPort in INMmode. The access type is controlled by the user with the /CS,/RD (/DS), and /WR (R/W) inputs. The RDY (/DTACK) signalis produced by the MicroPort to communicate to the user theMicroPort is ready for an access. RDY (/DTACK) goes low atthe start of the access and is released when the internal cycle iscomplete. See the timing diagrams for both the read and writemodes in the Specifications.

Motorola Non-Multiplexed Mode (MNM)ALE must be tied high to operate the AD6622 microprocessor inMNM mode. The access type is controlled by the user with the/CS, /DS (/RD), and R/W (/WR) inputs. The /DTACK (RDY)signal is produced by the MicroPort to acknowledge thecompletion of an access to the user. /DTACK (RDY) goes lowwhen an internal access is complete and then will return high after/DS (/RD) is de-asserted. See the timing diagrams for both theread and write modes in the Specifications.

The /DTACK pin is configured as an open drain so that multipledevices may be tied together at themicroprocessor/microcontroller without contention.

External External DataAddress D7 D6 D5 D4 D3 D2 D1 D0

7: Chan Wrinc Rdinc - - - IA10 IA9 IA86: Addr IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA05: Sync - beam hop start SyncD SyncC SyncB SyncA4: Reset Prog D Prog C Prog B Prog A SleepD SleepC SleepB SleepA3: Byte3 ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID242: Byte2 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID161: Byte1 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID80: Byte0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

External Address 7 Upper Address Register (Chan)Sets the 3 most significant bits of the internal address, effectivelyselecting channels 1, 2, 3 or 4 (D2:D0). The auto-increment ofread and write are also set (D7:D6).

External Address 6 Lower Address Register (Addr)Sets the internal address 8-LSBs (D7:D0).

External Address 5 Sync This register is Read only. Bits in this address control thesynchronization of the AD6622 channels. If the user intends tobring up channels with no synchronization requirements then allbits of this register should be written low. Two types of syncsignals are available with the AD6622. The first is Soft Sync.Soft Sync is software synchronization enabled through themiroport. The second synchronization method is Pin Sync. PinSync is enabled by a signal applied to the Sync pin (pin 62). Seethe Synchronization section of the data sheet for detailedexplanations of the different modes.

External Address 4 ResetBits in this register determine how the chip is programmed andenables the channels. The program bits (D7:D4) must be set highto allow programming of CMEM and DMEM for each channel.Sleep bits (D3:D0) are used to activate or sleep channels. Thesecan be used manually by the user to bring up a channel by simplywriting the required channel high. These bits can also be used inconjunction with the Start and Sync signals available in ExternalAddress 5 to synchronize the channels. See the Synchronizationsection of the data sheet for detailed explanation of differentmodes.

External Address 3:0 (Address Bytes)These bits set the internal address to be accessed for a read orwrite.



INTERNAL CONTROL REGISTERS AND ON-CHIP RAMListed below is the mapping of internal AD6622 registers.

Address Bit Width Name Notation Description Common Function Registers (not associated with a particular channel)0x000 8 Summation MODE Control 0: Clip Wideband Output

1: Offset Binary Wideband Output2: Reserved, must be set high3-7: Reserved, should be set low

0x001 8 Sync MODE Control 0: Ch.A Sync Pin Enable1: Ch.B Sync Pin Enable2: Ch.C Sync Pin Enable3: Ch.D Sync Pin Enable4: Start on Pin Sync5: Hop on Pin Sync6: Beam Steer on Pin Sync7: First Sync Only

Channel Function Registers (0x1XX=Ch.A, 0x2XX=Ch.B, 0x3XX=Ch.C, 0x4XX=Ch.D)0x100 16 Start Update Hold Off Counter Start Update Hold Off Counter0x101 8 NCO Control 1-0: Ch.A NCO Output Scale

2: Ch.A NCO Clear Phase Accum on Sync3: Ch.A NCO Phase Dither Enable4: Ch.A NCO Amp Dither Enable7-5: Reserved

0x102 32 NCO Frequency Ch.A NCO Frequency Value0x103 16 NCO Freq Hold Off Ch.A NCO Frequency Update Hold Off Ctr0x104 16 NCO Phase Offset Ch.A NCO Phase Offset0x105 16 NCO Phase Hold Off Ch.A NCO Phase Offset Update Hold Off Ctr0x106 8 CIC Scale 5-0: Ch.A CIC Scale

7-6: Reserved0x107 8 Reserved 7-0: Reserved0x108 8 CIC2 Interpolation-1 Ch.A CIC2 Interpolation Factor-10x109 8 CIC5 Interpolation-1 Ch.A CIC5 Interpolation Factor-10x10A 8 RCF Coefficient Count NRCF-1 6-0: Ch.A RCF Coefficient Count, NRCF-1

7: Reserved0x10B 8 RCF Coefficient Offset ORCF 6-0: Ch.A RCF Coefficient Offset

7: Reserved0x10C 8 Channel MODE Control 1 NRCF/LRCF-1 3-0: Ch.A NRCF/LRCF-1

5-4: Ch.A Input Format: 00=FIR6: Reserved7: Reserved

0x10D 8 Channel MODE Control 2 4-0: Ch.A Serial Clock Divider5: Ch.A Phase EQ Enable7-6: Ch.A RCF Coarse Scale: 00=0dB 01=-6dB 10=-12dB 11=-18dB

0x10E 16 16-0: Reserved0x10F 16 16-0: Reserved0x110 16 Phase EQ Coef1 Ch.A Phase EQ Coefficient 10x111 16 Phase EQ Coef2 Ch.A Phase EQ Coefficient 20x112-0x11F

Reserved Reserved



0x120-0x13F

16 Data Mem Ch.A Data Memory

0x140-0x17F

16 Reserved Reserved

0x180-0x1FF

16 Coef. Mem Ch.A Coefficient Memory

Additional Channels0x200-0x2FF

Various Channel B Ch.B Registers (organized as Ch.A above)

0x300-0x3FF

Various Channel C Ch.C Registers (organized as Ch.A above)

0x400-0x4FF

Various Channel D Ch.D Registers (organized as Ch.A above)

(0x000) Summation Mode ControlControls functions in the summation block of the AD6622.When set high, Bit 0 causes the output data to be clipped (nowrap-around) when over-range of the output occurs. When Bit 0is low, over-range will result in wrap-around. When set low, Bit1 formats the output data as 2s complement. Bit 1 set high willformat output data as offset binary.

(0x001) Sync Mode ControlBits 4-0 when high enable synchronization of these channels. Seethe Synchronization section of the data sheet for detailedexplanation.

Channel Function RegistersThe following registers are channel specific. ‘0x’ denotes thatthese values are represented as hexadecimal numbers. ‘represents the specified channel. Valid channels are n=1, 2, 3 and4.

(0xn00) Start Update Hold Off CounterThe Start Update Hold Off Counter is used to synchronize startup of AD6622 channels and can be used to synchronize multiplechips. The Start Update Hold Off Counter is clocked by theAD6622 CLK (master clock). See the Synchronization section ofthe data sheet for detailed explanation. If no synchronization isrequired, this register should be set to 0.

(0xn01) NCO ControlBit 1:0 set the NCO scaling per the table below.Bit 1 Bit0 NCO Output Level0 0 -6dB (no attenuation)0 1 -12dB attenuation1 0 -18dB attenuation1 1 -24dB attenuationBit 2 when high clears the NCO phase accumulator to 0 on eithera Soft Sync or Pin Sync (see Synchronization for details).Bit 3 when high enables NCO phase dither.Bit 4 when high enables NCO amplitude dither.Bit 7:5 are reserved and should be written low.

(0xn02) NCO Frequency

This register is a 32-bit unsigned integer that sets the NCOFrequency. The NCO Frequency contains a shadow register forsynchronization purposes. The shadow can be read backdirectly, the NCO Frequency can not.

)(*232

CLKf

NCO channelFrequency =

(0xn03) NCO Frequency Update Hold Off CounterThe Hold Off Counter is used to synchronize the change of NCOfrequencies. See the Synchronization section of the data sheet fordetailed explanation. If no synchronization is required, thisregister should be set to 0.

(0xn04) NCO Phase OffsetThis register is a 16-bit unsigned integer that is added to the phaseaccumulator of the NCO. This allows phase synchronization ofmultiple channels of the AD6622(s). See the Synchronizationsection of the data sheet for details. The NCO Phase Offsetcontains a shadow register for synchronization purposes. Theshadow can be read back directly, the NCO Phase Offset can not.

(0xn05) NCO Phase Offset Update Hold Off CounterThe Hold Off Counter is used to synchronize the change of NCOphases. See the Synchronization section of the data sheet fordetailed explanation. If no synchronization is required, thisregister should be set to 0.

(0xn06) CIC ScaleBits 5:0 set the CIC scaling per the equation below.

( )( )24

52log_ CICCIC LLceilScaleCIC ⋅=

See CIC section of the data sheet for details. Bits 7:6 are reservedand should be set to 0.

(0xn07) ReservedThis register is reserved and should be set to 0.

(0xn08) CIC2 Interpolation - 1This register sets the interpolation rate for the CIC2 filter stage(unsigned integer). The programmed value is the CIC2



scaling available (See CIC section of the data sheet).

(0xn09) CIC5 Interpolation - 1This register sets the interpolation rate for the CIC5 filter stage(unsigned integer). The programmed value is the CIC5Interpolation – 1. Maximum interpolation is limited by the CICscaling available (See CIC section of the data sheet).

(0xn0A) Number of RCF Coefficients - 1This register sets the number of RCF Coefficients and is limitedto a maximum of 128. The programmed value is the number ofRCF Coefficients – 1.

(0xn0B) RCF Coefficient OffsetThis register sets the offset for RCF Coefficients and is normallyset to 0. It can be viewed as a pointer which selects the portionof the CMEM used when computing the RCF filter. This allowsmultiple filters to be stored in the Coefficient memory space,selecting the appropriate filter by setting the offset.

(0xn0C) Channel Mode Control 1Bits 3:0 set NRCF/LRCF-1.Bits 5:4 set the channel input format as shown below.Bit 5 Bit 4 Input Mode0 0 FIR0 1 Reserved1 0 Reserved1 1 ReservedBit 6 ReservedBit 7 Reserved

(0xn0D) Channel Mode Control 2Bits 4:0 set the SCLKDivider that determines the serial clockfrequency based on the following equation.

)1(*2 +=

Divider

SCLK SCLKCLK

f

Bit 5 Reserved. Must be set low.Bits 7:6 set the RCF Coarse Scale as shown below.Bit 7 Bit 6 RCF Coarse Scale0 0 0dB0 1 -6dB1 0 -12dB1 1 -18dB

(0xn0E) Reserved

(0xn0F) Reserved

(0xn10) Reserved (Must be written to 0)

(0xn11) Reserved (Must be written to 0)

(0xn12-0xn1F) Reserved

(0xn20-0xn3F) Data MemoryThis group of registers contain the RCF Filter Data. See the RCFsection of the data sheet for additional detail.

(0xn40-0xn7F) Reserved

(0xn80-0xnFF) Coefficient MemoryThis group of registers contain the RCF Filter Coefficients. Seethe RCF section of the data sheet for additional detail.



WRITE PSEUDOCODE

Void Write_Micro(ext_address, int data);

Main()

{

/* This code shows the programming of the NCO frequencyregister using the Write_Micro function defined above. Thevariable address is the External Address A[2:0] and data is thevalue to be placed in the external interface register.

Internal Address = 0x102, channel 1*/

/*Holding registers for NCO byte wide access data*/int d3, d2, d1, d0;/*NCO frequency word (32 bits wide)*/NCO_FREQ=0x1BEFEFFF;/*write Chan */Write_Micro(7, 0x01);/*write Addr */Write_Micro(6,0x02);/*write Byte 3*/d3=(NCO_FREQ & 0xFF000000)>>24;Write_Micro(3,d3);/*write Byte 2*/d2=(NCO_FREQ & 0xFF0000)>>16;Write_Micro(2,d2);/*write Byte 1*/d1=(NCO_FREQ & 0xFF00)>>8;Write_Micro(1,d1);/*write Byte 0, Byte 0 is written last and causes an internal writeto occur*/d0=NCO_FREQ & 0xFF;Write_Micro(0,d0);}

READ PSEUDOCODE

Void Read_Micro(ext_address);

Main()

{

/* This code shows the reading of the NCO frequency registerusing the Read_Micro function defined above. The variableaddress is the External Address A[2:0]

Internal Address = 0x102, channel 1*/

/*Holding registers for NCO byte wide access data*/int d3, d2, d1, d0;/*NCO frequency word (32 bits wide)*//*write Chan */Write_Micro(7, 0x01);/*write Addr*/Write_Micro(6,0x02);/*read Byte 0, all data is moved from the Internal Registers to theinterface registers on this access, thus Byte 0 must be accessedfirst for the other Bytes to be valid*/d0=Read_Micro(0) & 0xFF;/*read Byte 1*/d1=Read_Micro(1) & 0xFF;/*read Byte 2*/d2=Read_Micro(2) & 0xFF;/*read Byte 0 */d3=Read_Micro(3) & 0xFF;}



APPLICATIONSThe AD6622 provides considerable flexibility for the control ofthe synchronization, relative phasing, and scaling of the individualchannel inputs. Implementation of a multi-channel transmitterinvariably begins with an analysis of the output spectrum thatmust be generated.

DIGITAL TO ANALOG CONVERTER (DAC)SELECTIONThe selection of a high performance DAC depends on a numberof factors. The dynamic range of the DAC must be consideredfrom a noise and spectral purity perspective. The 14-bitAD9754 and AD9772 are the best choices for overall bandwidth,noise, and spectral purity.

In order to minimize the complexity of the analog interpolationfilter which must follow the DAC, the sample rate of the masterclock is generally set to at least three times the maximum analogfrequency of interest.

In the case where a 15 MHz band of interest is to be up-converted to RF, the lowest frequency might be 5 MHz and theupper band edge at 20 MHz (offset from DC to afford the bestimage reject filter after the first digital IF). The minimum samplerate would be set to 65 MSPS.

Consideration must also be given to data rate of the incoming datastream, interpolation factors, and the clock rate of the DSP.

MULTIPLE TSP OPERATIONEach of the four Transmit Signal Processors (TSPs) of theAD6622 can adequately reject the interpolation images of narrowbandwidth carriers such as AMPS, IS-136, GSM, EDGE, andPHS. Wider bandwidth carriers such as IS-95 and UMTS requirea coordinated effort of multiple processing channels.

This section demonstrates how to coordinate multiple TSPs tocreate wider bandwidth channels without sacrificing imagerejection. As an example, a UMTS carrier is modulated using fourTSPs (an entire AD6622). The same principals can be applied todifferent designs using more or fewer TSPs. This section doesnot explore techniques for using multiple TSPs to solve problemsother than Serial Port or RCF throughput.

Designing filter coefficients and control settings for de-interleavedTSPs is no harder than designing a filter for a single TSP. Forexample, if four TSPs are to be used, simply divide the input datarate by four and generate the filter as normal. For any design, abetter filter can always be realized by incrementing the number ofTSPs to be used. When it is time to program the TSPs, only twosmall differences must be programmed. First each channel isconfigured with exactly the same filter, scalars, modes and NCOfrequency. Since each channel receives data at ¼ the data rate andin a staggered fashion, the Start Hold Off Counters must also bestaggered (see "Programming Multiple TSPs" section below).Second, the phase offset of each NCO must be set to match the

de-multiplexed ratio (¼ in this example). Thus the phase offsetshould be set to 90 degrees (16384 which is ¼ of a 16 bitregister).

Determining the Number of TSPs to UseThere are three limitations of a single TSP that can be overcomeby de-interleaving an input stream into multiple TSPs: Serial Portbandwidth, the time restriction to the RCF impulse responselength (NRCF), and the DMEM restriction to NRCF.

If the input sample rate is faster than the Serial Port can acceptdata, the data can be de-interleaved into multiple Serial Ports.Recalling from the Serial Port description, the SCLK frequency(fSCLK) is determined by the equation below. To minimize thenumber of processing channels, SCLKdivider should be set as lowas possible to get the highest fSCLK that the serial data source canaccept.

)1(2 +⋅=

rSCLKdividef

f CLKSCLK

A minimum of thirty-two SCLK cycles are required to accept aninput sample, so the minimum number of TSPs (NTSP) due tolimited Serial Port bandwidth is a function of the input samplerate (fIN), as shown by the equation below.

⋅≥

SCLK

INTSP f

fceilN

32

For an example UMTS system, we will assume fCLK = 61.44MHz, and the serial data source can drive data at 30.72 MBPS(SCLKdivider = 0). To achieve fIN=3.84 MHz, the minimumNTSP is 4 (This is TSP channels, not TSP ICs).

Multiple TSPs are also required if the RCF does not have enoughtime or DMEM space to calculate the required RCF filter.Recalling the maximum NTAPS equation from the RCF description,are three restrictions to the RCF impulse response length, NRCF.

)128,16,2

min( RCFRCF LL

N ⋅≤

TimeRestriction

DMEMRestriction

CMEMRestriction

whereIN

CLKTSPCICCICRCF f

fNLLLL

⋅=⋅⋅= 25

De-interleaving the input data into multiple TSPs will extend thetime restriction and may possibly extend the DMEM restriction,



but will not extend the CMEM restriction. De-interleaving theinput stream to multiple TSPs divides the input sample rate toeach TSP by the number of TSPs used (NTSP). To keep theoutput rate fixed, L must be increased by a factor of NCH, whichextends the time restriction. This increase in L may be achievedby increasing any one or more of LRCF, LCIC5, or LCIC2 within theirnormal limits. Achieving a larger L by increasing LRCF instead ofLCIC5 or LCIC2 will relieves the DMEM restriction as well.

In a UMTS example, NTSP=4, fCLK=61.44 MHz, and fIN=3.84MHz, resulting in L=64. Factoring L into LRCF=8, LCIC=8, andLCIC2=1 results in a maximum NRCF=32 due to the time restriction.Figure-MX shows an example RCF impulse response which has afrequency response as shown in Figure-MY from 0 Hz to 7.68MHz (fIN ⋅ LRCF/NTSP). The composite RCF and CIC frequencyresponse is shown in Figure-MZ, on the same frequency scale.This figure demonstrates a good approximation to a root-raised-cosine with a roll-off factor of 0.22, a pass-band ripple of 0.1 dB,and a stop-band ripple better than –65 dB until the lobe of thefirst image which peaks at –50 dB about 5.6 MHz from thecarrier center. This lobe could be reduced by shifting more of theinterpolation towards the RCF, but that would sacrifice near-inperformance. As shown, the first image can be easily rejected byan analog filter further up the signal path.

Scaling must be considered as normal with an interpolation factorof L, to guarantee no overflow in the RCF, CIC, or NCOs. Theoutput level at the summation port should be calculated using aninterpolation factor of L/NTSP.

Programming Multiple TSPsConfiguring the TSPs for de-interleaved operation is straightforward. All of the Channel Registers and CMEM of each TSP

are programmed identically, except the Start Hold-Off-Countersand NCO Phase Offset.

In order to separate the input timing to each TSP, the Hold-Off-Counters must be used to start each TSP successively in responseto a common Start SYNC. The Start SYNC may originate fromthe SYNC pin or the MicroPort. Each subsequent TSP musthave a Hold-Off-Counter value L/NTSP larger than itspredecessor's. If the TSPs are located on cascaded AD6622s, theHold-Off-Counters of the upstream device should be incrementedby an additional one.

In the UMTS example, L=64 and NTSP=4, so in order to respondas quickly as possible to a Start SYNC, the Hold-Off-Countervalues should be 1, 17, 33, and 49.

Driving Multiple TSP Serial PortsWhen configured properly, the AD6622 will drive each SDFS outof phase. Each new piece of data should be driven only into theTSP that pulses its SDFS pin at that time.

In the UMTS example, L=64 and NTSP=4, so each serial port needonly accept every 4th

input sample. Each serial port is shifting atpeak capacity, so sample 1, 2, and 3 begin shifting into SerialPorts B, C, and D before sample 0 is completed into Serial PortA.

SDFSA

SDFSB

SDFSC

SDFSD

0

1

2

3

4

5

6

7

1.024 McpsRAMCoefFilter

CICI

Q

RAMCoefFilter

CICI

Q

RAMCoefFilter

CIC5

I

Q

RAMCoefFilter

CICI

Q

DataRe-formatter

32

32

32

32

32

1.024 Mcps

1.024 Mcps

1.024 Mcps

4.096 Mcps

AD66228.196 Msps

8.196 Msps

8.196 Msps

8.196 Msps

NCO

NCO

NCO

NCO

SUMMATIONBLOCK

DAC

65.536 Msamples /sec

65.536 Msps

65.536 Msps

65.536 Msps

65.536 Msps

Complex signal 32 bits (16 I, 16 Q)

Real or Imaginary Signal



Coefj

j0 5 10 15 20 25 30

0

0.5

1

Figure MXTypical Impulse response for WBCDMA

Coef

0 1000 2000 3000 4000 5000 6000 7000 8000100

90

80

70

60

50

40

30

20

10

0

10RAM Coefficient Filter

kHz

dBc

Figure MY[Needs centering, monochrome, frequency scaling of 3.84/4.096, dBmin=-100]

1 1 500

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8120

110

100

90

80

70

60

50

40

30

20

10

0

dB AD662x f( )( )

dBH CIC f( )

level5

Spec f( )

f

MHz

Figure MZ



THERMAL MANAGEMENTThe power dissipation of the AD6622 is primarily determined bythree factors: the clock rate, the number of channels active, andthe distribution of interpolation rates. The faster the clock ratethe more power dissipated by the CMOS structures of theAD6622 and the more channels active the higher the overallpower of the chip. Low interpolation rates in the CIC stages(CIC5, CIC2) results in higher power dissipation. All thesefactors should be analyzed as each application has differentthermal requirements.

The AD6622 128-lead MQFP is specially designed to provideexcellent thermal performance. To achieve the best performancethe power and ground leads should be connected directly toplanes on the PC board. This provides the best thermal transferfrom the AD6622 to the PC board.



PACKAGE OUTLINE DIMENSIONSDimensions shown in mm.

128-Lead Terminal Metric Quad Flatpack (MQFP)

Dim Min. Nom. Max.A 3.4A1 0.25A2 2.6 2.7 2.8D 17.00 17.20 17.40D1 13.90 14.00 14.10E 23.00 23.20 23.40E1 19.90 20.00 20.10B 0.17 0.22 0.27e 0.5 BSC

Documents

a Transmit Signal Processor (TSP) Four Channel, 65 MSPS ...db.zmitac.aei.polsl.pl/Electronics_Firm_Docs/... · SDFSD SCLKD CIC RCF Filter NCO I Q I SPort Q data DATa SDINA SDFSA SCLKA