Design of CMOS IC ProcessA1-002-B: Semiconductor Fabrication
Process & Device Characterization for CMOS TechnologyNabilah
Binti Sk.Abd.Aziz (GIT 0755)
MODULE ASSIGNMENT
INTRODUCTION
The following exercise is to design and simulate MOSFET
transistors for a given device specifications using the Silvaco
TCAD tools.
OBJECTIVES
1.Silvaco Athena and Atlas software familiarization.2.Design of
MOSFET transistors using the given recipe to meet the device
specifications.
ASSIGNMENT CONTENT
PART 1: Silvaco Athena and Atlas software familiarization
1.Refer to the Athena & Atlas software manuals in Module A.1
section.2.Follow the instructions accordingly.
PART 2: MOSFET Design
1.Using Athena, design the NMOS and PMOS transistors with the
following specifications.
Gate length: 0.6um
Abs. Threshold voltage: 0.4 V < VTH < 0.5 V
Abs. Leakage current: < 0.1 nA
NMOS Drain current, ID > 1 mA at VGS = 3.3 V and VDS = 3.3
V
PMOS Drain Current, ID < 0.5 mA at VGS = -3.3V and VDS = -3.3
V
NMOS (ATHENA CODE)
OUTPUT STRUCTURE
I-V Curve:
The I-V curve above shows the ID when VDS and VGS are equal 3.3
V. The value of ID is larger than 1mA as in the specifications.
(ID=1.014 mA).
PMOS (ATHENA CODE)
Output Structure:
I-V CURVE
IV curve above shows the ID when VDS and VGS are equal 3.3 V. ID
is less than 0.5mA as in thespecifications. (ID=0.105 mA)
QUESTIONS AND DISCUSSION1.What are the design parameters that
affect the threshold voltage of the device?
i. Gate oxide thicknessii. Element used and concentration of
doping for threshold adjust implant,iii. Type of polysilicon doping
and its concentrationiv. Concentration of doping for source / drain
implant.
2.Explain the trade off in the design in order to meet the
specifications. Show with tables of various data points to prove
the theoretical assertions.
NMOS
In order to meet the specifications, there are several
parameters and element that have to change. The changes of element
for threshold voltage implant with the constant concentration and
gate oxide thickness for NMOS are as in the table below:
Gate Oxide Thickness ()Type of ElementDoping
Concentration(cm-3)Threshold Voltage , VT (V)Leakage Current Idoff
(A/m)Drain Current, ID (mA)
43.201Boron3e120.3244.065e-9 1.340
BF2 3e120.4051.050e-100.758
Gallium3e120.5095.039e-110.742
34.274Boron3e120.2315.136e-81.908
BF2 3e120.2501.019e-81.404
Gallium3e120.3841.423e-101.046
The result above is obtained by using the arsenic as a
polysilicon doping with concentration of5e16 and phosphorus as a
source/drain implant with concentration of 5e15. From the table
above, when the gate oxide thickness is decrease the threshold
voltage is also decrease for each type of element. As for the
leakage current, it increase along the type of element when the
gate oxide is decrease. The drain current is increase for each
element when the gate oxide thickness is decrease.
I think the most approximate result that meet the specification
is by using gallium. Thus, the doping concentration for gallium and
also the concentration of arsenic for the polysilicon doping is
adjusted to meet the specification as below:
Gate Oxide Thickness ()Doping Concentration of Gallium (cm-3
)Doping Concentration of Arsenic (cm-3) Threshold Voltage, VT
(V)Leakage Current Idoff (A/m)Drain Current, ID (mA)
43.2013.25e126e160.4903.916e-101.132
34.2743.25e126e160.4828.324e-111.014
When the concentration of gallium and arsenic is slightly
increase with the same value, the design is meet with all the
specifications at gate oxide thickness 34.274 .
PMOS
The changes for PMOS that affect the specifications are as in
the table below:
Based on the table above, it shows that the threshold voltage is
increase when the concentration of rhreshold voltage implant is
increase with constant doping concentration of polysilicon
andsource/drain implant. The gate oxide thickness affect both of
the threshold voltage and the leakagecurrent. The higher gate oxide
thickness gives the higher threshold voltage and lower leakage
current.The design meet all the specifications by using higher gate
oxide thickness and lower concentration ofpolysilicon doping.
As for conclusion, the parameters that mostly affect the
specifications are the gate oxidethickness and concentration of
threshold voltage implant and polysilicon doping. When the gate
oxidethickness is increase, VT increase while the leakage current
decrease.
When the concentration of polysilicon doping is lower, thus it
cause the electric field across thechannel to decrease. Threshold
voltage adjust implant also called backgate doping where backgate
doping has a major effect on the threshold voltage. If the backgate
is doped more heavily, then it becomes more difficult to invert to
create the channel. So a stronger electric field is required to
achieveinversion, and the threshold voltage increases. The backgate
doping of a MOS transistor can beadjusted by doing a shallow
implant under the gate dielectric to dope the channel region.
Show Id vs. Vds graphs for various values of Vgs.
NMOS
PMOS
