IEEE BCTM 1.2

A 5.2GHz Low Power Transceiver RFIC for WLAN Applications

Yin Shi1 Fa Foster Dai2 Senior Member, IEEE, Jun Yan1, Xueqing Hu1, Qiming Xu1 Hua Xu1,Xuelian Zhang1

1. Suzhou-CAS Semiconductors Integrated Technology Research Center, 328 Airport Road, SuzhouIndustrial Park, Suzhou 21 5021, China.

2. Dept of Electrical and Computer Eng., Auburn University, Auburn, AL 36849-5201.

Abstract This paper presents a low-power single chipWLAN 802.11a transceiver RFIC for personalcommunication terminal applications. The 5.2GHztransceiver RFIC is implemented in a 0.5gm SiGe technologywith 16 mm2 die size. It consumes 110/130mA inreceive/transmit mode under a 3.3V supply. The receiverpath shows a 6.4dB noise figure and a -2OdBm IIP3 under amaximal 67dB gain. The transmitter path 01P3 is measuredas 29.7dBm. The LC-tuned VCO has a tuning range from4.08GHz to 4.7GHz and the measured phase noise is -112dBc/Hz * IMHz offset.Index Terms - WLAN, 802.11a, SiGe, RFIC, low power,

low noise, linearity, personal communication terminal.

I. INTRODUCTION

Wireless communications has attracted great attentionsrecently, fueled by the emerging of wireless local areanetworks (WLAN) and the third generation W-CDMAtechnology [1-6]. The ever-increasing demand forwireless multimedia applications such as video streamingkeeps pushing future WLAN systems to support higherdata rates (54 MBit/s up to 1 GBit/s) at high linkreliability and over greater distances. Furthermore, thespeed gap between "wired" and "wireless" LANs shouldbe decreased so that WLAN can be seamlessly mergedinto high-data rate wired networks.With WLAN standards operating in very different

frequency bands, market leading WLAN solutions have tooffer multi-mode interoperability with transparentworldwide usage. Moreover, the frequency allocation ofthe WLAN standards in the "unlicensed" 5-GHz band isconstantly evolving. In particular, Japan proposed fouradditional RF channels in the 4.9 to 5.0-GHz band andfurther three channels in the 5.03 to 5.09-GHz band forthis standard. This change could significantly increase theavailable channels for 5-GHz WLAN in Japan, and createyet another difficulty for WLAN chipmakers by requiringthem to enable access to this lower-frequency band. It isthus desirable to design a WLAN transceiver with afuture-proofed multi-band frequency synthesis schemeagainst evolutions and changes in allocated spectrum

worldwide.This paper represents a low-power and low-cost WLAN

802.1 1a transceiver RFIC for personal communicationterminal applications. The 5.2GHz transceiver RFIC isimplemented in a 0.5Rtm SiGe technology with 16 mm2die size. It consumes 10OmA in receive mode and 130mAin transmit mode under a 3.3V supply. The receiver pathprovides a maximal 67dB and a minimal 20dB gain. Thereceiver path noise figure is measured as 6.4dB inmaximal gain mode and its IIP3 is measured as -20dBm.The transmitter path OIP3 is measured as 29.7dBm. TheLC-tuned VCO has a tuning range from 4.08GHz to4.7GHz and the measured phase noise is -112dBc/Hz i1MHz offset.

II. TRANSCEIVER ARCHITECTURE

fU

5.25GHzvi 1

,i

PA

Fig. I WLAN

Since the WLAN market is very cost-sensitive, for acompetitive radio, it must be low cost and low power.Choosing the transceiver architecture wisely is thuscritical. Superheterodyne radios require two synthesizers,but have a high level of transceiver performance. Theirinherent frequency diversity reduces DC offset and VCOpulling effects as compared to direct conversion receivers.Although by comparison direct conversion receiversrequire only one local oscillator, often times mixing

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schemes are used to achieve similar frequency diversity,resulting in a more complicated transceiver. Acompromise between the two approaches is to use awalking IF architecture where the RF LO is 4 times the IFLO [7]. Thus both LOs can be derived from a singlesynthesizer obtaining the benefit of a direct downconversion radio, but retaining the performanceadvantages of the superheterodyne radio.The implemented transceiver RFIC is illustrated in

Fig. 1. The walking IF architecture is chosen because asingle integer-N frequency synthesizer with a 16MHzreference would be enough to supply both RF and IF LOfrequencies. In addition, only one VCO with wide-tuningrange is needed to cover the 802.1 la low and middlebands from 5.18GHz to 5.32GHz. The receiver includes alow noise amplifier (LNA) followed by an image filter toreject the RF image tone at about 3.2GHz. The RF mixerdown-converts the received signal to IF frequency atabout 1.05GHz. The IF mixers further demodulate the IFsignal to baseband quadrature signals. The baseband blockincludes the VGAs for gain tuning and the baseband filteris off-chip. The transmitter starts with the baseband VGAblocks, followed by IF up-converters. The IF signal isfurther up-converted to 5.2 GHz signal by an RF mixerfollowed by an image filter. A pre-driver amplifies the5.2GHz signal with -5dBm output power for driving theoff-chip power amplifier.

II. RECEIVER FRONT-END DESIGN

Receiver front-end includes a differential LNA, animage-rejection filter and a down-converter mixer. Thedifferential LNA has good noise performance and lessdependence on the package parameters. Image-rejectionfilter is constructed with an inductor and two capacitors toremove the 3.2GHz image tones. RF mixer is also adifferential structure to interface with differential LNA.Down-mixer output goes off-chip to a SAW filter, whichhas 1.05GHz center frequency and 30MHz bandwidthwith 30dB out-of-band attenuations.The circuit schematic of the mixer is shown in Fig. 2,

which is a typical Gilbert cell with differential inputs andoutputs. Inductor LE is used as emitter degeneration toincrease the linearity of the mixer while consuming littlevoltage headroom. When LO is ideal square wave, themixer's voltage gain is given by

A _ RLAV =

T1zr + iri-,hI' e JWEI (1)

where RL is the load resistance and re is the emitterresistance of Q5 or Q6. Since mixer's IIP3 is proportionalto cWGmLE, LE should be carefully chosen to compromise

between the gain and the IIP3. Noise matching is achievedby selecting the sizes of LE and the transistors andoperating the RF transistors at the current density requiredfor minimum noise figure. Combining with the matchingnetwork, LE also achieves simultaneous noise and powermatching. Minimizing the noise of the mixer relies uponfast switching of the top quad-transistors. Note that thecurrent in the quad switching transistors is identical to thatflowing through the RF transistors below, where the biascurrent is tuned to the minimal noise figure current.Therefore, the top quad-transistors are sized such thattheir current density is close to that corresponding to thepeak fT. In this design, the ratio of the quad-transistor sizeto the RF transistor size is 1/6. The LO signals are appliedto the base of the quad transistors through LO buffers, sothat their amplitude can be kept large enough forcompletely switching. Lf and Cf are tuned to the LO+RFfrequency to get rid of the unwanted sideband. The LCtank formed by LT and CT are tuned to the second RFharmonic, acts as a filtered current source in the emitter ofthe input transistors.

vcc

fb D+! RL R 1 f+

Lf Cfotout- C =- ut

LO

LO- Q- JR Q6

Bias Bias

D J7 --iLE

RF I7MIh C L

I GND-.-RI-1-Fig. 2 schematic of the up-mixer.

III. TRANSMITTER DESIGN

A. Transmitter Baseband VGA

Transmitter variable gain stages attenuate the inputsignal by 0 30dB with a step size of 3 dB. Fig.3 illustratesthe gain cell and the digitally controlled current sources.The receiver variable gain range is 36dB with a step sizeof 3dB. IQ modulator includes two mixers similar to thereceiver IF mixers with image rejection. The summationof the quadrature mixer outputs is implemented by sharingthe load resistors.

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Fig. 3 Schematic of the VGA with digital control.

B. Power Amplifier Pre-Driver

The power amplifier driver consists of a differentialcascade amplifier, an emitter follower, and a common-emitter amplifier as shown in Fig.4. It is designed to drivethe 50 Q input of the off-chip 5.2GHz power amplifier.The degeneration inductors of the cascode amplifier helpwith the input matching of the PA driver, and they alsotrade the gain for linearity. The tanks are resonated at5.2GHz, which provides 35dB image rejection for out-of-band tones.

Fig. 5 Block diagram of the integer-N PLL for RF andwalking IF generations.

Fig. 6 Schematic of the wide tuning

Fig. 4 Schematic of the PA driver with image rejection.

IV. PLL FREQUENCY SYNTHESIZER DESIGN

In a walking-IF transceiver, the channel frequency isdefined as Fch=RF+IF=5180+20k, where k=0,1,...,7represents the 8 channels in WLAN 802.1 la low andmiddle bands. The RF mixer has a local oscillationfrequency (LO) at 4 times of the IF frequency, namely,RF=41F=4144+16k. Thus, the VCO frequency is requiredto cover 4144MHz to 4256MHz for 802.11a low andmiddle bands. The IF frequency is given byIF=RF/4=1036+4k. Therefore, the walking IF is from1036MHz to 1064MHz.

The integer-N phase lock loop (PLL) frequencysynthesizer is shown in Fig.5. It consists of an LC-tunedVCO which has a wide linear tuning range from 3.9GHzto 4.258GHz. Thus, the VCO can cover the entire5.15 5.35GHz 802.11 a bands. Schematics of the VCO isshown in Fig.6, where P-MOSFETs are used for theoscillation transistors such that the tank can be referencedto the ground for low phase noise. The VCO design alsoemploys an automatic-amplitude-control (AAC) circuitrythat can keep the VCO in current-limit region andalleviate the AM and AM to PM noise. AAC alsoprovides perfect ambient-proof characteristics overprocess, temperature and frequency variations.

In the PLL, an 8-bit programmable multi-modulusdivider (MMD) is designed using the topology ofcascaded 2/3 dual-modulus prescaler cell. The divide ratiocan be programmed from 256 to 511. But only the 259 to266 is used to generate the RF LO frequency from 4.144to 4.256GHz. The IF LO frequency is a quarter of the RFLO frequency, which is achieved by twice dividing by 2

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operations. In this process, the I-Q LO signals for IFmixer can also be generated. The phase frequency detector(PFD) is a totally differential structure for symmetric andnoise rejection. The charge pump (CP) is also differentialand its current can be programmed from 200uA to 2.1mAfor adjusting the loop gain. The control signal for MMDand programmable CP is input from a SPI data-loadinginterface.

IV. MEASURED RESULTS

Fig. 8 Measured EVM for IEEE 802.11 a transmission,EVM=6.30%, meeting IEEE 802.11 a OFDM requirement.

The 5.2GHz transceiver RFIC is implemented in a0.5Rim SiGe technology. Fig. 7 gives the die photographof the transceiver RFIC, which occupies 16mm2 areas andis packaged using a 48-pin leadless package. Fig. 8 givesthe measured error-vector-magnitude (EVM) for typicalIEEE 802.1 la transmission with 64 QAM OFDMmodulation. The measured EVM indicates that thepresented transceiver meets the IEEE 802.11 a OFDMrequirement. Table I summarizes the WLAN transceiverperformances. The receiver consumes 11OmA current andthe transmitter consumes 130mA current, respectively.

TABLE ISUMMARY OF TRANSCEIVER PERFORMANCE

SpecRX RX TX TX LowSpec High Gain Low Gain High Gain Gain

Gain 67.1 dB 20dB 14.8dB 5.5dBNF 6.4dB 16.7dB 38.4dB 38.5dB11P3 -25.4dBm 5.3dBm -5dB 3.2dBCurrent OlnOmA 130rnA

VI. CONCLUSION

This paper represents a low-power and low-cost SiGeRFIC WLAN 802.1 la transceiver RFIC design forpersonal communication terminal applications. Thetransceiver meets the IEEE 802.11a OFDM requirement.The receiver consumes 11OmA current and the transmitterconsumes 130mA current under a 3.3V supply.

REFERENCES

[1] Dave G. Rahn, Mark S. Cavin, Foster F. Dai, Neric Fong, RichardGriffith, Jose Macedo, David Moore, John W. M. Rogers, and MikeToner, "A Fully Integrated Multi-Band MIMO WLAN TransceiverRFIC," IEEE Journal on Solid State Circuits, Vol. 40, No. 8, pp.1629-1641, August, 2005.

[2] M. Zargari, et al. "A single-chip dual-band tri-mode CMOStransceiver for IEEE 802.1 1a/bg WLAN", IEEE International Solid-State Circuits Conference (ISSCC), p.96, Feb. 2004.

[3] T. Maeda, et al. "A direct-conversion CMOS transceiver for 4.9-5.95GHz multi-standard WLANs", IEEE International Solid-StateCircuits Conference (ISSCC), p.90, Feb. 2004.

[4] J. Bouras, et al. "A digitally calibrated 5.1 5-5.825GHz transceiver for802.11 a wireless LANs in 0.18,um CMOS" IEEE InternationalSolid-State Circuits Coniference (ISSCC), p.352, Feb. 2003.

[5] P. Zhang, et al. "A direct conversion CMOS transceiver for IEEE802.1 Ia WLANs"; IEEE International Solid-State CircuitsConference (ISSCC), p.354, Feb. 2003.

[6] A. Behzad, et al. "Direct-conversion CMOS transceiver withautomatic frequency control for 802.1 1a wireless LANs"; IEEEInternational Solid-State Circuits Conference (ISSCC), p.356, Feb.2003.

[7] J. W.M. Rogers, Foster F. Dai, Mark S. Cavin, and Dave G. Rahn, "AMulti-Band AT Fractional-N Frequency Synthesizer for a MIMOWLAN Transceiver RFIC," Journal of Solid State Circuits, vol. 40,No. 3, pp. 678-689, March 2005.

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