ABSTRACTLow power VLSI design is an emerging design methodology. It is very much importantto minimize the power consumption in circuit to have long battery life. Further as the size of devices is shrinking the leakage power dissipation is increasing, so a low-power design is the most viable solution.The work includes analysis of a full adder in static CMOS and pass transistor logic, in conventional design and sub-threshold design.Logic styles such as static CMOS and pass transistor logic are chosen because they have low power consumption as compared todynamic logic styles such as dynamic logic as well as other static logic styles such as pseudo-NMOS design logic.The work focuses on analysis of full adder in static CMOS and pass transistor logic in conventional design and tabulating the results. Then, the method of logical effort is used to design the sum section of an adder, using a two Xor gate design. This method is supplemented by considering the interconnect effect of wires. Then power-gating is used to design the circuits for low-leakage power design. This method with variations such as leakage-feedback, sleepy keeper approach is used to monitor the the static and dynamic power. Then the sub-threshold design is used to obtain optimum values of supply voltage and threshold voltage. Then the same static CMOS and pass transistor logic areused to evaluate the performance of the circuit. The circuit is designed iteratively to obtain the best possible waveform for output of sum section and thecarry section. The purpose of this work is to illustrate the pros and cons of sub-threshold design and to understand the viability of it. This is an iterative process and the results obtained are not exact they are just indicative. Sub-threshold designs are more suitable for low load applications. Full adders are used to simulate all the circuits and compute the results.