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Academy - High Volume FPGAs Page 2February 1999
Contents (7:45-9:45) High-Volume FPGA Organization
Spartan Marketing Message
Spartan Architecture
SpartanXL Features
Spartan Software
Other Families
AppLINX and Data Book Status
Academy - High Volume FPGAs Page 3February 1999
XC4000E1996
XC4000E1997
High Volume Product Families
Performance
XC52001996
Co
st E
ffect
ive
XC52001997
Spartan1Q 1998
SpartanXL4Q 1998
New: in ‘98No Compromises!
Performance, RAM, Cores, Low Prices
Academy - High Volume FPGAs Page 4February 1999
Product Families:
Spartan/XL: ASIC Replacement with RAMPlus … XC2000, XC3000, XC5200
Key Contacts:Primary Secondary
Spartan/XL Jay Aggarwal Steve SharpKurt Wong
XC2000/3000/A/L: Ed Chew Daniel ChanXC5200: Kurt Wong Steve SharpCompetitive Analysis: Mark Moran Ashok ChotaiApplication Support: Rick Mitchell Marc Baker
Kim GoldblattTactical Marketing Frank Carbone Daniel Chan
Denise Gibbons
High Volume FPGA Group
Academy - High Volume FPGAs Page 7February 1999
No Compromises
High Performance— Up to 80 MHz system performance
On-Chip SelectRAMTM
Wide range of IP and CORE solutions— PCI LogiCORE + AllianceCORE
Fully integrated software support— Alliance and Foundation Series software
Volume Pricing competitive with ASICs
Addresses the key needs of high volume logic users
Academy - High Volume FPGAs Page 8February 1999
Spartan Series Breaks The Mold to Penetrate New Applications
Simultaneous world-wide rollout (Jan 12, 98)
Extensive use of alternative media to reach broad audience— Sales kits, billboards, airport kiosks, ads, disti
promos, web pages
Academy - High Volume FPGAs Page 9February 1999
Xilinx Spartan Series FPGAsXilinx 4000
Heritage
Total Cost Management
Advanced ProcessTechnology
80 MHz PerformanceOn-chip SelectRAM
Software and cores
Smallest die size
Low packaging costLow test cost
Academy - High Volume FPGAs Page 10February 1999
Total Cost Management
Leading edge process technology— Smallest die size of any FPGA with on-chip RAM
Focused package offering— Low-power architecture allows use of highest volume
plastic packages– PLCC, VQ, TQ, PQ, BGA
Streamlined test flow— Lower cost test hardware— Built-in self test features— Shorter test times
Optimized manufacturing flows
Academy - High Volume FPGAs Page 11February 1999
Spartan Series Opens New Markets and Applications
No compromises:— Performance— On-chip RAM
(SelectRAM)— CORE support— Low cost
No compromises:— Performance— On-chip RAM
(SelectRAM)— CORE support— Low cost
Xilinx’s 2nd-generation ASIC alternative
Drive volumes higher— Aggressive pricing
Xilinx’s 2nd-generation ASIC alternative
Drive volumes higher— Aggressive pricing
Price leader for mainstream low-density FPGA market
Price leader for mainstream low-density FPGA market
Academy - High Volume FPGAs Page 12February 1999
FPGA Design Win FocusSelect Family Based on Logic Cells
Spartan/XL
Estimated design size (logic cells)
1500238 20,000
XC4000XLA/XV Virtex
S05/XL S10/XL S20/XL S30/XL S40/XL4013XLA 4020XLA… 4085XLA
40110XV ... 40250XVV50 V100 V150 V200 V300 V400 V600 V800 … V1000
28,000
Academy - High Volume FPGAs Page 13February 1999
Existing Design Strategy
XC4000E
XC4000XL
XC5200
Do Nothing Different
Do Nothing Different
Do Nothing Different
Do not convert existing designs to Spartan
Academy - High Volume FPGAs Page 14February 1999
Spartan Series Is Here Today
All Spartan Family devices available— Faster SpartanXL -5 coming soon
-4 devices available now— Enables 33 MHz PCI LogiCORE
COREs and software available— All Spartan Family devices in Base packages
Academy - High Volume FPGAs Page 15February 1999
Spartan Series Roadmap
1998 1999 2000
Spartan
$395
per 5K gates
Spartan
$395
per 5K gates
Pri
ce
SpartanXL
$295
per 5K gates
SpartanXL
$295
per 5K gates
0.35 5LM SpartanII
up to100K gates
SpartanII
up to100K gates
0.5 3LM
2.5 Volt
Higher Density + More Features
Without Compromises Pricing competitive with ASICs
High Performance
On-chip SelectRAMTM
PCI LogiCORE + AllianceCORE
3.3 Volt
5 Volt
*Prices are for 100K units, slowest speed, lowest cost package
0.25 5LM
SpartanNext Generation
up to200K gates
SpartanNext Generation
up to200K gates
1.8 Volt
0.18
Higher SpeedLower Power
Power Down Mode
Academy - High Volume FPGAs Page 16February 1999
Den
sit
y (S
yst
em G
ates
)
1997 1998 1999 2000 2001 2002
15K
40K
100K
100K unit volume price projections
60K
New Applications• Set Top Box• DVD• Digital Camera• PC Peripherals• Consumer Electronics
New Applications• Set Top Box• DVD• Digital Camera• PC Peripherals• Consumer Electronics
25K
60K
200K
100K
10K Gates/$ in 2002!10K Gates/$ in 2002!
Priced for High-Volume Leadership
Academy - High Volume FPGAs Page 17February 1999
Identifying the Spartan Arena
What are typical ASIC densities?
What are typical ASIC clock speeds?
What packages are most common for ASICs?
What cores are popular for ASICs and how often are they used?
Academy - High Volume FPGAs Page 18February 1999
Spartan Arena Covers ASIC Designs Up To 40,000 Gates
0
5
10
15
20
25
30
<10K 10-25K 25-50K 50-100K 100-150K
150-250K
>250K
Design Size (gates)
Per
cen
tag
e o
f D
esig
ns
Dataquest 1997 Gate Array Design Starts by Gate Count
The Spartan Arena
Academy - High Volume FPGAs Page 19February 1999
Spartan Arena Covers ASIC Designs Up To 80 MHz
02468
10121416
Average Clock Speed (MHz)
Per
cen
tag
e o
f D
esig
ns
Dataquest 1997 ASIC Design Starts by Average Clock Speed
The Spartan Arena
Academy - High Volume FPGAs Page 20February 1999
Spartan Arena Covers ASIC Designs from 84-256 Pins
02468
101214161820
<44 44-84
95-132
133-195
196-244
245-304
305-399
400-456
457-503
504-596
>596
Package Pin Count
Per
cen
tag
e o
f D
esig
ns
Dataquest 1997 ASIC Design Starts by Pin Count
The Spartan Arena
Academy - High Volume FPGAs Page 21February 1999
0% 25% 50% 75% 100%
Spartan Arena Addresses Most Popular ASIC Cores
Many CORES require RAM (PCI, DSP, USB, etc.)
Dataquest 1997 ASIC Designs By Core Usage
The Spartan Arena
Academy - High Volume FPGAs Page 22February 1999
Identifying the Spartan Arena of ASIC Designs
Up to 40,000 system gates
Up to 80 MHz system performance
84-256 package pins
RAM and/or COREs used
Up to 200K units/year
Academy - High Volume FPGAs Page 23February 1999
0
10
20
30
40
50
60
50 100 150 200 250
User I/O
Sys
tem
Gat
e C
ou
nt
(100
0's)
The Battlefield: Gates vs. I/Os
ASIC WINS
SPARTAN WINS!“The Spartan Arena”
Academy - High Volume FPGAs Page 24February 1999
0
10
20
30
40
50
60
50 100 150 200 250
User I/O
Sy
ste
m G
ate
Co
un
t (1
00
0's
)
Leverage Your Strengths: On-chip RAM Expands the Spartan Arena
“The Spartan Arena”
On-chip RAM
Academy - High Volume FPGAs Page 26February 1999
Spartan Series Changes the Battlefield for ASIC Designs
Leverage Spartan Series FPGA price leadership
Focus on high-I/O applications
Leverage on-chip RAM and COREs
Leverage FPGA benefits against ASICs— In-system programming, field upgrades,
easy prototyping— No ASIC can deliver these benefits!
Academy - High Volume FPGAs Page 27February 1999
Spartan Series Makes Altera Play By Our Rules
Design Requirement?
FLEX 10KFLEX 6K
Altera
On-Chip RAM Performance
Gates-only
Design Requirement?
Xilinx
On-Chip RAMPerformance
Low Cost
Altera still using “2 family” compromise strategy
Low cost High cost
Academy - High Volume FPGAs Page 28February 1999
Spartan Series Features Eliminate Competitive FPGAs
Goal: Leverage on-chip RAM and COREs against other FPGAs
Tactic: Establish on-chip RAM as an absolute requirement for ASIC-alternative FPGA solutions— Used in 75% of ASIC designs — Used in many FPGA COREs— Spartan Series delivers on-chip RAM at ASIC
prices
Academy - High Volume FPGAs Page 29February 1999
Project Aggressive Future Pricing
Use Spartan Series Advantages In The Quoting Process
Use “bracketing” in quotes to show options— Quote a multiple device sizes (downward)— Quote prices based on timeframe for orders— Quote different voltage options (Spartan vs.
SpartanXL)— Quote volume stepped pricing
Volume price steps strictly enforced
Academy - High Volume FPGAs Page 30February 1999
Call To Action
Find ASIC applications in the Spartan Arena and design-in Spartan Series FPGAs
Win back FLEX 10K 5-volt sockets
Keep FLEX 6K from getting any high-volume design wins
Academy - High Volume FPGAs Page 32February 1999
Spartan FPGA Architecture
Array of Configurable Logic Blocks (CLBs)
Perimeter Input/Output Blocks (IOBs)
Academy - High Volume FPGAs Page 33February 1999
CLB
Two Look-Up Tables (LUTs) create any function of four inputs
Two dedicated flip-flops
Academy - High Volume FPGAs Page 39February 1999
Interconnect Channel interconnect of varying lengths
— “Segmented” interconnect minimizes capacitance
— Maximizes speed and minimizes power
Single/double-length lines and long lines
Academy - High Volume FPGAs Page 40February 1999
Configuration
Single “Mode” Pin on 5V Spartan— High (default) = Slave Serial
– Externally-controlled configuration— Low = Master Serial
– FPGA-controlled configuration (from SPROM)
M1 pin on 3V SpartanXL enables parallel Express Mode
Mode pin(s) cannot be used as I/O
JTAG configuration supported
Academy - High Volume FPGAs Page 41February 1999
Mode Pins
XC4000 Spartan SpartanXL
M0 Master Serial Master Serial /Slave Serial /Slave Serial
M1 Don’t Connect /Express
M2 Don’t Connect /Powerdown
Academy - High Volume FPGAs Page 42February 1999
Pinouts
PQ208 pinout has been optimized— New pinout adds up to 9 I/Os, 8 VCCs— Optimizes noise
Other packages are not pinout- compatible with XC4000E due to
MODE pin
Academy - High Volume FPGAs Page 44February 1999
Xilinx Spartan Series 5 Volt -> XCS05 XCS10 XCS20 XCS30 XCS40
3.3 Volt -> XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K
Logic Cells 238 466 950 1368 1862
Max Logic Gates 3,000 5,000 10,000 13,000 20,000
Flip-Flops 360 616 1120 1536 2016
Max RAM bits 3,200 6,272 12,800 18,432 25,088
Max Avail. I/O 77 112 160 192 205
Performance 80MHz 80MHz 80MHz 80MHz 80MHz
No Compromises: Performance, RAM, Cores, and Low Price
Academy - High Volume FPGAs Page 45February 1999
Spartan Series Footprint Compatibility
Highest volume ASIC plastic packages
Footprint compatible in common packages
5 Volt XCS05 XCS10 XCS20 XCS30 XCS40
3.3 Volt XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
84 pin PC84 PC84
100 pin VQ100 VQ100 VQ100 VQ100
144 pin TQ144 TQ144 TQ144
208 pin PQ208 PQ208 PQ208
240 pin PQ240 PQ240
256 pin BG256 BG256
Underlined = available in Industrial range
Academy - High Volume FPGAs Page 46February 1999
XCS##XL-3PC84C
XCS = Spartan XL = 3.3 Voltno XL = 5 Volt
## = System Gates
Spartan Naming Logic cells are the best comparison metric
— Will be used in all collateral and comparisons
Spartan part name uses “System Gates”— Includes both RAM and Logic
– Top end of current “gate range”— Matches ASIC industry terminology (+ HardWire) — Consistent with future FPGA families
Academy - High Volume FPGAs Page 48February 1999
Spartan Speed Grades
Spartan speed grades increment from an arbitrary number (“-3”, “-4”)— No correspondence to a physical delay
Current XC4000 “-1”/”-09” do not correspond to
LUT delay
LUT alone does not reflect overall clock speed or routing speed
Academy - High Volume FPGAs Page 49February 1999
Spartan Speed Grades
Pe
rfo
rma
nc
e
5200 4000E Spartan,5V SpartanXL,3V
E-1
E-2
Spartan -4
Spartan -3
Higher Spartan speed grade = higher performance
-4
-3
SpartanXL-5
SpartanXL-4
Academy - High Volume FPGAs Page 51February 1999
Spartan Differences from XC4000E
No Asynchronous RAM—No RAM16X1, RAM32X1
– Only RAM16(32)X1S, RAM16X1D (synchronous)
No Edge Decoders (wide AND of I/Os)—No DECODEx
No Wired-AND of BUFTs—No WANDx or WOR2AND
No Parallel Configuration Modes (only serial)
Mode Pins Not Usable as I/O—No MD0, MD1, MD2
Academy - High Volume FPGAs Page 52February 1999
Spartan Cannot Fit an Existing XC4000 Socket Different pinout due to Mode pins
— Different PQ208 pinout
Different package offering
Different functionality
Different bitstreams
Different timing
Academy - High Volume FPGAs Page 54February 1999
Global Clock Buffers
Device BUFGP BUFGS BUFGLS BUFGE
Spartan 4 4 0 0
SpartanXL 0 0 8 0
XC4000X 0 0 8 8
General recommendation: Design with BUFG
— Software chooses appropriate specific buffer
— BUFGP/BUFGS will convert to BUFGLS automatically for SpartanXL target
Academy - High Volume FPGAs Page 55February 1999
SpartanXL CLB Latch
CLB flip-flops can be used as latches
LD, etc. components in SpartanXL library
Simplifies use of HDL synthesis
Similar to XC4000X
Academy - High Volume FPGAs Page 56February 1999
SpartanXL Interconnect
Carry only propagates upward— Significantly higher speed
– Similar to XC4000X— Standard long line can be used to continue at
the bottom of the next column
Datasheet figure shows upward carry only— Text describes that it is bidirectional in the 5V
Spartan family
All other device routing is identical to 5V Spartan family
Academy - High Volume FPGAs Page 58February 1999
SpartanXL 5V Compatibility
Can be driven by any 5V device and can drive 5V TTL (default)
Any 5 V
device
SpartanXLFPGA
Advanced 0.353.3V Core3.3V I/O
5V3.3V
5V
3.3V
Meets TTLLevels
Academy - High Volume FPGAs Page 59February 1999
Optional 3.3V Clamp for PCI
Programmable global 3.3V clamp for 3V PCI
Sacrifices 5V compatibility
BITGEN option– Default is “5V Tolerant I/Os”
Academy - High Volume FPGAs Page 60February 1999
SpartanXL Output Drive
Programmable 12 mA or 24 mA output drive— Pin-by-pin option— Default is 12 mA— 24 mA option supports 5V PCI V/I
requirements— Similar to XC4000XLA
Academy - High Volume FPGAs Page 61February 1999
Power Down
/PWRDWN pin activates low-power standby mode— Occupies the M2 pin on the corresponding XC4000E
device— Active Low— Timing is asynchronous
Academy - High Volume FPGAs Page 62February 1999
What Power Down Does
All inputs (including M0, M1, DONE, CCLK and TDO) except /PWRDWN are disconnected from their sources — The internal nodes are pulled to GND
All pull-up and pull-down resistors on all I/Os (except /PWRDWN) are disabled
The GSR net is active throughout Power Down
The GTS net is active throughout Power Down
Academy - High Volume FPGAs Page 63February 1999
To Achieve ICCO = 100 A during Power Down...
Clear the “5 V tolerant I/Os” option
Disable the internal pull-up resistor for /PWRDWN
Avoid contention
Avoid internal oscillators
Currently specified as typical— Will be specified over operating conditions
once characterization is complete
Academy - High Volume FPGAs Page 64February 1999
SpartanXL Output Mux
Output 2:1 mux or 2-input LUT supported in silicon and software— OMUX2, OAND2, etc. in SpartanXL library
Can use BUFGLS to drive one of the inputs for a fast path through the device
Academy - High Volume FPGAs Page 67February 1999
SpartanXL Bitstream
Different format than 5V Spartan bitstream— 1 more bit/frame, 1 more frame— Express mode is completely different
Must run BITGEN in M1.5 to program a SpartanXL device
Academy - High Volume FPGAs Page 68February 1999
SpartanXL Express Mode
M1 pin enables Express Mode configuration— True parallel configuration
– Similar to XC4000XLA— Default pull-up prevents Express mode— Use “BITGEN -g ExpressMode:Enable
-g CRC:Disable” in M1.5.21 or later (hidden)
Academy - High Volume FPGAs Page 69February 1999
XCS20XL PQ208 Adds 8 VCCs
XCS30 PQ208 added 8 VCCs vs. XC4000
XCS20 PQ208 had no additional VCC pads
XCS20XL adds 8 VCC pads— More important at higher speed/lower VCC— Bonded out to same locations as in XCS30/XL— P18, P33, P71, P86, P121, P140, P173, P192— Currently NCs on 5V XCS20
Make sure customers don’t connect these to GND or other signals now that they are VCC!
Academy - High Volume FPGAs Page 70February 1999
Software Support for Spartan
Rev.
Software Capability 1.5
Spartan Libraries X
SpartanXL Libraries X
Spartan Implementation X
Spartan Speed File X
SpartanXL Implementation X
SpartanXL Speed File FTP
Academy - High Volume FPGAs Page 71February 1999
SpartanXL Speed Files
Improved speeds from -3/-4 to -4/-5— Slower SpartanXL comparable to fast 5V
Spartan— Speed for free!
Advance speed files in 1.5i
Preliminary (production) speed files in 1.5i Service Pack— No changes to numbers
Academy - High Volume FPGAs Page 72February 1999
CORE Solutions
*Prices are for 100K units, plastic package
XCS30XL Percentage of EffectiveCore Function Price Device Used Function Cost
UART $6.95 17% $1.30
16-bit RISC Processor $6.95 36% $2.60
16-bit, 16-tap $6.95 27% $2.00Symmetrical FIR Filter
Reed-Solomon Encoder $6.95 6% $0.50
LogiCORE PCI32 Spartan $8.25 45% $3.80(in PQ208)
Academy - High Volume FPGAs Page 73February 1999
Costs Less Than Standard ICs
Standard Chip
External PLD7K Gates
7K Gates Logic
Com
pone
nt c
ost 1
00K
uni
ts
Standard ChipPCI Master I/F
XCS20XL-4 TQ144*
Solution <$7Solution <$7
PCI Master I/F
* Supported devices:XCS20XLXCS30XLXCS40XL
Power by$5
$20
$10
$15
Academy - High Volume FPGAs Page 76February 1999
What is FLEX 6000?
FLEX 6000 = Lower Price Replacement for 8K— Based upon 1994 XC5200 technology— Positioned as “first” Gate Array replacement FPGA
6000 Advantages
Improved FLEX 8K routing
50% less expensive than 10K
Equivalent performance to 8K
Faster than 5200
6000 Disadvantages
Limited devices available today
No RAM, no I/O Flip-Flops
Limited footprint compatibility
Slower than Spartan/XC4000
Non-Segmented Interconnect
Limited software support
Academy - High Volume FPGAs Page 77February 1999
Spartan Advanced 0.5 Process
ChipTransistor gates 0.5m- allows 5 V supply
All other features 0.35- small size- low capacitance- performance- low power
Combines 5 V operation with 0.35 benefits
Academy - High Volume FPGAs Page 78February 1999
0
1
2
3
4
0.6u FPGA2LM
0.6u FPGA3LM
0.5u FPGA3LM
Advanced 0.5uFPGA
AssemblyTestSilicon
Relative Cost
1993
1995
1996
Spartan Series addresses all aspects of cost
1997
Majority of cost is back end • Assembly• Test• Overhead
Spartan Series Total Cost Management
Academy - High Volume FPGAs Page 79February 1999
Spartan Series vs. Altera 6000/A
* A logic cell is a 4 input Look up table and a Flip-Flop** XL and A represent 3.3V devices for Xilinx and Altera respectively
Only 1 device for 5V, 3 devices for 3.3V
5 devices for 5V and 5 devices for 3.3V
Max Xilinx Logic Altera MaxI/O Device Cells Device I/O77 XCS05/XL 238
112 XCS10/XL 466880 EPF6010A 117
160 XCS20/XL 9501320 EPF6016/A 204/171
192 XCS30/XL 1368205 XCS40/XL 1862
1960 EPF6024A 218
Academy - High Volume FPGAs Page 80February 1999
Spartan Series vs. Altera 10KMax Xilinx Logic Altera MaxI/O Device Cells Device I/O77 XCS05/XL 238
112 XCS10/XL 466576 EPF10K10/A 134
160 XCS20/XL 9501152 EPF10K20 189
192 XCS30/XL 13681728 EPF10K30/A/E246/220
205 XCS40/XL 1862
* A logic cell is a 4 input Look up table and a Flip-Flop** XL and A represent 3.3V devices for Xilinx and Altera respectively
Only 2 low density 3.3V devices
5 devices for 5V and 5 devices for 3.3V
Academy - High Volume FPGAs Page 81February 1999
Xilinx Footprint Compatibility Leadership vs. FLEX 6K/A
Spartan Altera 6K SpartanXL Altera 6KA
5 Volt 3.3 VoltBG256
PQ240
PQ208
TQ144
VQ100
PC84
S05
S10
S20
S30
S40
6016
6010A
6016A
6024A
S05XL
S10XL
S20XL
S30XL
S40XL
Academy - High Volume FPGAs Page 83February 1999
0
10
20
30
40
50
60
10KE
XCS30XL6KA
10KA
Spartan 6K
10K
SpartanXL Provides Lowest K Factor
2.5V 3.3V
5.0V
SpartanXL K Factor = 11
Academy - High Volume FPGAs Page 86February 1999
Older ArchitecturesFamily Description Status
XC2000/L First FPGA LTB 12/31/98
XC3000 Original 2nd-gen arch. Not recommended;*low-volumepackages LTB12/31/98 & slowspeeds LTS 4/30/98
XC3100 Faster XC3000 Not recommended
XC3000A/L Enhanced 3K, 5V/3.3V Not focus; see *
XC3100A/L Faster 3KA/L, 5V/3.3V Not focus; see *
XC5200 Gates-only low-costFPGA
Not focus; .6 LTB12/31/98
Academy - High Volume FPGAs Page 89February 1999
AppLINX CD-ROM
Contains WebLINX + Xilinx File Download
WebCD Viewer functionality— Search by categories, including Solution
Records— Automatically looks for internet connection
and pulls updated files from WebLINX— Alternative: open root index.htm
Academy - High Volume FPGAs Page 91February 1999
1999 Data Book
See WebLINX for updated individual datasheets
Data Book PDF file available on AppLINX/WebLINX-FTP— Single 7M PDF file for use of Table of
Contents and Index, or Acrobat “Find” to search
— Also available as individual PDF files, as on WebLINX
Printed version shipping by 4/99