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Accelerated SLID Bonding Using Thin Multi -layer Copper-Solder Stack
for Fine-pitch Interconnections
Chinmay Honrao, Ting-Chia Huang, Makoto Kobayashi
#, Vanessa Smet, P. Markondeya Raj,
and Rao Tummala
3D Systems Packaging Research Center, Georgia Institute of Technology
813 Ferst Dr NW, Atlanta, GA 30332
# Namics Corporation, 3993 Nigorikawa, Kita-ku, Niigata City, Niigata Prefecture 950-313, Japan
Email: [email protected] / Phone: 734-604-4216
Abstract
Emerging 2.5D and 3D package-integration technologies
for mobile and high-performance applications are primarily
limited by advances in ultra-short and fine-pitch off-chip
interconnections. A range of technologies are being pursued
to advance interconnections, most notably with direct Cu-Cu
interconnections or Cu pillars with solder caps. While
manufacturability is still a major concern for the Cu-Cu
interconnections technologies, the copper-solder approaches
face limitations due to solder-bridging at fine-pitch,
electromigration, and reliability issues. Thus, novel low-
temperature, low-pressure, high-throughput, cost-effective
and manufacturable technologies are needed to enable
interconnections with pitches finer than 15 microns.
This paper focuses on an innovative multi-layered copper-
solder stack approach to achieve fine-pitch off-chip
interconnections with no residual solders after assembly.
Interconnections using this new technology enable higher
current-handling because of the stable intermetallics, high-
throughput assembly, and high yield even at low stand-off
heights. The elimination of solder-intermetallic (IMC)
interfaces is also expected to enhance the joint strength. This
paper describes the design, fabrication, assembly and
characterization of such stacked copper-solder
interconnections. A detailed study of the effect of bonding
parameters such as temperature and time on the rate of
formation of stable Cu-IMC-Cu structures is presented. Test-
vehicles were designed and fabricated as the first
demonstration of this technology.
Introduction
The I/O density, speed and bandwidth requirements for
emerging mobile and high-performance systems are projected
to drive the off-chip interconnection pitch to less than 20μm
by 2015 [1]. Various flip-chip interconnection materials and
processes have been developed over the past two decades to
meet the need for higher I/Os and enhanced electrical
performance. Lead-free solder bumps have been serving the
industry for the past 10 years, but face shortcomings for
emerging fine-pitch applications because of issues such as
solder-bridging and electromigration.
Direct copper-copper interconnections without solders
have the highest current-handling and lowest pitch
capabilities. However, there are fundamental challenges
associated with direct copper-copper bonding that include a
high temperature solid-state bonding process, inability to
accommodate non-planarity and non-uniformity of
interconnection bumps, and complex processes that are
required for the removal of residual oxides on the copper
surfaces prior to bonding [2]. The Georgia Tech-Packaging
Research Center recently made pioneering advances and
patented a low-temperature copper-copper thermo-
compression bonding process at less than 200oC, and
demonstrated HAST, TCT and electro-migration reliability at
30μm pitch using 10-15μm copper bumps [3]. The 30μm pitch
copper interconnections showed stable resistance for more
than 1000 hours even at 106A/cm
2, proving the high current-
carrying capability [4].
The copper pillar and solder-cap approach combines some
of the advantages of both copper and solder bump
technologies, and is the preferred option from the
manufacturability standpoint. Paik et al. recently
demonstrated reliability of 40μm pitch Cu-SnAg
interconnections with a stand-off height of 20μm using
anhydride-based NCFs [5]. However, the current
interconnection approaches using this technology are not
scalable to finer pitches as a result of electromigration and
reliability issues arising with decreased solder content. Being
a low-strength and low-fatigue resistance material, the solder
strains increase with decreased solder height. The formation
of copper-tin intermetallics leads to stresses at the IMC
(brittle)-solder (ductile) interfaces, which get further
aggravated at smaller stand-off heights and lower solder
volumes.
Solid Liquid Inter-Diffusion (SLID) bonding is being
explored as a promising approach to overcome some of the
challenges previously faced by copper-solder
interconnections. This technology is based on the rapid
formation of intermetallics between a high melting component
(in this case, Cu) and a low melting component (in this case,
Sn solder) at a temperature above the melting point of the
latter [6]. At this temperature, the copper diffuses into the
liquid tin at a very high rate, leading to much faster IMC
growth as compared to that in case of solid tin.
The reliability performance of SLID bonding has also
been investigated and reported. Labie et al. demonstrated
electromigration testing of 20μm diameter, Cu-Sn SLID-
bonded chip-chip interconnections at a current density of
6.3x104A/cm
2 at 150
oC [7]. No failures were observed till
1000 hours of current stressing. Chang et al. demonstrated
pressure-assisted SLID bonding of 20μm pitch micro-bumps
consisting of a 4μm copper-pillar and a 4μm tin-cap structure,
using a post-curing step at a temperature of 150oC for 30
minutes [8]. These interconnections were shown to be
978-1-4799-2407-3/14/$31.00 ©2014 IEEE 1160 2014 Electronic Components & Technology Conference
reliable over more than 1000 cycles of thermal cycling. SLID
bonding, however, faces certain process challenges. IMC
formation, being a diffusion driven process, requires long
assembly or post-annealing processes for a complete
conversion of solders to stable intermetallics. Infineon
Technologies developed a chip-stacking process based on
SLID bonding called SOLID-F2F, in which two chips are
bonded in the F2F (face-to-face) orientation [9]. The bonding
was completed in two steps, an initial soldering step at 260oC
for 1 minute, during which the Sn solder was completely
converted to Cu6Sn5 intermetallics. This was followed by a
20-minute-anneal at 300oC to convert the Cu6Sn5 into Cu3Sn.
For 30μm- pitch interconnections formed using this method,
they successfully demonstrated 1000 hours of temperature
cycling between -650C and 150
0C without any significant
increase in daisy-chain resistance [10].
A novel approach, based on a combination of SLID
bonding and alternate stacking of copper-solder layers, for
faster conversion of copper-solder to thermally-stable and
electromigration-resistant intermetallics is proposed. Figure 1
schematically shows the proposed interconnection approach
as compared to the current approach.
Figure 1. Current and proposed approaches for copper-
solder interconnections
The key advantages of such a technology are: (i) higher
electromigration resistance compared to traditional copper-
solder approaches, (ii) high throughput assembly at ultra-fine
pitch and low stand-off height without facing challenges such
as solder-bridging and solder-cracking, (iii) lower bonding
temperatures and pressures as compared to that used for Cu-
Cu interconnections, and (iv) enhanced thermal and
mechanical stability due to the elimination of solder/IMC
interfaces.
A first demonstration of this technology is presented along
with design, fabrication, assembly and characterization
results.
Modeling and Design
The Cu/Sn stacked structure should enable SLID bonding
with stable intermetallics using a short assembly time. This
section models the Cu/Sn structure to accomplish this.
Presence of silver in the solder inhibits the formation of
intermetallics. Since this approach requires faster formation of
intermetallics, pure tin was used as the solder. Based on the
atomic weights and densities of copper and tin, the minimum
thickness ratio of the copper and tin layers was calculated to
be 1.3 for conversion of tin to Cu3Sn.
Ideally, the thickness of individual copper and tin layers
should be as small as possible for lowest diffusion distances.
This, however, is restricted by the process capability for
copper and tin electroplating. A very thin layer of tin results in
insufficient wetting due to instant solidification of the tin
upon melting. From previous literature, it was observed that
the tin thickness used for SLID bonding is usually in the range
from 1-4μm. Based on the process capability of the available
copper and tin electroplating setup, a 1.5μm thick tin layer
was chosen for the bump structure. Based on the thickness
ratio previously calculated, the corresponding thickness of the
copper layer was 2μm.
The thickness of the initial copper layer was chosen to be
5μm as this layer is responsible for providing adhesion to the
seed layer, and as such, cannot be completely consumed to
form IMCs. For the final tin layer, the thickness was chosen to
be 3μm to ensure all bumps land on the substrate. A total of
three layers each of copper and tin were chosen to be stacked
alternately, resulting in a final bump height of 15μm. Figure 2
shows the final configuration of the bump for the copper-
solder stacked interconnections approach.
Figure 2. Bump configuration for copper-solder stacked
interconnections
Intermetallic formation between copper and tin is a
diffusion-limited process. During the bonding, Cu initially
reacts with Sn to form Cu6Sn5. Due to the high diffusion rate
of Cu into liquid Sn, complete conversion of Sn into Cu6Sn5 is
achieved in a few seconds [6]. Cu3Sn formation requires
solid-state interdiffusion between Cu and the previously
formed Cu6Sn5. As such, the Cu3Sn IMC formation can be
modeled using a parabolic law which is based on Fick’s first
law of diffusion, where the interdiffusion coefficient can be
calculated using the Arrhenius relationship. The parabolic law
and the Arrhenius relationship used are shown in Equation (I).
Equation (I)
1161
The assumptions made while simulating the intermetallic
growth were (i) constant concentration of the diffusing species
at the inter-layer boundaries, and (ii) constant concentration-
gradient along the inter-layer. Values for the activation energy
for the formation of Cu3Sn (Q) and its intrinsic diffusivity (k0)
were taken from previous studies based on the growth of
copper-tin intermetallics. These values differ with processing
techniques, and the values selected for this study were
applicable to thin films of copper and tin. The ‘Q’ and ‘k0’
values used were 66.1kJ/mol and 5.3E-8m2/s respectively [6].
Modeling the IMC formation is of importance as it
provides an estimation of the bonding temperature and time
needed for complete conversion of solder to Cu3Sn using the
above bump configuration. Based on the parabolic law,
Arrhenius relationship and the values for ‘Q’ and ‘k0’ it was
calculated that 2μm of Cu3Sn could be formed in 5 minutes at
a temperature of 250oC.
Fabrication of Copper-Solder Multi-layer Stack
As a proof-of-concept, 80μm pitch interconnections with
multi-layered copper-tin stack were fabricated. The process
was completed in two photo-lithography steps, one for the
routing layer and the other for the bumps. Figure 3 gives an
overview of the fabrication process.
Figure 3. Process for fabrication of copper-solder multi-layer
stacked structure
Hitachi RY-5315EB dry-film photoresist having a
thickness of 15μm was used for patterning the routing layer.
Karl-Suss MA6 Mask Aligner was used to expose the wafers
with a dose of 95mJ/cm2 using hard contact, after which they
were developed in 3% Na2CO3 solution at 85oC for about 2
minutes. Once the photoresist development was complete, the
wafers were plasma-cleaned to remove organic residue, if any,
from the openings in the photoresist. Copper was then
electroplated through these openings to form a 2-3μm thick
routing layer. Finally, Enthone PC 4025 was used to strip the
photoresist.
The same photoresist was used for patterning the bumping
layer. Photoresist lamination, exposure and development steps
were similar to the ones followed for patterning the routing
layer. After patterning, the wafers were plasma-cleaned,
before continuing with the plating process. Copper and tin
were plated alternately to obtain the copper-tin stacked
structure. Cupracid TP chemistry was used for plating copper
while tin was plated using the Stannobond FC chemistry, both
provided by Atotech. The wafers were thoroughly rinsed and
dried after electroplating each layer of the bump, so as not to
contaminate the two plating baths. The current densities used
for copper and tin electroplating were 15mA/cm2 and
20mA/cm2 respectively, and the resultant plating rates were
0.33μm/min and 1μm/min respectively. The plating time for
each layer was determined based on their respective target
thicknesses. The plated thickness was measured after each
plating step using the Dektak Profilometer.
After completing the plating, the photoresist was removed
using the Enthone PC 4025 stripper solution. This was
followed by seed-layer etching to remove the underlying
copper and tin seed layers. The alternate layers of copper and
tin in the fabricated interconnect structure are clearly visible,
as can be seen in Figure 4.
Figure 4. Copper-solder multi-layer stacked structure
Assembly and Characterization of Copper-Solder Stacked
Interconnections
Interconnections with 80μm pitch with the traditional
copper pillar-solder cap structure were assembled using SLID
bonding. SLID bonding assembly has to be performed at a
temperature above the melting point of tin, so as to enhance
the formation of intermetallics through diffusion of copper in
liquid tin. In this study, the aim was to convert the tin to the
intermetallics during the assembly process itself.
A FINETECH Lambda flip-chip bonder was used to
perform for assembly. Pre-applied BNUF was used to
minimize the process defects and further improve the
reliability of these interconnections. As determined by the
diffusion modeling described previously, the bonding
temperature and dwell-time used were 250oC and 300-900
seconds respectively. Figure 5 shows the temperature profile
used for this assembly process. The force applied during
bonding was 7.5N, which resulted in an equivalent pressure of
15MPa.
1162
Figure 5. Temperature profile used for SLID bonding of
copper-solder stacked interconnections
Assembled samples were cross-sectioned and
characterized using Energy Dispersive X-ray Spectroscopy
(EDS) to determine the presence of Cu6Sn5 and Cu3Sn, and to
study the thickness of the intermetallics.
Results and Discussion
1] IMC Formation Study
The diffusion model predicts the formation of 2μm of
Cu3Sn in 5 minutes at a bonding temperature of 250oC in the
ideal case. Referring to the Scanning Electron Microscope
(SEM) image shown in Figure 6(a), it can be seen that in 5
minutes, Cu3Sn was formed at the top-most and bottom-most
interfaces. Cu3Sn thickness was about 1μm at both interfaces
while the joint was mainly composed by Cu6Sn5. Moreover,
the intermediate Cu layer originally plated between the solder
layers was no longer observed. With extended assembly time
of 15 minutes, larger amounts of Cu3Sn were observed, while
significant amounts of Cu6Sn5 still remained, as seen in Figure
6(b). The different formation mechanisms for these two
intermetallics can help in explaining both the absence of
intermediate Cu layer, and the lower formation rate of Cu3Sn,
as described below.
The melting temperatures of Sn, Cu6Sn5 and Cu3Sn are
231.9oC, 415
oC and 670
oC respectively. The bonding
temperature used in this research is 250oC, which is slightly
higher than the melting temperature of the tin solder. By
exposing the copper-tin stacked structure to this temperature
for a sufficient amount of time, all of the tin is converted to
Cu6Sn5. During this liquid-phase reaction, the growth of
Cu6Sn5 consists of Cu dissolution and Cu6Sn5 precipitation
from molten solder. The dissolution of Cu into molten Sn can
be described by Dybkov’s analysis [11], where ‘Cs’ is the
solubility of Cu in molten solder at the reaction temperature,
‘C’ is the current concentration of Cu in molten solder, ‘k’ is
the dissolution rate constant, ‘S’ is the surface area of Cu pad
and ‘V’ is the volume of molten solder.
Figure 6. Cross-sections of stack-plated Cu-Sn
interconnections
At the early stage of liquid-phase reaction, the term (Cs-
C) will dominate the dissolution rate. In this study, pure tin
was used within the stack-plated structure. This implies that
the dissolution rate of Cu will be high during the beginning of
the liquid-phase reaction. This high dissolution rate of Cu has
been demonstrated in previous studies [12-13]. Since the
thickness of Cu layer within the stack-plated structure was
only 2μm, this dissolution mechanism can explain the absence
of the intermediate Cu layer that was originally a part of the
stack.
As the bonding temperature is below the melting point of
the formed Cu6Sn5, it is converted to Cu3Sn only through
solid-state diffusion. As a result, the conversion of Cu6Sn5 to
Cu3Sn requires much more time than that needed for the
formation of Cu6Sn5. Referring to the SEM image and EDS
characterization, the joint was mainly composed of Cu6Sn5
even after 900 seconds of bonding with a maximum
temperature of 250oC. The solder-based interconnection had
not fully transformed into Cu3Sn, but only a mixture of
Cu3Sn+Cu6Sn5. This result agrees with previous studies
focusing on Cu/Sn/Cu structure. Li et al. [14] found that
reflow at 350oC for 90 minutes was required to transform a
25μm Sn layer into Cu6Sn5, but it required another 390
minutes to achieve complete transformation from Cu6Sn5 to
Cu3Sn. For a 10μm Sn layer, Cu6Sn5 remained as the main
part of the solder joints even after 20 minutes reflow at 250oC
[15]. Although the designs varied from each other, all these
results indicate that Cu6Sn5 is the main product of liquid-
phase reaction. The growth rate of Cu3Sn by consuming
Cu6Sn5 has been found to be much lower than the rate of
formation of Cu6Sn5.
1163
Therefore, 5-15 min of bonding time at 250oC is sufficient
to completely eliminate the residual solders, though the most
stable Cu3Sn is not yet achieved. Increasing either the
temperature or time can lead to the stable Cu3Sn
intermetallics. However, due to the lower diffusion distances
resulting from the stacked structure of copper and tin, the
Cu3Sn formation time will at least be 2-3X smaller with the
current approach than what could be achieved with the
traditional solder cap structures.
2] Reliability of Cu/IMC joints
Solder and copper-tin intermetallics formed during
assembly significantly differ in their mechanical properties.
IMCs are inherently brittle while solders are ductile in nature.
Thus IMC formation is a known reason for stress generation
in the interconnection bumps during the cooling down of
solder. These stresses are usually concentrated at the interface
between the solder and the intermetallics [16]. This has an
adverse effect on the interconnection reliability, and this issue
needs to be addressed in order to achieve good-quality joints
at fine pitches and low stand-off heights.
The SLID bonding approach minimizes such stresses at
the solder-IMC interfaces by eliminating the solder-IMC
interface itself during an isothermal heat-treatment step. This
is achieved by converting all of the solder to IMCs, so as to
have uniform composition across the joint. Copper and tin
form two intermetallics, Cu6Sn5 and Cu3Sn, the latter being
the stable intermetallic. The residual solder after assembly
reflow in traditional copper-solder interconnections is
susceptible to electromigration and thermal-migration. Cu6Sn5
and Cu3Sn, on the other hand, have been shown to have a
higher electromigration resistance and better stability as
compared to solder [17]. By completely converting the Sn
solder to Cu3Sn, thermodynamic and metallurgical stability in
the joints can be achieved. The interfacial shear strength for
joints consisting of IMCs has been found to be higher than
Sn-dominated joints [18]. Thus, a Cu-IMC-Cu structure is not
only highly electromigration-resistant, but also mechanically
stable as compared to the Cu-IMC-SnAg-IMC-Cu structure
found in traditional copper-solder joints. The solder-free all-
intermetallic interconnections with Cu-solder SLID bonding
are shown to have good electromigration resistance and
thermal cycling reliability, as reported earlier [7-9]. The
reliability of SLID bonding with the present Cu/Sn stack
structures after complete elimination of residual solders is
currently being investigated as the next phase of this work.
Conclusions
An innovative bumping process with alternating copper
and tin plating layers to pre-designed thicknesses was
developed to fabricate ultra-short, fine-pitch interconnections
for 2.5 and 3D interposers and packages. Alternate layers of
copper and tin were electroplated on a blanket wafer and at 80
micron pitch, as a first demonstration of this stack-technology.
Formation of the intermetallics Cu6Sn5 and Cu3Sn was
investigated by SLID-bonding these stack-plated dies with
test substrates. The resulting interconnection structures
showed a mixture of Cu6Sn5 and Cu3Sn, and no presence of
any residual solders, potentially resulting in benefits such as
enhanced electromigration resistance and higher joint strength
with shorter processing times. With further process
development and optimization, this novel copper-solder
stacked approach can potentially achieve ultra-short fine-pitch
interconnections capable of handling current densities of
105A/cm
2 or higher.
Acknowledgments
The authors are grateful to the industry sponsors and
mentors for their funding and technical guidance. The authors
would also like to thank the staff at the Packaging Research
Center for their help in this research project.
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