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• FPGAs are far more different from uniprocessorsthan MPPs are from uniprocessors, and

• the process of parallelizing code for MPPs, whilechallenging, is still better understood and supportedthan porting codes to FPGAs.

Lawrence Snyder stated the three basic parameters forthe MPP portability problem.3 First, a parallel solutionusing P processors can improve the best sequential solu-tion by a factor of P, at most. Second, HPC problemstend to have third- or fourth-order complexity, and soparallel computation, while essential, offers only mod-est benefits. Third, “the whole force of parallelism mustbe transferred to the problem, not converted to ‘heat’ ofimplementational overhead.”

Researchers have addressed the portability problemperiodically over the past 30 years, with well-knownapproaches involving language design, optimizing com-pilers, emulation, software engineering tools and meth-ods, and function and application libraries. It is generallyagreed that compromises are required: Either restrict thevariety of architectures or scope of application, or boundexpectations of performance or ease of implementation.

AVOIDING IMPLEMENTATIONAL HEAT At Boston University’s Computer Architecture and

Automated Design Lab (www.bu.edu/caadlab), we have

Numerous application areas, including bioinformatics and computational biology,

demand increasing amounts of processing capability. In many cases, the computation

cores and data types are suited to field-programmable gate arrays.The challenge is

identifying the design techniques that can extract high performance potential from

the FPGA fabric.

Martin C. Herbordt, Tom VanCourt, Yongfeng Gu, Bharat Sukhwani, Al Conti, Josh Model, and Doug DiSabelloBoston University

A ccelerating high-performance computing(HPC) applications with field-programmablegate arrays (FPGAs) can potentially deliverenormous performance. A thousand-fold par-allelism is possible, especially for low-precision

computations. Moreover, since control is configured intothe logic itself, overhead instructions—such as arrayindexing and loop computations—need not be emu-lated, and every operation can deliver payload.

At the same time, using FPGAs presents significantchallenges1 including low operating frequency—anFPGA clocks at one-tenth that of a high-end micro-processor. Another is simply Amdahl’s law: To achievethe speedup factors required for user acceptance of anew technology (preferably 50 times),2 at least 98 per-cent of the target application must lend itself to sub-stantial acceleration. As a result, HPC/FPGA applicationperformance is unusually sensitive to the implementa-tion’s quality.

The problem of achieving significant speedups ona new architecture without expending exorbitantdevelopment effort, and while retaining flexibility,portability, and maintainability, is a classic one. Inthis case, accelerating HPC applications with FPGAsis similar to that of porting uniprocessor applica-tions to massively parallel processors, with two keydistinctions:

Achieving High Performancewith FPGA-Based Computing

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designed 12 methods to avoid generating implementa-tional heat while using FPGAs to accelerate several bioin-formatics and computational biology (BCB) applications.Table 1 categorizes the methods according to the type ofsupport required, such as programming tools, libraries,or programmer awareness of the target architecture.

We chose a standard PC with an FPGA coprocessor ona high-speed bus; to motivate using a nonstandard archi-tecture, we sought to achieve a 50 times speedup factor.

We selected widely used applications with high poten-tial parallelism, and preferably, low precision. In termsof programming effort, we considered a few months toa year or two (depending on potential impact) as beingrealistic. Our methods followed standard FPGA designprocedures, and were implemented primarily using theVHSIC Hardware Description Language (VHDL) sup-ported by our LAMP tool suite.4

We selected these methods for their ease of visual-ization; they are neither exhaustive nor disjoint. Inaddition, we avoided low-level issues related to logicdesign and synthesis in electronic design automation,as well as high-level issues such as partitioning andscheduling in parallel processing. Although we focusedon our own BCB work, the methods apply largely toother domains in which FPGAs are popular, such assignal and image processing.

APPLICATION RESTRUCTURINGThe first four methods address the restructuring HPC

applications generally require to enable substantialFPGA acceleration.

Method 1: Use an algorithm optimal for FPGAsHaving multiple plausible algorithms is common for

a given task—application and target hardware determinethe final selection. Frequently, the optimal algorithm foran FPGA differs from that for a serial computer or MPPwhen creating HPC/FPGA applications.

Application example. Modeling molecular interac-tions, or docking, is a key computational method usedfor in silico drug screening. A common technique digi-tizes each molecule onto a 3D voxel grid, then corre-lates a candidate drug molecule’s physical shape andchemical affinities to pockets within a protein or otherbiomolecule of medical interest. Fast Fourier transformsare used to compute the 3D correlations.5

Sample HPC/FPGA solution. The preferred FPGAalgorithm is based on direct summation, which, despitehaving higher asymptotic complexity, offers severaladvantages. First, small data type sizes, such as 1-bit val-ues for representing interior versus exterior information,offer little advantage on a microprocessor. On an FPGA,however, smaller processing elements allow for morePEs in a given amount of computing fabric, and imple-menting products of 1-bit values is trivial.

In addition, systolic arrays for correlation are efficient.The form we chose requires one input value and gener-ates one output value per cycle, while holding hundredsof partial sums in on-chip registers. Hundreds of dual-ported, on-chip block RAMs (BRAMs) hold intermedi-ate results, eliminating a potential bottleneck.

Finally, our implementation, after a brief setup phase,delivers one multiply-accumulate operation per clockcycle per PE, times hundreds to thousands of PEs in thecomputing array. Indexing, loop control, load/storeoperations, and memory stalls require no additionalmemory cycles.

Method 2: Use a computing mode appropriate for FPGAs

While FPGA configurations resemble high-level lan-guage programs, they specify hardware, not software.Because good computing modes for software are notnecessarily good computing modes for hardware,restructuring an application can often substantiallyimprove its performance. For example, while random-

March 2007 51

Table 1. HPC/FPGA application design techniques.

Type of support required Methods supported

Electronic design automation: languages and synthesis Use rate-matching to remove bottlenecksTake advantage of FPGA-specific hardwareUse appropriate arithmetic precisionCreate families of applications, not point solutionsScale application for maximal use of FPGA hardware

Function/arithmetic libraries Use appropriate FPGA structuresUse appropriate arithmetic mode

Programmer/designer FPGA awareness Use an algorithm optimal for FPGAsUse a computing mode appropriate for FPGAsHide latency of independent functionsMinimize use of high-cost arithmetic operations

None Living with Amdahl’s law

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access and pointer-based data structures are staples ofserial computing, they may yield poor performance onFPGAs. Streaming, systolic, and associative computingstructures, and arrays of fine-grained automata, arepreferable.6

Application example. Finding information about anewly discovered gene or protein by searching biomed-ical databases for similar sequences is a fundamentalbioinformatics task. The most commonly used applica-tions are based on the basic local alignment search tool,which operates in multiple phases. BLAST first deter-mines seeds, or good matches of short subsequences,then extends these seeds to find promising candidates,and finally processes the candidates in detail, often usingdynamic programming (DP) methods.

Sample HPC/FPGA solution. The preferred methodavoids random accesses into a largedatabase; rather, it streams the data-base through a two-dimensional sys-tolic array. The first dimensiongenerates, on every cycle, the char-acter-character match scores for aparticular alignment of the sequenceof interest versus the database. Thesecond dimension processes thescore sequence to find the maximallocal alignment. The tree structurekeeps the hardware cost low; pipelining assures gener-ation of maximal local alignments at the streaming rate.

Method 3: Use appropriate FPGA structuresCertain data structures such as stacks, trees, and pri-

ority queues are ubiquitous in application programs, asare basic operations such as search, reduction, and par-allel prefix, and using suffix trees. Equally ubiquitous indigital logic, the analogous structures and operationsusually differ from what is obtained by directly trans-lating software structures into hardware.

Application example. Another important bioinfor-matics task is analyzing DNA or protein sequences forpatterns indicative of disease or other functions funda-mental to cell processes. These patterns are often repet-itive structures, such as tandem arrays and palindromesunder various mismatch models.7 The asymptoticallyoptimal algorithms are often based on suffix trees; prac-tical algorithms often include heuristics.

Sample HPC/FPGA solution. A straightforward sys-tolic array, a palindrome finder’s hardware implemen-tation can test many possible palindrome lengths inone cycle.

Method 4: Living with Amdahl’s lawAmdahl’s law states that speeding up an application sig-

nificantly through an enhancement requires most of theapplication to be enhanced. This is sometimes difficult toachieve with existing HPC code—for example, profiling

often points to kernels that comprise just 60 to 80 percentof execution time. The problem is especially severe withlegacy codes and may require a substantial rewrite.

Not all is lost, however. The nonkernel code may lenditself to substantial improvement; as its relative execu-tion time increases, expending effort on its optimizationmay become worthwhile. Also, combining computa-tions not equally amenable to FPGA acceleration mayhave optimized the original code; separating them canincrease the acceleratable kernel.

Application example. Central to computational bio-chemistry, molecular dynamics applications predict mol-ecular structure and interactions. The MD computationitself is an iterative application of Newtonian mechanicson particle ensembles and alternates between two phases:force computation and motion update. The force com-

putation comprises several terms,some of which involve bonds. Themotion update and bonded forcecomputations are O(N) in the num-ber of particles being simulated,while the nonbonded are O(N log N)or (N2). The latter comprises theacceleratable kernel.

Sample HPC/FPGA solution.

Because MD codes tend to be highlycomplex, it is sometimes necessary to

start from scratch to achieve high performance. An exam-ple of an MD system, NAMD was also successfully accel-erated with FPGAs.8 Another example is the ProtoMolframework, which was designed especially for computa-tional experimentation and so has well-defined partitionsamong computations.9 We have found that the accelerat-able kernel not only comprises more than 90 percent ofexecution time with ProtoMol, but the modularity enablesstraightforward integration of an FPGA accelerator.10

DESIGN AND IMPLEMENTATIONMethods 5-7 address logic- or FPGA-specific design

issues.

Method 5: Hide latency of independent functions

Latency hiding is a basic technique for achieving highperformance in parallel applications. Overlap betweencomputation and communication is especially desirable.In FPGA implementations, further opportunities arise:Rather than allocating tasks to processors that must com-municate with one another, latency hiding simply laysout functions on the same chip to operate in parallel.

Application example. Returning to the example ofmodeling molecular interactions, the docking algorithmmust repeat the correlations at three-axis rotations—morethan 104 for typical 10-degree sampling intervals.Implementations on sequential processors typically rotatethe molecule in a step separate from the correlation.

Latency hiding

is a basic technique

for achieving

high performance

in parallel applications.

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Sample HPC/FPGA solution.Rather than performingan explicit rotation, an FPGA solution retrieves the pix-els in “rotated order.” The (i,j,k) of each voxel in indexspace can be expressed as a linear transformation of theoriginal (x,y,z) coordinates and the rotation. The pre-ferred technique is based on runtime index calculationand has two distinctive features. First, index computa-tion can be pipelined to generate indices at operatingfrequency due to the predictable order of access to vox-els. Second, because of the highly regular order of access,the indexing hardware can be optimized to take up justa few percent of a contemporary high-end FPGA’s area.

Method 6: Use rate-matching to remove bottlenecks

Computations often consist of independent functionsequences, such as a signal passingthrough a series of filters and trans-formations. Multiprocessor imple-mentations offer some flexibility inpartitioning by function or data, buton an FPGA, functions are neces-sarily laid out on the chip and sofunction-level parallelism is built in(although functions can also bereplicated for data parallelism). Thisimplies pipelining not only within,but also across, functions.

Application example. DNA microarrays simultane-ously measure the expression of tens of thousands ofgenes, and are used to investigate numerous questions inbiology. One approach is to analyze on the order of a hun-dred samples, each with tens of thousands of gene expres-sions, to find correlations between expression patternsand disease phenomena. The kernel operation is a seriesof dot-product and sum (DPS) calculations feeding covari-ance, matrix inversion, and regression (CIR) logic.

Sample HPC/FPGA solution. The FPGA’s powercomes from the parallel hardware it uses to handle aproblem. Usually the solution involves a very deeppipeline hundreds or even thousands of stages long.Difficulty arises, however, when successive functionshave different rates of sourcing and sinking data. Thesolution is to rate-match sequential functions by repli-cating the slower functions and then using them in rota-tion for the desired throughput. In the microarraykernel, the DPS units take about 10 times as long to sumover vectors as the CIR units take to consume DPSresults—so DPS calculations are replicated that manytimes per CIR.

Method 7: Take advantage of FPGA-specific hardware

FPGAs are often viewed as homogeneous substratesthat can be configured into arbitrary logic. In the pastfive years, however, an ever larger fraction of their chip

area has been devoted to hard-wired components, suchas integer multipliers and independently accessibleBRAMs. For example, the Xilinx VP100 has 400 inde-pendently addressable, 32-bit, quad-ported BRAMs; itachieves a sustained bandwidth of 20 terabytes per sec-ond at capacity. Using this bandwidth greatly facilitateshigh performance and is an outstanding asset of current-generation FPGAs.

Application example.In molecular dynamics, efficientalgorithms for computing the electrostatic interactionoften involve mapping charges onto a 3D grid. The firstphase of each iteration computes the 3D charge distrib-ution, while the second phase locates each atom in thatfield and applies a force to it according to its charges andthat region of the force field. Because atoms almost neveralign to the grid points on which the field is computed,

trilinear interpolation uses the eightgrid points nearest to the atom todetermine field strength. A variationof this computation uses tricubicinterpolation, which requires a 4 � 4� 4 grid neighborhood, and thus 64memory reads.

Sample HPC/FPGA solution. TheFPGA solution’s goal is to create astructure that computes forces at arate of one per cycle, accounting for

unpredictable sequences of atom positions. Key to sucha structure is simultaneous access to all grid points sur-rounding the atom. This in turn requires appropriate par-titioning of the 3D grid among the BRAMs to enablecollisionless access, and also efficient logic to convert atompositions into BRAM addresses. We have prototyped amemory-access configuration that supports tricubic inter-polation by fetching 64 neighboring grid-point values percycle. We have also generalized this technique into a tool that creates custom interleaved memories for accesskernels of various sizes, shapes, and dimensionality.

ARITHMETIC OPERATIONSThe next three methods deal with arithmetic opera-

tions on FPGAs.

Method 8: Use appropriate arithmetic precision

With high-end microprocessors having 64-bit datapaths, often overlooked is that many BCB applicationsrequire only a few bits of precision. In fact, even thecanonical floating point of MD is often implementedwith substantially reduced precision, although thisremains controversial. In contrast with microprocessors,FPGAs enable configuration of data paths into arbitrarysizes, allowing a tradeoff between precision and paral-lelism. An additional benefit of minimizing precisioncomes from shorter propagation delays through nar-rower arithmetic units.

March 2007 53

The FPGA’s power

comes from the

parallel hardware

it uses to

handle a problem.

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Application example. All BCB applications describedhere benefit substantially from the selection of nonstan-dard data type sizes. For example, microarray values andbiological sequences require only two to five bits, andshape characterization of a rigid molecule requires onlytwo to seven bits. While most MD applications requiremore than the 24 bits provided by a single-precision float-ing point, they might not need double precision (53 bits).10

Sample HPC/FPGA solution. We return to the mod-eling molecular interactions case study to illustrate thetradeoff between PE complexity and degree of paral-lelism. That study examined six different models describ-ing intermolecular forces. Molecule descriptions rangefrom two to seven bits per voxel, and scoring functionsvaried with the application. The number of PEs that fitthe various maximum-sized cubical computing arraysinto a Xilinx XC2VP70 ranged from 512 (83) to 2,744(143), according to the resources each PE needed. Sinceclock speeds also differed for each application-specificaccelerator, they covered a 7:1 performance range. If wehad been restricted to, for example, 8-bit arithmetic, theperformance differential would have been even greater.

Method 9: Use appropriate arithmetic modeMicroprocessors provide support for integers and

floating point, and, depending on multimedia features,8-bit saturated values. In digital signal processing sys-tems, however, cost concerns often require DSPs to haveonly integers. Software can emulate floating point whenrequired; also common is use of block floating point.FPGA’s analogous situation is that, although plausible,single-precision floating points remain costly and shouldbe avoided if possible, with well-tuned libraries avail-able. Alternatives include the block floating point, logrepresentations, and the semi-floating point.

Application example. The MD computation’s innerkernel operation requires computing r-14 and r-8 (theradius r between atoms), over a wide range, usually with a table lookup. We would generally use double-precision floating points for further computations.

Sample HPC/FPGA solution. Careful analysis showsthat the number of distinct alignments that must be com-puted is quite small even though the range of exponentsis large. This enables the use of a stripped-down floating-point mode, particularly one that does not require a vari-able shift. The resulting force pipelines (with 35-bitprecision) are 25 percent smaller than ones built with acommercial single-precision (24-bit) floating-point library.

Method 10: Minimize use of high-costarithmetic operations

The relative costs of arithmetic functions are differ-ent on FPGAs than on microprocessors. For example,FPGA integer multiplication is efficient compared toaddition, while division is orders-of-magnitude slower.Even if the division logic is fully pipelined to hide its

latency, the cost remains high in chip area, especially ifthe logic must be replicated. On an FPGA, implement-ing unused functions isn’t necessary; recovered area canbe used to increase parallelism. Thus, restructuringarithmetic with respect to an FPGA cost function cansubstantially increase performance.

Application example. The microarray data analysiskernel as originally formulated requires division.

Sample HPC/FPGA solution. We represent numbersas rationals, with a separate numerator and denomina-tor, replacing division operations with multiplication.This doubles the required number of bits, but rationalvalues are needed only at a short, late segment of thedata path. Consequently, the additional logic requiredfor the wider data path is far lower than the logic fordivision would have been.

SYSTEM AND INTEGRATION ISSUESThe final two methods deal with two familiar HPC

issues: flexibility and scalability. These methods differfrom the others in that they require design tools notwidely in use, either because they are currently propri-etary11 or exist only as prototypes.4

Method 11: Create families of applications,not point solutions

HPC applications are often complex and highly para-meterized, resulting in variations in applied algorithmsas well as data format. Contemporary object-orientedtechnology can easily support these variations, includ-ing function parameterization. This level of parameter-ization is far more difficult to implement in currenthardware description languages, but it enables higherreuse of the design, amortizes development cost over alarger number of uses, and relies less on skilled hard-ware developers for each application variation.

Application example. Other essential methods forsearching biological databases are based on dynamicprogramming. Although generally referred to by thename of one particular variation, Smith-Waterman, DP-based approximate string matching actually consists ofa large number of related algorithms that vary signifi-cantly in purpose and complexity.

Sample HPC/FPGA solution. Achieving high perfor-mance in HPC/FPGA applications requires careful tuning to application specifics, which limits componentreusability. Generally, programmable PEs rarelyapproach tuned applications’ speed or resource efficiency. Reusable HPC/FPGA applications must resolve the conflicting requirements of generality and customization.

In traditional hardware design systems, componentscomprise black boxes with limited internal parameter-ization. Reuse largely entails creating communicationand synchronization structures and connecting these to the memory subsystems. Moreover, in HPC/FPGA

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systems, the innermost com-ponents—the leaf data types and arithmetic expres-sions—change between ap-plications. System perfor-mance thus depends onmemory, synchronization,and communication, whichare the aspects most unfa-miliar to traditional pro-grammers. As with thestandard C library’s qsort(),control and communicationare the reusable parts; innerfunction blocks and datatypes are the customiza-tions—the opposite of whattypical design tools wouldsupport.

The term application fam-ily describes a computationthat matches this description, and DP-based approximatestring matching offers an example. Figure 1 illustrates theapplication family’s hierarchical structure. Each level ofdesign hierarchy has fixed interfaces to the componentsabove and below in that hierarchy. The fixed interfaceincludes data types defined and used in that level, but pos-sibly also passed through communication channels atother levels. Within a hierarchical level, each componenttype has several possible implementations, including def-initions of its data elements. The fixed interface, however,hides that variability from other design layers.

Our initial implementation allowed more than 200combinations of the three component types, with manymore variations possible through parameter settings.This structure was quite natural in the object-orientedalgorithms we used but required more configurabilitythan VHDL features provide.

Method 12: Scale application for maximal useof FPGA hardware

As the degree of parallelism typically dominates per-formance, part of accelerator design consists of instan-tiating as many PEs as the FPGA’s computing fabric willsupport. The number of PEs depends, often nonlinearly,on the attributes of both the application and FPGA.Given the frequency at which larger FPGAs becomeavailable, automated sizing of complex arrays willbecome increasingly important for porting applicationsamong FPGA platforms.

Application example. All the case studies can bescaled to use additional hardware resources.

Sample HPC/FPGA solution. The desired number ofPEs in an application is always “as many as possible.”Three factors that define any FPGA platform and appli-cation are the:

• FPGA, which is characterized by quantities of eachtype of computing resource;

• application family, which defines the structure of thecomputing array; and

• member of the application family, which specifiesthe PEs’ sizes.12

FPGA capacity has terms for each of the availablehardware resources, including hard multipliers andBRAMs as well as general-purpose logic elements.Depending on the application, any of the resources canbecome the limiting one.

The application family defines the computationarray’s geometry. As shown in Figure 2a, arrays can besimple linear structures. Figure 2b illustrates an arraywith two different architectural parameters—N1 rep-resents the rectangle’s height and N2 its width. In thiscase, the array can grow only in increments of wholerows or columns; architectural parameters are not lit-eral numbers of PEs. Computing arrays like those inFigure 2c have multiple subsystems of related sizes anddifferent algebraic growth laws. Figure 2d represents atree-structured array, showing how arrays can growaccording to exponential or other nonlinear laws. Onesubsystem can consume multiple types of FPGAresources, as shown in Figure 2e, so any of the resourcescan limit the computing array’s growth. Of course, acomputing array can include multiple architecturalparameters, nonlinear growth patterns, coupled sub-systems growing according to different algebraic laws,and multiple resource types.

Although the application family defines the comput-ing array’s form, sizes of PEs in the array depend on thespecific family member. In string matching, for exam-ple, PE size depends on the number of bits in the string

March 2007 55

Figure 1. Logical structure of application family for DP-based approximate string matching.

Each level of design hierarchy has fixed interfaces to the components above and below that

hierarchy. Within a hierarchical level, each component type has several possible implementa-

tions, which the fixed interface hides from other design layers.

…Param

ProteinParam

IUPACwild cards

Param

DNAParam

CharRuleParam

1

Smith-Waterman

Param

Needleman-Wunsch

Param

Match cellParam

N

Traceback

ScoreOnly

SequencerXAbstract

YConcrete

A B

A implements B

A B

A contains B

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element—for example, 2 bits for DNA or 5 bits for pro-teins—and on the type of comparison performed.

A computing array’s size is an outcome of other designfeatures rather than a design input. Array dimensionsnaturally grow when larger FPGAs offer more resources,and they decrease when complex applications consumemore resources per PE. Sizing the array means choosingarchitectural parameters to maximize a configuration’sdesirability, which a function represents. The “best”architectural parameter values define the most desirablearray, as long as the array’s structure is valid for thatapplication family and the FPGA’s resource budget.Automated sizing is possible within the experimentalLAMP design system4 but cannot be expressed in main-stream design tools or methodologies.

H igh-performance computing programmers are ahighly sophisticated but scarce resource. Such pro-grammers are expected to readily use new technol-

ogy but lack the time to learn a completely new skill suchas logic design. As a result, developers have expendedmuch effort to develop design tools that translate high-level language programs to FPGA configurations, butwith modest expectations of results.

A subset of the 12 design methods we have describedmust generally be applied for an HPC/FPGA applicationto obtain more than a fraction of its potential perfor-mance. The critical question is whether the methods’ goalsare compatible. In other words, what support wouldenable an HPC programmer to use these methods? Weare encouraged that all of the methods we have describedappear to be within reach of the HPC/FPGA community.

While there is potential for enormous speedup inFPGA-based acceleration of HPC applications, achiev-

ing it demands both selecting appropriate appli-cations and specific design methods that ensuresuch applications are flexible, scalable, and atleast somewhat portable. Such methods arefirmly entrenched in HPC tools and practices.

HPC/FPGA hardware is only now emergingfrom the prototype and early commercialstages, so tools and techniques have not yetcaught up. Manual techniques or prototypetools are addressing problems caused by cur-rent HPC/FPGA infrastructure. For applica-tions similar to what we’ve described here, themost important issues involve educating noviceHPC/FPGA developers in new programmingmodels and idioms, creating arithmetic andfunction libraries, and moving critical designcapabilities from prototypes into mainstreamdesign tools. ■

Acknowledgments

This work was supported in part by the NIH throughaward #RR020209-01, the US Naval ResearchLaboratory, and MIT Lincoln Labs, and was facilitatedby donations from Xilinx. We thank the anonymousreviewers for their many helpful suggestions.

References

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4. T. VanCourt and M.C. Herbordt, “LAMP: A Tool Suite forFamilies of FPGA-Based Application Accelerators,” Proc. Int’lConf. Field Programmable Logic and Applications, IEEEPress, 2005, pp. 612-617.

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Figure 2. Growth laws for computing arrays specified in terms of

architectural parameters. (a) Linear array—one structural parameter. (b)

Rectangular array—N1 � N2 PEs. (c) Coupled structures—related sizes N,

N 2, N 3. (d) Tree of depth N—2 N-1 PEs. (e) Multiple FPGA resources, with

dependencies between allocation amounts.

N(a)

N2

N1

(b)

N

(d)

(c)

N

(e)

RAMLogic

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Martin C. Herbordt is an associate professor in the Depart-ment of Electrical and Computer Engineering at Boston Uni-versity, where he directs the Computer Architecture andAutomated Design Laboratory. His research interests includecomputer architecture, applying configurable logic to high-performance computing, and design automation. Herbordtreceived a PhD in computer science from the University ofMassachusetts. He is a member of the IEEE, the IEEE Com-puter Society, and the ACM. Con-tact him at herbordt@bu.edu.

Tom VanCourt is a senior memberof the technical staff, software engi-neering, at Altera Corp. Hisresearch interests include applica-tions and tools for reconfigurablecomputing. VanCourt received aPhD in computer systems engi-neering from Boston University. Heis a member of the IEEE, the IEEEComputer Society, and the ACM.Contact him at tvancour@altera.com.

Yongfeng Gu is a PhD candidate inthe Department of Electrical andComputer Engineering at BostonUniversity. His research interestsinclude reconfigurable computing,computer architecture, and hard-ware/software codesign. Gu re-ceived an MS in computer sciencefrom Fudan University. Contacthim at maplegu@bu.edu.

Bharat Sukhwani is a PhD candidate in the Department ofElectrical and Computer Engineering at Boston University.His research interests include FPGA acceleration of scien-tific applications, high-level design environments for FPGA-based systems, and VLSI CAD tools for nanotechnologydevices. Sukhwani received an MS in electrical and com-puter engineering from the University of Arizona. He is astudent member of the IEEE. Contact him at bharats@bu.edu.

Al Conti is a digital design engineer at MITRE Corp. Hisresearch interests include using FPGAs and other hybridarchitectures in high-performance image and signal pro-cessing applications. Conti received an MS in electrical andcomputer engineering from Northeastern University and aBS in computer systems engineering from Boston University.He is a member of the IEEE. Contact him at aconti@mitre.org.

Josh Model is a master’s candidate in the Department ofElectrical and Computer Engineering at Boston Universityand an associate technical staff member at MIT LincolnLaboratory. His research interests include the use of FPGAsin scientific computing and hyperspectral image processing.Model received a BSE in electrical engineering from Prince-ton University. Contact him at jtmodel@bu.edu.

Doug DiSabello received an MS in computer systems engi-neering from Boston University. Contact him at douglasd@bu.edu.

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