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ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 1
Design Of Combinational Logic Circuits
• Dr. Costas Kyriacou and Dr. Konstantinos Tatas
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 2
Design of combinational digital circuits
• Steps to design a combinational digital circuit:– From the problem statement derive the truth table– From the truth table derive the unsimplified logic expression– Simplify the logic expression – From the simplified expression draw the logic circuit
• Example: Design a 3-input (A,B,C) digital circuit that will give at its output (X) a logic 1 only if the binary number formed at the input has more ones than zeros.
BCABACX
A B C
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
1
0
1
1
1
Inputs Output
0
1
2
3
4
5
6
7
BC00
0
01
1
11 10A0 0 1 0
0 1 1 1
A B C
X
7) 6, 5, (3,X
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 3
Design of combinational digital circuits (Cont.)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic 1 only if the binary number formed at the input is between 2 and 9 (including).
C BABACAX
A B C
X
,7,8,9)(2,3,4,5,6XA B C00
000
1
X00
Inputs Output
01
D0
00 0 0 12 10 0 1 13 10 1 0 14 00 1 1 15 00 1 0 16 10 1 1 17 11 0 0 18 01 0 1 19 01 0 0 010 11 0 1 011 11 1 0 012 01 1 1 013 01 1 0 014 11 1 1 015 1 D
CD00
00
01
01
11
11
10
10
AB0 0 1 1
1 1 1 1
0 0 0 0
1 1 0 0
X
Same
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 4
Design of combinational digital circuits (Cont.)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic 1 only if the binary number formed by the inputs (AB) is greater or equal to the binary number formed by the inputs (CD).
A B C
A B C00
000
1
Inputs
01
D0
00 0 02 10 0 13 10 1 04 00 1 15 00 1 06 10 1 17 11 0 08 01 0 19 01 0 010 11 0 111 11 1 012 01 1 113 01 1 014 11 1 115 1 D
CD00
00
01
01
11
11
10
10
AB
X X
Output
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 5
• Tutorial: Design a 4-input (A,B,C,D) digital circuit that will give at its output a binary number equal to the sum of the binary numbers formed by the inputs (AB) and (CD).
A B C
0
0
0
0
0
1
0
1
D
0
0
0 0 02 1
0 0 13 1
0 1 04 0
0 1 15 0
0 1 06 1
0 1 17 1
1 0 08 0
1 0 19 0
1 0 010 1
1 0 111 1
1 1 012 0
1 1 113 0
1 1 014 1
1 1 115 1
X = Y =
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
W = Z =
CD00
00
01
01
11
11
10
10
ABCD
00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 6
A
B
C
D
'0''1'
X = Y =
W = Z=
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 7
• Tutorial: Design a 4-input (A,B,C,D) digital circuit that will give at the output:– X a logic 1 if the binary number formed by the inputs (AB) is greater than (CD).– Y a logic 1 if the binary number formed by the inputs (AB) is less than (CD).– Z a logic 1 if the binary number formed by the inputs (AB) is equal to (CD).
A B C
0
0
0
0
0
1
0
1
D
0
0
0 0 02 1
0 0 13 1
0 1 04 0
0 1 15 0
0 1 06 1
0 1 17 1
1 0 08 0
1 0 19 0
1 0 010 1
1 0 111 1
1 1 012 0
1 1 113 0
1 1 014 1
1 1 115 1
X = Y =
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
W = Z =
CD00
00
01
01
11
11
10
10
ABCD
00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 8
A
B
C
D
'0''1'
X = Y =
W = Z=
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 9
• Homework: Design a 4-input (A,B,C,D) digital circuit that will give at the output:– X a logic 1 if in the binary number formed at the inputs there are more zeros than ones.– Y a logic 1 if in the binary number formed at the inputs there are less zeros than ones. – Z a logic 1 if in the binary number formed at the inputs there equal zeros and ones.
A B C
0
0
0
0
0
1
0
1
D
0
0
0 0 02 1
0 0 13 1
0 1 04 0
0 1 15 0
0 1 06 1
0 1 17 1
1 0 08 0
1 0 19 0
1 0 010 1
1 0 111 1
1 1 012 0
1 1 113 0
1 1 014 1
1 1 115 1
X = Y =
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
W = Z =
CD00
00
01
01
11
11
10
10
ABCD
00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 10
A
B
C
D
'0''1'
X = Y =
W = Z=
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 11
• Homework: Design a 4-input (A,B,C,D) digital circuit that will give at its output a binary number equal to the product of the binary numbers formed by the inputs (AB) and (CD).
A B C
0
0
0
0
0
1
0
1
D
0
0
0 0 02 1
0 0 13 1
0 1 04 0
0 1 15 0
0 1 06 1
0 1 17 1
1 0 08 0
1 0 19 0
1 0 010 1
1 0 111 1
1 1 012 0
1 1 113 0
1 1 014 1
1 1 115 1
X = Y =
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
W = Z =
CD00
00
01
01
11
11
10
10
ABCD
00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 12
A
B
C
D
'0''1'
X = Y =
W = Z=
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 13
Don’t Care Conditions
• In many application it is known in advance that some of the input combinations will never occur. These combinations are marked as “Don’t Care Conditions” and are used as either zero’s or one’s so that the application is implemented with the most simplified circuit.
• Example: Simplify the logic expression X(A,B,C,D) with the don’t care conditions d(A,B,C,D).
CD00
00
01
01
11
11
10
10
AB0 0 X 0
X 0 1 1
1 1 X 1
X 0 X 0
X = BC + ABd = (3,4,8,11,15)
X = (6,7,12,13,14)
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 14
Don’t Care Conditions: Examples
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 15
• Homework: Design a digital circuit that has as input a 1-digit Binary Coded Decimal (BCD) number. The circuit must give at its output a binary number equal to the absolute value of (2M – 5), where M is the number formed at the input.
A B C
0
0
0
0
0
1
0
1
D
0
0
0 0 02 1
0 0 13 1
0 1 04 0
0 1 15 0
0 1 06 1
0 1 17 1
1 0 08 0
1 0 19 0
1 0 010 1
1 0 111 1
1 1 012 0
1 1 113 0
1 1 014 1
1 1 115 1
X = Y =
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
W = Z =
CD00
00
01
01
11
11
10
10
ABCD
00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 16
A
B
C
D
'0''1'
X = Y =
W = Z=
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 17
A B C
0
0
0
0
0
1
0
1
D
0
0
0 0 02 1
0 0 13 1
0 1 04 0
0 1 15 0
0 1 06 1
0 1 17 1
1 0 08 0
1 0 19 0
1 0 010 1
1 0 111 1
1 1 012 0
1 1 113 0
1 1 014 1
1 1 115 1
X = Y =
CD00
00
01
01
11
11
10
10
AB
CD00
00
01
01
11
11
10
10
AB
W = Z =
CD00
00
01
01
11
11
10
10
ABCD
00
00
01
01
11
11
10
10
AB
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 18
A
B
C
D
'0''1'
X = Y =
W = Z=
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 19
Example Cell LibraryCellName
CellSchematic
NormalizedArea
TypicalInputLoad
TypicalInput-to-OutputDelay
BasicFunctionTemplates
Inverter 1.00 1.00 0.041 0.0123 SL
2NAND 1.25 1.00 0.051 0.0143 SL
2NOR 1.25 1.00 0.061 0.0183 SL
2-2 AOI 2.25 0.95 0.071 0.0193 SL
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 20
Mapping to NAND gates
• Assumptions:– Gate loading and delay are ignored
– Cell library contains an inverter and n-input NAND gates, n = 2, 3, …
– An AND, OR, inverter schematic for the circuit is available
• The mapping is accomplished by:– Replacing AND and OR symbols,
– Pushing inverters through circuit fan-out points, and
– Canceling inverter pairs
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 21
NAND Mapping Algorithm1. Replace ANDs and ORs:
2. Repeat the following pair of actions until there is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
....
.
.
....
.
.
....
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 22
NAND Mapping ExampleA
B
C
D
F
E
(a)
AB
C7
5
1
6
2
4
9
X
Y
38DE
F
(b)
AB
C
D
E
F
(d)
X
5
5
7
6Y
(c)
OI
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 23
Mapping to NOR gates
• Assumptions:– Gate loading and delay are ignored
– Cell library contains an inverter and n-input NOR gates, n = 2, 3, …
– An AND, OR, inverter schematic for the circuit is available
• The mapping is accomplished by:– Replacing AND and OR symbols,
– Pushing inverters through circuit fan-out points, and
– Canceling inverter pairs
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 24
NOR Mapping Algorithm1. Replace ANDs and ORs:
2. Repeat the following pair of actions until there is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
....
.
.
.
.
.
....
.
.
.
ACOE161 ACOE161 - Digital Logic for Computers - Frederick University 25
NOR Mapping Example
A
B
C
DE
F
(c)
F
A
B
X
C
DE
(b)
AB
C
DE
F
(a)
2
3
1
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