ACTgen Macros Reference Guideactel.kr/_actel/html/training/libero_5.0_trncd/content/... · 2003. 10. 8. · Cin Sum Cout DataA DataB Table 1-1. Port Description Port Name Size Type

ACTgen® Macros Reference Guide

Windows® and UNIX® Environments

2

Actel Corporation, Sunnyvale, CA 94086© 2003 Actel Corporation. All rights reserved.

Part Number: 5029108-9

Release: June 2003

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 7Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Your Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Arithmetic Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Array Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Adder/Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Incrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Decrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Incrementer/Decrementer . . . . . . . . . . . . . . . . . . . . . . . . 27Constant Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Advanced Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Magnitude/Equality Comparator . . . . . . . . . . . . . . . . . . . . 40Constant Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Gray Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Binary to Gray / Gray to Binary . . . . . . . . . . . . . . . . . . . . . 48

Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Table of Contents

Input Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62Bi-Directional Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . .64Tri-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67Global Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69PECL Global Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . .71PerPin FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73Dual Data Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .76Dual Data Rate FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80Logic (AND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Logic (OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82Logic (XOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Minicores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88CRC Minicore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

PLLs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96PLL for ProASICPLUS . . . . . . . . . . . . . . . . . . . . . . . . . .97Axcelerator PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Register (Storage Elements). . . . . . . . . . . . . . . . . . . . . . . . . . 106Storage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Storage Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Memory Macros for Non-Axcelerator Families . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Synchronous/Asynchronous Dual Port RAM . . . . . . . . . . . . . 120

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Table of Contents

Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Synchronous Dual Port FIFO without Flags . . . . . . . . . . . . . 131Synchronous Dual Port FIFO with Flags . . . . . . . . . . . . . . . 135FIFO Flag Controller (No RAM) . . . . . . . . . . . . . . . . . . . 143

Memory Macros for Axcelerator. . . . . . . . . . . . . . . . . . . . . . . 147Axcelerator RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Axcelerator EDAC RAM . . . . . . . . . . . . . . . . . . . . . . . 152Axcelerator FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . 153PerPin FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Memory Macros for Flash Devices . . . . . . . . . . . . . . . . . . . . . 158Synchronous/Asynchronous Dual Port RAM for Flash . . . . . . . 159Register File for Flash Devices . . . . . . . . . . . . . . . . . . . . . 161Synchronous/Asynchronous Dual Port FIFO for Flash Devices . . . 164FIFO Using Distributed Memory for Flash . . . . . . . . . . . . . . 167

Memory in Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . 170Distributed Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 176Timing for Distrubuted Memories . . . . . . . . . . . . . . . . . . . 182Using Multiple Memories in a Design . . . . . . . . . . . . . . . . . 185

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Table of Contents

6

Introduction

This guide provides descriptions of macros that you can generate using the Actel ACTgen Macro Builder software. For more information about instantiating macros, refer to the Actel HDL Coding Style Guide and the ACTgen online help.

The Actel ACTgen Macro Builder generates a large variety of commonly used functions. You can generate structural netlists in EDIF, VHDL, and Verilog. Furthermore, you can generate VHDL and Verilog behavioral models for most parameterized functions (the behavioral models may be used in a simulation environment).

Actel’s parameterized macros:

• Reduce the development time of complex functions.

• Offer a large set of implementations for each type of function.

• Offer a wide range of bit widths that provides a quick change of design definitions.

Document ConventionsThe following table describes the conventions that are used throughout this manual.

Table 1.Functional Description of Table Nomenclature

Symbol Definition

X Don’t care

1 Logical 1 or high

0 Logical 0 or low

↑ Rising edge

↓ Falling edge

Qn Value of the signal Q before the active edge of the clock

Qn+1 Value of the signal Q after the active edge of the clock

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Introduction

SymbolsEach macro symbol shows the input and output ports. Busses are highlighted with a bold line; scalar signals with a thin line. The actual symbols generated by ACTgen could look slightly different, depending on the particular CAE tool used. Some ports shown could be optional, as described in the port description tables. Default polarities are shown on the symbols.

Your CommentsActel Corporation strives to produce the highest quality online help and printed documentation. We want to help you learn about our products, so you can get your work done quickly. We welcome your feedback about this guide and our online help. Please send your comments to [email protected].

Online HelpThe Designer software comes with online help. Online help specific to each software tool is available in Libero, Designer, ACTgen, ACTmap, Silicon Expert, Silicon Explorer II, and Silicon Sculptor. Please refer to the ACTgen online help (open ACTgen and from the Help menu, select ACTgen Help) for a complete explanation of how to use the ACTgen tool.

Qn [width-1 : 0] Qn is a width-bit bus

Qn [width-1 Width-1 bit of Qn

m, n Binary pattern with width of function

Table 1.Functional Description of Table Nomenclature (Continued)

Symbol Definition

8

1Arithmetic Macros

9

Adder

Features • Parameterized word length• Optional carry-in and carry-out

signals• Multiple gate-level implementations

(speed/area tradeoffs)• Behavioral simulation model in

VHDL and Verilog

Family Support ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, eX, 500K, PA, 500K, Axcelerator

Description

Cin

Sum

Cout

DataA

DataB

Table 1-1. Port Description

Port Name Size Type Req/Opt Function

DataA WIDTH Input Req. Input Data

DataB WIDTH Input Req. Input Data

Cin 1 Input Opt. Carry-in

Sum WIDTH Output Req. Sum

Cout 1 Output Opt. Carry-out

Table 1-2. Parameter Description

Parameter Family Value Function

WIDTHa500K, PA 2-128

Word length of DataA, DataB and SumAxcelerator 2-156

Other 2-32

MAXFANOUT 500K, PA0 Automatic choice (function of WIDTH)

2-16 Manual setting of Max. Fanout

CI_POLARITY ALL 0 1 2 Carry-in polarity (active high, active low and not used)

10

Adder

The MAXFANOUT parameter enables you to perform logic replication for all Flash Adders, Subtractors, Adder/Subtractors and Accumulators. Inherently only the Sklansky algorithm generates high-fanout nets (max. fanout = WIDTH/2), so you will see effects only for this algorithm. The area increases exponentially for MAXFANOUT approaching 2 and it flattens out for higher values, as shown in Figure 1-1.

Figure 1-1. Adder Area as a Function of MAX FANOUT

Performance is not always as predictable (as shown in Figure 1-2). When you select automatic logic replication, ACTgen automatically chooses a value for MAXFANOUT based on WIDTH. This value returns a good, but not necessarily the best, result for that particular value of WIDTH.

Figure 1-2. Adder Performance as a Function of MAX FANOUT

CO_POLARITY ALL 0 1 2 Carry-out polarity (active high, active low and not used)

a. The Brent-Kung Adder extends the ranges from 32 to 128 bit for 54SX, 54SX-A and from 20 to 128 bitfor 500K



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ACTgen Macros

Table 1-3. Implementation Parameters

Parameter Family Value Description

LPMTYPE ALL LPM_ADD_SUB Adder category

LPM_HINT

500K, PA

SKADD Sklansky model

FBKADD Fast Brent-Kung model

BKADD (Compact) Brent-Kung model

ALL

FADDa Very fast carry select model

MFADDa Fast carry select model

RIPADD Ripple carry model

LPMTYPE Axcelerator LPM_FC_ADD_SUB Fast carry chain Adder category

LPM_HINT AxceleratorFC_FADD Fast carry chain selct model

FC_RIPADD Fast carry chain ripple carry model

a. FADD and MFADD are NOT recommended for Flash devices.

Table 1-4. Functional Description

DataA DataB Sum Couta

a. Cin and Cout are assumed to be active high

m[width-1 : 0] n[width-1 : 0] (m + n + Cin )[width-1 : 0] (m + n + Cin)[width]

12

Array Adder

Features • Parameterized word length and number of input buses

• DADDA tree architecture with optional Final Adder

• Optional pipeline for implementation with Final Adder

• Behavioral simulation model in VHDL and Verilog

Family Support 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description The Array-Adder implements a Sum-Function over an Array of Buses: where

In applications where designers have to add more than two operands at a time “Carry-Save- Techniques” might be used to build the final Sum. ACTgen makes these techniques available through the Array-Adder macro, which is using a Dadda tree algorithm. Usually this algorithm is more compact and faster than using Adder-trees consisting of multiple 2-operand adders, especially if the number of operands gets large and/or for large word width.

An example could be the FIR-filter architecture using a “distributed arithmetic” as described in the Application Note from September 1997 “Designing FIR Filters with Actel FPGAs.” This architecture generates a large number of partial products, which need to be summed up. Summing them up in an Adder-Tree would both be slow and area expensive. At the time of writing this document synthesis tools did not infer Multiple-Operand-Adders. Therefore making use of the Array-Adder in those types of applications might result in a significant gain in both speed and area.

The Array Adder comes with or without Final Adder. The version with Final Adder allows to instantiate a pipeline stage between the Dadda-tree and the Final Adder. The output bitwidth for Sum can be calculated using this formula:

OUTWIDTH = log2((m*exp2(n)-1)+1)

ACTgen Macros

SumA_Width

Array Adder

ARRADDP Pipelined Array Adder with Final Adder

ARRADD2 Array Adder without Final Adder

Table 1-8. Parameter Rules

Family Variation Parameter Rules

eXARRADD / ARRADDP WIDTH * SIZE

Subtractor

Features • Parameterized word length• Optional carry-in and carry-out

signals• Multiple gate-level implementations


VHDL and Verilog

Family Support ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description

Cin

Sum

Cout

DataA

DataB












Other 2-32



16

Subtractor

CI_POLARITY ALL 0 1 2 Carry-in polarity (active high, active low and not used)

CO_POLARITY ALL 0 1 2 Carry-out polarity (active high, active low and not used)

a. The Brent-Kung Subtractor extends the ranges from 32 to 128 bit for 54SX, 54SX-A and from 20 to128 bit for 500K

Table 1-10. Parameter Description (Continued)



Parameter Familiy Value Description

LPMTYPE ALL LPM_ADD_SUB Subtracter category

LPM_HINT

500K, PA

SKSUB Sklansky model

FBKSUB Fast Brent-Kung model

BKSUB (Compact) Brent-Kung model

ALL

FSUBa Very fast carry select model

MFSUBa Fast carry select model

RIPSUB Ripple carry model

LPMTYPE Axcelerator LPM_FC_ADD_SUB Fast carry chain Subtractor category

LPM_HINT AxceleratorFC_FSUB Fast carry chain selct model

FC_RIPSUB Fast carry chain ripple carry model

a. FSUB and MFSUB are not recommended for Flash devices.


DataA DataB Sum Couta

a. Cin and Cout are assumed to be active high

m[width-1 : 0] n[width-1 : 0] (m - n - Cin) [width-1 : 0] (m - n - Cin)[width]

17

Adder/Subtractor

Features • Parameterized word length• Optional carry-in and carry-out signals• Mulitiple gate-level implementations


VHDL and Verilog


Description

Cin

Sum

Cout

DataA

DataB

Addsub








Addsub 1 Input Req. Addition (AddSub = 1) or subtraction (Addsub = 0)





Other 2-32



CI_POLARITY ALL 0 1 2 Carry-in polarity (active high, active low, and not used)

18

Adder/Subtractor

CO_POLARITY ALL 0 1 2 Carry-out polarity (active high, active low, and not used)

a. The Brent-Kung Adder/Subtractor extends the ranges from 32 to 128 bit for 54SX, 54SX-A and from20 to 128 bit for 500K





LPMTYPE ALL LPM_ADD_SUB Adder/Subtracter category

LPM_HINT

500K, PA

SKADDSUB Sklansky model

FBKADDSUB Fast Brent-Kung model

BKADDSUB (Compact) Brent-Kung model

ALL

FADDSUBa

a. FADDSUB and MFADSUBB are not recommended for Flash devices.

Very fast carry select model

MFADDSUBa Fast carry select model

RIPADDSUB Ripple carry model


LPM_HINT AxceleratorFC_FADDSUB Fast carry chain selct model

FC_RIPADDSUB Fast carry chain ripple carry model


DataA DataB Addsub Sum Couta

m[width-1 : 0] n[width-1 : 0] (m + n + Cin )[width-1 : 0] (m + n + Cin)[width] m[width-1 : 0]

m[width-1 : 0] n[width-1 : 0] (m - n - Cin) [width-1 : 0] (m - n - Cin)[width] m[width-1 : 0]

a. Cin and Cout are assumed to be active high here.

19

Accumulator

Features • Parameterized word length• Optional carry-in and carry-out signals• Asynchronous reset• Accumulator enable• Multiple gate-level implementations


VHDL and Verilog

Family Support ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, eX, PA, 500K, Axcelerator

Description

DataA

Cin

Enable

Clock

Sum

Cout

Aclr







Enable 1 Input Opt Enable

Clock 1 Input Req. Clock

Aclr 1 Input Opt Asynchronous Reset

20

Accumulator





Other 2-32



CI_POLARITY ALL 0 1 2 Carry-in polarity (active high, active low, and not used)

CO_POLARITY ALL 0 1 2 Carry-out polarity (active high, active low, and not used)

CLR_POLARITY ALL 0 1 2 Asynchronous reset (active high, active low, and not used)

EN_POLARITY ALL 0 1 2 Accumulator enable (active high, active low, and not used)

FFTYPEb ALL except Flash REGULAR TMR FF type used (Regular, Triple Voting)

CLK_EDGE ALL RISE FALL Active High/Low

a. The Brent-Kung Accumulator extends the ranges from 32 to 128 bit for 54SX, 54SX-A and from 20 to 128 bit for 500K b. TMR is Triple Module Redundancy. Choosing this option makes ACTgen use TMR FlipFlops that are used to avoidSingle Event Upsets (SEUs) for Rad-hard Designs. Choosing this option causes the Sequential resource usage to be tripledin families where no TMR is implemented in Silicon.

Table 1-19. Fan-in Control Parameters

Parameter Value

CLR_FANIN AUTO MANUAL

CLR_VAL [default value for AUTO is 8, 1 for MANUAL]

EN_FANIN AUTO MANUAL

EN_VAL [default value for AUTO is 6, 1 for MANUAL]

CLK_FANIN AUTO MANUAL

CLK_VAL [default value for AUTO is 8, 1 for MANUAL]

21

ACTgen Macros



LPMTYPE LPM_ADD_SUB Accumulator category

LPM_HINT

500K, PA

SKACC Sklansky model

FBKACC Fast Brent-Kung model

BKACC (Compact) Brent-Kung model

ALL

FACCa

a. The FACC and MACC parameters are not recommended for Flash devices.

Very fast carry select model

MFACCa Fast carry select model

RIPACC Ripple carry model


LPM_HINT AxceleratorFC_FACC Fast carry chain selct model

FC_RIPACC Fast carry chain ripple carry model


DataA Sumn+1 Couta

a. Cin and Cout are assumed to be active high.

m[width-1 : 0] (m + Sumn + Cin )[width-1 : 0] (m + Sumn + Cin)[width]

22

Incrementer

Features • Parameterized word length• Optional Carry-out signals• One very fast gate level

implementation, FC High Speed and FC Ripple available


Family Support ACT 2/1200XL, ACT 3, 3200DX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Acelerator

Description

Sum

Cout

DataA

1







Parameter Value Function

WIDTH 2-322-156 for FC Macros Word length of DataA and Sum

CO_POLARITY 0 1 2 Carry-out polarity (active high, active low, and not used)

23

ACTgen Macros


Parameter Value Description

LPMTYPE LPM_ADD_SUB Incrementer category

LPM_HINT FINC; FC_FINC, FC_RIPINC Very fast carry look ahead


DataA Sum Cout

m m + 1 (m + 1) ≥ 2width

24

Decrementer




Family Support ACT 2/1200XL, ACT 3, 3200DX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description

Sum

Cout

DataA

1








WIDTH2-322-156 for FC_FDEC and FC_RIPDEC

Word length of DataA and Sum


25

ACTgen Macros



LPMTYPE LPM_ADD_SUB Decrementer category

LPM_HINT FDECFC_FDEC and FC_RIPDEC, Fast Carry Versions Very fast carry look ahead


DataA DataB Sum Cout

m n m - 1 (m-1) < 0

26

Incrementer/Decrementer





Description

Sum

Cout

DataA

1

Incdec






Incdec 1 Input Req. Increment (Incdec = 1) or decrement (Incdec = 0)



WIDTH2-322-156 for FC_FINCDEC and FC_RIPINCDEC

Word length of DataA and Sum


27

ACTgen Macros



LPMTYPE LPM_ADD_SUB Incrementer/Decrementer category

LPM_HINTFINCDECFC_FINCDEC FC_RIPINCDEC

Very fast carry look ahead


DataA Incdec Sum Cout

m 1 m + 1 (m + 1) ≥ 2width

m 0 m - 1 (m - 1) < 0

28

Constant Multiplier

Features • Parameterized word lengths and constant values

• Unsigned and signed (two’s complement) data representation

• Booth / Wallace architecture• Behavioral simulation model (for non-

pipelined multiplier only) in VHDL and Verilog

Family Support 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description The Constant Multiplier performs the multiplication of a data-input with a constant value. Area and performance of the Constant Multiplier depend on the value of the constant. Specifically, area and performance depend on the number of groups of 1's in the bit pattern of the constant. As a result, the worst-case constant has a bit pattern of alternating 1's and 0's (…010101…). However, even for that worst case the area and performance of the Constant Multiplier is superior to a regular Multiplier.

The Constant Multiplier macro output word length is always double the input word length. Depending on the value of the constant, some of the most significant bits might be sign-extension bits. You may be able to reduce hardware by calculating the actual number of bits needed and cutting all sign-extension bits. For example:

width =4, Constant = 1100, representation=signed

The worst case data for this example would be 1000 (-8) and therefore the worst case output data would be 010 0000 (-8 * -4 = 32). So with that we know, that Mult is just a sign-extension bit (Mult = Mult).

Keep in mind that some constant multiplications might be generated even more effectively, e.g. constants to the power of 2 are just shift-operations, or constants like 3,5,7,9,10, etc. can be generated using shift operations and a simple addition/subtraction (2+1, 4+1, 8-1, 8+1, 8+2, etc.). For these constants the implementation of the Constant Multiplier might not be as efficient as using shift operations and/or Adders/Subtractors.

Mult

DataA

Constant

29

ACTgen Macros

Usually synthesis infers regular Multipliers even for constant values. Therefore the use of the Constant Multiplier macro in a design, which performs one or more multiplications with constant values, is expected to be very beneficial.

An application example might be FIR-filters with constant coefficients, were the computation is organized in the “transposed form” as indicated in Figure 1-3.

Figure 1-3. FIR-filter Organized in the "Transposed Form" Using Constant Multipliers



Data WIDTH Input Req. Input data

Mult 2*WIDTH Output Req. Constant * Data



WIDTHa

a. For eX WIDTH is supported from 2-11

2-64 Word length Data

CONST Constant Constant value

RADIX HEX BIN DEC Radix for constant value

SIGNb

b. For signed constant multiplier

0 1 Positive, negative constant sign

C4

Din

C3 C2 C1 C0

Dout

30

Constant Multiplier

Parameter Rules:

1. DataA is always binary and of the size of Width.

2. Constant must be of the selected Radix and be of the selected width for HEX/BIN. ACTgen automatically pads zeroes if they are missing.

e.g.: Radix: BIN, Width: 5, Constant: 00010 Radix Hex, Width:8, Constant: 0A



LPMTYPE LPM_MULT Constant multiplier category

LPM_HINT UCMULT Unsigned constant multiplier

SCMULT Signed constant multiplier

31

Multiplier

Features • Parameterized word lengths• Unsigned and signed (two’s

complement) data representation• Booth or array implementation• Optional pipelining• Behavioral simulation model in

VHDL and Verilog

Family Support ACT 2/1200XL, ACT 3, 3200DX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Axcelerator1

Description

Mult

DataA

DataB

1. For more information on the Fast Carry Chain macros available with the Axcelerator family, please refer to “Fast Carry Chains (Axcelerator Only)” on page 20.



DataA WIDTHA Input Req. Input data

DataB WIDTHB Input Req. Input data

Clock 1 Input Opt. Clock

Mult WIDTHA+WIDTHB Output Opt. DataA*DataB

Mult0 WIDTHA+WIDTHB Output Opt. Mult0 + Mult1 = DataA*DataBMult1 WIDTHA+WIDTHB Output Opt.

32

Multiplier



WIDTHAa

a. For some of the multiplier variations there are small deviations from the limitsmentioned to ensure that the multiplier fits in the largest device of the selected family.

500K, PA, Axcelerator 2-64

Word length of DataAeX 2-14

Other 2-30

WIDTHB Same as WIDTHA Word length of DataB

REPRESENTATION UNSIGNED SIGNED Data representation

FFTYPEb

b. TMR: Triple Module Redundancy. Choosing this option makes ACTgen use TMRFlipFlops which are used to avoid Single Event Upsets (SEUs) for Rad-hard Designs.Choosing this option causes the Sequential resource usage to be tripled in families whereno TMR is implemented in Silicon.

CC: When combinatorial option is chosen for the Sequential Type, the FF is implementedusing two Combinatorial Cells instead of one Sequential Cell. This is useful when noSequential resources are available in the designs.

This option is applicable only to the pipelined multipliers.

ALL except Flash

REGULAR TMRCC

FF Type Used (Default, Triple Vot-ing, Combinatorial)

CLK_EDGE RISE FALL Clock (if pipelined)


DataA DataB Mult1a

m n m * n

33

ACTgen Macros

a. If pipelined, the sum is correct (available) after cycles. Latency is a function ofWIDTHA and WIDTHB, or the number of pipelined stages mentioned specifically (eg. 1 or2 pipelines).


DataA DataB Mult0/1a

a. Mult1 is always 0

m n Mult1 + Mult2 = m * n

Table 1-41. Parameter Rulesa

Family Variation Parameter rules

All All WIDTHA ≥ WIDTHB

eX

BOOTHMULT/P WIDTHA + WIDTHB

Multiplier

a. These are the most important parameter rules; additional rules may apply



LPMTYPE LPM_MULT Multiplier category

LPM_HINT

BOOTHMULT Booth multiplier

BOOTHMULT2a Booth multiplier without final Adder

BOOTHMULTP Pipelined booth multiplier

LPMTYPE

LPM_FC_MULT Fast Carry multiplier category (Axcelerator)b

PARRAYMULTFast Carry array multipliers in parallel; each array multiplier consists of a 1-bit multiplier (MULT1); the rows of the array use fast carry chains, but there is a regular routing between columns

BOOTHMULT1 Booth-encoded Wallace-tree with Fast Carry final adder

BOOTHMULT2 Booth-encoded multiplier with n-bit Fast Carry adder tree

a. Available for 54SX, 54SX-A, eX, 500K & PA

b. For information on multiplier area and performance please refer to the latest Actel application note available athttp://www.actel.com

Table 1-43. Axcelerator Multiplier Architecture Comparison Speeda

Architecture \ Speed

1 (fastest) 2 3 (slowest)

Parallel-2 Array Multiplier width

ACTgen Macros

Advanced OptionsClick the Advanced button (available for PA, 500K, and Axcelerator devices) to specify pipeline stages. If you are using a PA or 500K device, you can insert (default setting) or omit the final Adder stage.

Omitting the Final Adder

You can choose not to instantiate the final adder in the multiplier and add up the two buses Mult0 and Mult1 to the final result later in the design flow. This is often the most efficient implementation when a lot of partial results get summed up in a large summation network. Figure 1-4 shows an example for Y = (A x B) + C + D using the multiplier with 2 outputs in combination with the Array-Adder.

Figure 1-4. Efficient implementation using the 2-output multiplier in combination with the Array-Adder

Table 1-44. Axcelerator Multiplier Architecture Comparison: Area

Architecture \ Speed 1 (smallest) 2 3 (largest)

Parallel-2 Array Multiplier always

FC Booth-1 always

FC Booth-2 always

Mult1

Mult0

DataA

DataB Y

Data0

Data1

Data2

Data3

Sum

A

B

CD

36

Multiplier

Multiplier Pipelining

For 500K, PA and Axcelerator devices you can specify the number of pipeline stages (1, 2, or 3). However, three pipeline stages increases performance only for high bitwidth. Click the Advanced button in the GUI to access pipelining.

For ACT 2/1200XL, ACT 3, 3200DX, 42MX, 54SX, 54SX-A, eX the multiplier architecture does not allow you to select the latency of the pipelined multiplier or the number of logic levels between the pipeline stages. Registers are automatically inserted between the major components of the architecture, primarily the multiplexer and adder macros, as shown in Figure 1-5.

Figure 1-5. Booth Multiplier Architecture (Pipeline)

Table 1-45. Pipeline Stages

Pipeline StagesWidthB

w/ Final Adder w/o Final Adder

1 >= 2 >= 5

2 >= 5 >= 7

3 >= 7 Not applicable

GND

co1

co0

DataB [0] DataB [1]

DataB [2] DataB [3]

DataB [4] DataB [5]

Mux4[widtha+2]

Mux4[widtha+2]

Mux4[widtha+2]

Adder[widtha+1]

Adder[widtha+2]

Adder[widtha+2]

Product[widtha+5:4]

Product [3:2]

Product [1:0]

aux3 [widtha+1:0]

aux3 [widtha+1:2]

0.co1.aux3 [widtha+1:2]

aux1 [widtha+1:0]

aux0 [widtha+1:0]

0.0.aux0 [widtha+1:2]

aux1 [widtha+1:0]

aux1 [widtha+1:0]

DataA [n-1:0]

DataA [n-2:0].0

aux1 [widtha+1:0]

Register

37

ACTgen Macros

The number of pipeline stages is a function of the width of the DataB input. The number of logic levels per pipeline stage is a function of the width of the DataA input. Therefore, the number of logic levels per pipeline stage is equal to the number of logic levels of the first adder (WIDTHA + 1) plus 1 for the 4 to 1 multiplexer, as shown in Figure 1-5.

Table 1-46. Pipeline Stages as a Function of WidthB

WidthB Range Pipeline Stages

2 0

3-4 1

5-8 2

9-16 3

Table 1-47. Logic Levels as a Function of WidthA

WidthA Range Logic Levels

2-5 3

6-17 4

18-30 5

38

2Comparators

39

Magnitude/Equality Comparator

Features • Parameterized word length• Unsigned and signed (two’s

complement) data comparison • One very fast gate level

implementation• Behavioral simulation model in

VHDL and Verilog

Family Support1 ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description

DataA

DataB

AGBAGEBALBALEB

>><<

_

_

1. For Flash devices the Equality Comparator and the Magnitude Comparator are separate. For all other devices they are the same macro. There is a Fast Carry Magnitude Comparator available for Axcelerator.



DataA WIDTH Input Req. Input data

DataB WIDTH Input Req. Input data

AGB 1 Output Opt. Output comparison; A > B

AGEB 1 Output Opt. Output comparison; A ≥ B

ALB 1 Output Opt. Output comparison; A < B

ALEB 1 Output Opt. Output comparison; A ≤ B

AEB 1 Output Opt. Output comparison; A = B

ANEB 1 Output Opt. Output comparison; A ≠ B

40

Magnitude/Equality Comparator



WIDTH 2-32 Word length of DataA and DataB

REPRESENTATION UNSIGNED SIGNED

AGB_POLARITY 0 1 2 AGB polarity (active high, active low, and not used)

AGEB_POLARITY 0 1 2 AGEB polarity (active high, active low, and not used)

ALB_POLARITY 0 1 2 ALB polarity (active high, active low, and not used)

ALEB_POLARITY 0 1 2 ALEB polarity (active high, active low, and not used)

AEB_POLARITY 0 1 2 AEB polarity (active high, active low, and not used)

ANEB_POLARITY 0 1 2 ANEB polarity (active high, active low, and not used)



LPMTYPELPM_COMPARE Comparator category

LPM_FC_COMPARE Fast Comparator Category

LPM_HINTCOMPARE Very fast carry select

FC_MAGCOMP Very fast Magnitude Comparator


Parameter Rules

At lease one of the comparisons (AGB, AGEB, ALB, ALEB, AEB or ANEB) must be selected

41

ACTgen Macros

Only one of the magnitude comparisons (AGB, AGEB, ALB or ALEB) can be selected at the same time

Only one of the equality comparisons (AEB or ANEB) can be selected at the same time


DataA DataB AGB AGEB ALB ALEB AEB ANEB

m n m > n m ≥ n m < n m ≤ n m = n m ≠ n


Implementation (LPM_HINT) Description

COMPARE Very fast carry select model

FC_MAGCOMP Very fast Magnitude Comparator


Parameter rules

At least one of the comparisons (AGB, AGEB, ALB, ALEB, AEB or ANEB) must be selected

Only one of the magnitude comparisons (AGB, AGEB, ALB or ALEB) can be selected at the same time

Only one of the equality comparisons (AEB or ANEB) can be selected at the same time

Table 2-4. Parameter Rules (Continued)

Parameter Rules

42

Constant Decoder

Features • Parameterized word length• DEC/BIN/HEX radices for

constant• Equal/Not Equal comparison


Description

Aeb

DataA

Constant




Aeb 1 Output Req. Result



WIDTH 2-32a

a. For Flash devices, width is 2-128

Word length of DataA and Constant

Radix Dec/Bin/Hex Base of Constant

ConstantSame as Width in selected Radix

The value with which input data will be compared

AEB_POLARITY 0, 1 A equals B polarity (Active High, Active Low)

43

ACTgen Macros

Parameter Rules:

1. DataA is always binary and of the size of Width.

2. Constant must be of the selected Radix and be of the selected width for HEX/BIN.

e.g.: Radix: BIN, Width: 5, Constant: 00010 Radix Hex, Width:8, Constant: 0A



LPM_TYPE LPM_COMPARE Comparator category

LPM_HINT WDEC Very fast


Aeb

DataA = Constant

44

3Converters

45

Gray Counter

Features • Parameterized for Data Width • Asynchronous Clear,

Asynchronous Preset

Family support 54SX, Axcelerator

Description ACTgen can generate Gray Counters parameterized for a specified Data Width and with a choice of Enable, Asynchronous Clear, and Asynchronous Preset signals.

ENABLE Q

CLOCK

CLR

PRE



Clock WIDTH Input Req. Input Data

Q WIDTH Output Req. Output Data

Clr 1 Input Opt. Clear

Pre 1 Input Opt. Preset

Enable 1 Input Opt. Enable

46

Gray Counter



GRAYCOUNT 2-99 Output Data Width

CLR_POLARITY 0,1,2 Clear Polarity

PRE_POLARITY 0,1,2 Preset Polarity

EN_POLARITY 0,1 Enable Polarity

CLK_EDGE RISE,FALL Clock Edge



LPMTYPE LPM_GRAY COUNTER Gray Counter

47

Binary to Gray / Gray to Binary

Features • Parameterized for Data Width

Family support 54SX, Axcelerator

Description ACTgen can generate Binary to Gray and Gray to Binary Converters parameterized for a specified Data Width.

Datain Dataout



Datain WIDTH Input Req. Input Data

Dataout WIDTH Output Req. Output Data



GRAYDECODE/WIDTH 2-99 Input/Output Data Width



LPMTYPE LPM_GRAYENCODE/ LPMGRAYDECODE Binary to Gray and Gray to Binary Converter

48

4Counters

49

Binary Counter

Features • Parameterized word length• Up, Down and Up/Down

architectures• Asynchronous clear• Asynchronous preset (available only

for Flash devices)• Synchronous counter load• Synchronous count enable• Terminal count flag (not available

for Axcelerator) • Multiple gate level

implementations (area/speed tradeoffs)



Description The ACTgen binary counters are general purpose UP, DOWN, or UP/DOWN (direction) counters.

When the count value equals 2width-1, the signal Tcnt (terminal count), if used, is asserted high.

The counters are WIDTH bits wide and have 2width states from “000…0” to “111…1”. The counters are clocked on the rising (RISE) or falling (FALL) edge of the clock signal Clock (CLK_EDGE).

The Clear signal (CLR_POLARITY), active low or high, provides an asynchronous reset of the counter to “000…0”. You may choose to not implement the reset function.

In the case of an Up/Down counter, the Updown signal controls whether the counter counts up (Updown = 1) or down (Updown = 0).

The counter could be loaded with Data. The Sload signal (LD_POLARITY), active high or low, provides a synchronous load

Data

Updown

Enable

Clock

Q

Tcnt

Aclr

Sload

50

Binary Counter

operation with respect to the clock signal Clock. You can choose to not implement this function.

The ACTgen counters have a count enable signal Enable (EN_POLARITY). Enable can be active high or low. When Enable is not active, the counter is disabled and the internal state is unchanged.


Port Name Size Type

Req./Opt. Function

Data WIDTH input Opt. Counter load input

Aclr 1 input Opt. Asynchronous counter reset

Enable 1 input Req. Counter enable

Sload 1 input Opt. Synchronous counter load

Clock 1 input Req. Clock

Updown 1 input Opt. UP (Updown = 1), DOWN (Updown = 0)

Q WIDTH out-put Req. Counter output bus

Tcnt 1 out-put Opt. Terminal count (active high)



WIDTH 2-32 Word length of Data and Q

DIRECTION UP DOWN UPDOWN Counter direction

CLR_POLARITY 0 1 2 Aclr can be active low, active high or not used

EN_POLARITY 0 1 Enable can be active low, active high

51

ACTgen Macros

LD_POLARITY 0 1 2 Sload can be active low, active high or not used

CLK_EDGE RISE FALL

TCNT_POLARITY 1 2 Tcnt can be active high or not used

Table 4-3. Fan-in Control Parameters

Parameter Value

CLR_FANIN AUTO MANUAL

CLR_VAL [default value for AUTO is 8, 1 for MANUAL]

LD_FANIN AUTO MANUAL

LD_VAL [default value for AUTO is 6, 1 for MANUAL]

CLK_FANIN AUTO MANUAL

CLK_VAL [default value for AUTO is 8, 1 for MANUAL]


Parameter Value Description Family

LPMTYPE LPM_COUNTER Counter category

LPM_HINT LLCNT Prescaled model All

TLACNT Register look ahead model All

FBCNT Fast Balanced model 54SX, 54SX-A

BCNT Balanced model All

LECNT Fast Enable Balanced All

COMPCNT Compact model All

RIPPLE Ripple model All



52

Binary Counter

Implementations This section decribes the implementation of the Pre-Scaled Counter, Register Look Ahead Counter, Fast Balanced Counter and the Balanced Counter.

Pre-Scaled Counter

The pre-scaled counter achieves absolute maximum count and count enable performance by sacrificing synchronous load performance. This counter registers the two least significant bits and uses them as an enable for the upper bits. Count performance is limited only by the delay in the lower two bits and the enable path for the upper bits. Because the upper bits are only updated (enabled) every fourth cycle, they can accommodate more delay (up to one-fourth the clock frequency).

There are two limitations related to the use of the pre-scaled counter. The first is in analyzing the actual performance of the counter. The second is correctly performing data load functions; these two limitations are related. Two parameters must be measured to overcome these two limitations. The first parameter that must be measured is the worst internal delay inside the counter. The second parameter is the worst delay from Q0/Q1 to any upper bit. The minimum count period is then defined by the greater value of these two parameters.

Table 4-5. Functional Descriptiona

a. Assume Aclr is active low, Enable is active high, Sload is active high, Clock is rising, Tcnt isactive high

Data Aclr Enable Sload Clock Up down Qn+1 Tcnt n+1

X 0 X X X X 0’s 0

X 1 X X ↑ X Qn Qn+1== 2width-1

X 1 0 0 ↑ X Qn Qn+1== 2width-1

m 1 X 1 ↑ X m Qn+1== 2width-1

X 1 1 0 ↑ 1 Qn + 1 Qn+1== 2width-1

X 1 1 0 ↑ 0 Qn - 1 Qn+1== 2width-1

53

ACTgen Macros

The load function is a slave of the maximum internal path delay in the pre-scaled counter. The load function must be held for as many clock periods as required to exceed the maximum internal delay; this ensures that all internal nodes are settled and that correct count operation can be performed. This requirement can be waived if you can guarantee that 0’s will always be loaded in Q0 and Q1 (resulting in only a single load cycle).

The count path in pre-scaled counters without Sload or Enable functions only have a single logic level for ACT 2/1200XL, ACT 3, 3200DX, 42MX 54SX, 54SX-A, and eX. All other combinations of pre-scaled counters have two logic levels in their count path. In these cases, given the two limitations mentioned previously related to the pre-scaled counter, use the Register Look Ahead or Fast Balanced counters.

Register Look Ahead Counter

This counter achieves the absolute maximum performance for the count, count enable, and synchronous load functions. The counter operates by registering intermediate count values providing “look-ahead” carry circuitry. As a result, this counter variation requires more flip-flops (sequential modules) than other counters.

Fast Balanced Counter

This counter is only available for the 54SX, 54SX-A, and eX families. It takes advantage of the architectural features of these families, including flip-flops with built-in enable and more powerful combinatorial cells. Using these two features, it is possible to build a very fast and compact binary counter without using “look-ahead” carry circuitry. This counter should be preferred over all the others available for this family.

Balanced Counter

This counter achieves high performance for both the count and enable functions using standard design approaches. Module count performance is sacrificed to maintain high speed. This counter is the result of the performance balance between the count/enable functions and the balance between the performance/cost in building this architecture. This counter should address most counter needs for the ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX and 42MX families.

54

Binary Counter

Fast Enable Counter

This compact counter is fully synchronous and has higher performance than the ripple counter. However, this counter should only be used in moderate performance applications, especially for large widths.

Ripple Counter

The ripple counter is an asynchronous counter where the Q of each bit feeds the clock of the next bit; performance is sacrificed to build this variation. However, the ripple counter uses the least amount of logic resources. This counter should only be used in very low-performance applications or for very small counters.

Because of the asynchronous nature of the count function, this counter does not have a synchronous load function.

55

5Decoder

56

Decoder

Features • Parameterized output size (DECODES)


Family Support ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40 MX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description

Enable

EqData



Data declna

a. decln is an integer and log2 (DECODES) = decln d

ACTgen Macros


a. Assume enable is active low and Eq is active high.

Data Enable Eq

X 0 0’s

m 1 decb (m)==decodes-1 &&c dec(m)==decodes-2 && … &&

dec(m)==0

b. dec(m) defines the decimal value of m

c. && indicates bity concatenation

58

6IOs

59

Input Buffers

Features • Parameterized for data width• Choice of data buffers (Regular, Special, Pull-Up, Pull-Down)

Family support ACT2/1200XL, ACT3, 3200DX, 42MX, 54SX, 54SX-A, eX, 500K, PA, Axcelerator

Description ACTgen generates different types of Input Buffers with specified data width.



PAD WIDTH Input Req. Input Data

PADP (LVDS and LVPECL, Axcelera-tor Only)

WIDTH Input Req. Input Data for LVDS and LVPECL

PADN(LVDS and LVPECL, Axcelera-tor Only)

WIDTH Input Req. Input Data for LVDS and LVPECL

Y WIDTH Output Req. Output Data



WIDTH 1-99 (Limit may vary depending on the family) Data Width

60

Input Buffers

PULLUP (Flash Only) NO / YES Choice of Pull-up version

VOLT (Flash Only) 0,1,2 Choice of different volt-age levels. 3.3v, 2.5v or 2.5v(Low Power)

TYPE (Axcelerator Only)

REG, LVCMOS25, LVCMOS18, LVCMOS15, PCI, PCIX, GTLP25, GTLP33, HSTL_I, HSTL_II, SSTL3_I, SSTL3_II, SSTL2_I, SSTL2_II, LVDS, LVPECL, LVCMOS25U, LVCMOS25D, LVCMOS18U, LVCMOS18D, LVCMOS15U, LVCMOS15D.

Type of Buffer



LPMTYPE LPM_IO/ LPM_IB_IO (Flash) Input Buffers

LPM_HINT

INBUF / IB (Flash) Regular Input Buffers

INBUF_SP (Axcelerator Only) Special Input Buffers

INBUF_PU (Axcelerator Only) Pull-up Input Buffers

INBUF_PD (Axcelerator Only) Pull-down Input Buffers



61

Output Buffers

Features • Parameterized for data width• Choice of buffers (Regular, Special)


Description ACTgen generates different types of Output Buffers with specified data width.



Data/A (Flash) WIDTH Input Req. Input Data

PAD WIDTH Output Req. Output Data




VOLT (Flash Only) 0,1,2,3,4,5

Choice of different voltage levels. 3.3v(PCI), 3.3v & Low Strength, 2.5v & High Strength, 2.5v & Low Strength, 2.5v(Low Power) & High Strength, or 2.5v(Low Power) & Low Strength

62

Output Buffers

SLEW 0,1,2 Choice of different slew rates. Low, Normal or High


REG, S_8, S_12, S_16, S_24, F_8, F_12, F_16, F_24, LVCMOS25, LVCMOS18, LVCMOS15, PCI, PCIX, GTLP25, GTLP33, HSTL_I, HSTL_II, SSTL3_I, SSTL3_II, SSTL2_I, SSTL2_II, LVDS, LVPECL.

Type of Buffer Note : "S" in S_* denotes Low Slew Rate and "F" in F_* denotes High Slew Rate. Also 8,12,16,24 denote Output drive strengths of 1x, 2x, 3x, 4x respectively



LPMTYPE LPM_IO / LPM_OB_IO (Flash) Output Buffers

LPM_HINTOUTBUF / OB (Flash) Regular Output Buffers

OUTBUF_SP (Axcelerator Only) Special Output Buffers



63

Bi-Directional Buffers

Features • Parameterized for data width• Choice of buffers (Regular, Special, Pull-up, Pull-down)





PAD WIDTH Inout Req. Inout Data

Data / A (Flash) WIDTH Input Req. Input Data

Trien / ENABLE (Flash) 1 Input Req. Enable





64

Bi-Directional Buffers


Choice of different voltage levels. 3.3v(PCI), 3.3v & Low Strength, 2.5v & High Strength, 2.5v & Low Strength, 2.5v(Low Power) & High Strength, or 2.5v(Low Power) & Low Strength

SLEW (Flash Only) 0,1,2 Choice of the slew rates: Low, Normal, or High

PULLUP NO / YES Choice of Pull up version

TRIEN_POLARITY / EN_POLARITY (Flash)

0,1 Enable Polarity


REG, S_8, S_12, S_16, S_24, F_8, F_12, F_16, F_24, LVCMOS25, LVCMOS18, LVCMOS15, PCI, PCIX, GTLP25, GTLP33, S_8U, S_12U, S_16U, S_24U, F_8U, F_12U, F_16U, F_24U, S_8D, S_12D, S_16D, S_24D, F_8D, F_12D, F_16D, F_24D, LVCMOS25U, LVCMOS25D, LVCMOS18U, LVCMOS18D, LVCMOS15U, LVCMOS15D, HSTL_I, SSTL2_I, SSTL2_II, SSTL3_I, SSTL3_II

Type of Buffer. Note : "S" in S_* denotes Low Slew Rage and "F" in F_* denotes High Slew Rate. Also 8,12,16,24 denote Output drive strengths of 1x, 2x, 3x, 4x respec-tively



LPMTYPE LPM_IO / LPM_IOB_IO Bi-directional Buffers



65

ACTgen Macros

LPM_HINT

BIBUF / IOB, GLMIOB (Flash)

Regular Bi-directional Buffers / IO pad with Global Connection, Two Multiplexed Pads & Global Con-nection (Flash)

BIBUF_SP (Axcelerator Only) Special Bi-directional Buffers

BIBUF_PU (Axcelerator Only) Pull-up Bi-directional Buffers

BIBUF_PD (Axcelerator Only) Pull-down Bi-directional Buffers

Table 6-9. Implementation Parameters (Continued)


66

Tri-State Buffers

Features • Parameterized for data width• Choice of buffers (Regular, Special, Pull-up, Pull-down)





PAD WIDTH Inout Req. Inout Data

Data / A (Flash) WIDTH Input Req. Input Data

Trien / ENABLE (Flash) 1 Input Req. Enable





Choice of different voltage levels. 3.3v (PCI), 3.3v & Low Strength, 2.5v & High Strength, 2.5v & Low Strength, 2.5v (Low Power) & High Strength, or 2.5v (Low Power) & Low Strength

67

ACTgen Macros

SLEW (Flash Only) 0,1,2 Choice of the slew rates: Low, Normal, or High

TRIEN_POLARITY / EN_POLARITY (Flash)

0,1 Enable Polarity


REG, S_8, S_12, S_16, S_24, F_8, F_12, F_16, F_24, LVCMOS25, LVCMOS18, LVCMOS15, PCI, PCIX, GTLP25, GTLP33, S_8U, S_12U, S_16U, S_24U, F_8U, F_12U, F_16U, F_24U, S_8D, S_12D, S_16D, S_24D, F_8D, F_12D, F_16D, F_24D, LVCMOS25U, LVCMOS25D, LVCMOS18U, LVCMOS18D, LVCMOS15U, LVCMOS15D, HSTL_I, SSTL2_I, SSTL2_II, SSTL3_I, SSTL3_II

Type of Buffer. Note : "S" in S_* denotes Low Slew Rage and "F" in F_* denotes High Slew Rate. Also 8,12,16,24 denote Output drive strengths of 1x, 2x, 3x, 4x respectively



LPMTYPE LPM_IO / LPM_OB_IO Tri-State buffers

LPM_HINT

TRIBUFF / OTB (Flash) Regular Tri-State Buffers

TRIBUFF_SP (Axcelerator Only) Special Tri-State Buffers

TRIBUFF_PU (Axcelerator Only) Pull-up Tri-State Buffers

TRIBUFF_PD (Axcelerator Only) Pull-down Tri-State Buffers



68

Global Buffers

Features • Parameterized for data width• Choice of buffers (Regular, Multiplexed, Internal Driver)

Family support 500K, PA




PAD WIDTH Input Req. Inout Data

A WIDTH Input Req. Input Data

ENABLE 1 Input Req. Enable

GL 1 Output Req. Output Data




WIDTH 1-499 (Limit may vary depending on the type) Data Width

VOLT 0,1,2 Choice of different voltage levels: 3.3V, 2.5V, 2.5V (Low Power)

PULLUP NO / YES Choice of Pull-up version

69

ACTgen Macros



LPMTYPE LPM_GL_IO All buffers

LPM_HINT

GL Standard Global buffer

GLIB Standard Global buffer w/ an Input bufer

GLMIB Standard Global buffer with Multiplexed Input buffer

GLINT Global internal driver

70

PECL Global Buffers

Features • Parameterized for data width• Choice of buffers (Direct to Global, Multiplexed with Internal Signal)

Family support PA




PECLIN WIDTH Input Req. Input Data

PECLREF WIDTH Input Req. Reference Data

A WIDTH Input Req. Input Data

ENABLE 1 Input Req. Enable

GL WIDTH Output Req. Output Data




WIDTH 1-2 Data Width

71

ACTgen Macros



LPMTYPE LPM_GLPE_IO PECL Global buffers

LPM_HINTGLPE Direct to Global

GLPEMIB Multiplexed with Internal Signal

72

PerPin FIFO

Features • Parameterized for Data Width and almost Full/Empty Values.

• Choice of generating with Input or Output pads

• Choice of generating with or without a Controller

• Choice of Dedicated or Core Logiccontroller

• Asynchronou, or synchronous write

• Rising edge triggered or level sensitive

• Supported netlist formats: VHDL and Verilog

Family support Axcelerator

Description ACTgen can generate Input or Output PerPin FIFOs with or without a Controller parameterized depending on the 'Width' parameter.

When generating PerPin FIFOs with a Controller, you can specify almost full (AfVal) and almost empty (AeVal) values in the GUI. You can choose two types of controllers: either an Embedded PerPin FIFO controller or one that is generated using core logic.

The maximum number of PerPin FIFOs that a single Embedded controller can control is 26. ACTgen restricts generation of PerPin FIFOs with Embedded Controllers to a Max. Width of 26. The number of PerPin FIFOs that can be controlled using the core logic controller depends entirely on the available resources and PerPin FIFOs in the chip, hence there is no restriction on the core logic controller option. AeVal and AfVal accept any value between 1 and 63.

An I/O FIFO Embedded controller can support upto 26 PerPin FIFOs depending on the die size and the location of the PerPin FIFO on the die.

DATA

WE

RE

Q

FULL

AFULL

EMPTY

AEMPTYRClock

CLR

WClock

WithController

Option

73

ACTgen Macros

Please note that if more than 26 PerPin FIFOs are to be used, there will be 2 separate set of flags from each Embedded PerPin FIFO controller.



DATA WIDTH Input Req. Input Data

Q WIDTH Output Req. Output Data

WE 1 Input Req. Write Enable

RE 1 Input Req. Read Enable

Rclock 1 Input Req. Read Clock

WClock 1 Input Req. Write Clock

CLR 1 Input Req. Clear Signal

FULL 1 Output Opt. Full Flag

AFULL 1 Output Opt. Almost Full Flag

EMPTY 1 Output Opt. Empty Flag

AEMPTY 1 Output Opt. Almost Empty Flag



WIDTH

2-26 Data Width with Dedicated Controller

1-128 Data Width without a Controller or with Core Logic Controller

AEVAL 0-62 For Almost Empty Value Flag

AFVAL 1-63 For Almost Full Value Flag

74

PerPin FIFO

CTL 0,1 Dedicated or Core Logic Controller

PORT* Optional - Can be used if port name needs to be changed



LPMTYPE

LPM_IOFIFO_I_NC Input IOFIFO with no Controller

LPM_IOFIFO_O_NC Output IOFIFO with no Controller

LPM_IOFIFO_I_C Input IOFIFO with Controller

LPM_IOFIFO_O_C Output IOFIFO with Controller

LPM_HINT

IR, ISP, IPU, IPD, ILV Input IOFIFO - With Regular, Special, Pull up, Pull down input buffers

OR_NC, OSP_NC, OLV_NC

Output IOFIFO - With Regular, Special, LVDS/LVPECL output buffers

IR_C, ISP_C, IPU_C, IPD_C, ILV_C

Input IOFIFO - With Regular, Special, Pull up, Pull down input buffers

OR_C, OSP_C, OLV_C

Output IOFIFO - With Regular, Special, LVDS/LVPECL output buffers



75

Dual Data Rate Register

Features • Parameterized for Data Width and almost Full/Empty Values

• Choice of Input buffers


Description ACTgen can generate Dual Data Rate Registers parameterized for a specific Data Width and with a choice of the type of Input Buffers.

PAD PRE

E

QR

QF

CLK

CLR




QR WIDTH Output Req. Output Data

QF WIDTH Output Req. Ouput Data

E 1 Input Req. Enable

CLK 1 Input Req. Clock

CLR 1 Input Req. Clear

PRE 1 Output Req. Preset

76

Dual Data Rate Register



WIDTH 1-128 Data Width

DDR 0,1 0 for DDR Register and 1 for DDR FIFO



LPMTYPE LPM_DDR DDR Register / FIFO category

LPM_HINT

DDR DDR Register with Regular Input buffers

DDR_SP DDR Register with Special Input buffers

DDR_PU DDR Register with Pull-up Input buffers

DDR_PD DDR Register with Pull-down Input buffers

77

Dual Data Rate FIFO

Features • Parameterized for Data Width • Choice of Input buffers


Description ACTgen can generate Dual Data Rate FIFOs parameterized for specified Data Width and with a choice of Input Buffers.

RE

RCLK

WD

WE

QR

QF

WCLK

CLR

FULL

AFULL

EMPTY

AEMPTY

WithController

Option




QR WIDTH Output Req. Output Data

QF WIDTH Output Req. Ouput Data

REN 1 Input Req. Read Enable

WEN 1 Input Req. Write Enable

RCLK 1 Input Req. Read Clock

WCLK 1 Input Req. Write Clock

CLR 1 Input Req. Clear

FULL 1 Input Opt. Full Flag

AFULL 1 Input Opt. Almost Full Flag

EMPTY 1 Input Opt. Empty Flag

78

Dual Data Rate FIFO

AEMPTY 1 Input Req. Almost Empty Flag



WIDTH2-26 Data Width with Dedicated Controller

1-128 Data Width without a Controller or with Core Logic Controller

AEVAL 1-63 For Almost Empty Value Flag

AFVAL 1-63 For Almost Full Value Flag

CTL 0,1 Dedicated or Core Logic Controller

DDR 1 1 for DDR FIFO



LPMTYPE LPM_DDR DDR FIFO category

LPM_HINT

DDRF/DDR DDR FIFO with Regular Input buffers; note that the ‘F’ denotes ‘with controller’

DDRF_SP/DDR_SP DDR_FIFO with Special Input buffers

DDRF_PU/DDR_PU DDR FIFO with Pull-up Input buffers

DDRF_PD/DDR_PD DDR FIFO with Pull-down Input buffers

Table 6-25. Port Description (Continued)


79

7Logic

80

Logic (AND)

Features • Parameterized AND size• Behavioral simulation model in

VHDL and Verilog

Family Support ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, eX, 500K, PA

Description

Data Result



Data SIZE input Req. Input data

Result 1 output Req. output



SIZE 2-64 Word length of data

RESULT_POLARITY 0 1 Output polarity (active low or active high)


a. result is active; highresult is active high

Data Result

m m[0] and m[1] and … and m[SIZE-1]

81

Logic (OR)

Features • Parameterized OR size• Behavioral simulation model in

VHDL and Verilog


Description

Data Result



Data SIZE input Req. input data







a. result is active high

Data Result

m m[0] or m[1] or … or m[SIZE-1]

82

Logic (XOR)

Features • Parameterized XOR size• Behavioral simulation model in

VHDL and Verilog


Description

Data Result



Data SIZE input Req. input data







a. result is active high

Data Result

m m[0] xor m[1] xor … xor m[SIZE-1]

83

8Multiplexer

84

Multiplexer

Features • Parameterized word length• Parameterized multiplexer input

number• Behavioral simulation model in

VHDL and Verilog


Description

Data Result

SEL



Data0_port WIDTH Input Req. Input data

Data1_port WIDTH Input Req. Input data

… … … … …

DataSIZE-1_port WIDTH Input Req. Input data

Sel0 1 Input Req. Select line

Sel1 1 Input Req. Select line

… … … … …

SelSIZELN-1 1 Input Req. Select line

Result WIDTH Output Req. output



WIDTHAPA, 500K 1-48

Word length of DataAll Others 1-32

SIZE All 2-32 Number of data inputs

85

ACTgen Macros


Data0 Data1 … DataSIZE-1 Sel0 Sel1 … SelSIZELN-1 Result

m0 m1 … mSIZE-1 0 0 … 0 m0

m0 m1 … mSIZE-1 1 0 … 0 m1

… … … … … … … … …

m0 m1 … mSIZE-1 1 1 … 1 mSIZE-1

86

9Minicores

87

FIR Filter

Features • Variable input data width: 2 to16 bit input data

• Variable output data width: 3 to 64 bit output data

• Support for up to 64 taps

• Support of symmetric coefficients

• Optional IO insertion

• Optional registers for filter in- and output

• Verilog RTL model for simulation

• VHDL RTL model for synthesis1

Family support 54SX, 54SX-A, 500K, PA, Axcelerate

Design Flow An overview of the design flow required for the FIR filter is shown in Figure 9-1.

Figure 9-1. FIR Filter Design Flow

1. Synthesized filter designs are usually slower, but more compact.

Data Qout

Aclr

Clock

System LevelDesign Tool

ACTgen

Designer

.gen File w/ Implementation

Parameters

FIR.edn

TOP.ednFPGA

88

FIR Filter

Generate the filter coefficients and other implementation parameters using a system level design tool (like Matlab). This information is made available for ACTgen in form of a .gen file. .

From that point on it follows the regular design flow as described in the Actel Quick Start Guide.

Description The ACTgen FIR-filter macro supports symmetric, high-speed, parallel FIR-filters with up to 64 time taps.

Figure 9-2. Tap Transposed from FIR Filter

The architecture is a variation of the "transposed form" of the FIR-filter as shown in Figure 9-2, making use of ACTgen's signed Constant Multiplier. The data is assumed to be signed. Data- and coefficient widths are the same (D_WIDTH).

Figure 9-2 suggests that coefficients with a value of 0 are desirable for this type of architecture, since they will not generate any multiplication hardware. "Halfband" filters are trying to maximize the number of 0-coefficients and might result in significant area savings over regular filters of the same order .

* * * * *C0C1C2C3C4

Data

Qout

89

ACTgen Macros

The output width O_WIDTH has no impact on the filter size. Internally, ACTgen always uses the maximum precision filter, unless specified otherwise using the internal precision parameter PREC. If you set O_WIDTH to 0, ACTgen usese the maximum output resolution (MAX_RES). For values of O_WIDTH greater than MAX_RES the result is sign-extended. For values of


Port Name Size Type Req/Opt? Function

Data D_WIDTH input Req. Input Data

Clock 1 input Req. Filter clock

Aclr 1 input Opt. Asynchronous Clear

Qout O_WIDTH input Req. Filter output = Σ χι * δι



D_WIDTH 3 .. 16 Input Data Width

O_WIDTH 3 .. 64 Output Data Width

TAPS 3 .. 64 Number of time taps

CLK_EDGE RISE FALL Clock sensitivity

CLR_POLA 2 0 1 None, active high, active low

PREC Internal precision

INSERT_PAD NO YES Pad insertion

INSERT_IOREG NO YES Register inputs and outputs

C1 … C32 0 .. 2C_WIDTH 2's complement coefficients (integers)

90

FIR Filter

O_WIDTH smaller than MAX_RES ACTgen cuts some of the lower bits. An upper estimate for MAX_RES is

For example a 12-tap filter with 8-bit data and coefficients might yield up to (8 + 8 + 4 ) bit = 20 bit output resolution.

The coefficients C1 to C16 are positive integers, which will be interpreted as two's complement numbers. That means 0 to 2C_WIDTH-1-1 are considered positive, and 2C_WIDTH-1 to 2C_WIDTH-1 will be interpreted as negative numbers.

Only unique coefficients need to be specified properly, all other coefficients need to be set to any value, e.g. "0". An N-tap filter requires (N / 2) + (N % 2) unique coefficients.

Only unique coefficients need to be specified properly, all other coefficients need to be set to any value, e.g. "0". An N-tap filter requires (N / 2) + (N % 2) unique coefficients.


Family Variation Parameter rules

All FIR2 PREC >= O_WIDTH

54SX, 54SX-A All O_WIDTH

ACTgen Macros

Internal Precision (PREC) specifies the minimum number of bits

• For the time tab registers

• From multiplier outputs kept for further processing

• From adder outputs kept for further processing

Currently the RTL-model does not reflect the PREC parameter, so there may be differences between the simulated output of the structural netlist and the RTL-model for the low-order bits.

Integer Values Coefficient File

The Integer Values Coefficient File consists of the conversion of the quantized coefficients into regular integers. This file can be directly imported into ACTgen.

Table 9-5. Internal Precision (PREC)

Variation Value Description

Basic Options 97, 0 Maximum output resolution, same as O_WIDTH

Advanced Options PREC See parameter rules

Table 9-6. Sample Integer Coefficient File

20482037048204818920630102663001892204848020372048

92

CRC Minicore

Features • General-purpose cyclic redundancy Code generator• Fully synchronous, single clock operation (over 100 MHZ for many

configurations)

• Parameterized arbitrary polynomial (from 1 up to 64-bit)

• Parameterized data input width

• Parameterized register initialization

• Parameterized bit and byte ordering

• Parameterized bit pattern for CRC output XOR with

Family support SX, Axcelerator

Description CRC Minicore is a universal Cyclic Redundancy Check (CRC) Polynomial generator that validates data frames and ensures data integrity during data transmission.

To meet different application requirementa, CRC minicore provides many different configuration parameters. These parameters include Data Width, Register Initialization, and CRC output data characteristics.

• Data width specifies the number of bits upon which CRC Minicore generates the CRC value in a single clock cycle. For example, 8 bit data width CRC32 performs CRC calculations on 8 bit per clock.

• Register Initialization provides the seed value for CRC generation.

• CRC data characteristics parameters provide designers great flexibility of CRC data characteristics.

Thus, the parameter of CRC output XOR bit pattern controls how the CRC value is inverted before it is injected into the data stream. Although CRC Minicore generator (ACTgen) provides seven commonly used CRC polynomials, it does provide polynomial parameters (size and value) for any other generic CRC creation. The polynomial size can span from 1-bit to 64-bit.

93

ACTgen Macros

Table 9-7. XOROUT Configuration

XOROUT Description

1 All bits are not inverted (000000000) xor CRC

2 All bits are inverted (..FFFFFFFF) xor CRC

3 Even bits are inverted, odd bits are not inverted (….10101010) xor CRC

4 Odd bits are inverted, even bits are not inverted (….01010101) xor CRC

Table 9-8. CRC Operation Control

rst_n init_n enable Description

0 x x A synchronous reset, set to initial register value

1 0 x Synchronous initialize

1 1 0 Disable, register maintain the current value

1 1 1 Generate CRC on the input data


Port Name width Description

CLK 1 Clock port

rst_n 1 Asynchronous reset

init_n 1 Synchronous load CRC value

enable 1 CRC enable/disable control

data_in Data_width Input data word

CRC_in Poly_size CRC value to be load in

94

CRC Minicore

CRC_out Poly_size Generated CRC value

Table 9-10. Standard CRC Generator Parameters - Description

Name Poly_width Poly_value (HEX) initial xorout

CRC32 32 04C11DB7 FFFF.. FFFFFF....

CRC16/ARC 16 1005 FFFF... FFFFF....

CCIT CRC16 16 1021 FFFF…. FFFFFF….

CANBUS 16 4599 FFFFF... FFFFF....

ATM CRC10 10 233 FFFFF... FFFFF....

ATM CRC8 8 7 FFFF…. FFFFF..….

kermit 16 8408 000000… 000000000

Table 9-9. Port Description (Continued)

Port Name width Description

95

10PLLs

96

PLL for ProASICPLUS

You can use ACTgen to configure PLLs according to your needs, and generate a netlist that has a PLL primitive instantiated with the correct specified configuration

Features • Clock Delay Adjustment• Clock Frequency Synthesis

• Clock Phase Shifting

Family Support PA

Parameter Description



CLKS 1 2 Primary or Both outputs

FIN 1.5 - 240 MHz Input Frequency

PRIMFREQ 1.5 - 240 MHz Primary Output Frequency

PDELAYVAL 0 - 8 ns Primary Delay value, in steps of .25 ns

PDELAYSIGN 0 1 Positive or Negative primary delay

PPHASESHIFT 0 90 180 270 Primary Phase-shift

PBYPASS 0 1 No Yes. Primary Bypass

FIN2 1.5 - 240 MHz Secondary Input Frequency, Only if PLL is bypassed for Secondary Output

SECFREQ 1.5 - 240 MHz Primary Output Frequency

SDELAYVAL 0 - 8 ns Primary Delay value, in steps of 0.25 nsa

SDELAYSIGN 0 1 Positive or Negative primary delay

SPHASESHIFT 0 90 180 270 Primary Phase-shift

SBYPASS 0 1 No Yes. Primary Bypass

97

ACTgen Macros

Summary of the menu items available when you generate a PLL for ProASICPLUS.

Configuration - Dynamic or Static Configuration

In dynamic mode, designers are able to set all the configuration parameters using either the external JTAG port or an internally-defined serial interface. The dynamic-mode PLL can be switched to static mode during operation by just changing a mode selection bit. This way you can have one stable static configuration, yet for selected sequences of events, you can switch to dynamic mode and run the clock at a different frequency if required. For the Dynamic mode, ACTgen is used to specify a stable default configuration.

Input Clock Frequency - Floating point value between 6.0 and 240 MHz

Primary Clock Frequency - Floating point value between 6.0 and 240 MHz. If the specified frequency cannot be achieved, the closest approximate frequency is provided. There are some restrictions on the possible values of this frequency even in the specified range, based on the PLLCORE limitations. ACTgen takes all these limitations into consideration when generating a PLL. If the specified frequency cannot be achieved, the closest approximate frequency will be provided..

Bypass PLL in Primary Clock - Selecting this checkbox bypasses the PLL for the primary clock. This feature enables you to bypass the PLLCORE functionality and use the surrounding divider and delay elements. When the PLL is bypassed, the primary clock frequency must be equal to or be 1/2, 1/3 or ¼ of input frequency, as only a divider is available in the output path.

FBInternal DeskewedExternal

Feedback

CONF STATIC DYNAMIC Configuration

a. In the GUI, the delay is entered directly as a value between -3.75 and +3.75 without breakingit into sign and value



98

PLL for ProASICPLUS

Primary Clock Phase Shift - Supports 4 values 0, 90, 180, 270 degrees. Not valid when PLL is bypassed for primary clock. The secondary clock cannot be phase-shifted.

Primary Clock Delay - This is a floating point between -4.0 and 8.0 with increments of 0.25. When PLL is bypassed for primary clock, only 0, 0.25, 0.5 and 4 ns are valid delays.

Secondary Clock Input Frequency - Floating point value between 1.5 and 240 MHz. This is valid only when secondary clock is selected and PLL is bypassed.

Secondary Clock Output Frequency - Floating point value between 1.5 and 240 MHz. This is valid only when secondary clock is selected. If the specified value cannot be achieved, the closest approximate frequency will be provided.

Bypass PLL in Secondary clock - Selecting this checkbox bypasses the PLL for secondary clock. When the PLL is bypassed, the secondary clock frequency must be equal to or be 1/2, 1/3 or ¼ of secondary input frequency. This feature allows the user to bypass the PLLCORE functionality and use the surrounding divider and delay elements.

Secondary Clock Delay - This is a floating point between -4.0 and 8.0 with increments of 0.25. When PLL is bypassed for secondary clock, only 0, 0.25, 0.5 and 4 ns are the valid delays.

Feedback - A radio button to select between Internal, External and Deskewed feedback.

The clock-conditioning circuitry enables you to implement the feedback clock signal using either the output of the PLL, an internally generated clock, or an external clock. When external feedback is selected, an additional port EXTFB is made available to the user to drive the feedback . The internal feedback signal can be further delayed by a fixed amount designed to emulate the delay through the chip’s clock tree. This allows for clock-line de-skewing operations. This

99

ACTgen Macros

delay is included in the feedback path when deskewed feedback is chosen. This value is dependent on the device you are using.

For more detailed information on the various features of the APA PLL, please refer to Using

Documents

ACTgen Macros Reference Guideactel.kr/_actel/html/training/libero_5.0_trncd/content/... · 2003. 10. 8. · Cin Sum Cout DataA DataB Table 1-1. Port Description Port Name Size Type