Actuation Electronics For (Near) Future Detectors

Actuation Electronics For Actuation Electronics For (Near) Future Detectors(Near) Future Detectors

Alberto [email protected]

Cascina, June 9th 2005 A.Gennai (INFN Pisa) 2

IntroductionIntroduction The VIRGO Suspensions are complex

mechanical structures used to insulate optical elements from seismic noise. The structure, described by an 80 vibrational modes model, is controlled by 18 coil-magnet pairs commanded with two distinct Digital Signal Processors operating at 10 kHz sampling frequency. The suspension status is observed using 20 local sensors plus optional 3 global sensors.

The new control system foresees multi-DSP computing units, faster and higher resolution analog-to-digital and digital-to-analog converters and high dynamic power driver for coil-magnet pair actuators.


Last Stage ActuatorsLast Stage Actuators

Last stage actuators play a fundamental role applying forces directly on test masses.

This talk concentrates on two key aspects of actuators electronics:– Dynamical range– Electro-Magnetic

Immunity


VIRGO Suspension Control UnitVIRGO Suspension Control Unit 2 x Motorola PowerPC-based CPU

boards 2 x Motorola DSP96002-based boards 60 Analog I/O channels 4 Digital optical point-to-point links

(LAPP Annecy) CCD Camera Interface (LAPP Annecy)

10 kHz Sampling 16 (14.5 eff.) bits ADC 20 (17.5 eff.) bits DAC About 100 poles for each DSP


Actuators Electronics Dynamical RangeActuators Electronics Dynamical Range Power amplifiers used to drive coil-

magnet pair actuators steering VIRGO optical elements need a wide dynamical range:– Big force impulse required for acquiring the

lock of VIRGO optical cavities– Low noise during linear regime.

The rms value of correction signal decreases while sensitivity approaches VIRGO goal curve:– Need of a flexible solution able to easily adapt

to sensitivity changes without limiting control signal dynamics


The use of a Digital to Analog converter to drive actuators electronics limits the actuator dynamic.

At present in VIRGO we use 20 bit DAC – Vmax = 10 V– Vnoise = 300 nV/Hz1/2

New VIRGO coil driver shall supply– Imax = 2 A– Inoise = 3 pA/Hz1/2

LCoil3mH

1

2

RCoil10

Ref. Mass Coil

+

-

OUT

R2

R

R1R

Coil Driver

DAC

10-1

100

101

102

103

10-20

10-15

10-10

10-5

Actuators noise: current status

Frequency (Hz)

m/H

z1/2

Reference Mass - Mirror Actuators NoiseFilter #7 - Marionetta Actuators NoiseVIRGO Sentivity


New Coil DriversNew Coil Drivers

A new coil driver was designed using two distinct sections: – high power section for lock acquisition– low noise section for linear regime.

The two sections are driven by two independent digital-to-analog converter channels.


New Coil Driver: Basic OperationNew Coil Driver: Basic Operation Dynamical range extension is

obtained using two DAC channels.1. DAC #1 is used during

lock acquisition phase (2A current). During this phase DAC #2 is set to zero.

2. DAC #1 is then set to zero and simultaneously DAC #2 is activated

3. High power section is disconnected from coil actuator

LCoil3mH

1

2

RCoil10

Ref. Mass Coil

+

-

OUT

R2

R

R1R

Coil Driver

DAC 2RN

500

DAC 1Transconductance Amplifier


DAC Noise ContributionDAC Noise Contribution

100

101

102

103

10-21

10-20

10-19

10-18

10-17

10-16

10-15

10-14

10-13

10-12

Frequency (Hz)

PS

D (

m/s

qrt(

Hz)

)

VIRGO Goal SensitivityCoil Driver with 26 kOhm series resistorCoil Driver with 4 kOhm resistor + De-Emphasis filter

Simulated data

10

New Coil Driver: Block DiagramNew Coil Driver: Block Diagram For each actuator three distinct section are available (one

High Power plus two Low Noise). The High Power section is a transconductive amplifier able

to supply up to 2 A into the coil while the two Low Noise sections are voltage amplifiers with series resistor

The three sections architecture will allow switching from lock acquisition to linear lock regime in two (or more) steps.

High PowerSection

Low Noise Section #1


Analog IN #1

Analog IN #2

ControlSectionSerial Link

Low Noise Coil Current

Monitor

High PowerCoil Current

Monitor

Analog OUT #2

Analog OUT #1Coil

• Sections switch• Gain selection• De-enphasis filtering• Monitor configuration

High PowerSection

High PowerSection

Low Noise Section #1Low Noise Section #1

Low Noise Section #2Low Noise Section #2

Analog IN #1Analog IN #1

Analog IN #2Analog IN #2

ControlSectionControlSectionSerial LinkSerial Link


Monitor


Monitor


Monitor


Monitor

Analog OUT #2Analog OUT #2

Analog OUT #1Analog OUT #1CoilCoil

• Sections switch• Gain selection• De-enphasis filtering• Monitor configuration

Prototype (installed at terminal towers)Prototype (installed at terminal towers)

0 10 20 30 40 50 60-8

-6

-4

-2

0

2

4

6

8

Time (s ec)

Cur

rent

Mon

itor

Coil UpCoil DownSwitch

Time

0 10 20 30 40 50 60-8

-6

-4

-2

0

2

4

6

8

Time (s ec)

Cur

rent

Mon

itor

Coil UpCoil DownSwitch

Time

0 10 20 30 40 50 601.94

1.95

1.96

1.97

1.98

1.99

2

2.01

2.02

2.03

2.04x 10

-4

Time (sec)

Tra

nsm

itted

Pow

er


Experimental ResultsExperimental Results

100

101

102

103

104

10-6

10-5

10-4

10-3

10-2

10-1

100

Frequency (Hz)

PS

D (

V/s

qrt(

Hz)

)

High Power GPS 778606100Low Noise GPS 778606730High Power GPS 778606970Low Noise GPS 778607600

200 A/V

Current monitoring noise

DAC noise floor

DAC noise floor with new coil driver

100

101

102

103

104

10-6

10-5

100

101

102

103

104

10-6

10-5

10-4

10-3

10-2

10-1

100

10-4

10-3

10-2

10-1

100

Frequency (Hz)

PS

D (

V/s

qrt(

Hz)

)

High Power GPS 778606100Low Noise GPS 778606730High Power GPS 778606970Low Noise GPS 778607600

200 A/V

Current monitoring noise

DAC noise floor

DAC noise floor with new coil driver

Bad EMI due to bad PCB


Electro-Magnetic ImmunityElectro-Magnetic Immunity

Power Supply– Only linear power supply is allowed. Supply

shall be separated from analog circuits. A star grounding scheme shall be adopted.

PCB – Multi-layer circuit boards with signal lines

sandwiched between ground planes. – …

Circuits Shielding– Analog and digital circuits shall be separated

with independent Faraday shielding.– Shielded crates shall be utilized

External Wiring


EMI – External WiringEMI – External Wiring Each coil driver is connected

via a 30 meters long Shielded Twisted Pair (STP) cable to the digital to analog converter (DAC) board.

To improve EMI/EMC, digital to analog and analog to digital converters, shall be made available on-board.

Processing nodes shall be connected to front end electronics using galvanically isolated wiring with optical or RF couplers


Coil Drivers: Digital I/OCoil Drivers: Digital I/O

High Power Section



Digital IN

Control Section

Serial Link


Monitor

High Power Coil Current

Monitor

Digital OUT

Coil

• Sections switch• Gain selection • De-enphasis filtering• Monitor configuration

DAC

ADC

10 Mb/sec digital data electrically isolated

Digital IF

DAC

ADC


Digital I/ODigital I/O Several devices shall be connected to the

same serial line therefore selected communication protocol shall support multipoint (multiplex) transmission mode where multiple transmitters and receivers share the same line.

A single fiber optic link shall provide the connectivity between front end electronics and processing nodes.

IEEE 1394b-2002 standard will be adopted for physical layer


Facing “Control Noise”Facing “Control Noise” In addition to standard noise sources, a

new contribution, referred as “Control Noise”, is becoming more and more relevant

Control noise is the noise injected into the system by non optimal design of control algorithms often due to limited online computing resources

To face this problem we decided to drastically increase the computation power of processing units


Multiprocessor DSP Board: Main FeaturesMultiprocessor DSP Board: Main Features 6 x 100 MHz ADSP211160N SHARC DSP 3.4 GigaFLOPS 1800 MB/s of low latency inter processor

communication bandwidth 512 MB SDRAM 64-bit 66 MHz PCI bus On board 32-bit Master-Slave PCI to DSP Local

Bus bridge 256 kWord real Dual Port memory (PCI – DSP LB) VME to PCI Master – Slave bridge DSP LB to VSB bridge for I/O devices access 200 MB/s auxiliary I/O bandwidth 2 x Altera EP1C4 Cyclone FPGA Compact size: PMC standard (149 x 74 mm)


MDSPAS – Top ViewMDSPAS – Top View

DSP

1

234

5 6

AM

FPGA

B

Dual Port Memory


MDSPAS – Bottom ViewMDSPAS – Bottom View

SDRAM

PCI 64 – 66 MHz

VSBbusI/O TimDOL


How use 3.2 GFLOPS? How use 3.2 GFLOPS?

Digital Feedback Design in VIRGO– Usual specifications:

“Use high loop gain over some frequency range then decrease the gain as rapidly as possible”

– Classical Design Methods (SISO)• Discrete-time controllers derived from

continuous-time controllers (indirect design techniques)

– Design a continuous-time controller and then obtain the corresponding discrete-time controller using a transformation from G(s) to G(z).


Feedback Design MethodsFeedback Design Methods Classical Design Methods (SISO)

– Root locus method– Nyquist techniques (design based on frequency response)– PID Controller design methods

• Transient response method• Stability limit method

State Space Design Methods (SISO – MIMO)– Pole Placement– Optimal Control - LQG Methods– H-Infinity– ...

Adaptive Control– Model Reference adaptive control – Self-tuning regulators– …

Additional computational power will allow implementing MIMO and adaptive controllers, with major advantages from the so called “control noise” point of view


ConclusionsConclusions

Improving VIRGO sensitivity at low frequency requires huge dynamical range actuators electronics

Dynamical range can be improved using different hardware configurations for lock acquisition and linear lock phases

A good “stand-alone” device can easily become a bad one once installed. Special care shall be devoted to devices interconnections and EMI

Use of “clever” control algorithm

Documents

Actuation Electronics For (Near) Future Detectors