REV. 0

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices.

aAD8019

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

DSL Line Driverwith Power-Down

PIN CONFIGURATIONS

8

7

6

5

1

2

3

4

AD8019AR

–IN1

OUT1

OUT2

+IN1

–VS

+VS

–IN2

+IN2

14

13

12

11

10

9

8

1

2

3

4

5

6

7

AD8019ARU

NC = NO CONNECT

DGND

NC

PWDN

NC

NC

NC

OUT1

–IN1

+IN1

–VS

OUT2

+VS

–IN2

+IN2

FEATURES

Low Distortion, High Output Current Amplifiers

Operate from 12 V to 12 V Power Supplies,

Ideal for High-Performance ADSL CPE, and xDSL

Modems

Low Power Operation

9 mA/Amp (Typ) Supply Current

Digital (1-Bit) Power-Down

Voltage Feedback Amplifiers

Low Distortion

Out-of-Band SFDR –80 dBc @ 100 kHz into 100 Line

High Speed

175 MHz Bandwidth (–3 dB), G = +1

400 V/s Slew Rate

High Dynamic Range

VOUT to within 1.2 V of Power Supply

APPLICATIONS

ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI,

PCMCIA Modems, and Customer Premise Equipment

(CPE)

PRODUCT DESCRIPTIONThe AD8019 is a low cost xDSL line driver optimized to drive aminimum of 13 dBm into a 100 Ω load while delivering outstand-ing distortion performance. The AD8019 is designed on a 24 Vhigh-speed bipolar process enabling the use of ± 12 V powersupplies or 12 V only. When operating from a single 12 V sup-ply the highly efficient amplifier architecture can typically deliver170 mA output current into low impedance loads through a1:2 turns ratio transformer. Hybrid designs using ±12 V suppliesenable the use of a 1:1 turns ratio transformer, minimizing attenu-ation of the receive signal. The AD8019 typically draws 9 mA/amplifier quiescent current. A 1-bit digital power down featurereduces the quiescent current to approximately 1.6 mA/amplifier.

Figure 1 shows typical Out of Band SFDR performance underADSL CPE (upstream) conditions. SFDR is measured whiledriving a 13 dBm ADSL DMT signal into a 100 Ω line with50 Ω back termination.

The AD8019 comes in thermally enhanced 8-lead SOIC and14-lead TSSOP packages. The 8-lead SOIC is pin-compatiblewith the AD8017 12 V line driver.

FREQUENCY – kHz132.5

10d

B/D

IV

137.5 142.5

–80dBc

Figure 1. Out-of-Band SFDR; VS = ±12 V; 13 dBm OutputPower into 200 Ω, Upstream

8-Lead SOIC(R-8)

14-Lead TSSOP(RU-14)

OBSOLETE

REV. 0–2–

AD8019–SPECIFICATIONSParameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE–3 dB Bandwidth G = +5 35 MHz

G = +1, VOUT < 0.4 V p-p, RL = 100 Ω 175 180 MHzG = +2, VOUT < 0.4 V p-p, RL = 100 Ω 70 75 MHz

0.1 dB Bandwidth VOUT < 0.4 V p-p, RL = 100 Ω 6 MHzG = +5, VOUT < 0.4 V p-p, RL = 100 Ω 35 MHz

Large Signal Bandwidth VOUT = 4 V p-p 50 MHzSlew Rate Noninverting, VOUT = 4 V p-p 450 V/µsRise and Fall Time Noninverting, VOUT = 2 V p-p 5.5 nsSettling Time 0.1%, VOUT = 2 V p-p 40 ns

NOISE/DISTORTION PERFORMANCEDistortion VOUT = 3 V p-p (Differential)

Second Harmonic 100 kHz, RL(DM) = 50 Ω –78 dBc500 kHz, RL(DM) = 50 Ω –74 dBc

Third Harmonic 100 kHz, RL(DM) = 50 Ω –85 dBc500 kHz, RL(DM) = 50 Ω –80 dBc

Out-of-Band SFDR 144 kHz–1.1 MHz, Differential RL = 70 Ω –80 dBcMTPR 25 kHz–138 kHz, Differential RL = 70 Ω –72 dBcInput Voltage Noise f = 100 kHz 8 nV/√HzInput Current Noise f = 100 kHz 0.9 pA√HzCrosstalk f = 1 MHz, G = +2 –80 dB

DC PERFORMANCEInput Offset Voltage 8 20 mV

TMIN–TMAX 10 23 mVInput Offset Voltage Match 1 12 mV

TMIN–TMAX 2 17 mVOpen-Loop Gain VOUT = 6 V p-p, RL = 25 Ω 72 80 dB

TMIN–TMAX 72 80 dB

INPUT CHARACTERISTICSInput Resistance 10 MΩInput Capacitance 0.5 pF+Input Bias Current –3 +1 +3 µA

TMIN–TMAX –4 +4 µA–Input Bias Current –1.5 –0.5 +1.5 µA

TMIN–TMAX –1.8 +1.8 µA+Input Bias Current Match –1.0 –0.2 +1.0 µA

TMIN–TMAX –1.5 +1.5 µA–Input Bias Current Match –0.5 +0.1 +0.5 µA

TMIN–TMAX –0.8 +0.8 µACMRR ∆VCM = –4 V to +4 V 71 74 dBInput CM Voltage Range 2 10 V

OUTPUT CHARACTERISTICSOutput Resistance 0.2 ΩOutput Voltage Swing RL = 25 Ω –4.8 +4.8 VOutput Current SFDR –80 dBc into 25 Ω at 100 kHz 175 200 mAShort Circuit Current1 400 mA

POWER SUPPLYSupply Current/Amp PWDN = 5 V 9 10.5 mA

TMIN–TMAX 14.5 mAPWDN = 0 V 0.8 2.0 mA

Operating Range Dual Supply ±4.0 ±6.0 VPower Supply Rejection Ratio ∆±VS = +1.0 V to –1.0 V 65 68 dB

LOGIC LEVELS VPWDN = 0 V to 3 V; VIN = 10 MHz, G = +5tON 120 nstOFF 80 nsPWDN = “1” Voltage 1.8 +VS VPWDN = “0” Voltage 0.5 VPWDN = “1” Bias Current 220 µAPWDN = “0” Bias Current –100 µA

NOTES1This device is protected from overheating during a short-circuit by a thermal shutdown circuit.

Specifications subject to change without notice.

(@ 25C, VS = 12 V, RL = 25 , RF = 500 , TMIN = –40C, TMAX = +85C, unlessotherwise noted.)

OBSOLETE

REV. 0 –3–

AD8019

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE–3 dB Bandwidth G = +5 35 MHz

G = +1, VOUT < 0.4 V p-p 175 180 MHzG = +2, VOUT < 0.4 V p-p 70 75 MHz

0.1 dB Bandwidth VOUT < 0.4 V p-p 5.5 MHzLarge Signal Bandwidth VOUT = 4 V p-p 50 MHzSlew Rate Noninverting, VOUT = 4 V p-p 400 V/µsRise and Fall Time Noninverting, VOUT = 2 V p-p 5.5 nsSettling Time 0.1%, VOUT = 2 V p-p 40 ns

NOISE/DISTORTION PERFORMANCEDistortion VOUT = 16 V p-p (Differential)

Second Harmonic 100 kHz, RL(DM) = 200 Ω –80 dBc500 kHz, RL(DM) = 200 Ω –72 dBc

Third Harmonic 100 kHz, RL(DM) = 200 Ω –85 dBc500 kHz, RL(DM) = 200 Ω –80 dBc

Out-of-Band SFDR 144 kHz–500 kHz, Differential RL = 200 Ω –80 dBcMTPR 25 kHz–138 kHz, Differential RL = 200 Ω –73 dBcInput Voltage Noise f = 100 kHz 8 nV/√HzInput Current Noise f = 100 kHz 0.9 pA√HzCrosstalk f = 1 MHz, G = +2 –85 dB

DC PERFORMANCEInput Offset Voltage 5 20 mV

TMIN–TMAX 10 mVInput Offset Voltage Match 1 12 mV

TMIN–TMAX 2 18 mVOpen-Loop Gain VOUT = 18 V p-p, RL = 100 Ω 86 92 dB

TMIN–TMAX 90 dB

INPUT CHARACTERISTICSInput Resistance 10 MΩInput Capacitance 0.5 pF+Input Bias Current –3 –0.5 +3 µA

TMIN–TMAX –3.8 +3.8 µA–Input Bias Current –1.5 –0.2 +1.5 µA

TMIN–TMAX –1.7 +1.7 µA+Input Bias Current Match –1.0 +0.2 +1.0 µA

TMIN–TMAX –2.4 +2.4 µA–Input Bias Current Match –1.0 +0.1 +1.0 µA

TMIN–TMAX –2.5 +2.5 µACMRR ∆VCM = –10 V to +10 V 71 76 dBInput CM Voltage Range –10 +10 V

OUTPUT CHARACTERISTICSOutput Resistance 0.2 ΩOutput Voltage Swing RL = 100 Ω –10.8 +10.8 VOutput Current SFDR –80 dBc into 100 Ω at 100 kHz 125 170 mAShort Circuit Current1 800 mA

POWER SUPPLYSupply Current/Amp PWDN = High 9 10 mA

TMIN–TMAX 11.5 mAPWDN = Low 0.8 1.75 mA

Operating Range Dual Supply ±4.0 ±12 VPower Supply Rejection Ratio ∆±VS = +1.0 V to –1.0 V 61 64 dB

LOGIC LEVELS VPWDN = 0 V to 3 V; VIN = 10 MHz, G = +5tON 120 nstOFF 80 nsPWDN = “1” Voltage 1.8 +VS VPWDN = “0” Voltage 0.5 VPWDN = “1” Bias Current 220 µAPWDN = “0” Bias Current –100 µA

NOTES1This device is protected from overheating during a short-circuit by a thermal shutdown circuit.

Specifications subject to change without notice.

(@ 25C, VS = 12 V, RL = 100 , RF = 500 , TMIN = –40C, TMAX = +85C, unless otherwise noted.)

OBSOLETE

REV. 0

AD8019

–4–

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD8019 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 VInternal Power Dissipation

TSSOP-14 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 WSOIC-8 Package3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W

Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ±VS

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±VS

Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°COperating Temperature Range . . . . . . . . . . . –40°C to +85°CLead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.

2Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at85°C 14-lead TSSOP package: θJA = 90°C/W.

3Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at85°C 8-lead SOIC package: θJA = 100°C/W.

MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the AD8019is limited by the associated rise in junction temperature. Themaximum safe junction temperature for a plastic encapsulateddevice is determined by the glass transition temperature of theplastic, approximately 150°C. Temporarily exceeding this limitmay cause a shift in parametric performance due to a change inthe stresses exerted on the die by the package.

The output stage of the AD8019 is designed for maximum loadcurrent capability. As a result, shorting the output to commoncan cause the AD8019 to source or sink 500 mA. To ensureproper operation, it is necessary to observe the maximum powerderating curves. Direct connection of the output to either powersupply rail can destroy the device.

AMBIENT TEMPERATURE – C

MA

XIM

UM

PO

WE

R D

ISS

IPA

TIO

N –

W

2.5

2.0

1.5

1.0

0.5

0–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

SOIC

TSSOP

Figure 2. Plot of Maximum Power Dissipation vs.Temperature for AD8019 for TJ = 150°C

ORDERING GUIDE

Temperature Package PackageModel Range Description Option

AD8019ARU –40°C to +85°C 14-Lead TSSOP RU-14AD8019ARU-Reel –40°C to +85°C 14-Lead TSSOP RU-14 ReelAD8019ARU-EVAL –40°C to +85°C Evaluation Board ARU-EVALAD8019AR –40°C to +85°C 8-Lead SOIC R-8AD8019AR-Reel –40°C to +85°C 8-Lead SOIC R-8 ReelAD8019AR-EVAL –40°C to +85°C Evaluation Board AR EVALOBSOLETE

REV. 0 –5–

Typical Performance Characteristics–AD8019

0.1F

0.1F

10F

10F

49.9

124 499

RL

VOUT

+VS

–VS

+

+

VIN

TPC 1. Single-Ended Test Circuit; G = +5

TIME – ns

VO

UT –

mV

100

–60

–80

–100–100 0 100 200 300 400 500 600 700

–40

–20

0

20

40

60

80

TPC 2. 100 mV Step Response; G = +5, VS = ±6 V,RL = 25 Ω, Single-Ended

TIME – ns

VO

UT –

Vo

lts

–3

–4–100 0 100 200 300 400 500 600 700

–2

–1

0

1

2

3

4

TPC 3. 4 V Step Response; G = +5, VS = ±6 V,RL = 25 Ω, Single-Ended

500

50

+VIN

RL

500

50

–VIN

+VO

–VO

0.1F 55

550.1F

0.1F

–VS

+VS

+47F

TPC 4. Differential Test Circuit; G = +10

TIME – 100ns/DIV

VO

LT

S –

mV

–80

–100–100 0 100 200 300 400 500 600 700

–60

–40

–20

0

20

40

60

80

100

TPC 5. 100 mV Step Response; G = +5, VS = ±12 V,RL = 100 Ω, Single-Ended

TIME – ns

VO

UT –

Vo

lts

–3

–4–100 0 100 200 300 400 500 600 700

–2

–1

0

1

2

3

4

TPC 6. 4 V Step Response; G = +5, VS = ±12 V,RL = 100 Ω, Single-Ended

OBSOLETE

REV. 0

AD8019

–6–

5FREQUENCY – MHz

–1000.01

DIS

TO

RT

ION

– d

Bc

10.1

–90

–80

–70

–60

–50

–40

–30

–20

3RD2ND

TPC 7. Distortion vs. Frequency; VS = ±12 V, RL = 200 Ω,Differential, VO = 16 V p-p

–100

DIS

TO

RT

ION

– d

Bc

–90

–80

–70

–60

–50

–40

–30

PEAK OUTPUT CURRENT – mA

50 75 100 125 150 175 200

2ND HARMONIC

3RD HARMONIC

TPC 8. Distortion vs. Peak Output Current; VS = ±6 V;RL = 10 Ω; f = 100 kHz; Single-Ended; Second Harmonic

–100

DIS

TO

RT

ION

– d

Bc

–90

–80

–70

–60

–50

–40

–30

PEAK OUTPUT CURRENT – mA

50 75 100 125 150 175 200 225 250

–20

2ND HARMONIC

3RD HARMONIC

TPC 9. Distortion vs. Peak Output Current; VS = ±12 V;RL = 25 Ω; f = 100 kHz; Single-Ended; Second Harmonic

5

FREQUENCY – MHz

–1000.01

DIS

TO

RT

ION

– d

Bc

10.1

–90

–80

–70

–60

–50

–40

–30

–20

3RD

2ND

TPC 10. Distortion vs. Frequency; VS = ±6 V, RL = 50 Ω,Differential, VO = 3 V p-p

–100

DIS

TO

RT

ION

– d

Bc

–90

–80

–70

–60

–50

–40

–30

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

0 2 4 6 8 10

–20

12 14 16 18 20

2ND3RD

TPC 11. Distortion vs. Output Voltage; f = 100 kHz,VS = ±6 V, G = +10, RL = 50 Ω, Differential

–100

DIS

TO

RT

ION

– d

Bc

–90

–80

–70

–60

–50

–40

–30

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

0 2 4 6 8 10

–20

12 14 16 18 20–110

–10

2ND

3RD

TPC 12. Distortion vs. Output Voltage; f = 500 kHz,VS = ±6 V, G = +10, RL = 50 Ω, Differential

OBSOLETE

REV. 0

AD8019

–7–

–100

DIS

TO

RT

ION

– d

Bc

–90

–80

–70

–60

–50

–40

–30

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

0 5 10 15 20 25

–20

30 35 40 45 50

2ND3RD

TPC 13. Distortion vs. Output Voltage; f = 100 kHz,VS = ±12 V, G = +10, RL = 200 Ω, Differential

–100

DIS

TO

RT

ION

– d

Bc

–90

–80

–70

–60

–50

–40

–30

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

0 5 10 15 20 25

–20

30 35 40 45 50–110

–10

2ND 3RD

TPC 14. Distortion vs. Output Voltage; f = 500 kHz,VS = ±12 V, G = +10, RL = 200 Ω, Differential

100.5

10010.1

0.6

0.8

0.9

1.0

1.1

1.2

LOAD CURRENT – mA

OU

TP

UT

SA

TU

RA

TIO

N V

OL

TA

GE

– V

olt

s

0.7

1000

–40C

+25C

+85C

VOL

VOH

VOH

VOH

VOL

VOL

TPC 15. Output Saturation Voltage vs. Load; VS = ±12 V,VS = ±6 V

1000

FREQUENCY – MHz

–191

OU

TP

UT

VO

LT

AG

E –

dB

V

10010

–16

–13

–10

–7

–4

–1

2

5

8

11

TPC 16. Output Voltage vs. Frequency; VS = ±12 V,RL = 100 Ω; G = +5

1000FREQUENCY – MHz

–901

CM

RR

– d

B

10010

–80

–70

–60

–50

–40

–30

0

0.10.01

–20

–10

VIN

909909

909

909

50

50

50

VOUT

TPC 17. CMRR vs. Frequency; VS = ±12 V, RL = 100 Ω

1000

FREQUENCY – MHz

–191

OU

TP

UT

VO

LT

AG

E –

dB

V

10010

–16

–13

–10

–7

–4

–1

2

5

8

11

TPC 18. Output Voltage vs. Frequency; VS = ±6 V,RL = 100 Ω; G = +5

OBSOLETE

REV. 0

AD8019

–8–

1000FREQUENCY – MHz

–901

PS

RR

– d

B

10010

–80

–70

–60

–50

–40

–30

0.10.01

–20

–10

–PSRR

+PSRR

TPC 19. PSRR vs. Frequency; RL = 100 Ω

1000FREQUENCY – kHz

1 100100.10.01

–INOISE

VNOISE

+INOISE

VN

OIS

E –

nV

Hz

1

10

100

0.1

100

10

1

0.1

I NO

ISE –

pA

Hz

TPC 20. Noise vs. Frequency

20ns/DIV

2mV

/DIV

0.

1%

VIN

VOUT

1.1k1.1k

VINVOUT

50

50

50

6.8pF

TPC 21. Settling Time 0.1%; VS = ±12 V, RL = 100 Ω,VOUT = 2 V p-p

1000FREQUENCY – MHz

–90

1

CR

OS

ST

AL

K –

dB

10010

–80

–70

–60

–50

–40

–30

0.10.01

–20

–100

TPC 22. Crosstalk vs. Frequency, VS = ±12 V, VS = ±6 V;G = +2; VIN = 10 dBm

FREQUENCY – MHz

–200.001

GA

IN –

dB

0

0.01 10000.1 1 10 100

–10

10

20

30

40

50

60

70

80

90

100

110

120

2k

50 10

500

10

50

50

50

50

AOL

PHASE

–45

PH

AS

E –

Deg

rees

0

45

90

135

180

225

270

TPC 23. Open-Loop Gain and Phase vs. Frequency

VIN

20ns/DIV

2mV

/DIV

0.

1%

1.1k1.1k

VINVOUT

50

50

50

6.8pF

VOUT

TPC 24. Settling Time 0.1%; VS = ±6 V, RL = 100 Ω,VOUT = 2 V p-p

OBSOLETE

REV. 0

AD8019

–9–

FREQUENCY – MHz

1

OU

TP

UT

IMP

ED

AN

CE

–

100100.10.01

1

10

100

1000

0.1

0.01

0.001

TPC 25. Output Impedance vs. Frequency; VS = ±12 V;VS = ±6 V

–100

0V

0V

0 100 200 300 400 500 600 700 800 900

VIN

VOUT VIN = 2V/DIVVOUT = 5V/DIV

TIME – ns

TPC 26. Overload Recovery; VS = ±12 V, G = +5, RL =100 Ω

–100

0V

0V

0 100 200 300 400 500 600 700 800 900

VIN

VOUT

VIN = 2V/DIVVOUT = 5V/DIV

TIME – ns

TPC 27. Overload Recovery; VS = ±12 V, G = +5, RL = 100 Ω

–200

0V

0 400 800 1200 1600

VIN

VOUT VIN = 1V/DIVVOUT = 2V/DIV

TIME – ns

0V

TPC 28. Overload Recovery; VS = ±6 V, G = +5, RL = 100 Ω

–200

0V

0 400 800 1200 1600

VIN = 1V/DIVVOUT = 2V/DIV

TIME – ns

0V

VIN

VOUT

TPC 29. Overload Recovery; VS = ±6 V, G = +5, RL = 100 Ω

OBSOLETE

REV. 0

AD8019

–10–

11dBm

1.2

TURNS RATIO – N

1.0

MT

PR

– d

Bc

1.1–80

–70

–60

–50

–40

–30

–20

10dBm

–10

0

1.3 1.4 1.5 1.6 1.7

12dBm

13dBm

TPC 30. MTPR vs. Turns Ratio; VS = ±6 V, RL = 100 Ω Line

18dBm

17dBm

1.2

TURNS RATIO – N

1.0

MT

PR

– d

Bc

1.1–80

–70

–60

–50

–40

–30

1.3 1.4 1.5 1.6 1.7

13dBm

16dBm

TPC 31. MTPR vs. Turns Ratio; VS = ±12 V, RL = 100 Ω Line

1.2

TURNS RATIO – N

1.0

SF

DR

– d

Bc

1.1–90

–80

–70

–60

–50

–40

–30

1.3 1.4 1.5 1.6 1.7

11dBm12dBm

13dBm

10dBm

TPC 32. SFDR vs. Turns Ratio; VS = ±6 V, RL = 100 Ω Line

1.2

TURNS RATIO – N

1.0

SF

DR

– d

Bc

1.1–90

–85

–80

–75

–70

–65

1.3 1.4 1.5 1.6 1.7

–60

–55

–50

17dBm

16dBm 13dBm

18dBm

TPC 33. SFDR vs. Turns Ratio; VS = ±12 V, RL = 100 Ω Line

OBSOLETE

REV. 0

AD8019

–11–

RL

–VS

+VO

+VS

–VO

+VS

–VS

Figure 3. Simplified Differential Driver

Remembering that each output device only dissipates for halfthe time gives a simple integral that computes the power foreach device:

12

2∫ ×

( – )

( )V V

VR

S OO

L

The total supply power can then be computed as:

P V V V I V PTOT S O O Q S OUT= ∫ − ∫ × + +4

12

22( | | ) α

In this differential driver, VO is the voltage at the output of oneamplifier, so 2 VO is the voltage across RL. RL is the totalimpedance seen by the differential driver, including backtermination. Now, with two observations the integrals are easilyevaluated. First, the integral of VO

2 is simply the square of therms value of VO. Second, the integral of | VO | is equal to theaverage rectified value of VO, sometimes called the mean averagedeviation, or MAD. It can be shown that for a DMT signal, theMAD value is equal to 0.8 times the rms value.

P V rmsV V rms

RI V PTOT O S O

LQ S OUT= × + +4 0 8

122( . – ) α

For the AD8019 operating on a single 12 V supply and delivering atotal of 16 dBm (13 dBm to the line and 3 dBm to the matchingnetwork) into 17.3 Ω (100 Ω reflected back through a 1:1.7transformer plus back termination), the dissipated power is:

= 332 mW + 40 mW

= 372 mW

Using these calculations and a θJA of 90°C/W for the TSSOPpackage and 100°C/W for the SOIC, Tables I–IV show junc-tion temperature versus power delivered to the line for severalsupply voltages while operating with an ambient temperatureof 85°C. The shaded areas indicate operation at a junctiontemperature over the absolute maximum rating of 150°C, andshould be avoided.

Table I. Junction Temperature vs. Line Power and OperatingVoltage for TSSOP

VSUPPLY

PLINE, dBm 12 12.5 13

13 132 134 13714 134 137 13915 136 139 14116 139 141 14417 141 144 14718 143 147 150

GENERAL INFORMATIONThe AD8019 is a voltage feedback amplifier with high outputcurrent capability. As a voltage feedback amplifier, the AD8019features lower current noise and more applications flexibility thancurrent feedback designs. It is fabricated on Analog Devices’proprietary High Voltage eXtra Fast Complementary BipolarProcess (XFCB-HV), which enables the construction of PNPand NPN transistors with similar fTs in the 4 GHz region. Theprocess is dielectrically isolated to eliminate the parasitic andlatch-up problems caused by junction isolation. These featuresenable the construction of high-frequency, low-distortion amplifiers.

POWER-DOWN FEATUREA digitally programmable logic pin (PWDN) is available on theTSSOP-14 package. It allows the user to select between twooperating conditions, full on and shutdown. The DGND pin isthe logic reference. The threshold for the PWDN pin is typically1.8 V above DGND. If the power-down feature is not beingused, it is better to tie the DGND pin to the lowest potentialthat the AD8019 is tied to and place the PWDN pin at a poten-tial at least 3 V higher than that of the DGND pin, but lowerthan the positive supply voltage.

POWER SUPPLY AND DECOUPLINGThe AD8019 can be powered with a good quality (i.e., low-noise)supply anywhere in the range from +12 V to ±12 V. In order tooptimize the ADSL upstream drive capability of 13 dBm andmaintain the best Spurious Free Dynamic Range (SFDR), theAD8019 circuit should be powered with a well-regulated supply.

Careful attention must be paid to decoupling the power supply.High quality capacitors with low equivalent series resistance(ESR) such as multilayer ceramic capacitors (MLCCs) shouldbe used to minimize supply voltage ripple and power dissipa-tion. In addition, 0.1 µF MLCC decoupling capacitors shouldbe located no more than 1/8 inch away from each of the powersupply pins. A large, usually tantalum, 10 µF to 47 µF capacitoris required to provide good decoupling for lower frequencysignals and to supply current for fast, large signal changes atthe AD8019 outputs.

POWER DISSIPATIONIt is important to consider the total power dissipation of theAD8019 in order to properly size the heat sink area of an appli-cation. Figure 3 is a simple representation of a differential driver.With some simplifying assumptions we can estimate the totalpower dissipated in this circuit. If the output current is largecompared to the quiescent current, computing the dissipationin the output devices and adding it to the quiescent power dissipa-tion will give a close approximation of the total power dissipation inthe package. A factor α (~0.6-1) corrects for the slight errordue to the Class A/B operation of the output stage. It can beestimated by subtracting the quiescent current in the outputstage from the total quiescent current and ratioing that to thetotal quiescent current. For the AD8019, α = 0.833.

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Table II. Junction Temperature vs. Line Power and OperatingVoltage for SOIC

VSUPPLY

PLINE, dBm 12 12.5 13

13 137 140 14314 140 142 14515 142 145 14816 145 148 15117 147 150 15418 150 153 157

Table III. Junction Temperature vs. Line Power andOperating Voltage for TSSOP

VSUPPLY

PLINE, dBm +12 +13

13 115 11814 116 11915 118 12116 120 123

Table IV. Junction Temperature vs. Line Power andOperating Voltage for SOIC

VSUPPLY

PLINE, dBm +12 +13

13 118 12114 120 12315 122 12516 124 128

Thermal stitching, which connects the outer layers to the inter-nal ground plane(s), can help to utilize the thermal mass of thePCB to draw heat away from the line driver and other activecomponents.

LAYOUT CONSIDERATIONSAs is the case with all high-speed applications, careful attentionto printed circuit board layout details will prevent associatedboard parasitics from becoming problematic. Proper RF designtechnique is mandatory. The PCB should have a ground planecovering all unused portions of the component side of the boardto provide a low-impedance return path. Removing the groundplane on all layers from the areas near the input and output pinswill reduce stray capacitance, particularly in the area of theinverting inputs. The signal routing should be short and directin order to minimize parasitic inductance and capacitance asso-ciated with these traces. Termination resistors and loads shouldbe located as close as possible to their respective inputs andoutputs. Input and output traces should be kept as far apart aspossible to minimize coupling (crosstalk) though the board.

Wherever there are complementary signals, a symmetricallayout should be provided to the extent possible to maximizebalanced performance. When running differential signals over along distance, the traces on the PCB should be close together orany differential wiring should be twisted together to minimizethe area of the loop that is formed. This will reduce the radiated

energy and make the circuit less susceptible to RF interference.Adherence to stripline design techniques for long signal traces(greater than about 1 inch) is recommended.

Evaluation BoardThe AD8019 is available installed on an evaluation board forboth package styles. Figures 8 and 9 show the schematics for theTSSOP evaluation board.

The receiver circuit on these boards is typically unpopulated.Requesting samples of the AD8022AR, along with either of theAD8019 evaluation boards, will provide the capability to evaluatethe AD8019 along with other Analog Devices products in a typicaltransceiver circuit. The evaluation circuits have been designedto replicate the CPE side analog transceiver hybrid circuits.

The circuit mentioned above is designed using a 1-transformertransceiver topology including a line receiver, line driver, linematching network, an RJ11 jack for interfacing to line simula-tors, and differential inputs.

AC-coupling capacitors of 0.1 µF, C8, and C10, in combinationwith 10 kΩ, resistors R24 and R25, will form a 1st order high-pass pole at 160 Hz.

Transformer SelectionCustomer premise ADSL requires the transmission of a 13 dBm(20 mW) DMT signal. The DMT signal has a crest factor of 5.3,requiring the line driver to provide peak line power of 560 mW.560 mW peak line power translates into a 7.5 V peak voltage ona 100 Ω telephone line. Assuming that the maximum low distor-tion output swing available from the AD8019 line driver on a±12 V supply is 20 V and taking into account the power lost dueto the termination resistance, a step-up transformer with turnsratio of 1:1 is adequate for most applications. If the modemdesigner desires to transmit more than 13 dBm down the twistedpair, a higher turns ratio can be used for the transformer. Thistrade-off comes at the expense of higher power dissipation bythe line driver as well as increased attenuation of the downstreamsignal that is received by the transceiver.

In the simplified differential drive circuit shown in Figure 7,the AD8019 is coupled to the phone line through a step-uptransformer with a 1:1 turns ratio. R1 and R2 are back termi-nation or line matching resistors, each 50 Ω (100 Ω/(2 × 12))where 100 Ω is the approximate phone line impedance. Atransformer reflects impedance from the line side to the ICside as a value inversely proportional to the square of the turnsratio. The total differential load for the AD8019, including thetermination resistors, is 200 Ω. Even under these conditionsthe AD8019 provides low distortion signals to within 2 V ofthe power supply rails.

One must take care to minimize any capacitance present at theoutputs of a line driver. The sources of such capacitance caninclude, but are not limited to EMI suppression capacitors,overvoltage protection devices and the transformers used in thehybrid. Transformers have two kinds of parasitic capacitances,distributed, or bulk capacitance, and interwinding capacitance.Distributed capacitance is a result of the capacitance createdbetween each adjacent winding on a transformer. Interwindingcapacitance is the capacitance that exists between the windingson the primary and secondary sides of the transformer. Theexistence of these capacitances is unavoidable, but in specifying

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a transformer, one should do so in a way to minimize them inorder to avoid operating the line driver in a potentially unstableenvironment. Limiting both distributed and interwinding capaci-tance to less than 20 pF each should be sufficient for mostapplications.

Stability EnhancementsVoltage feedback amplifiers may exhibit sensitivity to capaci-tance present at the inverting input. Parasitic capacitance, as smallas several picofarads, in combination with the high-impedance ofthe input can create a pole that can dramatically decrease the phasemargin of the amplifier. In the case of the AD8019, a compen-sation capacitor of 10 pF–20 pF in parallel with the feedbackresistor will form a zero that can serve to cancel out the effectsof the parasitic capacitance. Placing 100 Ω in series with each ofthe noninverting inputs serves to isolate the inputs from eachother and from any high frequency signals that may be coupledinto the amplifier via the midsupply bias.

It may also be necessary to configure the line driver as two sepa-rate, noninverting amplifiers rather than a single differentialdriver. When doing this, the two gain resistors can share an accoupling capacitor of 0.1 µF to minimize any dc errors.

Adhering to previously mentioned layout techniques will also beof assistance in keeping the amplifier stable.

Receive Channel ConsiderationsA transformer used at the output of the differential line driver tostep up the differential output voltage to the line has the inverseeffect on signals received from the line. A voltage reduction orattenuation equal to the inverse of the turns ratio is realized inthe receive channel of a typical bridge hybrid. The turns ratio ofthe transformer may also be dictated by the ability of the receivecircuitry to resolve low-level signals in the noisy twisted pair tele-phone plant. While higher turns ratio transformers boost transmitsignals to the appropriate level, they also effectively reduce thereceived signal to noise ratio due to the reduction in the receivedsignal strength.

Using a transformer with as low a turns ratio as possible will limitdegradation of the received signal.

The AD8022, a dual amplifier with typical RTI voltage noise ofonly 2.5 nV/√Hz and a low supply current of 4 mA/amplifier isrecommended for the receive channel.

DMT Modulation, Multi-Tone Power Ratio (MTPR) andOut-of-Band SFDRADSL systems rely on Discrete Multi-Tone (or DMT) modula-tion to carry digital data over phone lines. DMT modulationappears in the frequency domain as power contained in severalindividual frequency subbands, sometimes referred to as tonesor bins, each of which are uniformly separated in frequency. Auniquely encoded, Quadrature Amplitude Modulation (QAM)-like signal occurs at the center frequency of each subband ortone. See Figure 4 for an example of a DMT waveform in thefrequency domain, and Figure 5 for a time domain waveform.Difficulties will exist when decoding these subbands if a QAMsignal from one subband is corrupted by the QAM signal(s)

from other subbands, regardless of whether the corruptioncomes from an adjacent subband or harmonics of other subbands.

Conventional methods of expressing the output signal integrityof line drivers such as single tone harmonic distortion or THD,two-tone Intermodulation Distortion (IMD) and third orderintercept (IP3) become significantly less meaningful whenamplifiers are required to process DMT and other heavilymodulated waveforms. A typical ADSL upstream DMT signalcan contain as many as 27 carriers (subbands or tones) of QAMsignals. Multi-Tone Power Ratio (MTPR) is the relative differ-ence between the measured power in a typical subband (at onetone or carrier) versus the power at another subband specifi-cally selected to contain no QAM data. In other words, aselected subband (or tone) remains open or void of intentionalpower (without a QAM signal) yielding an empty frequency bin.MTPR, sometimes referred to as the ‘empty bin test,’ is typicallyexpressed in dBc, similar to expressing the relative differencebetween single tone fundamentals and second or third harmonicdistortion components. Measurements of MTPR are typicallymade on the line side or secondary side of the transformer.

FREQUENCY – kHz

–8050

PO

WE

R –

dB

m

–60

–40

–20

0

20

0 100 150

Figure 4. DMT Waveform in the Frequency Domain

MTPR versus transformer turns ratio is depicted in TPCs 30 and31 and covers a variety of line power ranging from 10 dBm to18 dBm. As the turns ratio increases, the driver hybrid candeliver more undistorted power to the load due to the highoutput current capability of the AD8019. Significant degrada-tion of MTPR will occur if the output of the driver swings tothe rails, causing clipping at the DMT voltage peaks. DrivingDMT signals to such extremes not only compromises “in band”MTPR, but will also produce spurs that exist outside of thefrequency spectrum containing the transmitted signal. “Out-of-band” spurious free dynamic range (SFDR) can be definedas the relative difference in amplitude between these spurs and atone in one of the upstream bins. Compromising out-of-bandSFDR is the equivalent of increasing near-end cross talk (NEXT).Regardless of terminology, maintaining out-of-band SFDRwhile reducing NEXT will improve the overall performance ofthe modems connected at either end of the twisted pair.

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R117.3

RL = 100

R217.3

1:1.7TRANSFORMER

POUT16dBm

LINEPOWER13dBm

301

301

50

500.1F

10k

10k

0.1F

0.1F

+12V

100

1000.1F

VIN

6V

0.1F 10F

Figure 6. Recommended Application Circuit for Single +12 V Supply

R112.4

RL = 100

R212.4

1:1TRANSFORMER

POUT16dBm

LINEPOWER13dBm

301

301

50

500.1F

10k

10k

0.1F

+12V

100

1000.1F

VIN

0.1F

–12V 0.1F 10F

10F

Figure 7. Recommended Application Circuit for ±12 V Supply

–0.25 –0.15 –0.05 0

TIME – ms

0.10 0.15 0.20

VO

LT

S

–3

–2

–1

0

1

2

3

4

0.05–0.10–0.20

Figure 5. DMT Signal in the Time Domain

Generating DMT SignalsAt this time, DMT-modulated waveforms are not typicallymenu-selectable items contained within arbitrary waveformgenerators. Even using (AWG) software to generate DMT sig-nals, AWGs that are available today may not deliver DMTsignals sufficient in performance with regard to MTPR due tolimitations in the D/A converters and output drivers used byAWG manufacturers. Similar to evaluating single-tone distor-tion performance of an amplifier, MTPR evaluation requires aDMT signal generator capable of delivering MTPR performancebetter than that of the driver under evaluation. GeneratingDMT signals can be accomplished using a Tektronics AWG2021 equipped with Option 4, (12-/24-bit, TTL Digital DataOut), digitally coupled to Analog Devices’ AD9754, a 14-bitTxDAC®, buffered by an AD8002 amplifier configured as adifferential driver. Note that the DMT waveforms, available onthe Analog Devices website, www.analog.com, or similar. WFMfiles are needed to produce the necessary digital data required todrive the TxDAC from the optional TTL Digital Data output ofthe TEK AWG2021.

TxDAC is a registered trademark of Analog Devices, Inc.

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B

3

2

1

JP3

P4

1

+V –V

U1

1

2

34

513

VC

C

VE

E

–V +VU

15

3

13

AD

8019

AD

8019

11

1210

1 2

AB

2

JP7

VC

C-2

C5

0.1

F

R28

DN

I

TP

6

R20

DN

I

TP

7P

R1

A

C11

DN

I

C22

DN

IR

3D

NI

R1

100

1WA

TT

R38

DN

I

R8

100

C8

0.1

F

TP

10

R24

10k

R40

DN

I

C28

DN

I

R29

10k

R41

DN

I

R14

100

C27

DN

IR

4D

NI

R21

DN

IC

12D

NI

R39

DN

IR

37D

NI

PR

2

TP

9 B

TP

8

R30 0

VC

C

2

B

JP4

3 1 AP

4 2

P4

3

S5

S6

VC

C

VC

C

S3

P3

1

P3

2

P3

3

U2

U2

AD

8022

AD

8022

S4

B

3

2

1JP6

A

TB

1 2

TB

1 3

TB

1 1

+

+DN

IR

35D

NI

C29

DN

I

R36

DN

I

C7

DN

I

C9

DN

I

R32

100

NC

= 5

,6

T1

1 23 478 910

TP

1

C6

DN

IP

1

1 2 3 4

78

5 6T

P2

TP

23T

P24

TP

25T

P26

VC

CIN

L5

BE

AD

L1

BE

AD C

410

F

25V

C21

0.1

FC

200.

1F

C17

DN

I

U1

DE

CO

UP

LIN

G

U1

DE

CO

UP

LIN

G U2

DE

CO

UP

LIN

G

U2

DE

CO

UP

LIN

G

C23

DN

I

TP

19

TP

12

C15

0.01

F

C14

10

F25

V

C26

0.1

F

VC

C

VE

E

JP5

C18

DN

I

TP

4

TP

5

VC

C-2

C3

DN

IC

16D

NI

R22 DN

IR

13D

NI

R10

DN

I

R9

DN

I

C2

DN

I

R23

DN

I

C1

DN

I

R5

DN

I

R6

DN

I

VC

C

R7

DN

I

R34

DN

I

R33

DN

I

R12

DN

I

VC

C;8

VE

E;4

VC

C;8

VE

E;4

756

1

23

TP

18

TP

17

VC

C-2

C19

0.1

F

R17

5k

R16

5k TP

3

TP

11

C10

0.1

F

VE

ER

1550

R31 0

A

R42

DN

I

R2

50

R18

301

C13

0.1

F

R19

301

A

R11

50

*D

NI :

DO

NO

T IN

ST

AL

L

Figure 8. TSSOP Noninverting DSL Evaluation Board Schematic

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VCC

R25VAL

R26VAL

R27VAL

C24VAL

NC4

NC1 NC2 NC3

1 7 148

9

6

12

3

B

JP1PWDN

DGND

U1 AD8019A

Figure 9. DSL Driver Input Control Circuit

Figure 10. TSSOP Evaluation Board Silkscreen Top

Figure 11. TSSOP Evaluation Board Silkscreen Bottom

2

AGNDAGND

Figure 12. TSSOP Evaluation Board Power PlaneOBSOLETE

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Figure 13. Solder Mask Top

Figure 14. Solder Mask Bottom

Figure 15. Ground Plane Bottom

Figure 16. Assembly TopOBSOLETE

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Figure 17. Ground Plane Top Figure 18. Assembly Bottom

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Figure 19. Board Fabrication

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AD8019OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead TSSOP(RU-14)

14 8

71

0.256 (6.50)0.246 (6.25)

0.177 (4.50)0.169 (4.30)

PIN 1

0.201 (5.10)0.193 (4.90)

SEATINGPLANE

0.006 (0.15)0.002 (0.05)

0.0118 (0.30)0.0075 (0.19)

0.0256(0.65)BSC

0.0433 (1.10)MAX

0.0079 (0.20)0.0035 (0.090)

0.028 (0.70)0.020 (0.50)

80

8-Lead SOIC(R-8)

0.0098 (0.25)0.0075 (0.19)

0.0500 (1.27)0.0160 (0.41)

0.0196 (0.50)0.0099 (0.25)

45

80

0.102 (2.59)0.094 (2.39)

SEATINGPLANE

0.0098 (0.25)0.0040 (0.10)

0.0192 (0.49)0.0138 (0.35)

8 5

41

0.1968 (5.00)0.1890 (4.80)

PIN 1

0.1574 (4.00)0.1497 (3.80)

0.0500 (1.27)BSC

0.2440 (6.20)0.2284 (5.80)

C02

551–

1.5–

4/01

(0)

PR

INT

ED

IN U

.S.A

.OBSOLETE