AD8129/AD8130 Low Cost 270 MHz Differential Receiver ... · Low Cost 270 MHz Differential Receiver Amplifiers AD8129/AD8130 Rev. C Information furnished by Analog Devices is believed

Low Cost 270 MHz Differential Receiver Amplifiers

AD8129/AD8130

Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

FEATURES High speed

AD8130: 270 MHz, 1090 V/μs @ G = +1 AD8129: 200 MHz, 1060 V/μs @ G = +10

High CMRR 94 dB min, dc to 100 kHz 80 dB min @ 2 MHz 70 dB @ 10 MHz

High input impedance: 1 MΩ differential Input common-mode range ±10.5 V Low noise

AD8130: 12.5 nV/√Hz AD8129: 4.5 nV/√Hz

Low distortion, 1 V p-p @ 5 MHz AD8130, −79 dBc worst harmonic @ 5 MHz AD8129, −74 dBc worst harmonic @ 5 MHz

User-adjustable gain No external components for G = +1

Power supply range +4.5 V to ±12.6 V Power-down APPLICATIONS High speed differential line receivers Differential-to-single-ended converters High speed instrumentation amps Level shifting

CONNECTION DIAGRAM

AD8129/AD8130

1

2

3

4

+IN –IN

–VS +VS

PD OUT

REF FB

8

7

6

5

+

0246

4-00

1

Figure 1.

The AD8129/AD8130 are differential-to-single-ended amplifiers with extremely high CMRR at high frequency. Therefore, they can also be effectively used as high speed instrumentation amps or for converting differential signals to single-ended signals.

The AD8129 is a low noise, high gain (10 or greater) version intended for applications over very long cables, where signal attenuation is significant. The AD8130 is stable at a gain of 1 and can be used for applications where lower gains are required. Both have user-adjustable gain to help compensate for losses in the transmission line. The gain is set by the ratio of two resistor values. The AD8129/AD8130 have very high input impedance on both inputs, regardless of the gain setting.

GENERAL DESCRIPTION

The AD8129/AD8130 are designed as receivers for the transmission of high speed signals over twisted-pair cables to work with the AD8131 or AD8132 drivers. Either can be used for analog or digital video signals and for high speed data transmission.

120

110

100

90

80

70

60

50

40

3010k 100k 1M 10M 100M

FREQUENCY (Hz)

CM

RR

(dB

)

0246

4-00

2

Figure 2. AD8129 CMRR vs. Frequency

The AD8129/AD8130 have excellent common-mode rejection (70 dB @ 10 MHz), allowing the use of low cost, unshielded twisted-pair cables without fear of corruption by external noise sources or crosstalk. The AD8129/AD8130 have a wide power supply range from single +5 V to ±12 V, allowing wide common-mode and differential-mode voltage ranges while maintaining signal integrity. The wide common-mode voltage range enables the driver-receiver pair to operate without isolation transformers in many systems where the ground potential difference between drive and receive locations is many volts. The AD8129/AD8130 have considerable cost and performance improvements over op amps and other multiamplifier receiving solutions.

RF

VOUT

VIN

RG

VOUT = VIN [1+(RF/RG)]

PD+VS

–VS

1

8

4

5

3

2

7

6

0246

4-00

3

Figure 3. Typical Connection Configuration

http://www.analog.com/en/prod/0%2C2877%2CAD8131%2C00.html

http://www.analog.com/en/prod/0%2C2877%2CAD8132%2C00.html

AD8129/AD8130

Rev. C | Page 2 of 40

TABLE OF CONTENTS Features .............................................................................................. 1

Applications....................................................................................... 1

Connection Diagram ....................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

AD8129/AD8130 Specifications..................................................... 3

5 V Specifications ......................................................................... 3

±5 V Specifications....................................................................... 5

±12 V Specifications..................................................................... 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Typical Performance Characteristics ........................................... 10

AD8130 Frequency Response Characteristics........................ 10

AD8129 Frequency Response Characteristics........................ 13

AD8130 Harmonic Distortion Characteristics ...................... 16

AD8129 Harmonic Distortion Characteristics ...................... 18

AD8130 Transient Response Characteristics.......................... 23

AD8129 Transient Response Characteristics.......................... 26

Theory of Operation ...................................................................... 32

Op Amp Configuration............................................................. 32

Applications..................................................................................... 33

Basic Gain Circuits..................................................................... 33

Twisted-Pair Cable, Composite Video Receiver with Equalization Using an AD8130................................................... 33

Output Offset/Level Translator ................................................ 34

Resistorless Gain of 2 ................................................................. 35

Summer ....................................................................................... 35

Cable-Tap Amplifier .................................................................. 35

Power-Down ............................................................................... 36

Extreme Operating Conditions ................................................ 36

Power Dissipation....................................................................... 37

Layout, Grounding, and Bypassing.......................................... 38

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 40

REVISION HISTORY

11/05—Rev. B to Rev. C Changes to 5 V Specifications......................................................... 3 Changes to Table 4 and Maximum Power Dissipation Section.. 9 Changes to Figure 16...................................................................... 11 Changes to Figure 17...................................................................... 12

9/05—Rev. A to Rev. B Extended Temperature Range...........................................Universal Deleted Figure 5................................................................................ 5 Added Thermal Resistance Section ............................................... 9 Updated Outline Dimensions ....................................................... 39 Changes to Ordering Guide .......................................................... 40

3/05—Rev. 0 to Rev. A Changes to Specifications.................................................................2 Replaced Figure 3 ..............................................................................5 Changes to Ordering Guide .............................................................6 Updated Outline Dimensions....................................................... 27

Revision 0: Initial Version

AD8129/AD8130


AD8129/AD8130 SPECIFICATIONS 5 V SPECIFICATIONS

AD8129 G = +10, AD8130 G = +1, TA = 25°C, +VS = 5 V, −VS = 0 V, REF = 2.5 V, PD ≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to TMAX = −40°C to +125°C, unless otherwise noted.

Table 1. Model AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE

−3 dB Bandwidth VOUT ≤ 0.3 V p-p 160 185 220 250 MHz VOUT = 1 V p-p 160 185 180 205 MHz Bandwidth for 0.1 dB

Flatness VOUT ≤ 0.3 V p-p, SOIC/MSOP

25/40 25 MHz

Slew Rate VOUT = 2 V p-p, 25% to 75%

810 930 810 930 V/μs

Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns Rise and Fall Times VOUT ≤ 1 V p-p, 10%

to 90% 1.8 1.5 ns

Output Overdrive Recovery 20 30 ns NOISE/DISTORTION

Second Harmonic/Third Harmonic

VOUT = 1 V p-p, 5 MHz −68/−75 −72/−79 dBc

VOUT = 2 V p-p, 5 MHz −62/−64 −65/−71 dBc VOUT = 1 V p-p, 10 MHz −63/−70 −60/−62 dBc VOUT = 2 V p-p, 10 MHz −56/−58 −68/−68 dBc IMD VOUT = 2 V p-p, 10 MHz −67 −70 dBc Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.3 nV/√Hz Input Current Noise (+IN, −IN) f ≥ 100 kHz 1 1 pA/√Hz Input Current Noise

(REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz

Differential Gain Error AD8130, G = +2, NTSC 100 IRE, RL ≥ 150 Ω

0.3 0.13 %

Differential Phase Error AD8130, G = +2, NTSC 100 IRE, RL ≥ 150 Ω

0.1 0.15 Degrees

INPUT CHARACTERISTICS Common-Mode Rejection

Ratio DC to 100 kHz, VCM = 1.5 V to 3.5 V

86 96 86 96 dB

VCM = 1 V p-p @ 1 MHz 80 80 dB VCM = 1 V p-p @ 10 MHz 70 70 dB CMRR with VOUT = 1 V p-p VCM = 1 V p-p @ 1 kHz,

VOUT = ±0.5 V dc 80 72 dB

Common-Mode Voltage Range

V+IN − V−IN = 0 V 1.25 to 3.7

1.25 to 3.8

V

Differential Operating Range ±0.5 ±2.5 V Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ Common mode 4 4 MΩ Capacitance Differential 3 3 pF

Common mode 4 4 pF

AD8129/AD8130


Model AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE

Closed-Loop Gain Error VOUT = ±1 V, RL ≥ 150 Ω ±0.25 ±1.25 ±0.1 ±0.6 % TMIN to TMAX 20 20 ppm/°C Open-Loop Gain VOUT = ±1 V 86 71 dB Gain Nonlinearity VOUT = ±1 V 250 200 ppm Input Offset Voltage 0.2 0.8 0.4 1.8 mV TMIN to TMAX 2 20 μV/°C TMIN to TMAX 1.4 3.5 mV Input Offset Voltage vs.

Supply +VS = 5 V, −VS = −0.5 V to +0.5 V

−88 −80 −74 −70 dB

−VS = 0 V, +VS = +4.5 V to +5.5 V

−100 −86 −90 −76 dB

Input Bias Current (+IN, −IN)

±0.5 ±2 ±0.5 ±2 μA

Input Bias Current (REF, FB)

±1 ±3.5 ±1 ±3.5 μA

TMIN to TMAX (+IN, −IN, REF, FB)

5 5 nA/°C

Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA TMIN to TMAX 0.2 0.2 nA/°C

OUTPUT PERFORMANCE Voltage Swing RLOAD ≥ 150 Ω 1.1 3.9 1.1 3.9 V Output Current 35 35 mA Short-Circuit Current To common −60/+55 −60/+55 mA TMIN to TMAX −240 −240 μA/°C Output Impedance PD ≤ VIL, in power-

down mode 10 10 pF

POWER SUPPLY Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V Quiescent Supply Current 9.9 10.6 9.9 10.6 mA TMIN to TMAX 33 33 μA/°C PD ≤ VIL 0.65 0.85 0.65 0.85 mA

PD ≤ VIL, TMIN to TMAX 1 1 mA

PD PIN

VIH +VS − 1.5 +VS − 1.5 V VIL +VS − 2.5 +VS − 2.5 V IIH PD = min VIH −30 −30 μA

IIL PD = max VIL −50 −50 μA

Input Resistance PD ≤ +VS − 3 V 12.5 12.5 kΩ

PD ≥ +VS − 2 V 100 100 kΩ

Enable Time 0.5 0.5 μs OPERATING TEMPERATURE

RANGE −40 +125 −40 +125 °C

AD8129/AD8130


±5 V SPECIFICATIONS

AD8129 G = +10, AD8130 G = +1, TA = 25°C, VS = ±5 V, REF = 0 V, PD ≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to TMAX = −40°C to +125°C, unless otherwise noted.

Table 2. AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE

−3 dB Bandwidth VOUT ≤ 0.3 V p-p 175 200 240 270 MHz VOUT = 2 V p-p 170 190 140 155 MHz Bandwidth for 0.1 dB

Flatness VOUT ≤ 0.3 V p-p, SOIC/MSOP

30/50 45 MHz


925 1060 950 1090 V/μs

Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns Rise and Fall Times VOUT ≤ 1 V p-p,

10% to 90% 1.7 1.4 ns



VOUT = 1 V p-p, 5 MHz −74/−84 −79/−86 dBc

VOUT = 2 V p-p, 5 MHz −68/−74 −74/−81 dBc VOUT = 1 V p-p, 10 MHz −67/−81 −74/−80 dBc VOUT = 1 V p-p, 10 MHz −61/−70 −74/−76 dBc IMD VOUT = 2 V p-p, 10 MHz −67 −70 dBc Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.5 nV/√Hz Input Current Noise

(+IN, −IN) f ≥ 100 kHz 1 1 pA/√Hz

Input Current Noise (REF, FB)

f ≥ 100 kHz 1.4 1.4 pA/√Hz


0.3 0.13 %


0.1 0.15 Degrees


Ratio DC to 100 kHz, VCM = −3 V to +3.5 V

94 110 90 110 dB


VOUT = ±0.5 V dc 100 83 dB


V+IN − V−IN = 0 V ±3.5 ±3.8 V

Differential Operating Range

±0.5 ±2.5 V

Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ Common mode 4 4 MΩ Capacitance Differential 3 3 pF

Common mode 4 4 pF

AD8129/AD8130


AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE

Closed-Loop Gain Error VOUT = ±1 V, RL ≥ 150 Ω ±0.4 ±1.5 ±0.15 ±0.6 % TMIN to TMAX 20 10 ppm/°C Open-Loop Gain VOUT = ±1 V 88 74 dB Gain Nonlinearity VOUT = ±1 V 250 200 ppm Input Offset Voltage 0.2 0.8 0.4 1.8 mV TMIN to TMAX 2 20 μV/°C TMIN to TMAX 1.4 3.5 mV Input Offset Voltage vs.

Supply +VS = +5 V, −VS = −4.5 V to −5.5 V

−90 −84 −78 −74 dB

−VS = −5 V, +VS = +4.5 V to +5.5 V

−94 −86 −80 −74 dB

Input Bias Current (+IN, −IN)

±0.5 ±2 ±0.5 ±2 μA

Input Bias Current (REF, FB) ±1 ±3.5 ±1 ±3.5 μA TMIN to TMAX (+IN, −IN,

REF, FB) 5 5 nA/°C


OUTPUT PERFORMANCE Voltage Swing RLOAD = 150 Ω/1 kΩ 3.6/4.0 3.6/4.0 ±V Output Current 40 40 mA Short-Circuit Current To common −60/+55 −60/+55 mA TMIN to TMAX −240 −240 μA/°C Output Impedance PD ≤ VIL, in power-

down mode 10 10 pF

POWER SUPPLY Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V Quiescent Supply Current 10.8 11.6 10.8 11.6 mA TMIN to TMAX 36 36 μA/°C PD ≤ VIL 0.68 0.85 0.68 0.85 mA

PD ≤ VIL, TMIN to TMAX 1 1 mA

PD PIN



Input Resistance PD ≤ +VS − 3 V 12.5 12.5 kΩ

PD ≥ +VS − 2 V 100 100 kΩ


RANGE −40 +125 −40 +125 °C

AD8129/AD8130


±12 V SPECIFICATIONS

AD8129 G = +10, AD8130 G = +1, TA = 25°C, VS = ±12 V, REF = 0 V, PD ≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 3. AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE

−3 dB Bandwidth VOUT ≤ 0.3 V p-p 175 200 250 290 MHz VOUT = 2 V p-p 170 195 150 175 MHz Bandwidth for 0.1 dB Flatness VOUT ≤ 0.3 V p-p,

SOIC/MSOP 50/70 110 MHz


935 1070 960 1100 V/μs

Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns Rise and Fall Times VOUT ≤ 1 V p-p, 10%

to 90% 1.7 1.4 ns



VOUT = 1 V p-p, 5 MHz −71/−84 −79/−86 dBc

VOUT = 2 V p-p, 5 MHz −65/−74 −74/−81 dBc VOUT = 1 V p-p, 10 MHz −65/−82 −74/−80 dBc VOUT = 2 V p-p, 10 MHz −59/−70 −74/−74 dBc IMD VOUT = 2 V p-p, 10 MHz −67 −70 dBc Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm Input Voltage Noise (RTI) f ≥ 10 kHz 4.6 13 nV/√Hz Input Current Noise

(+IN, −IN) f ≥ 100 kHz 1 1 pA/√Hz

Input Current Noise (REF, FB)

f ≥ 100 kHz 1.4 1.4 pA/√Hz


0.3 0.13 %


0.1 0.2 Degrees


Ratio DC to 100 kHz, VCM = ±10 V

92 105 88 105 dB


VOUT = ±0.5 V dc 93 80 dB


V+IN − V–IN = 0 V ±10.3 ±10.5 V

Differential Operating Range ±0.5 ±2.5 V Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ Common mode 4 4 MΩ Capacitance Differential 3 3 pF Common mode 4 4 pF

AD8129/AD8130


AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE

Closed-Loop Gain Error VOUT = ±1 V, RL ≥ 150 Ω ±0.8 ±1.8 ±0.15 ±0.6 % TMIN to TMAX 20 10 ppm/°C Open-Loop Gain VOUT = ±1 V 87 73 dB Gain Nonlinearity VOUT = ±1 V 250 200 ppm Input Offset Voltage 0.2 0.8 0.4 1.8 mV TMIN to TMAX 2 20 μV/°C TMIN to TMAX 1.4 3.5 mV Input Offset Voltage vs. Supply +VS = +12 V, −VS =

–11.0 V to −13.0 V −88 −82 −77 −70 dB

−VS = −12 V, +VS = +11.0 V to +13.0 V

−92 −84 −88 −70 dB

Input Bias Current (+IN, −IN) ±0.25 ±2 ±0.25 ±2 μA Input Bias Current (REF, FB) ±0.5 ±3.5 ±0.5 ±3.5 μA TMIN to TMAX

(+IN, −IN, REF, FB) 2.5 2.5 nA/°C


OUTPUT PERFORMANCE Voltage Swing RLOAD = 700 Ω ±10.8 ±10.8 V Output Current 40 40 mA Short-Circuit Current To common −60/+55 −60/+55 mA TMIN to TMAX −240 −240 μA/°C Output Impedance PD ≤ VIL, in power-

down mode 10 10 pF

POWER SUPPLY Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V Quiescent Supply Current 13 13.9 13 13.9 mA TMIN to TMAX 43 43 μA°C PD ≤ VIL 0.73 0.9 0.73 0.9 mA

PD ≤ VIL, TMIN to TMAX 1.1 1.1 mA

PD PIN



Input Resistance PD ≤ +VS − 3 V 3 3 kΩ

PD ≥ +VS − 2 V 100 100 kΩ


RANGE −40 +85 −40 +85 °C

AD8129/AD8130


ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage 26.4 V Power Dissipation Refer to Figure 4Input Voltage (Any Input) −VS − 0.3 V to +VS + 0.3 V Differential Input Voltage (AD8129)

VS ≥ ±11.5 V ±0.5 V Differential Input Voltage (AD8129)

VS < ±11.5 V ±6.2 V Differential Input Voltage (AD8130) ±8.4 V Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in a circuit board in still air.

Table 5. Thermal Resistance Package Type θJA Unit 8-Lead SOIC/4-Layer 121 °C/W 8-Lead MSOP/4-Layer 142 °C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8129/AD8130 packages is limited by the associated rise in junction temp-erature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8129/AD8130. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure.

The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations.

Airflow reduces θJA. In addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θJA.

Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC (121°C/W) and MSOP (θJA = 142°C/W) packages on a JEDEC standard 4-layer board. θJA values are approximations.

AMBIENT TEMPERATURE (°C)

MA

XIM

UM

PO

WER

DIS

SIPA

TIO

N (W

)

1.75

1.50

1.00

1.25

0.50

0.25

0.75

0–40–30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110120

SOIC

MSOP

0246

4-00

5

Figure 4. Maximum Power Dissipation vs. Temperature

ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

AD8129/AD8130


TYPICAL PERFORMANCE CHARACTERISTICS AD8130 FREQUENCY RESPONSE CHARACTERISTICS G = +1, RL = 1 kΩ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25°C, unless otherwise noted.

GA

IN (d

B)

3

0

–3

–4

–5

–6

–7

–2

–1

1

2

FREQUENCY (MHz)1 10 100 400

0246

4-00

6

VOUT = 0.3V p-pVS = ±2.5V

VS = ±12V

VS = ±5V

Figure 5. AD8130 Frequency Response vs. Supply, VOUT = 0.3 V p-p

FREQUENCY (MHz)

GA

IN (d

B)

3

1

0

–3

–4

–5

–6

–7

–2

–1

1

2

10 100 300

0246

4-00

7

VS = ±2.5V

VS = ±12V

VS = ±5V

VOUT = 1V p-p

Figure 6. AD8130 Frequency Response vs. Supply, VOUT = 1 V p-p

FREQUENCY (MHz)

GA

IN (d

B)

1

–3

–4

–5

–6

–7

–2

–1

10 100 300

3

0

1

2

0246

4-00

8

VOUT = 2V p-p

VS = ±2.5V

VS = ±12V

VS = ±5V


FREQUENCY (MHz)

GA

IN (d

B)

6

1

3

0

–1

–2

–3

–4

1

2

4

5

10 100 300

0246

4-00

9

CL = 2pF

VS = ±5V CL = 20pF

CL = 10pF

CL = 5pF

Figure 8. AD8130 Frequency Response vs. Load Capacitance

FREQUENCY (MHz)

GA

IN (d

B)

0.7

1

0.4

0.1

0

–0.1

–0.2

–0.3

0.2

0.3

0.5

0.6

10 100 300

0246

4-01

0

VS = ±2.5V

VS = ±12V

VS = ±5V

RL = 1kΩ

Figure 9. AD8130 Fine Scale Response vs. Supply, RL = 1 kΩ

FREQUENCY (MHz)

GA

IN (d

B)

0.5

1

0.2

–0.1

–0.2

–0.3

–0.4

–0.5

0

0.1

0.3

0.4

10 100 300

0246

4-01

1

VS = ±2.5V

VS = ±12V

VS = ±5V

RL = 150Ω

Figure 10. AD8130 Fine Scale Response vs. Supply, RL = 150 Ω

AD8129/AD8130


FREQUENCY (MHz)

GA

IN (d

B)

3

1

0

–3

–4

–5

–6

–7

–2

–1

1

2

10 100 400

0246

4-01

2

VS = ±2.5V

VS = ±12V

VS = ±5V

RL = 150Ω

Figure 11. AD8130 Frequency Response vs. Supply, RL = 150 Ω

FREQUENCY (MHz)

GA

IN (d

B)

3

1

0

–3

–4

–5

–6

–7

–2

–1

1

2

10 100 300

0246

4-01

3

VS = ±2.5V

VS = ±12V

VS = ±5V

G = +2VOUT = 0.3V p-p

Figure 12. AD8130 Frequency Response vs. Supply,

G = +2, VOUT = 0.3 V p-p

FREQUENCY (MHz)

GA

IN (d

B)

3

1

0

–3

–4

–5

–6

–7

–2

–1

1

2

10 100 300

0246

4-01

4

VS = ±2.5V

VS = ±12V

VS = ±5V

G = +2VOUT = 2V p-p


G = +2, VOUT = 2 V p-p

FREQUENCY (MHz)

GA

IN (d

B)

3

1

0

–3

–4

–5

–6

–7

–2

–1

1

2

10 100 300

0246

4-01

5

RF = RG = 1kΩ

RF = RG = 750Ω

RF = RG = 499Ω

RF = RG = 250Ω

G = +2VS = ±5V

Figure 14. AD8130 Frequency Response for Various RF/RG

FREQUENCY (MHz)

GA

IN (d

B)

0.3

1 10 100

0

–0.3

–0.4

–0.5

–0.6

–0.7

–0.2

–0.1

0.1

0.2

0246

4-01

6

VS = ±2.5V

VS = ±12V

VS = ±5V

G = +2RL = 1kΩ

Figure 15. AD8130 Fine Scale Response vs. Supply, G = +2, RL = 1 kΩ

FREQUENCY (MHz)

GA

IN (d

B)

0.3

1 10

0

–0.3

–0.4

–0.5

–0.6

–0.7

–0.2

–0.1

0.1

0.2

100

0246

4-01

7

VS = ±2.5V

VS = ±12V

VS = ±5V

G = +2RL = 150Ω

Figure 16. AD8130 Fine Scale Response vs. Supply, G = +2, RL = 150 Ω

AD8129/AD8130


FREQUENCY (MHz)

GA

IN (d

B)

3

1 30010 100

0

–3

–4

–5

–6

–7

–2

–1

1

2

0246

4-01

8

VS = ±2.5V

VS = ±12V

VS = ±5V

G = +2RL = 150Ω

FREQUENCY (MHz)

GA

IN (d

B)

3

1 10 100

0

–3

–4

–5

–6

–7

–2

–1

1

2

0.1

0246

4-02

1

VS = ±2.5V

RL = 150Ω

VS = ±5V, ±12V

G = +10 G = +5

VS = ±5V, ±12V


G = +2, RL = 150 Ω

Figure 20. AD8130 Frequency Response vs. Supply, G = +5, G = +10, RL = 150 Ω

FREQUENCY (MHz)

GA

IN (d

B)

0.3

0.1

0

–0.3

–0.4

–0.5

–0.6

–0.7

–0.2

–0.1

0.1

0.2

1 10FREQUENCY (MHz)

OU

TPU

T VO

LTA

GE

(dB

V)

12

10

6

0

–6

–12

–18

–24

–30

–36

–42

–48100 400

0dB = 1V rms

0246

4-02

2

VS = ±5V

30

0246

4-01

9

VOUT = 2V p-p

VS = ±2.5V

VS = ±12V

VS = ±5V

VS = ±5V, ±12V

VS = ±2.5V

G = +10 G = +5

Figure 18. AD8130 Fine Scale Response vs. Supply,

G = +5, G = +10, VOUT = 2 V p-p

Figure 21. AD8130 Frequency Response for Various Output Levels

FREQUENCY (MHz)

GA

IN (d

B)

3

1 10 100

0

–3

–4

–5

–6

–7

–2

–1

1

2

0.1

0246

4-02

0

VOUT = 2V p-p

VS = ±12V

VS = ±5V, ±12V

VS = ±2.5V

G = +10

G = +5

0246

4-02

3

1

8

4

5

6

TEK P6245FET PROBE

RL CL

RG RF

50Ω

G

125

10

RF

0Ω499Ω

8.06kΩ4.99kΩ

RG

–499Ω2kΩ

549Ω

Figure 19. AD8130 Frequency Response vs. Supply, G = +5, G = +10, VOUT = 2 V p-p

Figure 22. AD8130 Basic Frequency Response Test Circuit

AD8129/AD8130


AD8129 FREQUENCY RESPONSE CHARACTERISTICS G = +10, RL = 1 kΩ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25°C, unless otherwise noted.

FREQUENCY (MHz)

GA

IN (d

B)

3

1 30010 100

0

–3

–4

–5

–6

–7

–2

–1

1

2

0246

4-02

4


VS = ±12V

VS = ±5V

Figure 23. AD8129 Frequency Response vs. Supply, VOUT = 0.3 V p-p

FREQUENCY (MHz)

GA

IN (d

B)

3

1 30010 100

0

–3

–4

–5

–6

–7

–2

–1

1

2

0246

4-02

5

VS = ±2.5V

VS = ±12V

VS = ±5VVOUT = 1V p-p


FREQUENCY (MHz)

GA

IN (d

B)

1

–3

–4

–5

–6

–7

–2

–1

10 100 300

3

0

1

2

0246

4-02

6

VOUT = 2V p-pVS = ±2.5V

VS = ±12VVS = ±5V


FREQUENCY (MHz)

GA

IN (d

B)

4

1

1

–2

–3

–4

–5

–6

–1

0

2

3

10 100 300

0246

4-02

7

VS = ±5V CL = 20pF

CL = 10pF

CL = 5pF

CL = 2pF

Figure 26. AD8129 Frequency Response vs. Load Capacitance

0246

4-02

8

FREQUENCY (MHz)

GA

IN (

dB)

0.5

0.2

–0.1

–0.2

–0.3

–0.4

–0.5

0

0.3

0.4

1 30010 100

RL = 1kΩ VS = ±2.5V

VS = ±5V

VS = ±12V

0.1

Figure 27. AD8129 Fine Scale Response vs. Supply, RL = 1 kΩ

0246

4-02

9

FREQUENCY (MHz)

GA

IN (d

B)

30010 100

0.3

0

–0.3

–0.4

–0.5

–0.6

–0.7

–0.2

–0.1

0.1

0.2

1

RL = 150Ω VS = ±2.5V

VS = ±5V

VS = ±12V

Figure 28. AD8129 Fine Scale Response vs. Supply, RL = 150 Ω

AD8129/AD8130


0246

4-03

0

FREQUENCY (MHz)

GA

IN (d

B)

30010010

3

2

1

0

–1

–2

–3

–4

–5

–6

–7

RL = 150Ω

VS = ±2.5V

VS = ±5V

VS = ±12V

Figure 29. AD8129 Frequency Response vs. Supply, RL = 150 Ω

0246

4-03

1

FREQUENCY (MHz)

GA

IN (d

B)

3001001

3

2

1

0

–1

–2

–3

–4

–5

–6

–7

G = +20VOUT = 0.3V p-p

VS = ±5V, ±12V

VS = ±2.5V

10


G = +20, VOUT = 0.3 V p-p

0246

4-03

2

FREQUENCY (MHz)

GA

IN (d

B)

3001001

3

2

1

0

–1

–2

–3

–4

–5

–6

–710

G = +20VOUT = 2V p-p

VS = ±2.5V

VS = ±5V, ±12V


G = +20, VOUT = 2 V p-p

0246

4-03

3

FREQUENCY (MHz)

GA

IN (d

B)

3001001 10

0.8

0.6

0.4

0.2

0

–0.2

0.2

0

–0.2

–0.4

–0.6

G = +10VS = ±5V 2kΩ/221Ω

909Ω/100Ω

499Ω/54.9Ω

2kΩ/221Ω

909Ω/100Ω499Ω/54.9Ω

SOIC

μSOIC

Figure 32. AD8129 Fine Scale Response vs. SOIC and MSOP

for Various RF/RG

0246

4-03

4

FREQUENCY (MHz)

GA

IN (d

B)

301 10

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

G = +20RL = 1kΩ

VS = ±2.5V

VS = ±5V

VS = ±12V

Figure 33. AD8129 Fine Scale Response vs. Supply

0246

4-03

5

FREQUENCY (MHz)

GA

IN (d

B)

301 100.1

0.3

0

–0.3

–0.4

–0.5

–0.6

–0.7

–0.2

–0.1

0.1

0.2G = +20RL = 150Ω

VS = ±5V, ±12V

VS = ±2.5V

Figure 34. AD8129 Fine Scale Response vs. Supply

AD8129/AD8130


0246

4-03

6

FREQUENCY (MHz)

GA

IN (d

B)

1 30010 100

3

0

–3

–4

–5

–6

–7

–2

–1

1

2

VS = ±5V, ±12V

VS = ±2.5V

G = +20RL = 150Ω


G = +20, RL = 150 Ω

0246

4-03

7

FREQUENCY (MHz)

GA

IN (d

B)

0.1 1 10

0.2

–0.1

–0.4

–0.5

–0.6

–0.7

–0.8

–0.3

–0.2

0

0.1

VS = ±2.5V

VS = ±12V

VS = ±12V

VS = ±5V

VOUT = 2V p-p

G = +50G = +100

Figure 36. AD8129 Fine Scale Response vs. Supply,

G = +50, G = +100, VOUT = 2 V p-p

0246

4-03

8

FREQUENCY (MHz)

GA

IN (d

B)

0.1 1 10

3

0

–3

–4

–5

–6

–7

–2

–1

1

2

50

VOUT = 2V p-p

G = +100 G = +50

VS = ±2.5V

VS = ±5V

VS = ±12V


G = +50, G = +100, VOUT = 2 V p-p

0246

4-03

9

FREQUENCY (MHz)

GA

IN (d

B)

0.1 1 10

3

0

–3

–4

–5

–6

–7

–2

–1

1

2

50

RL = 150Ω

G = +100 G = +50

VS = ±5VVS = ±2.5V

VS = ±12V


G = +50, G = +100, RL = 150 Ω

0246

4-04

0

FREQUENCY (MHz)

OU

TPU

T VO

LTA

GE

(dB

V)

12

6

0

–6

–12

–18

–24

–30

–36

–42

–4810 100 400

0dB = 1V rms

VS = ±5V

Figure 39. AD8129 Frequency Response for Various Output Levels

1

8

4

5

6

RFRG

TEK P6245FET PROBE

102050

100

RFG2kΩ2kΩ2kΩ2kΩ

221Ω105Ω41.2Ω20Ω

RL CL

50Ω

0246

4-04

1

RG

Figure 40. AD8129 Basic Frequency Response Test Circuit

AD8129/AD8130


AD8130 HARMONIC DISTORTION CHARACTERISTICS RL = 1 kΩ, CL = 2 pF, TA = 25°C, unless otherwise noted.

VS = ±12V

0246

4-04

2

1–90

–84

–78

–72

–66

–60

40FREQUENCY (MHz)

HD

2 (d

Bc)

10

VOUT = 1V p-p

G = +1

G = +2

VS = ±12V

VS = ±5V

Figure 41. AD8130 Second Harmonic Distortion vs. Frequency

G = +2

0246

4-04

3

1–84

–78

–72

–66

–60

–54

40FREQUENCY (MHz)

HD

2 (d

Bc)

10

VOUT = 2V p-p

G = +1VS = ±5V

VS = ±12V

VS = ±5VG = +1

VS = ±12V


0246

4-04

4

0.5–91

–85

–79

–73

–67

–61

1VOUT (V p-p)

HD

2 (d

Bc)

10

–55

G = +2

fC = 5MHz

G = +1

VS = ±5V

VS = ±12V

VS = ±5V

VS = ±12V

Figure 43. AD8130 Second Harmonic Distortion vs. Output Voltage

1–99

–93

–87

–81

–75

–69

10FREQUENCY (MHz)

HD

3 (d

Bc)

40

–63

–57

–51G = +1VS = ±5V

VS = ±5V

G = +2

G = +1

G = +1VS = ±12V

VOUT = 1V p-p

VS = ±12V

0246

4-04

5

Figure 44. AD8130 Third Harmonic Distortion vs. Frequency

1–93

–87

–81

–75

–69

–63

10FREQUENCY (MHz)

HD

3 (d

Bc)

40

–57

–51

–45

G = +1

0246

4-04

6

VOUT = 2V p-p

G = +2

VS = ±5V

G = +2, VS = ±12V

G = +2, VS = ±5V

VS = ±12V


0246

4-04

7

0.5–94

–88

–82

–76

–70

–64

1VOUT (V p-p)

HD

3 (d

Bc)

10

–58

–52

–46

G = +1

fC = 5MHz VS = ±12V

VS = ±5V

G = +2

VS = ±12V

VS = ±5V

Figure 46. AD8130 Third Harmonic Distortion vs. Output Voltage

AD8129/AD8130


0246

4-04

8

1–79

–73

–67

–61

–55

–49

10FREQUENCY (MHz)

HD

2 (d

Bc)

40

–43

G = +1

VS = ±2.5V

G = +1

G = +2

G = +2

VOUT = 2V p-p

VOUT = 1V p-p

0246

4-05

0

0 0.5 1.0 1.5 2.0 2.5 3.0–94

–88

–82

–76

–70

–64

VOUT (V p-p)

HD

(dB

c)

–58

–52

–46VS = ±2.5VfC = 5MHz

G = +2, HD3

G = +2, HD3

G = +1, HD3

G = +1, HD2

G = +2, HD2G = +2, HD2

Figure 49. AD8130 Harmonic Distortion vs. Output Voltage


02

464-

049

1–96

–90

–84

–78

–72

–66

10FREQUENCY (MHz)

HD

3 (d

Bc)

40

–60

–54

–48

–42VS = ±2.5V

VOUT = 2V p-p

VOUT = 1V p-p

G = +1

G = +2

G = +2

G = +1


AD8129/AD8130


AD8129 HARMONIC DISTORTION CHARACTERISTICS RL = 1 kΩ, CL = 2 pF, TA = 25°C, unless otherwise noted.

FREQUENCY (MHz)

HD

2 (d

Bc)

–51

1

–57

–63

–69

–75

–81

–8710 40

VOUT = 1V p-p

G = +10,VS = ±12V

G = +20,VS = ±12V

0246

4-05

1

G = +10,VS = ±5V

G = +20,VS = ±5V


FREQUENCY (MHz)

HD

2 (d

Bc)

–42

1

–48

–54

–60

–66

–72

–78

10 40

VOUT = 2V p-p

–84

G = +10

G = +20

0246

4-05

2

G = +10,VS = ±12V

G = +20,VS = ±12V

G = +10,VS = ±5V

G = +20,VS = ±5V


VOUT (V p-p)

HD

2 (d

Bc)

1 10

–62

–68

–74

–80

–86

–56

–50fC = 5MHz

0.5

0246

4-05

3

G = +10,VS = ±12V

G = +20,VS = ±12V

G = +10,VS = ±5V

G = +20,VS = ±5V

Figure 52. AD8129 Second Harmonic Distortion vs. Output Voltage

FREQUENCY (MHz)

HD

3 (d

Bc)

1 10 40–96

–66

–72

–78

–84

–90

–60

–54VOUT = 1V p-p

0246

4-05

4

G = +10,VS = ±12V

G = +20,VS = ±12V

G = +10,VS = ±5V

G = +20,VS = ±5V


FREQUENCY (MHz)

HD

3 (d

Bc)

1

–45

–51

–57

–63

–69

–75

–81

–8710 40

VOUT = 2V p-p

�

0246

4-05

5

G = +10,VS = ±12V

G = +20,VS = ±12V

G = +10,VS = ±5V

G = +20,VS = ±5V

G = +10,VS = ±12V

G = +10,VS = ±5V


VOUT (V p-p)

–48

–84

0.5

–54

–60

–66

–72

–78

1 10

fC = 5MHz

–90

–96

HD

3 (d

Bc)

0246

4-05

6

G = +20,VS = ±12V

G = +20,VS = ±5V

G = +10,VS = ±12V

G = +10,VS = ±5V

Figure 55. AD8129 Third Harmonic Distortion vs. Output Voltage

AD8129/AD8130


FREQUENCY (MHz)

HD

2 (d

Bc)

1

–44

–50

–56

–62

–68

–74

–8010 40

VS = ±2.5V

G = +20

G = +10

VOUT = 1V p-p

0246

4-05

7

VOUT = 2V p-p


FREQUENCY (MHz)

HD

3 (d

Bc)

1

–42

–48

–54

–60

–66

–72

–78

–84

10 40

VS = ±2.5V

–90

G = +20

G = +10

VOUT = 1V p-p

0246

4-05

8

VOUT = 2V p-p


VOUT (V p-p)

–50

0

–56

–62

–68

–74

–80

–860.5 1.0 1.5 2.0 2.5 3.0

VS = ±2.5VfC = 5MHz

G = +10HD3

HD

(dB

c)

0246

4-05

9

G = +20HD3

G = +10HD2

G = +20HD2

Figure 58. AD8129 Harmonic Distortion vs. Output Voltage

0246

4-06

0

–87

–81

–75

–69

–63

–57

VCM (V)

DIS

TOR

TIO

N (d

Bc)

–51

–45

–39

–5 –4 –3 –2 –1 0 1 2 3 4 5

HD2

HD3

G = +1VOUT = 2V p-pVS = ±5VRL = 1kΩfC = 5MHz

Figure 59. AD8130 Harmonic Distortion vs. Common-Mode Voltage

0246

4-06

1

–97

–91

–85

–79

–73

–67

RL (Ω)

DIS

TOR

TIO

N (d

Bc)

–61

100 1k

G = +1fC = 5MHz

VOUT = 1V p-p

VS = ±5V

VS = ±2.5V

HD2

HD3

VS = ±12VHD3

HD3

VS = ±5V, ±12VHD2

VS = ±2.5V

Figure 60. AD8130 Harmonic Distortion vs. Load Resistance

0246

4-06

2

–86

–80

–74

–68

–62

–56

RL (Ω)

DIS

TOR

TIO

N (d

Bc)

–50

100 1k

G = +1fC = 5MHz

VOUT = 2V p-p

HD2VS = ±2.5V

VS = ±5V, ±12VHD2

VS = ±2.5VHD3

VS = ±5V, ±12VHD3


AD8129/AD8130


0246

4-06

3

–78

–72

–66

–60

–54

–48

VCM (V)

DIS

TOR

TIO

N (d

Bc)

–42

–36

–5 –4 –3 –2 –1 0 1 2 3 4 5

HD3

HD2

G = +10VOUT = 2V p-pVS = ±5VRL = 1kΩfC = 5MHz

Figure 62. AD8129 Harmonic Distortion vs. Common-Mode Voltage

0246

4-06

4

–90

–84

–78

–72

–68

–60

RL (Ω)

DIS

TOR

TIO

N (d

Bc)

–54

100 1k

HD3

VS = ±2.5V

–48G = +10fC = 5MHz

VOUT = 1V p-p

VS = ±2.5V

VS = ±12V

VS = ±12VVS = ±5V

VS = ±5VHD2


0246

4-06

5

–80

–74

–68

–62

–56

–50

RL (Ω)

DIS

TOR

TIO

N (d

Bc)

–44

100 1k

HD3

G = +10fC = 5MHz

VOUT = 2V p-p

VS = ±2.5V

VS = ±12V

VS = ±5V

VS = ±2.5V

VS = ±12V

VS = ±5V


0246

4-06

6

VCM

200Ω

1:2

12

1020

RFG RG

0Ω499Ω2kΩ2kΩ

–499Ω221Ω105Ω

MINI-CIRCUITS®:# T4-6T, fC ≤ 10MHz# TC4-1W, fC > 10MHz

RG RF

RL

RLCL

Figure 65. AD8129/AD8130 Basic Distortion Test Circuit, VCM = 0 V, Unless Otherwise Noted

0246

4-06

7

0.1

1.0

10

FREQUENCY (Hz)

100

10 100k100 1k 10k 1M 10M

CU

RR

ENT

NO

ISE

(pA

/√H

z)

Figure 66. AD8129/AD8130 Input Current Noise vs. Frequency

0246

4-06

8

1

10

FREQUENCY (Hz)

100

CU

RR

ENT

NO

ISE

(nV/√H

z)

10 100k100 1k 10k 1M 10M

AD8130

AD8129

Figure 67. AD8129/AD8130 Input Voltage Noise vs. Frequency

AD8129/AD8130


FREQUENCY (Hz)

CO

MM

ON

-MO

DE

REJ

ECTI

ON

(dB

)

–30

10k 100M100k 1M 10M

–40

–50

–60

–70

–80

–90

–100

–110

–120

VS = ±5V, ±12V

0246

4-06

9

VS = ±2.5V

Figure 68. AD8130 Common-Mode Rejection vs. Frequency

FREQUENCY (Hz)

POW

ER S

UPP

LY R

EJEC

TIO

N (d

B)

0

1k

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010k 100k 1M 10M 100M

VS = ±2.5V

0246

4-07

0

VS = ±5V

VS = ±12V

Figure 69. AD8130 Positive Power Supply Rejection vs. Frequency

FREQUENCY (Hz)

POW

ER S

UPP

LY R

EJEC

TIO

N (d

B)

0

1k

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010k 100k 1M 10M 100M

VS = ±12V

0246

4-07

1

VS = ±5V

VS = ±2.5V

Figure 70. AD8130 Negative Power Supply Rejection vs. Frequency

FREQUENCY (Hz)

CO

MM

ON

-MO

DE

REJ

ECTI

ON

(dB

)

–30

10k 100M100k 1M 10M

–40

–50

–60

–70

–80

–90

–100

–110

–120

VS = ±5V, ±12V� �

VS = ±2.5V

0246

4-07

2

Figure 71. AD8139 Common-Mode Rejection vs. Frequency

FREQUENCY (Hz)

POW

ER S

UPP

LY R

EJEC

TIO

N (d

B)

0

1k

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010k 100k 1M 10M 100M

0246

4-07

3

VS = ±12V

VS = ±5V

VS = ±2.5V

Figure 72. AD8129 Positive Power Supply Rejection vs. Frequency

FREQUENCY (Hz)

POW

ER S

UPP

LY R

EJEC

TIO

N (d

B)

0

1k

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010k 100k 1M 10M 100M

VS = ±5V

VS = ±2.5V

0246

4-07

4

VS = ±12V

Figure 73. AD8129 Negative Power Supply Rejection vs. Frequency

AD8129/AD8130


FREQUENCY (Hz)

OPE

N-L

OO

P G

AIN

(dB

)

80

1k

70

60

50

40

30

20

10

0

–1010k 100k 1M 10M 100M 300M

180

135

90

45

0

PHA

SE M

AR

GIN

(Deg

rees

)

φM = 58°

2pF

+

–

+

–

PHASE

GAIN

0246

4-07

5

1kΩ

VOUT

100Ω

VIN

1kΩ

Figure 74. AD8130 Open-Loop Gain and Phase vs. Frequency

FREQUENCY (Hz)

OPE

N-L

OO

P G

AIN

(dB

)

80

1k

70

60

50

40

30

20

10

0

90

10k 100k 1M 10M 100M 300M

180

135

90

45

0

PHA

SE M

AR

GIN

(Deg

rees

)

2pF

1kΩ

VOUT

100Ω

VIN

1kΩ

PHASE

GAIN

0246

4-07

6

φM = 56°

Figure 75. AD8129 Open-Loop Gain and Phase vs. Frequency

FREQUENCY (Hz)

OU

TPU

T IM

PED

AN

CE

(Ω)

100

1k

10

1

100m

10m

1m10k 100k 1M 10M 100M

AD8130, G = +1

AD8129, G = +10

VS = ±5V

0246

4-07

7

Figure 76. Closed-Loop Output Impedance vs. Frequency

AD8129/AD8130


AD8130 TRANSIENT RESPONSE CHARACTERISTICS G = +1, RL = 1 kΩ, CL = 2 pF, VS = ±5 V, TA = 25°C, unless otherwise noted.

0246

4-07

8

5.00ns250mV


Figure 77. AD8130 Transient Response, VS = ±2.5 V, VOUT = 1 V p-p

0246

4-07

9

5.00ns250mV

VOUT = 1V p-pVS = ±5V

Figure 78. AD8130 Transient Response, VS = ±5 V, VOUT = 1 V p-p

0246

4-08

0

5.00ns250mV



0246

4-08

1

5.00ns50mV


VS = ±12V

VS = ±5V

Figure 80. AD8130 Transient Response vs. Supply, VOUT = 0.2 V p-p

0246

4-08

2

VOUT = 1V p-pCL = 5pF

VS = ±2.5VVS = ±5V

VS = ±12V

5.00ns250mV

Figure 81. AD8130 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF

0246

4-08

3

5.00ns500mV

VS = ±2.5V

VS = ±12V

VS = ±5V



AD8129/AD8130


0246

4-08

4

10.00ns50mV

VOUT = 0.2 V p-pCL = 10pFCL = 5pF

CL = 2pF

Figure 83. AD8130 Transient Response vs. Load Capacitance, VOUT = 0.2 V p-p

0246

4-08

5

5.00ns500mV

0.5V p-p

2V p-p

1V p-p

Figure 84. AD8130 Transient Response vs. Output Amplitude, VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p

0246

4-08

6

5.00ns1.00V

1V p-p

2V p-p

4V p-p

Figure 85. AD8130 Transient Response vs. Output Amplitude, VOUT = 1 V p-p, 2 V p-p, 4 V p-p

250mV 5.00ns

VOUT = 1V p-pG = +2

VS = ±5V, CL = 10pF

0246

4-08

7

VS = ±5V, CL = 2pF

Figure 86. AD8130 Transient Response vs. Load Capacitance, VOUT = 1 V p-p, G = +2

500mV 5.00ns

0246

4-08

8

VOUT = 2V p-pG = +2

VS = ±5V

VS = ±12V

Figure 87. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, G = +2

2.00V 5.00ns

0246

4-08

9

VOUT = 8V p-p

CL = 10pF

CL = 2pF

G = +2VS = ±5V

Figure 88. AD8130 Transient Response vs. Load Capacitance, VOUT = 8 V p-p

AD8129/AD8130


1.00V 10.0ns

4V p-p

2V p-p

1V p-p

0246

4-09

3

G = +5VS = ±5VCL = 10pF

1.00V 5.00ns

VOUT

VIN

0246

4-09

0

Figure 89. AD8130 Transient Response with +3 V Common-Mode Input

Figure 92. AD8130 Transient Response vs. Output Amplitude

2.00V 10.0ns

VOUT = 8V p-p

0246

4-09

4

G = +5VS = ±5VCL = 10pF

1.00V 5.00ns

VOUT

VIN

0246

4-09

1

Figure 90. AD8130 Transient Response with −3 V Common-Mode Input

Figure 93. AD8130 Transient Response, VOUT = 8 V p-p, G = +5, VS = ±5 V

2.50V 5.00ns

G = +2VS = ±12V

VOUT = 10V p-p

0246

4-09

2

5.00V 10.0ns

VOUT = 20V p-p

0246

4-09

5

G = +5VS = ±12VCL = 10pF

Figure 94. AD8130 Transient Response, VOUT = 20 V p-p, G = +5, VS = ±12 V Figure 91. AD8130 Transient Response, VOUT = 10 V p-p, G = +2, VS = ±12 V

AD8129/AD8130


AD8129 TRANSIENT RESPONSE CHARACTERISTICS G = +10, RF = 2 kΩ, RG = 221 Ω, RL = 1 kΩ, CL = 1 pF, VS = ±5 V, TA = 25°C, unless otherwise noted.

250mV 5.00ns


0246

4-09

6

Figure 95. AD8129 Transient Response, VS = ±2.5 V, VOUT = 1 V p-p

250mV 5.00ns


0246

4-09

7


250mV 5.00ns

0246

4-09

8



100mV 5.00ns


VS = ±5V

VS = ±12V

0246

4-09

9

Figure 98. AD8129 Transient Response vs. Supply, VOUT = 0.4 V p-p

250mV 5.00ns


VS = ±2.5V

VS = ±5V

VS = ±12V

0246

4-10

0


0246

4-10

1

250mV 5.00ns


VS = ±5V

VS = ±2.5V

VS = ±12V


AD8129/AD8130


100mV 5.00ns

VOUT = 0.4V p-p

CL = 10pF

CL = 5pF

CL = 2pF

0246

4-10

2

Figure 101 Transient Response vs. Load Capacitance, VOUT = 0.4 V p-p

500mV 5.00ns

VO = 2V p-p

VO = 1V p-p

VO = 0.5V p-p

0246

4-10

3

Figure 102. Transient Response vs. Output Amplitude, VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p

1.00V 5.00ns

VO = 4V p-p

VO = 2V p-p

VO = 1V p-p

0246

4-10

4

Figure 103. Transient Response vs. Output Amplitude, VOUT = 1 V p-p, 2 V p-p, 4 V p-p

250mV 5.00ns

G = +20CL = 20pFVOUT = 1V p-p

0246

4-10

5

Figure 104. AD8129 Transient Response, VOUT = 1 V p-p, VS = ±2.5 V to ±12 V

500mV 5.00ns

G = +20CL = 20pF

VOUT = 2V p-p

0246

4-10

6

Figure 105. AD8129 Transient Response, VOUT = 2 V p-p, VS = ±5 V

2.00V 5.00ns

G = +20CL = 20pF

0246

4-10

7

VOUT = 8V p-p

Figure 106. AD8129 Transient Response, VOUT = 8 V p-p, VS = ±5 V

AD8129/AD8130


1.00V 5.00ns

VIN

VOUT

0246

4-10

8

Figure 107. AD8129 Transient Response with +3.5 V Common-Mode Input

VOUT

VIN

0246

4-10

9

Figure 108. AD8129 Transient Response with −3.5 V Common-Mode Input

2.50V 5.00ns

G = +20VS = ±12VCL = 20pF

VOUT = 10V p-p

0246

4-11

0

Figure 109. AD8129 Transient Response, VOUT = 10 V p-p, G = +20

1.00V 12.5ns

4V p-p

2V p-p

1V p-p

0246

4-11

1

G = +50VS = ±5VCL = 20pF

Figure 110. AD8129 Transient Response vs. Output Amplitude, VOUT = 1 V p-p, 2 V p-p, 4 V p-p

2.00V 12.5ns

VOUT = 8V p-p

0246

4-11

2

G = +50VS = ±5VCL = 20pF


5.00V 12.5ns

VOUT = 20V p-p

0246

4-11

3

G = +50VS = ±12VCL = 10pF


AD8129/AD8130


G = +1VS = ±5V

23

20

17

14

11–5 –4 –3 –2 –1 0 1 2 3 4 5

DIFFERENTIAL INPUT (V)

SUPP

LY C

UR

REN

T (m

A)

0246

4-11

4

Figure 113. AD8130 DC Power Supply Current vs. Differential Input Voltage

37

31

25

19

13–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0


SUPP

LY C

UR

REN

T (m

A)

0246

4-11

5

G = +1VS = ±10V

Figure 114. AD8129 DC Power Supply Current vs. Differential Input Voltage

TEMPERATURE(°C)

DIF

FER

ENTI

AL

INPU

T (V

)

3.0

–50

0

–1.0

–2.0

–3.0

1.0

2.0

–35 –20 –5 10 25 40 55 70 85 100

AD8130

AD8129

AD8130

VOUT = 100mV AC @ 1kHz

0246

4-11

6

AD8129

Figure 115. AD8129/AD8130 Input Differential Voltage Range vs.

Temperature, 1% Gain Compression

G = +1VS = ±5VRL = 1kΩ

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0OUTPUT VOLTAGE (V)

GA

IN N

ON

LIN

EAR

ITY

(0.0

05%

/DIV

)

0246

4-11

7

Figure 116. AD8130 Gain Nonlinearity, VOUT = 2 V p-p

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5OUTPUT VOLTAGE (V)

GA

IN N

ON

LIN

EAR

ITY

(0.0

8%/D

IV)

0246

4-11

8

G = +1VS = ±5VRL = 1kΩ


4

2

0

–2

–4–5 –4 –3 –2 –1 0 1 2 3 4 5


V OU

T (V

)

3

1

–1

–3

0246

4-11

9

VS = ±5V

Figure 118. AD8130 Differential Input Clipping Level

AD8129/AD8130


–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0OUTPUT VOLTAGE (V)

GA

IN N

ON

LIN

EAR

ITY

(0.0

05%

/DIV

)

0246

4-12

0

G = +10VS = ±5VRL = 1kΩ


–5 –4 –3 –2 –1 0 1 2 3 4 5OUTPUT VOLTAGE (V)

GA

IN N

ON

LIN

EAR

ITY

(0.2

%/D

IV)

0246

4-12

1

G = +10VS = ±12VRL = 1kΩ


8

4

0

–4

–8–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0


OU

TPU

T VO

LTA

GE

(V)

6

2

–2

–6

VS = ±10V

0246

4-12

2

Figure 121. AD8129 Differential Input Clipping Level

TOTAL SUPPLY VOLTAGE (V)

SUPP

LY C

UR

REN

T (m

A)

15

90 3010 15 20 25

14

13

12

11

10

0246

4-12

3

5

Figure 122. Quiescent Power Supply Current vs. Total Supply Voltage

TEMPERATURE (°C)

SUPP

LY C

UR

REN

T (m

A)

17

–50

16

15

14

13

12

11

10

9

8

7–35 –20 –5 10 25 40 55 70 85 100

VS = ±2.5

0246

4-12

4

VS = ±5

VS = ±12

115125

Figure 123. Quiescent Power Supply Current vs. Temperature

TEMPERATURE (°C)

INPU

T B

IAS

CU

RR

ENT

(μA

)

0.60

0.15–50

0.45

0.30

–35 –20 –5 10 25 40 55 70 85 100

INPU

T O

FFSE

T C

UR

REN

T (n

A)

40

10

30

20

IB

IOS

0246

4-12

5

Figure 124. Input Bias Current and Input Offset Current vs. Temperature

AD8129/AD8130


VOUT = 100mVAC AT 1kHz

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

INPU

T C

OM

MO

N M

OD

E (V

)

–50 –35 –20 –5 10 25 40 55 70 85 100TEMPERATURE (°C)

AD8130AD8129

AD8130AD8129

VS = 5V

0246

4-12

6

Figure 125. Common-Mode Voltage Range vs. Temperature,

Typical 1% Gain Compression

TEMPERATURE (°C)

INPU

T C

OM

MO

N M

OD

E (V

)

4.00

–50

3.75

3.50

3.25

3.00

2.75

–3.00

–3.25

–3.50

–3.75

–4.00–35 –20 –5 10 25 40 55 70 85 100

AD8130AD8129

�

AD8130

AD8129

0246

4-12

7

VS = ±5V




TEMPERATURE (°C)

INPU

T C

OM

MO

N M

OD

E (V

)

11.0

–50

10.5

10.0

9.5

9.0

8.5

–9.0

–9.5

–10.0

–10.5

–11.0–35 –20 –5 10 25 40 55 70 85 100

AD8130AD8129

VS = ±12V

AD8130

AD8129


0246

4-12

8



OUTPUT CURRENT (mA)

OU

TPU

T VO

LTA

GE

(V)

4.0

0

3.5

3.0

2.0

1.5

1.05 10 15 20 25 30 35 40

SINKING

VS = 5V

SOURCING

0246

4-12

9


+25°C–40°C+100°C

Figure 128. Output Voltage Range vs. Output Current,


OUTPUT CURRENT (mA)

OU

TPU

T VO

LTA

GE

(V)

4.0

0

3.5

3.0

–3.0

–3.5

–4.040

0246

4-13

0

VS = ±5V


5 10 15 20 25 30 35

+25°C–40°C+100°C



OUTPUT CURRENT (mA)

11

0

10

9

–9

–10

–115 10 15 20 25 30 35 40

VS = ±12V

0246

4-13

1

OU

TPU

T VO

LTA

GE

(V)

+25°C–40°C+100°C



AD8129/AD8130


THEORY OF OPERATION The AD8129/AD8130 use an architecture called active feedback, which differs from that of conventional op amps. The most obvious differentiating feature is the presence of two separate pairs of differential inputs compared with a conventional op amp’s single pair. Typically, for the active feedback architecture, one of these input pairs is driven by a differential input signal, while the other is used for the feedback. This active stage in the feedback path is where the term active feedback is derived.

The active feedback architecture offers several advantages over a conventional op amp in many types of applications. Among these are excellent common-mode rejection, wide input common-mode range, and a pair of inputs that are high impedance and completely balanced in a typical application. In addition, while an external feedback network establishes the gain response as in a conventional op amp, its separate path makes it completely independent of the signal input. This eliminates any interaction between the feedback and input circuits, which traditionally causes problems with CMRR in conventional differential-input op amp circuits.

Another advantage is the ability to change the polarity of the gain merely by switching the differential inputs. A high input-impedance inverting amplifier can be made. Besides a high input impedance, a unity-gain inverter with the AD8130 has a noise gain of unity. This produces lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity-gain inverter.

The two differential input stages of the AD8129/AD8130 are each transconductance stages that are well matched. These stages convert the respective differential input voltages to internal currents. The currents are then summed and converted to a voltage, which is buffered to drive the output. The compensation capacitor is in the summing circuit.

When the feedback path is closed around the part, the output drives the feedback input to the voltage that causes the internal currents to sum to 0. This occurs when the two differential inputs are equal and opposite; that is, their algebraic sum is 0.

In a closed-loop application, a conventional op amp has its differential input voltage driven to near 0 under nontransient conditions. The AD8129/AD8130 generally has differential input voltages at each of its input pairs, even under equilibrium conditions. As a practical consideration, it is necessary to limit the differential input voltage internally with a clamp circuit.

Therefore, the input dynamic ranges are limited to about 2.5 V for the AD8130 and 0.5 V for the AD8129 (see the AD8129/AD8130 Specifications section for more detail). For this and other reasons, it is not recommended to reverse the input and feedback stages of the AD8129/AD8130, even though some apparently normal functionality may be observed under some conditions. A few simple circuits can illustrate how the active feedback architecture of the AD8129/AD8130 operates.

OP AMP CONFIGURATION If only one of the input stages of the AD8129/AD8130 is used, it functions very much like a conventional op amp (see Figure 131). Classical inverting and noninverting op amps circuits can be created, and the basic governing equations are the same as for a conventional op amp. The unused input pins form the second input and should be shorted together and tied to ground or a midsupply voltage when they are not used.

–VS

PD +VS+

+

RF

RG

–V

VOUTVIN

+V

6

25

4

8

1

3 70.1μF 10μF

0.1μF 10μF

0246

4-13

2

NOTES1. THIS CIRCUIT IS PROVIDED TO DEMONSTRATE DEVICE OPERATION. IT IS NOT RECOMMENDED TO USE THIS CIRCUIT IN PLACE OF AN OP AMP.

Figure 131. With Both Inputs Grounded, the Feedback Stage Functions like

an Op Amp: VOUT = VIN (1 + RF/RG).

With the unused pair of inputs shorted, there is no differential voltage between them. This dictates that the differential input voltage of the used inputs is also 0 for closed-loop applications. Because this is the governing principle of conventional op amp circuits, an active feedback amplifier can function as a conventional op amp under these conditions.

Note that this circuit is presented only for illustration purposes to show the similarities of the active feedback architecture functionality to conventional op amp functionality. If it is desired to design a circuit that can be created from a conven-tional op amp, it is recommended to choose a conventional op amp with specifications that are better suited to that application. These op amp principles are the basis for offsetting the output, as described in the Output Offset/Level Translator section.

AD8129/AD8130


APPLICATIONS BASIC GAIN CIRCUITS The gain of the AD8129/AD8130 can be set with a pair of feedback resistors. The basic configuration is shown in Figure 132. The gain equation is the same as that of a conventional op amp: G = 1 + RF/RG. For unity-gain applications using the AD8130, RF can be set to 0 (short circuit), and RG can be removed (see Figure 133). The AD8129 is compensated to operate at gains of 10 and higher; therefore, shorting the feedback path to obtain unity gain causes oscillation.

RF

RG

–V

VOUT

+V

VIN

–VS

PD +VS+

+

AD8129/AD8130

6

25

4

8

1

3 7

0.1μF 10μF

0.1μF 10μF02

464-

133

Figure 132. Basic Gain Circuit: VOUT = VIN (1 + RF/RG)

0.1μF–V

VOUT

+V

0.1μF 10μF

VIN

AD8130

–VS

PD +VS+

+6

25

4

8

13 7

10μF

0246

4-13

4

Figure 133. An AD8130 with Unity Gain

The input signal can be applied either differentially or in a single-ended fashion—all that matters is the magnitude of the differential signal between the two inputs. For single-ended input applications, applying the signal to the +IN with −IN grounded creates a noninverting gain, while reversing these connections creates an inverting gain. Because the two inputs are high impedance and matched, both of these conditions provide the same high input impedance. Thus, an advantage of the active feedback architecture is the ability to make a high input impedance inverting op amp. If conventional op amps are used, a high impedance buffer followed by an inverting stage is needed. This requires two op amps.

TWISTED-PAIR CABLE, COMPOSITE VIDEO RECEIVER WITH EQUALIZATION USING AN AD8130 The AD8130 has excellent common-mode rejection at its inputs. This makes it an ideal candidate for a receiver for signals that are transmitted over long distances on twisted-pair cables. Category 5 cables are very common in office settings and are extensively used for data transmission. These cables can also be used for the analog transmission of signals such as video.

These long cables pick up noise from the environment they pass through. This noise does not favor one conductor over another and therefore is a common-mode signal. A receiver that rejects the common-mode signal on the cable can greatly enhance the signal-to-noise ratio performance of the link.

The AD8130 is also very easy to use as a differential receiver, because the differential inputs and the feedback inputs are entirely separate. This means that there is no interaction between the feedback network and the termination network, as there would be in conventional op amp types of receivers.

Another issue with long cables is that there is more attenuation of the signal at longer distances. Attenuation is also a function of frequency; it increases to roughly the square root of frequency.

For good fidelity of video circuits, the overall frequency response of the transmission channel should be flat vs. frequency. Because the cable attenuates the high frequencies, a frequency-selective boost circuit can be used to undo this effect. These circuits are called equalizers.

An equalizer uses frequency-dependent elements (Ls and Cs) to create a frequency response that is the opposite of the rest of the channel’s response to create an overall flat response. There are many ways to create such circuits, but a common technique is to put the frequency-selective elements in the feedback path of an op amp circuit. The AD8130 in particular makes this easier than other circuits, because, once again, the feedback path is completely independent of the input path and there is no interaction.

The circuit in Figure 134 was developed as a receiver/equalizer for transmitting composite video over 300 meters of Category 5 cable. This cable has an attenuation of approximately 20 dB at 10 MHz for 300 meters. At 100 MHz, the attenuation is approximately 60 dB (see Figure 135).

AD8129/AD8130


RF1kΩ 0.1μF 10μF

–V

VOUT

+V

0.1μF 10μF

VIN

R1100Ω RG

499Ω

–VS

PD +VS+

+

C1200pF

AD8130

100Ω

6

25

4

8

1

3 7

0246

4-13

5

Figure 134. An Equalizer Circuit for Composite Video Transmissions

over 300 Meters of Category-5 Cable

20

10

–10

–20

–30

–40

–50

–60

–70

–80

FREQUENCY (Hz)

I/O R

ESPO

NSE

0

10k 100k 1M 10M 100M

0246

4-13

6

Figure 135. Transmission Response of 300 Meters of Category-5 Cable

The feedback network is between Pin 6 and Pin 5 and from Pin 5 to ground. C1 and RF create a corner frequency of about 800 kHz. The gain increases to provide about 15 dB of boost at 8 MHz. The response of this circuit is shown in Figure 136.

20

10

–10

–20

–30

–40

–50

–60

–70

–80

FREQUENCY (Hz)

I/O R

ESPO

NSE

0

10k 100k 1M 10M 100M

0246

4-13

7

Figure 136. Frequency Response of Equalizer Circuit

It is difficult to calculate the exact component values via strictly mathematical means, because the equations for the cable attenuation are approximate and have functions that are not simply related to the responses of RC networks. The method used in this design was to approximate the required response via graphical means from the frequency response and then select components that would approximate this response. The circuit was then built, measured, and finally adjusted to obtain an acceptable response—in this case, flat to 9 MHz to within approximately 1 dB (see Figure 137).

20

10

–10

–20

–30

–40

–50

–60

–70

–80

FREQUENCY (Hz)

I/O R

ESPO

NSE

0

10k 100k 1M 10M 100M

0246

4-13

8

Figure 137. Combined Response of Cable Plus Equalizer

OUTPUT OFFSET/LEVEL TRANSLATOR The circuit in Figure 133 has the reference input (Pin 4) tied to ground, which produces a ground-referenced output signal. If it is desired to offset the output voltage from ground, the REF input can be used (see Figure 138). The level VOFFSET appears at the output with unity gain.

0.1μF–V

VOUT = VIN +VOFFSET

+V

0.1μF 10μF

VIN

VOFFSET–VS

PD +VS+

+

AD8130

10μF

6

25

4

8

1

3 702

464-

139

Figure 138. The Voltage Applied to Pin 4 to the Unity-Gain Output Voltage

Produced by VIN

If the circuit has a gain higher than unity, the gain must be factored in. If RG is connected to ground, the voltage applied to REF is multiplied by the gain of the circuit and appears at the output—just like a noninverting conventional op amp. This situation is not always desirable; the user may want VOFFSET to appear at the output with unity gain.

AD8129/AD8130


One way to accomplish this is to drive both REF and RG with the desired offset signal (see Figure 139). Superposition can be used to solve this circuit. First, break the connection between VOFFSET and RG. With RG grounded, the gain from Pin 4 to VOUT is 1 + RF/RG. With Pin 4 grounded, the gain though RG to VOUT is −RF/RG. The sum of these is 1. If VREF is delivered from a low impedance source, this works fine. However, if the delivered offset voltage is derived from a high impedance source, such as a voltage divider, its impedance affects the gain equation. This makes the circuit more complicated because it creates an interaction between the gain and offset voltage.

VOUT =VIN × (1 + RF/RG) + VOFFSET

–V

+V

VIN

VOFFSET

–VS

PD +VS+

+

RF

RG

AD8129/AD8130

6

25

4

8

1

3 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

0

Figure 139. In this Circuit, VOFFSET Appears at the Output with Unity Gain. This

Circuit Works Well if the VOFFSET Source Impedance Is Low.

A way around this is to apply the offset voltage to a voltage divider whose attenuation factor matches the gain of the amplifier and then apply this voltage to the high impedance REF input. This circuit first divides the desired offset voltage by the gain, and the amplifier multiplies it back up to unity (see Figure 140).

VOUT =VIN × (1 + RF/RG) + VOFFSET

–V

+V

VIN

–VS

PD +VS+

+

RFRG

RG

VOFFSETRF

AD8129/AD8130

6

2

5

4

8

1

3 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

1

Figure 140. Adding an Attenuator at the Offset Input Causes It to Appear at

the Output with Unity Gain.

RESISTORLESS GAIN OF 2 The voltage applied to the REF input (Pin 4) can also be a high bandwidth signal. If a unity-gain AD8130 has both +IN and REF driven with the same signal, there is unity gain from VIN and unity gain from VREF. Thus, the circuit has a gain of 2 and requires no resistors (see Figure 141).

VOUT

–V

+V

VIN

–VS

PD +VS+

+

AD8130

6

25

4

8

1

3 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

2

Figure 141. Gain-of-2 Connections with No Resistors

SUMMER A general summing circuit can be made by the previous technique. A unity-gain configured AD8130 has one signal applied to +IN, while the other signal is applied to REF. The output is the sum of the two input signals (see Figure 142).

VOUT = V1 + V2

V1

V2

–V

+V

–VS

+VS+

+

AD8130

6

25

4

8

1

3 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

3

PD

Figure 142. A Summing Circuit that is Noninverting

with High Input Impedance

This circuit offers several advantages over a conventional op amp inverting summing circuit. First, the inputs are both high impedance and the circuit is noninverting. It would require significant additional circuitry to make an op amp summing circuit that has high input impedance and is noninverting.

Another advantage is that the AD8130 circuit still preserves the full bandwidth of the part. In a conventional summing circuit, the noise gain is increased for each additional input, so the bandwidth response decreases accordingly. By this technique, four signals can be summed by applying them to two AD8130s and then summing the two outputs by a third AD8130.

CABLE-TAP AMPLIFIER It is often desirable to have a video signal drive several pieces of equipment. However, the cable should only be terminated once at its endpoint; therefore, it is not appropriate to have a termination at each device. A loop-through connection allows a device to tap the video signal while not disturbing it by any excessive loading.

AD8129/AD8130


Such a connection, also referred to as a cable-tap amplifier, can be simply made with an AD8130 (see Figure 143). The circuit is configured with unity gain, and if no output offset is desired, the REF pin is grounded. The negative differential input is connected directly to the shield of the cable (or an associated connector) at the point at which it wants to be tapped.

75Ω

75Ω

VIDEOIN

VOUT

–V

+V

–VS

PD +VS+

+

AD8130

6

25

4

8

1

3 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

4

Figure 143. The AD8130 Can Tap the Video Signal at Any Point Along the

Cable Without Loading the Signal.

The center conductor connects to the positive differential input of the AD8130. The amplitude of the video signal at this point is unity, because it is between the two termination resistors. The AD8130 provides a high impedance to this signal so that the signal is not disturbed. A buffered unity-gain version of the video signal appears at the output.

POWER-DOWN The AD8129/AD8130 have a power-down pin that can be used to lower the quiescent current when the amplifier is not being used. A logic low level on the PD pin causes the part to power down. Because there is no ground pin on the AD8129/AD8130, there is no logic reference to interface to standard logic levels. For this reason, the reference level for the PD input is VS. If the AD8129/AD8130 are run with VS = 5 V, there is direct compatibility with logic families. However, if VS is higher than this, a level-shift circuit is needed to interface to conventional logic levels. A simple level-shifting circuit that is compatible with common logic families is presented in Figure 144.

AD8129/AD8130

7+VS

+VS

3 PD

1kΩ

4.99kΩLOW =POWER-DOWN

2N2222OR EQ

0246

4-14

5

Figure 144. Circuit that Shifts the Logic Level When VS Is Not Equal to

Approximately 5 V.

EXTREME OPERATING CONDITIONS The AD8129/AD8130 are designed to provide high performance over a wide range of supply voltages. However, there are some extremes of operating conditions that have been observed to produce suboptimal results. One of these conditions occurs when the AD8130 is operated at unity gain with low supply voltage—less than approximately ±4 V.

At unity gain, the output drives FB directly. With supplies of ±VS less than approximately ±4 V at unity gain, the output can drive FB’s voltage too close to the rail for the circuit to stay properly biased. This can lead to a parasitic oscillation.

A way to prevent this is to limit the input signal swing with clamp diodes. Common silicon-junction signal diodes like the 1N4148 have a forward bias of approximately 0.7 V when about 1 mA of current flows through them. Two series pairs of such diodes connected antiparallel across the differential inputs can be used to clamp the input signal and prevent this condition. It should be noted that the REF input can also shift the output signal; therefore, this technique only works when REF is at ground or close to it (see Figure 145).

AD8130

VOUT

–V

+V

–VS

PD +VS+

+

VIN

1N4148

VIN

6

25

4

8

13 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

6

Figure 145. Clamping Diodes at the Input Limits the Input Swing Amplitude

AD8129/AD8130


Another problem can occur with the AD8129 operating at a supply voltage of greater than or equal to ±12 V. The architecture causes the supply current to increase as the input differential voltage increases. If the AD8129 differential inputs are overdriven too far, excessive current can flow into the device and potentially cause permanent damage.

A practical means to prevent this from occurring is to clamp the inputs differentially with a pair of antiparallel Schottky diodes (see Figure 146). These diodes have a lower forward voltage of approximately 0.4 V. If the differential voltage across the inputs is restricted to these conditions, no excess current is drawn by the AD8129 under these operating conditions.

If the supply voltage is restricted to less than ±11 V, the internal clamping circuit limits the differential voltage and excessive supply current is not drawn. The external clamp circuit is not needed.

VIN

AGILENTHSMS 2822

1 2

3

VOUT

–V

+V

–VS

PD +VS+

+VIN

AD8129

6

25

4

8

13 7

0.1μF 10μF

0.1μF 10μF

0246

4-14

7

Figure 146. Schottky Diodes Across the Inputs

Limits the Input Differential Voltage

In both circuits, the input series resistors function to limit the current through the diodes when they are forward biased. As a practical matter, these resistors must be matched so that the CMRR is preserved at high frequencies. These resistors have minimal effect on the CMRR at low frequency.

POWER DISSIPATION The AD8129/AD8130 can operate with supply voltages from +5 V to ±12 V. The major reason for such a wide supply range is to provide a wide input common-mode range for systems that can require this. This would be encountered when significant common-mode noise couples into the input path. For applications that do not require a wide dynamic range for the input or output, it is recommended to operate with lower supply voltages.

The AD8129/AD8130 is also available in a very small 8-lead MSOP package. This package has higher thermal impedance than larger packages and operates at a higher temperature with the same amount of power dissipation. Certain operating conditions that are within the specifications range of the parts can cause excess power dissipation. Caution should be exercised.

The power dissipation is a function of several operating conditions, including the supply voltage, the input differential voltage, the output load, and the signal frequency.

A basic starting point is to calculate the quiescent power dissipation with no signal and no differential input voltage. This is just the product of the total supply voltage and the quiescent operating current. The maximum operating supply voltage is 26.4 V, and the quiescent current is 13 mA. This causes a quiescent power dissipation of 343 mW. For the MSOP package, the θJA specification is 142°C/W. Therefore, the quiescent power causes about a 49°C rise above ambient in the MSOP package.

The current consumption is also a function of the differential input voltage (see Figure 113 and Figure 114). This current should be added onto the quiescent current and then multiplied by the total supply voltage to calculate the power.

The AD8129/AD8130 can directly drive loads of as low as 100 Ω, such as a terminated 50 Ω cable. The worst-case power dissipation in the output stage occurs when the output is at midsupply. As an example, for a 12 V supply with the output driving a 250 Ω load to ground, the maximum power dissipation in the output occurs when the output voltage is 6 V. The load current is 6 V/250 Ω = 24 mA. This same current flows through the output across a 6 V drop from VS. It dissipates 144 mW. For the 8-lead MSOP package, this causes a temperature rise of 20°C above ambient. Although this is a worst-case number, it is apparent that this can be a considerable additional amount of power dissipation.

Several changes can be made to alleviate this. One is to use the standard 8-lead SOIC package. This lowers the thermal impedance to 121°C/W, which is a 15% improvement. Another is to use a lower supply voltage unless absolutely necessary.

Finally, do not use the AD8129/AD8130 when it is operating on high supply voltages to directly drive a heavy load. It is best to use a second op amp after the output stage. Some of the gain can be shifted to this stage so that the signal swing at the output of the AD8129/AD8130 is not too large.

AD8129/AD8130


LAYOUT, GROUNDING, AND BYPASSING The AD8129/AD8130 are very high speed parts that can be sensitive to the PCB environment in which they operate. Realizing their superior specifications requires attention to various details of standard high speed PCB design practice.

The first requirement is for a good solid ground plane that covers as much of the board area around the AD8129/AD8130 as possible. The only exception to this is that the ground plane around the FB pin should be kept a few millimeters away, and the ground should be removed from the inner layers and the opposite side of the board under this pin. This minimizes the stray capacitance on this node and helps preserve the gain flatness vs. frequency.

The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high frequency ceramic chip capacitors should be used, and the bypassing should be done with a capacitance value of 0.01 μF to 0.1 μF for each supply. Farther away, low frequency bypassing should be provided with 10 μF tantalum capacitors from each supply to ground.

The signal routing should be short and direct to avoid parasitic effects. Where possible, signals should be run over ground planes to avoid radiating or to avoid being susceptible to other radiation sources.

AD8129/AD8130


OUTLINE DIMENSIONS

0.25 (0.0098)0.17 (0.0067)

1.27 (0.0500)0.40 (0.0157)

0.50 (0.0196)0.25 (0.0099)× 45°

8°0°

1.75 (0.0688)1.35 (0.0532)

SEATINGPLANE

0.25 (0.0098)0.10 (0.0040)

41

8 5

5.00 (0.1968)4.80 (0.1890)

4.00 (0.1574)3.80 (0.1497)

1.27 (0.0500)BSC

6.20 (0.2440)5.80 (0.2284)

0.51 (0.0201)0.31 (0.0122)COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 147. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.800.600.40

8°0°

4

8

1

5

PIN 10.65 BSC

SEATINGPLANE

0.380.22

1.10 MAX

3.203.002.80

COPLANARITY0.10

0.230.08

3.203.002.80

5.154.904.65

0.150.00

0.950.850.75

Figure 148. 8-Lead Mini Small Outline Package [MSOP]

(RM-8) Dimensions shown in millimeters

AD8129/AD8130


ORDERING GUIDE Model Temperature Range1 Package Description Package Option Branding AD8129AR −40°C to +85°C 8-Lead SOIC R-8 AD8129AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8129AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8129ARZ2 −40°C to +85°C 8-Lead SOIC R-8 AD8129ARZ-REEL2 −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8129ARZ-REEL72 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8129ARM −40°C to +85°C 8-Lead MSOP RM-8 HQA AD8129ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HQA AD8129ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HQA AD8129ARMZ2 −40°C to +85°C 8-Lead MSOP RM-8 HQA# AD8129ARMZ-REEL2 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HQA# AD8129ARMZ-REEL72 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HQA# AD8130AR −40°C to +85°C 8-Lead SOIC R-8 AD8130AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8130AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8130ARZ2 −40°C to +85°C 8-Lead SOIC R-8 AD8130ARZ-REEL2 −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8130ARZ-REEL72 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8130ARM −40°C to +85°C 8-Lead MSOP RM-8 HPA AD8130ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HPA AD8130ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HPA AD8130ARMZ2 −40°C to +85°C 8-Lead MSOP RM-8 HPA# AD8130ARMZ-REEL2 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HPA# AD8130ARMZ-REEL72 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HPA# 1 Operating temperature range for ±5 V or +5 V operation is −40°C to +125°C. 2 Z = Pb-free part; # indicates lead-free, may be top or bottom marked.

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02464–0–11/05(C)

Documents

AD8129/AD8130 Low Cost 270 MHz Differential Receiver ... · Low Cost 270 MHz Differential Receiver Amplifiers AD8129/AD8130 Rev. C Information furnished by Analog Devices is believed