AD9445 14-Bit, 105/125 MSPS, IF Sampling ADC Data Sheet ... file14-Bit, 105/125 MSPS, IF Sampling ADC AD9445 Rev. 0 Information furnished by Analog Devices is believed to be accurate

14-Bit, 105/125 MSPS, IF Sampling ADC AD9445

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved.

FEATURES 125 MSPS guaranteed sampling rate (AD9445BSV-125) 78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p) 74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p) 77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p) 74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p) 73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p) 102 dBFS 2-tone SFDR with 30 MHz and 31 MHz 92 dBFS 2-tone SFDR with 170 MHz and 171 MHz 60 fsec rms jitter Excellent linearity

DNL = 0.25 LSB typical INL = 0.8 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available 3.3 V and 5 V supply operation

APPLICATIONS Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Medical imaging Communications instrumentation

GENERAL DESCRIPTION

The AD9445 is a 14-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip IF sampling track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates at up to a 125 MSPS conversion rate and is designed for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment.

The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.

FUNCTIONAL BLOCK DIAGRAM

CMOSOR

LVDSOUTPUTSTAGING

CLOCKAND TIMING

MANAGEMENT

AGND DRGND DRVDD

VREF

CLK+

VIN+

AD9445

VIN

CLKDCO

0548

9-00

1

AVDD1 AVDD2

DCS MODEDFSRF ENABLE

OUTPUT MODET/H

BUFFER14

PIPELINEADC

2

28

2

OR

D13 TO D0

REF

REFBSENSE REFT

Figure 1.

Optional features allow users to implement various selectable operating conditions, including input range, data format select, high IF sampling mode, and output data mode.

The AD9445 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range 40C to +85C.

PRODUCT HIGHLIGHTS

1. High performance: outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.

2. Ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an output clock simplifies data capture.

3. Packaged in a Pb-free, 100-lead TQFP/EP package.

4. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths.

5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.

6. RF enable pin allows users to configure the device for optimum SFDR when sampling frequencies above 210 MHz (AD9445-125) or 240 MHz (AD9445-105).

AD9445

Rev. 0 | Page 2 of 40

TABLE OF CONTENTS Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Terminology .......................................................................................9

Pin Configurations and Function Descriptions ......................... 10

Equivalent Circuits ......................................................................... 15

Typical Performance Characteristics ........................................... 16

Theory of Operation ...................................................................... 24

Analog Input and Reference Overview ................................... 24

Clock Input Considerations...................................................... 26

Power Considerations................................................................ 27

Digital Outputs ........................................................................... 27

Timing ......................................................................................... 27

Operational Mode Selection ..................................................... 28

Evaluation Board ............................................................................ 29

Outline Dimensions ....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

10/05Revision 0: Initial Version

AD9445


SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = 1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.

Table 1. AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full 7 +7 7 +7 mV 25C 3 3 mV Gain Error Full 3 +3 3 +3 % FSR 25C 2 +2 2 +2 % FSR Differential Nonlinearity (DNL)1 Full 0.6 0.25 +0.65 0.6 0.25 +0.65 LSB 5 5 Integral Nonlinearity (INL)1 25C 0.65 0.8 LSB Full 1.6 +1.6 2 +2 LSB

VOLTAGE REFERENCE Output Voltage VREF = 1.0 V Full 0.9 1.0 1.1 0.9 1.0 1.1 V Load Regulation @ 1.0 mA Full 2 2 mV Reference Input Current (External VREF = 1.6 V) Full A

INPUT REFERRED NOISE 25C 1.0 1.0 LSB rms ANALOG INPUT

Input Span VREF = 1.6 V Full 3.2 3.2 V p-p VREF = 1.0 V Full 2.0 2.0 V p-p

Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.1 3.9 3.1 3.9 V Input Resistance2 Full 1 1 k Input Capacitance2 Full 6 6 pF

POWER SUPPLIES Supply Voltage

AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V DRVDDLVDS Outputs Full 3.0 3.6 3.0 3.6 V DRVDDCMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V

Supply Current1 AVDD1 Full 335 364 384 424 mA AVDD21, 3 Full 169 196 172 199 mA IDRVDD1LVDS Outputs Full 63 78 63 78 mA IDRVDD1CMOS Outputs Full 14 14 mA

PSRR Offset Full 1 1 mV/V Gain Full 0.2 0.2 %/V

POWER CONSUMPTION LVDS Outputs Full 2.2 2.4 2.3 2.6 W CMOS Outputs (DC Input) Full 2.0 2.1 W

1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3 For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.

AD9445


AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = 1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted.

Table 2. AD9445BSVZ-105 AD9445BSVZ-125

Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)

fIN = 10 MHz 25C 74.3 74.1 dB fIN = 30 MHz 25C 73.3 74.3 72.9 73.8 dB Full 73 72.5 dB fIN = 170 MHz 25C 72.9 73.6 72.3 73.2 dB fIN = 225 MHz1 25C 72.2 73 72 72.9 dB Full 72.2 71.4 dB fIN = 300 MHz2 25C 71.4 72.1 71.3 72 dB fIN = 400 MHz2 25C 71 71 dB fIN = 450 MHz2 25C 70.5 70.5 dB fIN = 10 MHz (3.2 V p-p Input) 25C 77.6 77.3 dB fIN = 30 MHz (3.2 V p-p Input) 25C 77.5 77.3 dB fIN = 170 MHz (3.2 V p-p Input) 25C 76 76 dB fIN = 225 MHz (3.2 V p-p Input)1 25C 75.3 75.4 dB fIN = 300 MHz (3.2 V p-p Input)2 25C 73.7 73.5 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25C 74.2 73.9 dB fIN = 30 MHz 25C 73.2 74.2 72.8 73.7 dB Full 72.8 72.3 dB fIN = 170 MHz 25C 72.3 73.3 72.4 73.0 dB fIN = 225 MHz1 25C 71.4 72.5 71.9 72.5 dB Full 71.3 70.7 dB fIN = 300 MHz2 25C 70.2 71.7 69.3 71.5 dB fIN = 400 MHz2 25C 67.2 66.3 dB fIN = 450 MHz2 25C 65.2 64.3 dB fIN = 10 MHz (3.2 V p-p Input) 25C 77.4 76.9 dB fIN = 30 MHz (3.2 V p-p Input) 25C 77.3 76.8 dB fIN = 170 MHz (3.2 V p-p Input) 25C 75.7 75.4 dB fIN = 225 MHz (3.2 V p-p Input)1 25C 75.1 75.2 dB fIN = 300 MHz (3.2 V p-p Input)2 25C 72.5 71.8 dB

EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25C 12.2 12.2 Bits fIN = 30 MHz 25C 12.2 12.1 Bits fIN = 170 MHz 25C 12.1 12.0 Bits fIN = 225 MHz1 25C 12.0 12.0 Bits fIN = 300 MHz2 25C 11.8 11.8 Bits fIN = 400 MHz2 25C 11.7 11.7 Bits fIN = 450 MHz2 25C 11.6 11.6 Bits

AD9445


AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE

(SFDR, Second or Third Harmonic)

fIN = 10 MHz 25C 95 95 dBc fIN = 30 MHz 25C 84 92 85 94 dBc Full 83 82 dBc fIN = 170 MHz 25C 82 94 80 91 dBc fIN = 225 MHz1 25C 76 87 83 88 dBc Full 75 75 dBc fIN = 300 MHz2 25C 76 87 75 87 dBc fIN = 400 MHz2 25C 75 73 dBc fIN = 450 MHz2 25C 70 69 dBc fIN = 10 MHz (3.2 V p-p Input) 25C 92 92 dBc fIN = 30 MHz (3.2 V p-p Input) 25C 88 91 dBc fIN = 170 MHz (3.2 V p-p Input) 25C 86 86 dBc fIN = 225 MHz (3.2 V p-p Input)1 25C 81 80 dBc fIN = 300 MHz (3.2 V p-p Input)2 25C 77 76 dBc

WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS

fIN = 10 MHz 25C 97 97 dBc fIN = 30 MHz 25C 99 90 98 89 dBc Full 90 88 dBc fIN = 170 MHz 25C 99 92 93 85 dBc fIN = 225 MHz1 25C 94 88 94 84 dBc Full 86 80 dBc fIN = 300 MHz2 25C 97 90 92 82 dBc fIN = 400 MHz2 25C 93 93 dBc fIN = 450 MHz2 25C 82 87 dBc fIN = 10 MHz (3.2 V p-p Input) 25C 97 95 dBc fIN = 30 MHz (3.2 V p-p Input) 25C 97 95 dBc fIN = 170 MHz (3.2 V p-p Input) 25C 97 95 dBc fIN = 225 MHz (3.2 V p-p Input)1 25C 95 94 dBc fIN = 300 MHz (3.2 V p-p Input)2 25C 93 91 dBc

TWO-TONE SFDR fIN = 30.3 MHz @ 7 dBFS,

31.3 MHz @ 7 dBFS 25C 102 102 dBFS

fIN = 170.3 MHz @ 7 dBFS, 171.3 MHz @ 7 dBFS

25C 92 91 dBFS

ANALOG BANDWIDTH Full 615 615 MHz 1 RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125. 2 RF ENABLE = high (AVDD1).

AD9445


DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 k, unless otherwise noted.

Table 3. AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full 2.0 2.0 V Low Level Input Voltage Full 0.8 0.8 V High Level Input Current Full 200 200 A Low Level Input Current Full 10 +10 10 +10 A Input Capacitance Full 2 2 pF

DIGITAL OUTPUT BITSCMOS MODE (D0 to D13, OTR)1 DRVDD = 3.3 V

High Level Output Voltage Full 3.25 3.25 V Low Level Output Voltage Full 0.2 0.2 V

DIGITAL OUTPUT BITSLVDS MODE (D0 to D13, OTR) VOD Differential Output Voltage2 Full 247 545 247 545 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V

CLOCK INPUTS (CLK+, CLK) Differential Input Voltage Full 0.2 0.2 V Common-Mode Voltage Full 1.3 1.5 1.6 1.3 1.5 1.6 V Differential Input Resistance Full 1.1 1.4 1.7 1.1 1.4 1.7 k Differential Input Capacitance Full 2 2 pF

1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 .

SWITCHING SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4. AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full 105 125 MSPS Minimum Conversion Rate Full 10 10 MSPS CLK Period Full 9.5 8.0 ns CLK Pulse Width High1 (tCLKH) Full 3.8 3.2 ns CLK Pulse Width Low1 (tCLKL) Full 3.8 3.2 ns

DATA OUTPUT PARAMETERS Output Propagation DelayCMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns Output Propagation DelayLVDS (tPD)3 (Dx+), (tCPD)3 (DCO+) Full 2.1 3.6 4.8 2.3 3.6 4.8 ns Pipeline Delay (Latency) Full 13 13 Cycles Aperture Delay (tA) Full ns Aperture Uncertainty (Jitter, tJ) Full 60 60 fsec

rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. 3 LVDS RTERM = 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

AD9445


TIMING DIAGRAMS

N 13 N 12 N N + 1

AIN

CLK+

CLK

DATA OUT

DCO+

DCO

N

N + 1

N 1

tCLKHtCLKL

1/fS

tPD

13 CLOCK CYCLES

tCPD

0548

9-00

2

Figure 2. LVDS Mode Timing Diagram

N + 1N + 2

N 1

tCLKL

13 CLOCK CYCLES

0548

9-00

3

N

tCLKH

tPD

VIN

CLK+

CLK

DX

DCO+

DCO

N 13 N 12 N 1 N

Figure 3. CMOS Timing Diagram

AD9445


ABSOLUTE MAXIMUM RATINGS

Table 5. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

With Respect To Parameter Rating

ELECTRICAL AVDD1 AGND 0.3 V to +4 V AVDD2 AGND 0.3 V to +6 V DRVDD DGND 0.3 V to +4 V AGND DGND 0.3 V to +0.3 V

THERMAL RESISTANCE AVDD1 DRVDD 4 V to +4 V

The heat sink of the AD9445 package must be soldered to ground. AVDD2 DRVDD 4 V to +6 V AVDD2 AVDD1 4 V to +6 V Table 6. D0 to D13 DGND 0.3 V to DRVDD + 0.3 V Package Type JA JB JC Unit CLK+/CLK AGND 0.3 V to AVDD1 + 0.3 V 100-lead TQFP/EP 19.8 8.3 2 C/W

AGND 0.3 V to AVDD1 + 0.3 V OUTPUT MODE, DCS MODE, DFS, SFDR, RF ENABLE

Typical JA = 19.8C/W (heat sink soldered) for multilayer board in still air. VIN+, VIN AGND 0.3 V to AVDD2 + 0.3 V

VREF AGND 0.3 V to AVDD1 + 0.3 V Typical JB = 8.3C/W (heat sink soldered) for multilayer board in still air. SENSE AGND 0.3 V to AVDD1 + 0.3 V

REFT, REFB AGND 0.3 V to AVDD1 + 0.3 V Typical JC = 2C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path.

ENVIRONMENTAL 65C to +125C Storage Temperature

Range Airflow increases heat dissipation, effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the JA. It is required that the exposed heat sink be soldered to the ground plane.

40C to +85C Operating Temperature Range

300C Lead Temperature (Soldering 10 sec)

Junction Temperature 150C

ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

AD9445


TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay (tA) Offset Error The major carry transition should occur for an analog value of LSB below VIN+ = VIN. Offset error is defined as the deviation of the actual transition from that point.

The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time The sample-to-sample variation in aperture delay. The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.

Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels.

Differential Nonlinearity (DNL, No Missing Codes) Power-Supply Rejection Ratio An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges.

The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit.

Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.

The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:

( )6.02

1.76=

SINADENOB Signal-to-Noise Ratio (SNR)

The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.

Gain Error The first code transition should occur at an analog value of LSB above negative full scale. The last transition should occur at an analog value of 1 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs LSB before the first code transition. Positive full scale is defined as a level 1 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX.

Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Maximum Conversion Rate

The clock rate at which parametric testing is performed. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

AD9445


PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

74 D8+73 D872 D7+

69 D6

70 D6+

71 D7

75 DRGND

68 DCO+67 DCO66 D5+

64 DRVDD63 DRGND62 D4+61 D460 D3+59 D358 D2+57 D256 D1+55 D154 D0+53 D0 (LSB)52 DNC51 DNC

65 D5

PIN 1

DNC = DO NOT CONNECT

100

RF

ENA

BLE

99

AG

ND

98

AG

ND

97

AVD

D1

96

AVD

D1

95

AVD

D1

94

AVD

D1

93

AVD

D1

92

AVD

D1

91

AG

ND

90

OR

+

89

OR

88

DR

VDD

87

DR

GN

D

86

D13

+ (M

SB)

85

D13

84

D12

+

83

D12

82

D11

+

81

D11

80

D10

+

79

D10

78

D9+

77

D9

76

DR

VDD

26

AVD

D2

27

AVD

D2

28

AVD

D2

29

AVD

D2

30

AVD

D2

31

AVD

D2

32

AVD

D1

33

AVD

D1

34

AVD

D1

35

AVD

D2

36

AVD

D1

37

AVD

D2

38

AVD

D1

39

AG

ND

40

CLK

+

41

CLK

42

AG

ND

43

AVD

D1

44

AVD

D1

45

AVD

D1

46

AG

ND

47

DR

GN

D

48

DR

VDD

49

DN

C

50

DN

C

2DNC3OUTPUT MODE4DFS

7SENSE

6AVDD1

5LVDS_BIAS

1DCS MODE

8VREF9AGND10REFT

12AVDD213AVDD214AVDD215AVDD216AVDD217AVDD218AVDD119AVDD120AVDD121AGND22VIN+23VIN24AGND25AVDD2

11REFB

AD9445LVDS MODE

TOP VIEW(Not to Scale)

0548

9-00

4

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

AD9445


Table 7. Pin Function Descriptions100-Lead TQFP/EP in LVDS Mode Pin No. Mnemonic Description 1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to

enable DCS (recommended); DCS = high (AVDD1) to disable DCS. 2, 49 to 52 DNC Do Not Connect. These pins should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;

OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data.

DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97

AVDD1 3.3 V (5%) Analog Supply.

7 SENSE Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for external reference.

8 VREF 1.0 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 F and 10 F capacitors.

9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink

AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.

10 REFT Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 14) with 0.1 F and 10 F capacitors.

11 REFB Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 13) with 0.1 F and 10 F capacitors.

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (5%). 22 VIN+ Analog InputTrue. 23 VIN Analog InputComplement. 40 CLK+ Clock InputTrue. 41 CLK Clock InputComplement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 53 D0 (LSB) D0 Complement Output Bit (LVDS Levels). 54 D0+ D0 True Output Bit. 55 D1 D1 Complement Output Bit. 56 D1+ D1 True Output Bit. 57 D2 D2 Complement Output Bit. 58 D2+ D2 True Output Bit. 59 D3 D3 Complement Output Bit. 60 D3+ D3 True Output Bit. 61 D4 D4 Complement Output Bit. 62 D4+ D4 True Output Bit. 65 D5 D5 Complement Output Bit. 66 D5+ D5 True Output Bit. 67 DCO Data Clock OutputComplement. 68 DCO+ Data Clock OutputTrue. 69 D6 D6 Complement Output Bit. 70 D6+ D6 True Output Bit. 71 D7 D7 Complement Output Bit. 72 D7+ D7 True Output Bit. 73 D8 D8 Complement Output Bit. 74 D8+ D8 True Output Bit. 77 D9 D9 Complement Output Bit. 78 D9+ D9 True Output Bit. 79 D10 D10 Complement Output Bit. 80 D10+ D10 True Output Bit. 81 D11 D11 Complement Output Bit. 82 D11+ D11 True Output Bit.

AD9445


Pin No. Mnemonic Description 83 D12 D12 Complement Output Bit. 84 D12+ D12 True Output Bit. 85 D13 D13 Complement Output Bit. 86 D13+ (MSB) D13 True Output Bit. 89 OR Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 RF ENABLE RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of

the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input frequencies 230 MHz for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power dissipation from AVDD2 increases by 150 mW to 200 mW.

AD9445


74 D273 D172 D0 (LSB)

69 DNC

70 DNC

71 DNC

75 DRGND

68 DCO+67 DCO66 DNC

64 DRVDD63 DRGND62 DNC61 DNC60 DNC59 DNC58 DNC57 DNC56 DNC55 DNC54 DNC53 DNC52 DNC51 DNC

65 DNC

PIN 1

DNC = DO NOT CONNECT

100

RF

ENA

BLE

99

AG

ND

98

AG

ND

97

AVD

D1

96

AVD

D1

95

AVD

D1

94

AVD

D1

93

AVD

D1

92

AVD

D1

91

AG

ND

90

OR

89

D13

(MSB

)

88

DR

VDD

87

DR

GN

D

86

D12

85

D11

84

D10

83

D9

82

D8

81

D7

80

D6

79

D5

78

D4

77

D3

76

DR

VDD

26

AVD

D2

27

AVD

D2

28

AVD

D2

29

AVD

D2

30

AVD

D2

31

AVD

D2

32

AVD

D1

33

AVD

D1

34

AVD

D1

35

AVD

D2

36

AVD

D1

37

AVD

D2

38

AVD

D1

39

AG

ND

40

CLK

+

41

CLK

42

AG

ND

43

AVD

D1

44

AVD

D1

45A

VDD

146

AG

ND

47

DR

GN

D

48

DR

VDD

49

DN

C

50

DN

C

2DNC3OUTPUT MODE4DFS

7SENSE

6AVDD1

5LVDS_BIAS

1DCS MODE

8VREF9AGND10REFT

12AVDD213AVDD214AVDD215AVDD216AVDD217AVDD218AVDD119AVDD120AVDD121AGND22VIN+23VIN24AGND25AVDD2

11REFB

AD9445CMOS MODE

TOP VIEW(Not to Scale)

0548

9-00

5

Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode

AD9445


Table 8. Pin Function Descriptions100-Lead TQFP/EP in CMOS Mode Pin No. Mnemonic Description 1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable

DCS (recommended); DCS = high (AVDD1) to disable DCS. 2, 49 to 62, 65 to 66, 69 to 71 DNC Do Not Connect. These pins should float. 3 OUTPUT

MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode; OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97

AVDD1 3.3 V (5%) Analog Supply.

7 SENSE Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for external reference.

8 VREF 1.0 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 F and 10 F capacitors.

9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink

AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.

10 REFT Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 14) with 0.1 F and 10 F capacitors.

11 REFB Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 13) with 0.1 F and 10 F capacitors.

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (5%). 22 VIN+ Analog InputTrue. 23 VIN Analog InputComplement. 40 CLK+ Clock InputTrue. 41 CLK Clock InputComplement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 67 DCO Data Clock OutputComplement. 68 DCO+ Data Clock OutputTrue. 72 D0 (LSB) D0 True Output Bit (CMOS levels). 73 D1 D1 True Output Bit. 74 D2 D2 True Output Bit. 77 D3 D3 True Output Bit. 78 D4 D4 True Output Bit. 79 D5 D5 True Output Bit. 80 D6 D6 True Output Bit. 81 D7 D7 True Output Bit. 82 D8 D8 True Output Bit. 83 D9 D9 True Output Bit. 84 D10 D10 True Output Bit. 85 D11 D11 True Output Bit. 86 D12 D12 True Output Bit. 89 D13 (MSB) D13 True Output Bit. 90 OR Out-of-Range True Output Bit. 100 RF ENABLE RF ENABLE CMOS-compatible Control Pin. Optimizes the configuration of the analog front end.

Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input frequencies 230 MHz for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR. Power dissipation from AVDD2 increases by 150 mW to 200 mW.

AD9445


EQUIVALENT CIRCUITS

X13.5V

1k

1k

AVDD2

VIN+

VIN

T/H

AVDD2

0548

9-00

66pF

6pF

DX

DRVDD

0548

9-00

9

Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent CMOS Digital Output Circuit

RF ENABLE, DCSMODE, OUTPUT

MODE, DFS

VDD

30k

0548

9-01

0

0548

9-00

7

1.2V

DRVDD DRVDD

K

3.74k ILVDSOUTLVDS_BIAS

Figure 10. Equivalent Digital Input Circuit,

DFS, DCS MODE, OUTPUT MODE Figure 7. Equivalent LVDS_BIAS Circuit

CLK+

3k

2.5k

3k

2.5k

AVDD2

CLK

0548

9-01

1

DRVDD

DX DX+

V

V

V

V

0548

9-00

8

Figure 11. Equivalent Sample Clock Input Circuit Figure 8. Equivalent LVDS Digital Output Circuit

AD9445


TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25C, 2.0 V p-p differential input, AIN = 1.0 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.

0

1300 62.500

0548

9-01

2

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)

125MSPS30.3MHz @ 1.0dBFSSNR = 73.4dBENOB = 12.1BITSSFDR = 94dBc

10

20

30

40

50

60

70

80

90

100

110

120

15.625 31.250 46.875

0

1300 62.500

0548

9-01

5

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

15.625 31.250 46.875

Figure 12. AD9445-125 64k Point Single-Tone FFT/125 MSPS/30.3 MHz Figure 15. AD9445-125 64k Point Single-Tone FFT/125 MSPS/225.3 MHz

0

1300 62.500

0548

9-01

3

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)

125MSPS100.3MHz @ 1.0dBFSSNR = 0dBENOB = 12.1BITSSFDR = 96dBc

10

20

30

40

50

60

70

80

90

100

110

120

15.625 31.250 46.875

0

1300 62.500

0548

9-01

6

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

15.625 31.250 46.875


0

1300 62.500

0548

9-01

4

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

15.625 31.250 46.875

0

1300 62.500

0548

9-01

7

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

15.625 31.250 46.875


AD9445


100

95

90

85

80

75

70

65

60

550 50 100 150 200 250 300 350 400 450

0548

9-01

8

ANALOG INPUT FREQUENCY (MHz)

(dB

)

SFDR +25C

SNR +25C

SFDR +85C

SFDR 40C

SNR +85C

SNR 40C

100

95

90

85

80

75

70

65

60

550 50 100 150 200 250 300 350 400 450

0548

9-02

1


(dB

)

SFDR +25C

SNR +25C

SFDR +85CSFDR 40C

SNR +85C

SNR 40C

Figure 18. AD9445-125 SNR/SFDR vs. Analog Input Frequency,

125 MSPS, 2.0 V p-p Input Range Figure 21. AD9445-125 SNR/SFDR vs. Analog Input Frequency,

125 MSPS, 3.2 V p-p Input Range

100

550 100

0548

9-01

9


(dB

)

SFDR +25C

SNR +25C

SFDR +85C

SFDR 40C

SNR +85C

SNR 40C

20 30 40 50 60 70 80 90

95

90

85

80

75

70

65

60

10

105

700

0548

9-02

2

SAMPLE RATE (MSPS)

(dB

)

100

95

90

85

80

75

20 40 60 80 100 120 140

105M SFDR dBc

125M SFDR dBc

105M SNR dB

125M SNR dB


3.2 V p-p Input Range, 125 MSPS, CMOS Output Mode Figure 22. AD9445 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz

120

0100 0

0548

9-02

0

ANALOG INPUT AMPLITUDE (dB)

(dB

)

100

80

60

40

20

90 80 70 60 50 40 30 20 10

SNR dB

SNR dBFS

SFDR dBc

SFDR dBFS120

0100 0

0548

9-02

3


(dB

)

100

80

60

40

20

90 80 70 60 50 40 30 20 10

SNR dB

SNR dBFS

SFDR dBc

SFDR dBFS

Figure 20. AD9445-125 SNR/SFDR vs. Analog Input Level,

125 MSPS/225.3 MHz Figure 23. AD9445-125 SNR/SFDR vs. Analog Input Level,

125 MSPS/225.3 MHz, CMOS Output Mode

AD9445


0

1300 52.500

0548

9-02

4

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

13.125 26.250 39.375

0

1300 52.500

0548

9-02

7

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

13.125 26.250 39.375


0

1300 52.500

0548

9-02

5

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

13.125 26.250 39.375

0

1300 52.500

0548

9-02

8

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

13.125 26.250 39.375


0

1300 52.500

0548

9-02

6

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

13.125 26.250 39.375

0

1300 52.500

0548

9-02

9

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


10

20

30

40

50

60

70

80

90

100

110

120

13.125 26.250 39.375


AD9445


100

95

90

85

80

75

70

65

60

550 50 100 150 200 250 300 350 400 450

0548

9-03

0


(dB

)

SFDR +25C

SNR +25C

SFDR +85C

SFDR 40C

SNR +85C

SNR 40C

100

95

90

85

80

75

70

65

60

550 50 100 150 200 250 300 350 400 450

0548

9-03

3


(dB

)

SFDR +25C

SNR +25C

SFDR +85CSFDR 40C

SNR +85C

SNR 40C


105 MSPS, 2.0 V p-p Figure 33. AD9445-105 SNR/SFDR vs. Analog Input Frequency,

105 MSPS, 3.2 V p-p

100

602.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

0548

9-03

4

ANALOG INPUT COMMON-MODE VOLTAGE

(dB

)

SNR dB

SFDR dBc95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

60

550 180

0548

9-03

1


(dB

)

SFDR +25C

SNR +25C

SFDR +85C

SFDR 40C

SNR +85C

SNR 40C

20 40 60 80 100 120 140 160


3.2 V p-p Input Range, 105 MSPS, CMOS Output Mode Figure 34. AD9445-105 SNR/SFDR vs. Analog Input Common Mode,

105 MSPS/10.3 MHz

120

0100 0

0548

9-03

2


(dB

)

100

80

60

40

20

90 80 70 60 50 40 30 20 10

SNR dB

SNR dBFS

SFDR dBc

SFDR dBFS120

0100 0

0548

9-03

5


(dB

)

100

80

60

40

20

90 80 70 60 50 40 30 20 10

SNR dB

SNR dBFS

SFDR dBc

SFDR dBFS

Figure 32. AD9445-105 SNR/SFDR vs. Analog Input Level,

105 MSPS/225.3 MHz Figure 35. AD9445-105 SNR/SFDR vs. Analog Input Level,

105 MSPS/225.3 MHz, CMOS Output Mode

AD9445


0

140

130

0 54.500

0548

9-03

7

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)

125MSPS30.3MHz @ 7.0dBFS31.3MHz @ 7.0dBFSSFDR = 102dBFS

1020304050607080

90100110

120

13.625 27.250 40.875

0

120100 0

0548

9-04

1

FUNDAMENTAL LEVEL (dB)

SPU

R A

ND

IMD

3 (d

B)

20

40

60

80

100

10

30

50

70

90

110

90 80 70 60 50 40 30 20 10

SFDR dBFS

SFDR dBc

WORST IMD3 dBc

WORST IMD3 dBFS

Figure 36. AD9445-125 64k Point Two-Tone FFT/

125 MSPS/30.3 MHz, 31.3 MHz Figure 39. AD9445-125 Two-Tone SFDR vs. Analog Input Level

125 MSPS/170.3 MHz, 171.3 MHz

0

120100 0

0548

9-03

8


SPU

R A

ND

IMD

3 (d

B)

20

40

60

80

100

10

30

50

70

90

110

90 80 70 60 50 40 30 20 10

SFDR dBFS

SFDR dBc

WORST IMD3 dBc

WORST IMD3 dBFS

0

140

130

0

0548

9-04

2

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


1020304050607080

90100110

120

0 52.50013.125 26.250 39.375

Figure 37. AD9445-125 Two-Tone SFDR vs. Analog Input Level

125 MSPS/30.3 MHz, 31.3 MHz Figure 40. AD9445-105 64k Point Two-Tone FFT/105 MSPS/30.3 MHz, 31.3 MHz

0

140

130

0 54.500

0548

9-04

0

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


1020304050607080

90100110

120

13.625 27.250 40.875

0

120100 0

0548

9-04

3


SPU

R A

ND

IMD

3 (d

B)

20

40

60

80

100

10

30

50

70

90

110

90 80 70 60 50 40 30 20 10

SFDR dBFS

SFDR dBc

WORST IMD3 dBc

WORST IMD3 dBFS

Figure 38. AD9445-125 64k Point Two-Tone FFT/

125 MSPS/170.3 MHz, 171.3 MHz Figure 41. AD9445-105 Two-Tone SFDR vs. Analog Input Level

105 MSPS/30.3 MHz, 31.3 MHz

AD9445


25000

0 0548

9-04

4

OUTPUT CODE

FREQ

UEN

CY

N + 4

621127

7968

2219023754

135575 2

20000

15000

10000

5000

N 4 N 3 N 2 N 1 N N + 1 N + 2 N + 3

9003

30000

0 0548

9-04

7

OUTPUT CODE

FREQ

UEN

CY

N + 4

3 307

3350

15743

26294

3493

227 2N 4 N 3 N 2 N 1 N N + 1 N + 2 N + 3

16117

25000

20000

15000

10000

5000

SAMPLE SIZE = 65538

Figure 42. AD9445-125 Grounded Input Histogram Figure 45. AD9445-105 Grounded Input Histogram

0

140

130

0

0548

9-04

5

FREQUENCY (MHz)

AM

PLIT

UD

E (d

BFS

)


1020304050607080

90100110

120

0 52.50013.125 26.250 39.375

0

0.840

0548

9-04

8

TEMPERATURE (C)

GA

IN E

RR

OR

(%FS

R)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

20 0 20 40 60 80

Figure 43. AD9445-105 64k Point Two-Tone FFT/105 MSPS/170.3 MHz, 171.3 MHz Figure 46. AD9445-125 Gain vs. Temperature

0.4

0.40

0548

9-04

9

OUTPUT CODE

DN

L ER

RO

R (L

SB)

0 16384

0.3

0.2

0.1

0

0.1

0.2

0.3

4096 8192 12288

0

120100 0

0548

9-04

6


SPU

R A

ND

IMD

3 (d

B)

20

40

60

80

100

10

30

50

70

90

110

90 80 70 60 50 40 30 20 10

SFDR dBFS

SFDR dBc

WORST IMD3 dBc

WORST IMD3 dBFS

Figure 44. AD9445-105 Two-Tone SFDR vs. Analog Input Level

105 MSPS/170.3 MHz, 171.3 MHz Figure 47. AD9445-105 DNL Error vs. Output Code, 105 MSPS, 10.3 MHz

AD9445


0.4

0.40

0548

9-05

0

OUTPUT CODE

DN

L ER

RO

R (L

SB)

0 16384

0.3

0.2

0.1

0

0.1

0.2

0.3

4096 8192 12288

1.0

1.00

0548

9-05

3

OUTPUT CODE

INL

ERR

OR

(LSB

)

0 163844096 8192 12288

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

Figure 48. AD9445-125 DNL Error vs. Output Code, 125 MSPS, 10.3 MHz Figure 51. AD9445-125 INL Error vs. Output Code, 125 MSPS, 10.3 MHz

400

00

0548

9-06

6

SAMPLE RATE (MSPS)

I SU

PPLY

(mA

)

160

350

300

250

200

150

100

50

20 40 60 80 100 120 140

DRVDD

AVDD2

AVDD1

1.014

1.012

1.010

1.008

1.006

1.004

1.00240

0548

9-05

1

TEMPERATURE (C)

VREF

20 0 20 40 60 80

Figure 52. AD9445-105 Power Supply Current vs. Sample Rate

10.3 MHz @ 1 dBFS Figure 49. AD9445-125 VREF vs. Temperature

78

711.8

0548

9-06

7

ANALOG INPUT RANGE (V p-p)

(dB

)

4.2

170.3MHz SNR dB

225.3MHz SNR dB

300.3MHz SNR dB

77

76

75

74

73

72

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

0.5

0.50

0548

9-05

2

OUTPUT CODE

INL

ERR

OR

(LSB

)

0 163844096 8192 12288

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4

Figure 53. AD9445-125 SNR vs. Analog Input Range, 125 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz

Figure 50. AD9445-105 INL Error vs. Output Code, 105 MSPS, 10.3 MHz

AD9445


78

711.8

0548

9-06

8


(dB

)

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

170.3MHz SFDR dBc

225.3MHz SFDR dBc

300.3MHz SFDR dBc

77

75

76

74

73

72

95

701.8

0548

9-07

1


(dB

)

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

170.3MHz SFDR dBc

225.3MHz SFDR dBc

300.3MHz SFDR dBc

90

85

80

75

Figure 54. AD9445-105 SNR vs. Analog Input Range, 105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz

Figure 57. AD9445-105 SFDR vs. Analog Input Range, 105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz

400

00

0548

9-06

9

SAMPLE RATE (MSPS)

I SU

PPLY

(mA

)

160

350

300

250

200

150

100

50

20 40 60 80 100 120 140

DRVDD

AVDD2

AVDD1

81

741.8 4.2

0548

9-03

9


(dB

)

80

79

78

77

76

75

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

105M SNR dBFS

125M SNR dBFS

Figure 55. AD9445-125 Power Supply Current vs. Sample Rate

10.3 MHz @ 1 dBFS Figure 58. SNR vs. Analog Input Range, 2.3 MHz @ 30 dBFS

95

701.8

0548

9-07

0


(dB

)

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

170.3MHz SFDR dBc

225.3MHz SFDR dBc

300.3MHz SFDR dBc

90

85

80

75

Figure 56. AD9445-125 SFDR vs. Analog Input Range, 125 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz

AD9445


THEORY OF OPERATION The AD9445 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW A stable and accurate 0.5 V band gap voltage reference is built into the AD9445. The input range can be adjusted by varying the reference voltage applied to the AD9445, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly.

Internal Reference Connection

A comparator within the AD9445 detects the potential at the SENSE pin and configures the reference into three possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 59), setting VREF to ~1.0 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a ~1.0 V reference output. If a resistor divider is connected as shown in Figure 60, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as

+=

R1R2VVREF 15.0

In all reference configurations, REFT and REFB drive the analog-to-digital conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the production test to adjust the gain (analog input voltage range) of the AD9445. Therefore, there is little advantage to the user supplying an external voltage reference to the AD9445. The gain trim is performed with the AD9445 input range set to 2.0 V p-p nominal (SENSE

connected to AGND). Because of this trim and the maximum ac performance provided by the 2.0 V p-p analog input range, there is little benefit to using analog input ranges

AD9445


3.5V

VIN+

VIN

1V p-p

DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s

0548

9-05

6

External Reference Operation

The AD9445s internal reference is trimmed to enhance the gain accuracy of the ADC. An external reference may be more stable over temperature, but the gain of the ADC is not likely to improve. Figure 49 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1.6 V.

Figure 61. Differential Analog Input Range for VREF = 1.0 V

Therefore, the analog source driving the AD9445 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD9445 is to use an RF transformer to convert single-ended signals to differential (see

Analog Inputs

As with most new high speed, high dynamic range ADCs, the analog input to the AD9445 is differential. Differential inputs improve on-chip performance because signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion of the AD9445 cannot be realized with a single-ended analog input, so such configurations are discouraged. Contact sales for recommendations of other 14-bit ADCs that support single-ended analog input configurations.

Figure 62). Series resistors between the output of the transformer and the AD9445 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The series resistors, along with the 1 k resisters connected to the internal 3.5 V bias, must be considered in impedance matching the transformer input. For example, if RT is set to 51 , RS is set to 33 , and there is a 1:1 impedance ratio trans-former, the input will match a 50 source with a full-scale drive of 10.0 dBm. The 50 impedance matching can also be incor-porated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 67).

0548

9-05

70.1F

RT AD9445VIN+

VINRS

RSADT11WTANALOGINPUT

SIGNAL

With the 1 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD9445 analog input is nominally 2.0 V p-p or 1.0 V p-p on each input (VIN+ or VIN).

Figure 62. Transformer-Coupled Analog Input Circuit

High IF Applications The AD9445 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 k resistor to the 3.5 V bias voltage and to the input of a differential buffer. The internal bias network on the input properly biases the buffer for maximum linearity and range (see the

In applications where the analog input frequency range is >100 MHz, the phase and amplitude matching at the analog inputs becomes critical to optimize performance of the ADC. The circuit in Figure 63 can be used to optimize the matching of these parameters. This configuration uses a double balun config-uration that has low parasitics, high bandwidth, and parasitic cancellation.

Equivalent Circuits section).

0548

9-05

8

0.1FCT AD9445

VIN+

VIN

3325

50SOURCE

2533

ETC1113ETC1113

0.1F

Figure 63. Double Balun-Coupled Analog Input Circuit

AD9445


CLOCK INPUT CONSIDERATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. For that reason, considerable care was taken in the design of the clock inputs of the AD9445, and the user is advised to give careful thought to the clock source.

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9445 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. Noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 30 MHz nominally. The loop is associated with a time constant that should be considered in applications where the clock rate can change dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time that the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. In such an application, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.

The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the duty cycle stabilizer, and logic high (AVDD1 = 3.3 V) disables the controller.

The AD9445 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. (See the AN-501 Application Note, Aperture Uncertainty and ADC System Performance.) For optimum performance, the AD9445 must be clocked differentially. The sample clock inputs are internally biased to ~2.2 V, and the input signal is usually ac-coupled into the CLK+ and CLK pins via a transformer or capacitors. Figure 64 shows one preferred method for clocking the AD9445. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back

Schottky diodes across the secondary of the transformer limit clock excursions into the AD9445 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9445 and limits the noise presented to the sample clock inputs.

If a low jitter clock is available, it may help to band-pass filter the clock reference before driving the ADC clock inputs. Another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 65.

0548

9-05

9

0.1F AD9445CLK+

CLKHSMS2812

DIODES

CLOCKSOURCE

ADT11WT

Figure 64. Crystal Clock Oscillator, Differential Encode

0548

9-06

0

0.1F

AD9445ENCODE

ENCODE

0.1F

VT

VT

ECL/PECL

Figure 65. Differential ECL for Encode

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) and rms amplitude due only to aperture jitter (tJ) can be calculated using the following equation:

SNR = 20 log[2fINPUT tJ]

In the equation, the rms aperture jitter represents the root-mean-square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, see Figure 66.

The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9445. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be synchronized by the original clock during the last step.

http://www.analog.com/UploadedFiles/Application_Notes/3956522730668848977365163734AN501.pdf#xml=http://search.analog.com/search/pdfPainter.aspx?url=http://www.analog.com/UploadedFiles/Application_Notes/3956522730668848977365163734AN501.pdf&fterm=an-501&fterm=an-501&la=enhttp://www.analog.com/UploadedFiles/Application_Notes/3956522730668848977365163734AN501.pdf#xml=http://search.analog.com/search/pdfPainter.aspx?url=http://www.analog.com/UploadedFiles/Application_Notes/3956522730668848977365163734AN501.pdf&fterm=an-501&fterm=an-501&la=en

AD9445


INPUT FREQUENCY (MHz)

SNR

(dB

c)

140

75

70

65

60

55

50

45

100010010

0548

9-06

1

0.2ps

0.5ps

1.0ps

1.5ps

2.0ps2.5ps3.0ps

resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic performance, including both SFDR and SNR, is maximized when the AD9445 is used in LVDS mode; designers are encouraged to take advantage of this mode. The AD9445 outputs include complimentary LVDS outputs for each data bit (Dx+/Dx), the overrange output (OR+/OR), and the output data clock output (DCO+/DCO). The RSET resistor current is multiplied on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 IRSET). A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended, with a 100 termination resistor placed as close to the receiver as possible. It is recommended to keep the trace length less than 2 inches and to keep differential output trace lengths as equal as possible.

Figure 66. SNR vs. Input Frequency and Jitter

POWER CONSIDERATIONS Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that may be received by the AD9445. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors.

CMOS Mode

In applications that can tolerate a slight degradation in dynamic performance, the AD9445 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits, Dx, are single-ended CMOS, as is the overrange output, OR. The output clock is provided as a differential CMOS signal, DCO+/DCO. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. The capacitive load to the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 ) to minimize switching transients caused by the capacitive loading.

The AD9445 has separate digital and analog power supply pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V), and the digital supply pins are denoted DRVDD. Although the AVDD1 and DRVDD supplies can be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9445 is a dedicated supply for the digital outputs in either LVDS or CMOS output mode. When in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply can be connected from 2.5 V to 3.6 V for compatibility with the receiving logic. TIMING

The AD9445 provides latched data outputs with a pipeline delay of 13 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of CLK+. Refer to

DIGITAL OUTPUTS LVDS Mode Figure 2 and

Figure 3 for detailed timing diagrams. The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin 3 (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 k RSET

AD9445


OPERATIONAL MODE SELECTION Data Format Select

The data format select (DFS) pin of the AD9445 determines the coding format of the output data. This pin is 3.3 V CMOS-compatible, with logic high (or AVDD1, 3.3 V) selecting twos complement and DFS logic low (AGND) selecting offset binary format. Table 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility, as well as the pinout of the digital outputs. This pin is a CMOS-compatible input. With OUTPUT MODE = 0 (AGND), the AD9445 outputs are CMOS compatible, and the pin assignment for the device is as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9445 outputs are LVDS compatible, and the pin assignment for the device is as defined in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the DCS, and logic high (AVDD1, 3.3 V) disables the controller.

RF ENABLE

The RF ENABLE pin is a CMOS-compatible control pin that optimizes the configuration of the AD9445 analog front end. The crossover analog input frequency for determining the RF ENABLE connection differs for the 105 MSPS and 125 MSPS speed grades. For the 125 MSPS speed grade, connecting the RF ENABLE to AGND optimizes SFDR performance for appli-cations with analog input frequencies 210 MHz, this pin should be connected to AVDD1 for optimum SFDR performance. Connecting this pin to AVDD1 reconfigures the ADC, thereby improving high IF and RF spurious performance. Operating in this mode increases power dis-sipation from AVDD2 by 150 mW to 200 mW. For the 105 MSPS speed grade, connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input frequencies 230 MHz, this pin should be connected to AVDD1 to optimize performance.

Table 10. Digital Output Coding

Code VIN+ VIN Input Span = 3.2 V p-p (V)

VIN+ VIN Input Span = 2 V p-p (V)

Digital Output Offset Binary (D13D0)

Digital Output Twos Complement (D13D0)

16,383 +1.600 +1.000 11 1111 1111 1111 01 1111 1111 1111 8192 0 0 10 0000 0000 0000 00 0000 0000 0000 8191 0.000195 0.000122 01 1111 1111 1111 11 1111 1111 1111 0 1.60 1.00 00 0000 0000 0000 10 0000 0000 0000

AD9445


EVALUATION BOARD Evaluation boards are offered to configure the AD9445 in either CMOS or LVDS mode only. This design represents a recommended configuration for using the device over a wide range of sampling rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics are shown in Figure 67 through Figure 70. Gerber files are available from engineering applications demon-strating the proper routing and grounding techniques that should be applied at the system level.

It is critical that signal sources with very low phase noise (

AD9445


OPTIONAL

15 20 23

9796

86

12 21 2216

95

24 25

2627

34929394

28293031

4039

19

4142

35

38

9091

87

189

64 63

4344

7273

767778798081 45

46

4950

51525556575859606566686970716

88

8485

48

53616774

82

47

546275

83

3233

100

893637

101

98

7 141310

99

11 172 3 4 5 81R

111k

VC

C

GN

D

R3

3.74

k

DR

GN

DD

RVD

D

E24

EXTR

EF

D0_C (LSB)D0_T

D1_

CD

1_T

D3_

CD

3_T

D4_

CD

4_T

D5_

CD

5_T

D7_

CD

7_T

DR

D8_

C/D

0_Y

D8_

T/D

1_Y

D9_

C/D

2_Y

D9_

T/D

3_Y

D10

_C/D

4_Y

C98

DN

P

GN

D

D15_C/D14_Y

E41

E25

E27

E26

VCC

GN

D

E6E5E

4

GN

D

C3

0.1

F

C9

0.1

F

C86

0.1

F

R1

DN

P

GN

D

5VVCC

D14_C/D12_Y

DR

GN

D

D6_

T

D2_

T

DRGND

D13_T/D11_Y

D10

_T/D

5_Y

DR

B

D6_

C

D2_

C

DRVDD

D14_T/D13_Y

GNDVCCD13_C/D10_Y

D12_T/D9_YD12_C/D8_YD11_T/D7_YD11_C/D6_Y

DRVDD

VCCVCC

GN

D

VCC

VCC

VCC

5V

VCC

ENCB

GNDENC

GND

VCC

5V

VCC

5VGN

D

VCC

5V5V5V 5V 5V

GN

DSCLK

VCCVCCGND

VCC

GN

D5V

C13

DN

P

R35

33

R28

33

R9

DN

P

C910.1F

C8

0.1

F

GN

D

GN

D

VCC

GN

D

VCC

EPAD

AD

9445

/AD

9446

U1

R4

36

P1P2P3P

22PT

MIC

RO

4

VCC

5V

GND

GNDP4

1234

P1P2P3P

21PT

MIC

RO

4

EXTREF

DRVDD

XTALPWR

DRGNDP4

1234

DC

S M

OD

ED

NC

OU

TPU

T M

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ED

FSLV

DSB

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AVD

D1

SEN

SEVR

EFA

GN

DR

EFT

REF

BA

VDD

2A

VDD

2A

VDD

2A

VDD

2A

VDD

2A

VDD

2A

VDD

1A

VDD

1A

VDD

1A

GN

DVI

N+

VIN

A

GN

DA

VDD

2

VCC

DRGND

DOR_CDOR_T/DOR_Y

GNDVCCVCC

DRVDD

(MSB) D15_T/D15_Y

E1E9E

10

GN

D

VCC

E14

E2E3

GN

D

VCC

E66

E18

E19

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D

VCC

C12

0.1

FC

50.

1F

J4SM

BM

ST

R5

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P

GN

D

TIN

B

GN

D

AN

ALO

G

L1 10nH

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R6

36

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PC

5110

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0548

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2

DR

GN

DD

10_T

D10

_CD

9_T

D9_

CD

8_T

D8_

CD

CO

DC

OB

D7_

TD

7_C

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GN

DD

6_T

D6_

CD

5_T

D5_

CD

4_T

D4_

CD

3_T

D3_

CD

2_T

D2_

CD

1_T

D1_

C

D12_TD12_CD11_TD11_CDRVDD

AGNDAGNDAGNDAVDD1AVDD1AVDD1AVDD1

OR_COR_TAGNDAVDD1AVDD1

DRVDDDRGNDD15_TD15_CD14_TD14_CD13_TD13_C

AVDD2AVDD2

AVDD2AVDD2AVDD2AVDD2

AVDD1AVDD1AVDD1AVDD2AVDD1AVDD2AVDD1

ENCAGND

ENCBAGND

AVDD1AVDD1AVDD1AGND

DRGNDDRVDD

D0_CD0_T

H4MTHOLE6

GND

DRGND

H3MTHOLE6

H1MTHOLE6

H2MTHOLE6

GN

DC

3910

F

+

TOU

TC

T

TOU

TB

C7

0.1

F

PRI

SEC

GN

D

GN

D

T5A

DT1

-1W

T

T2

1 5 3

6 2 4N

C

GN

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GN

D

TIN

BTO

UTB

TOU

T

CT

PRI SEC

ETC1-1-13

3 4

1

25

PRI

SEC

T1ET

C1-

1-13

15

34

2

Figure 67. AD9445 Evaluation Board Schematic

AD9445


IN

OU

TO

UT1

5V

C34

10F

C89

10F

3

421

AD

P333

8U

14

GN

D

GN

D

GN

D 5VX

5VX

5VX

5V

GN

D

VIN

GN

D

+

+

IN

OU

TO

UT1

3.3V

L3FE

RR

ITE

C6

10F

C87

10F

3

421

AD

P333

8U

7

GN

D

GN

D VC

CX

VCC

X

GN

D

VIN

GN

D

+

+

IN

OU

TO

UT1

3.3V

C4

10F

C88

10F

3

421

AD

P333

8U

3

DR

GN

D

DR

GN

D

DR

VDD

XD

RVD

DX

DR

GN

D

VIN

GN

D

+

+

PJ-1

02A

C33

10F

132

P4

GN

D

VIN

+

132

POW

ER O

PTIO

NS

AD

T1-1

WT

PRI

SEC

NC

ENC

ENC

B

GN

D

J5SM

BM

ST

R7

DN

P

DN

P

R39 0

R8

50

C26

0.1

F

C36

DN

P1

2

356

T3

23

1

CR2

CR1

C42

0.1

FG

ND

XTA

LIN

PUT

GN

D

CR

2 TO

MA

KE

LAYO

UT

AN

D P

AR

ASI

TIC

LOA

DIN

G S

YMM

ETR

ICA

L

4

J1SM

BM

ST

13

2

ENC

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EG

ND

OU

TVC

C

VEE

~OU

T+

GN

D

GN

D

XTA

LIN

PUT

E30

C1

10F

E31

814 7

U6

ECLO

SC

E20

VXTA

L

GN

D

5V XTA

LPW

R

VXTA

L

VXTA

L

1

+C

4410

F

C41

0.1

F

OPT

ION

AL

ENC

OD

E C

IRC

UIT

S

VCC

XVC

C

L4FE

RR

ITE

DR

VDD

XD

RVD

D

L5FE

RR

ITE

DR

GN

DG

ND

L2 DN

P

0548

9-06

3

Figure 68. AD9445 Evaluation Board Schematic (Continued)

AD9445


C960.1F

C970.1F

C840.1F

C460.1F

C220.1F

C590.1F

C930.1F

C940.1F

C950.1F

5V

GND

C600.1F

C100.1F

C610.1F

C750.1F

C270.1F

C900.1F

C500.1F

C300.01F

C280.1F

C350.1F

C320.1F

VCC

BYPASS CAPACITORS

GND

C31XX

C38XX

C29XX

C19XX

C17XX

C16XX

C15XX

C11XX

C14XX

VCC

GND

C370.1F

C480.1F

C180.1F

C530.1F

C520.1F

C580.01F

C5610F

+ C850.1F

5V

GND

C110XX

C108XX

C109XX

C72XX

C73XX

5V

GND

C210.1F

C200.1F

C6510F

+ C470.1F

C230.1F

DRVDD

DRGND

C6410F

+ C430.1F

C45XX

C49XX

C69XX

C70XX

DRVDD

DRGND

C5510F

+EXTREF

GND

0548

9-06

4


AD9445


0548

9-06

5

RSO

16IS

O220

R8

R7

R6

R5

R4

R3

R1

R2

RSO

16IS

O220

8765431 2

16 15 14 13 12 11 10 9

RZ4

8765431 2

16 15 14 13 12 11 10 9

RZ5

D1O

D0O

D2O

D4O

D5O

D6O

D7O

D3OD8O

D9O

D10

O

D11

O

D12

O

D13

O

D14

O

D15

O

GN

D5

VCC

6VC

C5

GN

D4

END

D4Y

D3Y

D2Y

D1Y

ENC

C4Y

C3Y

C2Y

C1Y

GN

D3

VCC

4VC

C3

GN

D2

B4Y

B3Y

B2Y

B1Y

ENB

A4Y

A3Y

A2Y

A1Y

ENA

GN

D1

VCC

2VC

C1

GN

D

D4B

D4A

D3B

D3A

D2B

D2A

D1B

D1A

C4B

C4A

C3B

C3A

C2B

C2A

C1B

C1A

B4B

B4A

B3B

B3A

B2B

B2A

B1B

B1A

A4B

A4A

A3B

A3A

A2B

A2A

A1B

A1A

3334353637383940414243444546474849505152535455565758596061626364

3231302928272625242322212019181716151413121110987654321

U8

SN75

LVD

S386

D15

_C/D

14_Y

D14

_C/D

12_Y

D13

_C/D

10_Y

D12

_C/D

8_Y

D11

_C/D

6_Y

D10

_C/D

4_Y

D9_

C/D

2_Y

D3_

C

D15

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15_Y

D14

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13_Y

D13

_T/D

11_Y

D12

_T/D

9_Y

D11

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7_Y

D10

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5_Y

D9_

T/D

3_Y

D8_

T/D

1_Y

D8_

C/D

0_Y

D7_

TD

7_C

D6_

TD

6_C

D5_

CD

5_T

D4_

TD

4_C

D3_

T

D2_

TD

2_C

D1_

TD

1_C

D0_

TD

0_C

DR

VDD

DR

VDD

DR

GN

D

DR

GN

D

DR

GN

D

DR

VDD

DR

VDD

DR

GN

DD

RVD

DD

RVD

DD

RG

ND

DR

VDD

DR

VDD

DR

VDD

DR

VDD

DR

GN

DP1P3P5P7P9P1

1

P13

P15

P17

P19

P21

P23

P25

P27

P29

P31

P33

P35

P37

P39

P2P4P6P8P10

P12

P14

P16

P18

P20

P22

P24

P26

P28

P30

P32

P34

P36

P38

P40

P6C

40M

S

13579111315171921232527293133353739

246810121416182022242628303234363840

D14

_C/D

12_Y

D12

_C/D

8_Y

D10

_C/D

4_Y

D8_

C/D

O_Y

DR

B

D7_

C

D4_

C

D3_

C

D2_

C

D5_

C

D6_

C

D9_

C/D

2_Y

D11

_C/D

6_Y

D13

_C/D

10_Y

D1_

C

DO

R_C

DR

GN

D

D15

_C/D

14_Y

DR

GN

D

D0_

C

D14

_T/D

13_Y

D12

_T/D

9_Y

D10

_T/D

5_Y

D8_

T/D

1_Y

DR

D7_

T

D4_

T

D3_

T

D2_

T

D5_

T

D6_

T

D9_

T/D

3_Y

D11

_T/D

7_Y

D13

_T/D

11_Y

D1_

T

DO

R_T

/DO

R_Y

DR

GN

D

D15

_T/D

15_Y

DR

GN

D

D0_

TR

8

R7

R6

R5

R4

R3

R1

R2

EN_3

_44Y3YG

ND

VCC2Y1Y

EN_1

_2

4B4A3B3A2B2A1B1A

910111213141516

87654321

U15

SN75

LVD

T390

R19 0 R10 0

DR

B

DO

R_CD

R

DO

R_T

/DO

R_Y

DR

OD

RVD

D

DR

VDD

DR

GN

D

OR

OD

RVD

D

C76

0.1

FC

820.

1F

C77

0.1

FC

780.

1F

DR

VDD

DR

GN

D

P1P3P5P7P9P11

P13

P15

P17

P19

P21

P23

P25

P27

P29

P31

P33

P35

P37

P39

P2P4P6P8P10

P12

P14

P16

P18

P20

P22

P24

P26

P28

P30

P32

P34

P36

P38

P40

P7C

40M

S

13579111315171921232527293133353739

246810121416182022242628303234363840

D15

O

D13

O

D11

O

D9O

D8O

D7O

D4O

D3O

D2O

D5O

D6O

D10

O

D12

O

D14

O

D1O

DR

O

DR

GN

DD

RG

ND

GN

DN

DR

GN

D

OR

O

DR

GN

D

D0O


AD9445


Table 11. AD9445-125 Baseband Customer Evaluation Board Bill of Materials Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No. 1 7 C4, C6, C33, C34, C87,

C88, C89 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, C60, C76, C77, C78, C82, C84, C85, C86, C90, C91, C94, C95, C96, C97

Capacitor 402 0.1 F Digi-Key Corporation PCC2146CT-ND

3 2 C30, C58 Capacitor 201 0.01 F Digi-Key Corporation 445-1796-1-ND 4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2 5 1 C51 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND 6 1 CR1 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND 7 1 CR2 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND 8 20 E1, E2, E3, E4, E5, E6,

E9, E10, E14, E18, E19, E20, E24, E25, E26, E27, E30, E31, E36, E41

Header EHOLE Mouser Electronics 517-6111TG

9 2 J1, J4 SMA SMA Digi-Key Corporation ARFX1231-ND 10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU 11 3 L3, L4, L5 EMIFIL

BLM31PG500SN1L 1206MIL Mouser Electronics 81-BLM31P500S

12 1 P4 PJ-002A PJ-002A Digi-Key Corporation CP-002A-ND 13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA 14 1 R3 Resistor 402 3.74 k Digi-Key Corporation P3.74KLCT-ND 15 1 R8 Resistor 402 50 Digi-Key Corporation P49.9LCT-ND 16 4 R10, R19, R39, L2 Resistor 402 0 Digi-Key Corporation P0.0JCT-ND 17 1 R11 BRES402 402 1 k Digi-Key Corporation P1.0KLCT-ND 18 2 R28, R35 Resistor 402 33 Digi-Key Corporation P33JCT-ND 19 2 RZ4, RZ5 Resistor array 16PIN 22 Digi-Key Corporation 742C163220JCT-ND 20 2 T3, T5 Transformer ADT1-1WT Mini-Circuits ADT1-1WT 21 1 U1 AD9445BSVZ-125 SV-100-3 Analog Devices, Inc. AD9445BSVZ-125 22 1 U14 ADP3338-5 SOT-223HS Analog Devices, Inc. ADP3338-5 23 2 U3, U7 ADP3338-3.3 SOT-223HS Analog Devices, Inc. ADP3338-33 24 1 U8 SN75LVDT386 TSSOP64 Arrow Electronics, Inc. SN75LVDT386DGG 25 1 U15 SN75LVDT390 SOIC16PW Arrow Electronics, Inc. SN75LVDT390PW 26 2 R4, R6 Resistor 402 36 Digi-Key Corporation P36JCT-ND 27 2 C1, C44, C551 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2 28 23 C13, C14, C16, C17,

C18, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, C108, C109, C1101

CAP402 402 XX

29 1 C981 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND 30 E151 Header EHOLE Mouser Electronics 517-6111TG 31 J51 SMA SMA Digi-Key Corporation ARFX1231-ND 32 P61 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA 33 2 R1, R21 BRES402 402 XX 34 3 R5, R7, R91 BRES402 402 XX 35 1 U21 ECLOSC DIP4(14)

AD9445


Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No. 36 4 H1, H2, H3, H41 MTHOLE6 MTHOLE6 37 2 T1, T21 Balun transformer SM-22 M/A-COM ETC1-1-13 38 2 P21, P221 Term strip PTMICRO4 Newark Electronics 1 Parts not populated.

Table 12. AD9445-125 IF Customer Evaluation Board Bill of Materials Item Qty. Reference Designator Description Package Value Manufacturer MFG_PART_NO 1 7 C4, C6, C33, C34, C87,

C88, C89 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

2 44 C2, C3, C5, C7, C8, C9, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, C60, C76, C77, C78, C82, C84, C85, C86, C90, C91, C94, C95, C96, C97

Capacitor 402 0.1 F Digi-Key Corporation PCC2146CT-ND

3 2 C30, C58 Capacitor 201 0.01 F Digi-Key Corporation 445-1796-1-ND 4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2 5 1 C51 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND 6 1 CR1 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND 7 1 CR2 Diode SOT23M5 Digi-Key Corporation MA3X71600LCT-ND 8 20 E1, E2, E3, E4, E5, E6,

E9, E10, E14, E18, E19, E20, E24, E25, E26, E27, E30, E31, E36, E41

Header EHOLE Mouser Electronics 517-6111TG

9 2 J1, J4 SMA SMA Digi-Key Corporation ARFX1231-ND 10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU 11 3 L3, L4, L5 EMIFIL BLM31PG500SN1L 1206MIL Mouser Electronics 81-BLM31P500S 12 1 P4 PJ-002A PJ-002A Digi-Key Corporation CP-002A-ND 13 1 P7 Header C40MS Samtec, Inc. TSW-120-08-L-D-RA 14 1 R3 Resistor 402 3.74 k Digi-Key Corporation P3.74KLCT-ND 15 1 R8 Resistor 402 50 Digi-Key Corporation P49.9LCT-ND 16 4 R10, R19, R39, L2 Resistor 402 0 Digi-Key Corporation P0.0JCT-ND 17 1 R11 BRES402 402 1 k Digi-Key Corporation P1.0KLCT-ND 18 2 R28, R35 Resistor 402 33 Digi-Key Corporation P33JCT-ND 19 2 RZ4, RZ5 Resistor array 16PIN 22 Digi-Key Corporation 742C163220JCT-ND 20 1 U1 AD9445BSVZ-125 SV-100-3

Documents

AD9445 14-Bit, 105/125 MSPS, IF Sampling ADC Data Sheet ... file14-Bit, 105/125 MSPS, IF Sampling ADC AD9445 Rev. 0 Information furnished by Analog Devices is believed to be accurate