Compensator Design for Adaptive Voltage Positioning (AVP) for Multiphase VRMs

Martin Lee*, Dan Chen*, Chih-Wen Liu*, Kevin Huang†, Eddie Tseng† and Ben Tai† * Department of Electrical Engineering

National Taiwan University Taipei, Taiwan

† RichTek Technology Corp. Chupei City, Hsinchu, Taiwan

Abstract—In an AVP scheme, feedback compensation design is crucial to achieve a desirable constant converter output impedance while maintaining converter stability. The model proposed and the analysis given provides insightful view of the interaction of the two performances. Depending on the relative location of the noise-suppressing compensation pole with respect to the capacitor ESR-zero frequency, the performance of output impedance and stability margin can be vary a great deal. If the two frequencies are too close to each other, the stability margins get small, and Zoc exhibits a spike /dip at the ESR-zero frequency. This happens in a realistic case, when ceramics capacitors are used and switching frequency is set high. This conclusion is verified in a SIMPLIS simulation of a practical 4-phase VRM.

I. INTRODUCTION Adaptive Voltage Positioning (AVP) scheme has been

used in multiphase synchronous rectifier buck converter topology for satisfying the power requirement of Intel’s CPUs [1]. Use of such a scheme normally leads to lower power dissipation in the CPU and smaller output capacitors required in the power converter circuit.

It has been pointed out that to achieve AVP the closed-loop small-signal output impedance of the converter circuit should be a constant value which is specified by Intel’s requirements [2-3]. The goal of the feedback design is therefore to achieve a desirable output impedance characteristic while still maintaining feedback stability margin.

Figure 1 shows a simplified diagram of a AVP control scheme to achieve active droop control. It has been pointed out that by proper switching-frequency and component scalings, the control behavior of a multiphase converter can be represented by a simplified single-phase control circuit shown in Fig.1 [4]. In the diagram, the sensed output inductor current information is subtracted from the reference voltage and fed into the non-inverting terminal of the error amplifier EA. And the output voltage signal is fed into the inverting terminal. This scheme allows the converter characteristic of output voltage declining with increasing load current as AVP requires.

In this paper, the small-signal average model of buck converter circuit will be reviewed first. A model will then be developed for the AVP control scheme shown in Fig. 1. Investigation will be conducted to the compensator design

for a variety of circumstances. Simulations will be used to verify the results. Practical conclusions will be drawn from the investigation.

S.R. Buck VRMPower Stage

Zf

Z2

Ri1

iL

vo

vdroop

RoVgd

vc

Zoi

Vref

EAFm

Zoc

VP

Fig. 1. VRM buck Controller with AVP control.

II. CONTROL BLOCK DIAGRAM

A. Compensator transfer functions From Fig.1, the diagram around the error amplifier EA

is isolated and redrawn in Fig. 2. From this figure, one can derive that:

vcZfZ2

− vo vdroop+( )⋅ vdroop− ( 1 )

From this equation, the equivalent circuit of the error

amplifier compensation circuit is shown in Fig.3. The voltage droop caused by changing the Vref voltage has been represented by adding the two Vdroop inputs in the circuit shown in Fig.3 . .

Fig. 2. Compensator circuit diagram.

Fig. 3. The equivalent circuit diagram of that shown in Fig.2.

B. Control Block Diagram The control scheme shown in Fig.1 can be represented

by the small-signal block diagram shown in Fig. 4. In the lower-right corner of Fig. 4, Vdroop signal is fed into Sumers A and B. This is to incorporate the equivalent circuit shown in Fig. 3 into the block diagram. Gcom(s) is a transfer function of the compensator and is equal to –Zf /Z1 according to Fig. 3. With the exception of the lower-right corner, the block diagram is similar to that of a conventional current-mode control buck converter. All the transfer functions have been derived before [5], and are listed in Table I.

Fig. 4. Small-signal control block diagram of the AVP circuit shown in

Fig. 1

TABLE I THE TRANSFER FUNCTIONS OF THE CONTROL BLOCK DIAGRAM OF FIG. 4.

Transfer Functions Output current to inductor current:

Gii s( )iL s( )

io s( )

1s

ωesr+

Δ

Duty cycle to inductor current:

Gid s( )iL s( )

d s( )

VgRo

1s

ωR+

Δ⋅

Input voltage to output voltage:

Gvg s( )vo s( )

vg s( )D

1s

ωesr+

Δ⋅

Duty cycle to output voltage:

Gvd s( )vo s( )

d s( )Vg

1s

ωesr+

Δ⋅

Input voltage to inductor current:

Gig s( )iL s( )

vg s( )D

s Co⋅

Δ⋅

Output current to output voltage:

Zo s( )vo s( )

io s( )Resl

1s

ωesr+⎛

⎜⎝

⎞⎟⎠

1s

ωL+⎛

⎜⎝

⎞⎟⎠

⋅

Δ⋅

Voltage loop gain:

Tv s( ) Fm Gvd s( )⋅ Gcom s( )⋅≡

Current loop gain:

Ti s( ) Fm Gid s( )⋅ Ri1⋅ 1 Gcom s( )+( )⋅≡

Compensator gain:

Gcom s( )Zf s( )−

Z2 s( )

Modulator gain:

Fmd s( )vc s( )

1VP

Where VP is the peak value of the saw-tooth waveform.Parameters

ωoRo

Lo Co⋅ Ro Co+( )⋅

ωR1

Ro Co⋅

ωesr1

Resr Co⋅ ωL

ReslLo

Q1

ωo

1

Resr Co⋅LoRo

+

⋅

Δ 1s

Q ωo⋅+

s2

ωo+

Resr : output capacitor ESR. Ro : load resistance. Resl : output inductor resistance. Zoi : output impedance with Ti closed and Tv opened. Zoc : output impedance with both Ti and Tv closed. fzc : frequency of compensation zero. fpc : frequency of switching-noise-suppressing

compensation pole.

The diagram in Fig. 4 is further simplified into that in

Fig. 5, where 1+ Gcom-1 is the equivalent transfer

function when Sumer B in Fig. 4 is eliminated.

Fig. 5. Equivalent control block diagram of that shown in Fig. 4.

C. Useful Equations Loop gains:

From Fig. 5, two loop gain functions, Ti and Tv, are defined as followed:

Tv s( ) Fm Gvd s( )⋅ Gcom s( )⋅≡ ( 2 )

Ti s( ) Fm Gid s( )⋅ Ri1⋅ 1 Gcom s( )+( )⋅≡ ( 3 )

By applying the Mason’s gain formula, the two loop gain, T1(s) and T2(s), evaluated by X and Y respectively, are shown as below:

T1 s( ) Ti s( ) Tv s( )+

( 4 )

T2 s( )Tv s( )

1 Ti s( )+

( 5 )

Converter output impedance transfer functions: The output impedance transfer function with current

loop closed and voltage loop opened is expressed as:

Zoi s( )Zo s( ) 1 Ti s( )+( ) Fm Gii s( )⋅ Gvd s( )⋅ Ri1⋅+

1 Ti s( )+( 6 )

The output impedance transfer function with both the current and the voltage loop closed is expressed as:

Zoc s( )Zo s( ) 1 Ti s( )+( ) Fm Gii s( )⋅ Gvd s( )⋅ Ri1⋅+

1 Ti s( )+ Tv s( )+( 7 )

The relationships between Zoc(s) and Zoi(s) can be derived as:

Zoc s( )Zoi s( )

1 T2 s( )+ ( 8 )

Fig. 6 shows the comparison plots of Zo and Zoi. It can be seen the current loop actually increases the output impedance. Only when the voltage loop is closed will the output impedance be brought down. If a proper T2 is used, the output impedance can be brought to a constant output impedance shown by the “desirable Zoc”.

III. DESIGN FOR A CONSTANT OUTPUT IMPEDANCE FOR AVP

It has been pointed out that a constant output impedance is required to accomplish AVP [5]. In this section, discussion will be given to feedback control to accomplish such a goal. As results of accomplishing this goal, other converter performances such as converter

stability and audio-susceptibility are affected. These performances will be taken into considerations in the discussion.

A. Desirable T2(s) to accomplish a constant output impedance

Using (2), (3), and (5), if Ti>>1, and Gcom>>1, T2 is approximated as follow:

R

esr

i

o

s

s

RRsT

ω

ω

+

+⋅≅

1

1)(

12

( 9 )

To achieve a constant Zoc as shown in Fig. 6, T2 must satisfy the following two conditions:

(a) Ri1 is set to be Resr in (9). (b) T2>>1 for f < fesr. It can be seen that T2 is independent of Gcom as long as

the two assumptions, Ti>>1 and Gcom>>1, hold. Therefore, one can use compensation function Gcom to shape T2 and T2 stability margin without much affecting the output impedance performance.

The two assumptions, Ti>>1 and Gcom>>1, are generally true for frequency much lower than fesr because a compensating pole is normally placed at dc frequency. This will be explained later in Section III-B.

B. Compensation design for AVP Beside output impedance, two other key issues, i.e. the

stability and the audio-susceptibility, need to be taken into considerations. As described previously, T2 is unchanged by the compensation Gcom as long as Gcom and Ti are both much greater than 1. Therefore, a low frequency compensation pole (integrator) can be used in Gcom to boost the low-frequency gain of Ti and Tv and consequently T1 so that audio-susceptibility performance can be improved without much affecting T2 characteristics and the close-loop output impedance performance Zoc. A compensation zero, fzc, should also be placed near the resonance frequency fo to stabilize the loop gain T1. Finally, a compensation pole fpc is normally used to suppress switching-frequency noise. Placement of fpc is flexible, depending on the amount of the noise attenuation required. However, if fpc is too close to fesr, then fpc may have noticeable effects on T1 and T2 stability margin, and Zoc may spike near fesr. This effect will be discussed in details in Sections III-E and F.

C. Cross-over frequewncy fesr From the discussion in the last section, T2 crosses over

at fesr as shown in Fig. 7. As a result, Ti and Tv must also crosses over at fesr. Because of (5), T2 value for frequency beyond fesr can be decreasing with -1 slope or -2 slope depending on whether a noise-suppressing pole is placed. Fig. 7 shows the plots for both cases. In either case, Zoc is essentially the same except for frequency near fesr. Zoc is more likely to exhibit a spike near f = fesr for the case in Fig. 7(b). T2 stability margin will also be affected by the cross-over slope of T2.

A quick explanation of T2 behavior is given below. From (5), for low frequency when Ti>>1, T2 ≈ Tv/Ti, for frequency when Ti<<1, T2 ≈ Tv. Near the cross over frequency fesr, where Ti≈1, T2 behavior depends on the phase angles of Ti and Tv at that frequency. This affects T2 stability phase margin. And according to (8), T2 phase margin affects Zoc behavior near fesr. Spiking of Zoc characteristics may show up near fesr because of low T2 stability margin. This will be explained in Section III-D.

ωR ωoωL ωesr

Fig. 6. Plots of Zo, Zoi and Zoc.

Desirable T2

Tv s( )

Ti s( )

Ro/Resr

Ro/Resr

ωR ωzc ωo

ωesr

(a)

Tv s( )

Ti s( )

ωR ωzc ωo

ωesr

ωpc

(b)

Fig. 7. Plots of Ti, Tv and T2, (a) noise-suppression pole ωpc is much larger than ωesr and

(b) noise-suppression pole ωpc is placed at ω=ωesr.

Fig. 8. Vector summation of 1+Ti.

D. Behavior of Zoc, T2, and T1 near fesr

Near fesr, the amplitude of Ti is nearly unity. However, because of vector summation, 1+Ti can vary from 0 to 2 depending on ∠Ti at that frequency. Fig. 8 shows two examples of 1+ Ti. If ∠Ti =90 degree, then 1+Ti= 2 . If ∠Ti =120 degree, then 1+Ti =1. For any frequency at which ∠Ti >120 degree, then 1+Ti<1 Therefore, T2 function may shows a spike near the fesr according to (5). And the ∠T2 is the difference of ∠Tv and ∠(1+Ti). By the same argument, T2 phase angle at f = fesr affect Zoc near fesr also according to (8).

E. Effects of switching-noise-suppressing compensating pole fpc on Zoc, T1 and T2.

As mentioned in Section III-B, a compensation pole fpc may be used to suppress hardware switching frequency noise in the circuit. To be effective, fpc must be significantly lower than the switching frequency. If fpc >> fesr, then the use of fpc has no direct effect on T2 and Zoc behavior. However, if fpc is close to or even less than fesr, then that may significantly degrade T2 stability margin and Zoc may exhibit a spike near fesr. This is because fpc significantly affects Ti and Tv phase angle at f = fesr, which affects Zoc and T2 at that frequency according to the discussion given in Section III-D.

F. Compensation for circuit using ceramic capacitaors Capacitor ESR zero, fesr, for ceramic capacitors is

normally much larger compared with a electrolytic capacitors such as a commonly used OSCAN capacitors. Therefore, fesr is much closer to or even greater than switching frequency. This means that fpc in such a case is close to or even less than fesr. Similar to the case mentioned in Section III-E, T2 and Zoc behavior would be degraded. In other words, T2 stability margin would be reduced and Zoc would display a spiking behavior. Two practical examples will be shown in the next section to illustrate the point.

IV. DESIGN EVALUATION AND SIMULATION RESULTS

Using the model and the expressions given above, T2 and Zoc functions will be plotted for two practical cases. In case I, large OSCAN capacitors were used in which fesr is relatively small compared to switching frequency.

In case II, small ceramics capacitors were used in which fesr is close to switching frequency.

In both cases, a noise-suppression compensation pole fpc was used. To be effective, fpc must be significantly below switching frequency. The exact component values of the two cases are listed in TABLE II.

TABLE II KEY COMPONENT PARAMETERS Circuit Parameters

CASE I. using large capacitor type Co :Oscon, (820 μF/ 12 mΩ) x12 → 9,840 μF/ 1 mΩ,

fesr=16.17 kHz. Lo :470 nH, per-phase fsw :300 kHz fpc :100 kHz

CASE II. using ceramic capacitors Co :Ceramic, (100 μF/ 1.5 mΩ) x4 → 400 μF/ 1 mΩ,

fesr=1.1 MHz. Lo :100 nH, per-phase fsw :1 MHz fpc :300 kHz Lo : output inductance Co : output capacitance Resr : capacitance ESR In both cases, SIMPLIS simulations were run for a

practical 4-phase VRM to verify the results [6]. The circuit diagram for a SIMPLIS simulation is shown in Fig. 9. From Fig.10 to 14 shows the T2 and Zoc plots for the two cases. Results obtained both the theoretical average-model calculation and the SIMPLIS simulations are shown. The agreement between the calculated and the simulated is generally good. It can also be seen that Zoc exhibits a large spike /dip near f = fesr which leads to less ideal step-load response. Fig.14 and Fig. 15 show the load-step response for the two cases. It can be seen that case I gives a better step response because of no voltage overshoot at step instant.

Fig. 9. Circuit diagram of SIMPLIS simulations for a 4 phase VRM

buck converter

10-(a)

10-(b) Fig. 10. Theoretical T2 plots for (a) CASE I and (b) CASE II.

11-(a)

Zoc

11-(b)

Fig. 11. Theoretical Zoc plots for (a) CASE I and (b) CASE II.

12-(a)

12-(b)

Fig. 12. Simulated T2 plots for (a) CASE I and (b) CASE II.

13-(a)

13-(b) Fig. 13. Simulated Zoc plots for (a) CASE I and (b) CASE II.

Fig. 14. Simulated step-load transient response for CASE I.

Fig. 15. Simulated step-load transient response for CASE II.

V. CONCLUSIONS A Small-signal model was developed for a multiphase

synchronous buck converter with AVP control. Based on the model, various compensation design issues were explored. Depending on the relative location of the noise-suppressing compensation pole frequency with respect to the capacitor ESR-zero frequency, the

Zoc

performance of converter output impedance Zoc and stability margin near the cross-over frequency may vary a great deal. If the two frequencies are closer to each other, the stability margin get smaller, and Zoc is more likely to exhibit a spike/ dip at the ESR frequency and step-load response gets overshoot. This happens in a realistic case when ceramics capacitors are used. This conclusion is verified in a SIMPLIS simulation of a practical 4-phase VRM.

ACKNOWLEDGEMENT This work was supported by grant from National

Science Council of Taiwan (R.O.C.) under Award Number NSC 94-2213-E-002-122 to National Taiwan University. Also the authors would like to thank Transim Technology Corporation, U.S.A. for providing SIMPLIS simulation tool.

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[3] K. Yao, Y. Meng and F.C. Lee, “Control bandwidth and transient response of buck converters,” in Proc. IEEE PESC, 2002, pp. 137−142.

[4] P.L. Wong, “Performance improvements of multi-channel interleaving voltage regulator modules with integrated coupling inductors,” Dissertation of Virginia Polytechnic Institute and State University, March 2001.

[5] R.B. Ridley, B.H. Cho and F.C. Lee, “analysis and interpretation of loop gains of multiloop-controlled switching regulators,” IEEE Trans. Power Electron., ϖολ.3, ππ.489−498, Oct. 1988.

[6] B. Wang, S. Wang, D. Chen, K. Huang, B. Tai and E. Tseng, “Practical Simulation of Control Characteristics of a Current-Mode DC/DC Converter,” in Proc. IEEE PESC, 2006.