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ADC Ultra-Low Power for Micro-Sensors
Ricardo Miguel Farinha Alves
Thesis to obtain the Master of Science Degree in
Electronics Engineering
Examination Committee
Chairperson: Professor Jorge Manuel Torres Pereira Supervisor: Professor Carlos Mexia de Almeida de Azeredo Leme
Co-Supervisor: Professor João Manuel Torres Caldinhas Simões Vaz Member of the Committee: Professor Marcelino Bicho dos Santos
November 2013
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Abstract
Analog-to-Digital converters give us an essential interface between the analog and
digital worlds. These kinds of circuits perform a very important role in mixed-signal electronic
systems.
Over the last years, both power consumption and cost of such circuits have been
continuously decreasing mainly due to the evolution of MOS transistor channel length and new
techniques of power saving as well.
Low power sensors applications such as bio-medical applications, environmental
monitoring or even wireless sensor networks, require highly power efficient ADCs typically with
resolutions of 10 bit with a sample rate of 100 kS/s [1].
One of the typical approaches to implement low power ADCs often involves the choice
of the SAR architecture. This kind of architecture is suitable for low power applications since it
only consumes dynamic power and because there are few active circuits during a conversion.
In a SAR ADC, the energy is consumed mainly by 3 blocks. One is the comparator,
another is the control logic and the other is the charging and discharging of the DAC capacitors.
Minimization of consumption in all three blocks is achieved by careful design leading to below
1uA at 1.2V of supply voltage using 130nm CMOS technology in a 10-bit 100kSps ADC.
Keywords Analog-to-Digital converter, Digital to Analog converter, Switched-Capacitors
Successive approximations algorithm, Switching Techniques, Ultra low Power.
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Resumo
Os conversores analógico-digitais constituem uma interface essencial entre o mundo
digital e analógico. Este tipo de circuitos desempenham um papel muito importante nos
sistemas electrónicos de sinal misto.
Ao longo dos últimos anos, tanto o consumo de potência, como o custo deste tipo de
circuitos tem vindo a decrescer continuamente principalmente devido à evolução do
comprimento do canal do transístor MOS e também devido ao aparecimento de novas técnicas
de poupança de consumo.
Aplicações de sensores ultra low-power tais como aplicações bio-médicas,
monitorização ambiental ou redes de sensores sem fios requerem em geral, ADCs com
resolução de 10 bit e com uma frequência de amostragem de 100 kS/s [1].
Uma das arquitecturas preferidas para implementação de ADCs de baixa potência é a
arquitectura baseada nas aproximações sucessivas, SAR ADC. Este tipo de arquitectura é
adequada para aplicações que exijam baixa potência, porque apenas consomem potência
dinâmica e para além disso, durante um processo de conversão existem poucos circuitos
activos ao mesmo tempo quando comparando com outras arquitecturas.
Num SAR ADC o consumo de energia é dominado por 3 blocos. Um é o comparador,
outro a lógica de controlo e o outro é a carga e descarga dos condensadores do DAC.
Minimização do consumo em todos estes três blocos é conseguida com técnicas apropriadas
obtendo-se um ADC de 10 bits a 100kSps com menos de 1uA de consumo com uma
alimentação de 1.2V usando a tecnologia CMOS de 130nm.
Palavras-Chave Conversor Analógico-Digital, Conversor Digital-Analógico, Condensadores Comutados,
Algoritmo de Aproximações Sucessivas, Técnicas de comutação, Técnica de comutação de
VCM, Ultra Low Power.
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Acronyms
Acronym English Designation Designação em
Português
ADC Analog-to-Digital converter Conversor Analógico-Digital
DAC Digital-to-Analog Converter Conversor Digital-Analógico
ENOB Effective number of bits Número efectivo de bits
FoM Figure of Merit Figura de mérito
LSB Least significant bit Bit menos significativo
MSB Most significant bit Bit mais significativo
RMS Root Mean Square Valor eficaz
SAR Successive approximations
register
Registo de aproximações
sucessivas
SNR Signal to Noise Ratio Relação Sinal Ruído
SINAD Signal to noise and distortion
ratio
Relação sinal ruído e
distorção
VCM Common mode voltage Tensão de modo comum
UMC United Microelectronics
Corporation
United Microelectronics
Corporation
viii
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Acknowledgments
Firstly I would like to thank my supervisors, Professor Carlos Leme and Professor João
Vaz for the support and all the suggestions given throughout the elaboration of this dissertation.
I thank them for providing me the opportunity to work on this project. Their knowledge,
experience and patience was an important factor to complete this work.
I express my gratitude to all my friends at Instituto Superior Técnico, especially André
Costa, Patrick Pereira and Tiago Carvalho. Their company, friendship and support along this
dissertation was a valuable help to complete the work.
Thanks to all other friends and classmates I have had the pleasure to meet and to work
with along the 5 years spent at the university.
I dedicate this work to my parents Libânio Alves and Maria de Lurdes to my sister Inês
Alves and to my closest family. Without their support I couldn’t ever achieve my life goals.
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Content
Abstract ......................................................................................................................................... iii
Resumo ......................................................................................................................................... v
Acronyms ...................................................................................................................................... vii
Acknowledgments ......................................................................................................................... ix
List of figures ............................................................................................................................... xiii
Introduction .................................................................................................... 1 Chapter 1 -
1.1. Motivation .................................................................................................................. 1
1.2. Goals and Challenges ............................................................................................... 1
1.3. Document Organization ............................................................................................. 2
State of the Art ............................................................................................... 3 Chapter 2 -
2.1. Principle of Operation of the SAR ADC ..................................................................... 3
2.2. Successive Approximations Algorithm ...................................................................... 6
SAR ADC Overview ....................................................................................... 9 Chapter 3 -
3.1. Proposed Architecture ............................................................................................... 9
3.2. DAC Switching Techniques ..................................................................................... 10
3.2.1. Set-and-Down Technique ................................................................................ 11
3.2.2. VCM Switching Technique .............................................................................. 12
3.2.3. VCM Buffer-Free Switching Technique ........................................................... 13
3.3. Digital-to-Analog Converter design ......................................................................... 17
3.3.1. DAC Design Constraints and Considerations ................................................. 17
3.3.1.1. Noise Analysis ............................................................................................. 18
3.3.1.2. Capacitor Mismatch ..................................................................................... 19
3.3.2. Binary Weighed Switched-Capacitor DAC ...................................................... 20
3.3.3. Segmented Array DAC .................................................................................... 21
3.3.4. DAC Switches Design and Charge Injection Effects ....................................... 24
3.4. Dynamic Comparator ............................................................................................... 26
3.4.1. Noise Analysis ................................................................................................. 27
3.4.2. Input referred offset Analysis ........................................................................... 27
3.4.3. Kickback Noise ................................................................................................ 31
3.5. Asynchronous Control Logic ................................................................................... 34
3.5.1. Monostable based Delay Element ................................................................... 38
Pre-Layout Results and Simulations ........................................................... 41 Chapter 4 -
xii
4.1. ADC Consumption ................................................................................................... 44
4.2. ADC Static DC Performance ................................................................................... 45
Layout and Post-Layout Results and Simulations ....................................... 47 Chapter 5 -
5.1. Layout Design .......................................................................................................... 47
5.2. Post-Layout Simulations .......................................................................................... 50
Conclusions and Future Work ..................................................................... 53 Chapter 6 -
6.1. Conclusion ............................................................................................................... 53
6.2. Future Work ............................................................................................................. 53
References .................................................................................................................................. 57
Appendix ...................................................................................................................................... 59
xiii
List of figures
Figure 1 - 4 bits ADC illustrating the sampling operation. ............................................................. 3
Figure 2 - 4 bits A/D converter illustrating hold mode. .................................................................. 3
Figure 3 - 4 bits ADC converter illustrating redistribution mode operation.................................... 4
Figure 4 - A/D converter with 4 bit final configuration. .................................................................. 4
Figure 5 - Flow graph for the successive approximation algorithm. .............................................. 6
Figure 6 - evolution of DAC voltage for a 600 mV input signal in a 4 bit ADC. ............................. 7
Figure 7 - Simplified SAR ADC architecture. ................................................................................ 9
Figure 8 - Some control signals during conversion process. ........................................................ 9
Figure 9 - 3-bit ADC example illustrating Set-and-down switching technique. ........................... 11
Figure 10 - 2 bit DAC configuration for 1st and 2nd bit estimation. ............................................ 12
Figure 11 - 3 bit ADC example comparing VCM Switching technique and Set-and-down. ........ 13
Figure 12 - DAC with differential configuration and corresponding circuit to generate VCM. ..... 14
Figure 13 - Steps for VCM generation. ....................................................................................... 14
Figure 14 - DAC and VCM capacitor configuration and steps using the proposed switching
method. ........................................................................................................................................ 15
Figure 15 - Phases of VCM voltage generation and parasitic capacitance Cp influence. .......... 16
Figure 16 - SAR ADC algorithm convergence to VCM voltage (300 mV input signal). .............. 16
Figure 17 - SAR ADC algorithm convergence to VCM voltage (800 mV input signal). .............. 17
Figure 18 - Proposed Filtered DAC in [8]. ................................................................................... 19
Figure 19 - Binary weighted DAC array for an ADC with 10 bit. ................................................. 21
Figure 20 – 6 bit SAR ADC example with segmented array DAC. ............................................. 21
Figure 21 - Proposed segmented DAC architecture with 2 5-bit sub-DACs. .............................. 22
Figure 22 - Segmented DAC with parasitic capacitances in critical nodes. ................................ 23
Figure 23 - Comparison between output DAC voltages in (a) - Binary weighed DAC and (b) -
Segmented DAC. ........................................................................................................................ 23
Figure 24 – Simulated Transmission Gate on-resistance as a function of the input voltage. ..... 24
Figure 25 - Diagram with the necessary switches for each DAC capacitor. ............................... 25
Figure 26 - Charge injection and clock feedthrough effects in a sampling circuit. ...................... 25
Figure 27 - Proposed dynamic comparator schematic. .............................................................. 26
Figure 28 - Probability of comparator correct decision as a function of C1 and C2 .................... 27
Figure 29 - Example of a run in MonteCarlo simulation (for this run the obtained offset is 60
mV). ............................................................................................................................................. 30
Figure 30 - Histogram for comparator MonteCarlo simulation (with minimum widths of input pair
transistors). .................................................................................................................................. 31
Figure 31 - Histogram for comparator MonteCarlo simulation (after redesigning widths of input
pair transistors). ........................................................................................................................... 31
xiv
Figure 32 - Kickback noise generation at the input of differential pair.(a) – Without kickback
noise compensation, (b) – With kickback noise compensation. .................................................. 32
Figure 33 - Simulated input of the comparator without kickback noise compensation (a) and with
kickback noise compensation (b). ............................................................................................... 33
Figure 34 - Block Diagram for asynchronous controller and respective control signals. ............ 34
Figure 35 - Simulated control signals for comparator and for delay generator block. ................ 35
Figure 36 - Schematic of transmission gate based D Flip-Flop with reset. ................................. 36
Figure 37 - Successive Approximation Register, logic block and principal control signals......... 37
Figure 38 - Control Signals generated by Successive approximation register block. ................. 38
Figure 39 - Delay element based on a monostable circuit. ......................................................... 39
Figure 40 -Test Bench setup to measure ADC performance parameters. ................................. 42
Figure 41 - ADC input signal with 12.5 kHz (black line) and ADC output signal (red line). ........ 42
Figure 42 - ADC input signal with 12.5 kHz (black line) ADC output signal (red line). ............... 43
Figure 43 - Measured FFT (1024-point FFT) at a sampling rate of 400 kHz and an input signal
of 8.984 kHz. ............................................................................................................................... 43
Figure 44 - Measured FFT (256-point FFT) at a sampling rate of 200 kHz and an input signal of
10.9 kHz. ..................................................................................................................................... 44
Figure 45 - ADC consumption. .................................................................................................... 44
Figure 46 - Current consumption as a function of the sampling rate. ......................................... 45
Figure 47 - 10 bit ADC characteristics. ....................................................................................... 46
Figure 48 - SAR ADC floorplan. .................................................................................................. 47
Figure 49 - Common centroid configuration of the DAC capacitors. ........................................... 48
Figure 50 - Unitary capacitor designed for this work (based on MOM capacitors). ................... 49
Figure 51 - DAC capacitances and parasitic capacitances after layout extraction. .................... 49
Figure 52 - Common Centroid diagram for comparator input differential pair. ........................... 50
Figure 53 - Successive approximation algorithm convergence at DAC output (Vin = 800 mV). 50
Figure 54 - ADC input signal with 10.937 kHz (black line) ADC output signal (red line). ........... 51
Figure 55 - Measured FFT (512-point FFT) at a sampling rate of 400 kHz and an input signal of
10.156 kHz. ................................................................................................................................. 51
Figure 56 - Conventional NMOS bootstrap switch. ..................................................................... 54
Figure 57 - Comparator layout. ................................................................................................... 59
Figure 58 - SAR ADC layout. ...................................................................................................... 60
Figure 59 - DAC layout. ............................................................................................................... 61
1
Introduction Chapter 1 -
1.1. Motivation
Data converters are widely used as an interface between digital and analog worlds. This
creates a high demand for data conversion circuits. Such circuits are classified into two
categories which are the Analog-to-Digital Converters (ADCs) and Digital-to-Analog converters
(DACs).
Nowadays, the use of portable electronic devices powered by battery has increased in a
large scale. As a consequence, the low power consumption is the most relevant concern when
designing applications of this kind.
ADCs play a key role in wireless sensor networks to create a “network of things”. In the
sensor nodes, the sensed environmental information such as humidity, temperature or magnetic
field, needs to be digitized. This kind of applications requires ultra-low power ADCs.
Lately, several techniques and new circuits with new techniques to save power have been
published. However, the development of new techniques for low power consumption has
continued due to two major reasons. Firstly, semiconductor technology has evolved
continuously, creating new opportunities and solutions to implement new techniques. Secondly,
there has been a constant demand for further reduction of power consumption in this type of
circuits.
There are many approaches for low power ADCs. However the ADC architecture based on
successive approximations is the most suitable for low power applications, mainly due to the
few circuitry active during a conversion process. In addition, this type of architecture is good for
applications with low to medium sampling rates.
This work presents a SAR ADC with 10 bit resolution and asynchronous operation to avoid
the high frequency clock that generally increases the power consumption. Asynchronous logic
allows to use only the conversion clock and no oversampling clock is needed. A dynamic
comparator is used which consumes power only during the actual comparison transient. A split
array allows the reduction of parasitic capacitances and area to the minimum. These techniques
allow to reach below 1uA consumption in a 10-bit ADC running at 100 kSps.
1.2. Goals and Challenges
The main challenge of this work is to design a SAR ADC that consumes about 1 µA.
In order to achieve this goal, an innovative switching capacitors technique will be presented.
The proposed ADC is designed to operate at a sampling rate of 100 kS/s with a 10 bit
resolution. The SAR ADC is implemented with asynchronous logic that minimizes the digital
power consumption. The unit capacitance is designed to achieve not only the noise constraints
2
but also to reduce the analog power consumption. The target performance for this work is to
achieve 9.5 ENOB (Effective Number of Bits) including all noise and distortion sources.
1.3. Document Organization
In Chapter 2 the basic principles of the SAR ADC and the successive approximation
algorithm are explained.
In Chapter 3, the architecture of the SAR ADC is described in detail, including the novel
capacitor switching technique, the dynamic comparator and the asynchronous logic. The basic
blocks of the proposed topology are analyzed and the more important simulations to prove the
working principle are reported as well.
The more relevant schematic simulations of the ADC performance are reported in Chapter
4.
Chapter 5 describes all the considerations taken for the lay-out of the complete ADC and
includes the post-layout simulations.
The conclusions and the future work to be done are reported in Chapter 6.
3
State of the Art Chapter 2 -
2.1. Principle of Operation of the SAR ADC
The SAR ADC consists basically of a comparator, a binary weighted capacitor array, switches and
a control logic to drive the conversion [2].
A conversion process from an analog signal into a digital word is performed by a sequence of
three basic steps. The first step shown in Figure 1 corresponds to the sampling of input voltage Vin.
The capacitors top plate is connected to ground and the bottom plates are connected to the input
voltage. This configuration results in a stored charge at the capacitor top plates which is proportional
to the input voltage Vin.
Figure 1 - 4 bits ADC illustrating the sampling operation.
In the hold mode, depicted in Figure 2, the switch in the top plate is opened and the capacitor
bottom plates are then connected to ground. Considering the charge conservation, the voltage at node
Vx goes to -Vin.
Figure 2 - 4 bits A/D converter illustrating hold mode.
Qx = -2CVin
Qx = -2CVin
4
In the redistribution mode, the conversion process starts by testing the most significant bit (MSB)
which corresponds to the largest capacitor (C). This operation is performed by connecting the
capacitor C bottom plate to the Vref voltage, while the remaining capacitors keep connected to ground.
At this phase, the equivalent circuit corresponds to a voltage divider between two equal capacitors. In
the previous phase, the node Vx, was equal to –Vin and at this phase it increased by half the reference
voltage as shown in (2.1) and in Figure 3.
(2.1)
Figure 3 - 4 bits ADC converter illustrating redistribution mode operation.
The comparator output has the logic value ‘1’ if Vx < 0 and presents the logic value ‘0’ if Vx > 0 as
shown in (2.2)
(2.2)
Similarly, the next bits will be tested until all bits from the most significant to the least significant
are decided. A possible final configuration is represented in Figure 4.
Figure 4 - A/D converter with 4 bit final configuration.
In the final configuration shown in Figure 4 the digital word is 1010. This configuration
corresponds in terms of contribution for the Vx voltage to the value given for (2.3).
(2.3)
Qx = -2CVin
Qx = -2CVin
5
Table 1 shows the state of the art for some ADCs based on successive approximation
architecture. All papers referenced in the table present special switching techniques for the DAC
capacitors in order to reduce the overall consumption of the ADC.
Equation (2.6) indicates the figure of merit (FoM) of an ADC. The equation provides a good way
to compare ADCs in terms of power consumed during the conversion process. The figure of merit of
an ADC is usually expressed in Joules per number of effective quantification steps.
The parameter ENOB corresponds to the effective number of bits, which in turn is given by
equation (2.5). The parameter SINAD reflects the overall ADC performance, since it includes all
components related to noise and harmonic distortion as shown in equation (2.4)
(
) (2.4)
(2.5)
[J/step] (2.6)
In [3] an input range prediction capacitors switching technique is used that allows to reduce the
consumption of the DAC array by up to 81% when compared to the classical topology described
above. However it requires sampling the input signal at the top plate and is sensitive to charge
injection and distortion.
The ADC in [4] also uses top plate sampling.
In [5] , the VCM – switching technique is introduced and it pre-charges the capacitors to a mid-
voltage between Vref and ground. This allows to reduce the DAC consumption by about 56%, but
requires a buffer for the VCM voltage, which can consume significant power.
Table 1 - ADCs performance comparison.
Reference [3] [4] [5]
Architecture SAR SAR SAR
Tecnology 0.13 µm 90 nm 0.18 µm
Resolution 10 bit 10 bit 8 bit
ENOB 8.5 bit 9.1 bit 7.5 bit
Supply Voltage 1.2 V 1.2 V 1V
Sampling rate 50MS/s 100MS/s 500KS/s
Power 920 µW 3 mW 7.75 µW
FoM 51 fJ/step 55 fJ/step 86 fJ/step
6
2.2. Successive Approximations Algorithm
The converters based on successive approximations, implement a binary search algorithm to
determine the closest digital word to the correspondent sampled analog signal.
In the first period, the most significant bit (b1) is determined. In the second period, the next most
significant bit (b2) is determined, followed by bit 3 and so on, until all N bits are decided. Therefore, a
conversion requires N clock cycles to complete an N-bit conversion and requires a high frequency
clock to complete the conversion within one conversion cycle.
The successive approximation algorithm is based on the following procedure. Considering a
random number from 1 to 128, the first question may be whether this number is greater or smaller
than 64 (half scale). If the number is greater, then the next question to ask is whether the number is
greater or smaller than 96, which corresponds to the middle of the range between 64 and 128.
However, if the number is smaller, the next question to ask is whether the number is greater or smaller
than 32, which is the middle value from the range between 0 and 64. Next steps consist on
successively dividing the scales by two until the initial random number is determined. Figure 5
illustrates the algorithm.
To more intuitively understand the algorithm of successive approximation AD converter, the Figure
6 shows an evolution of the voltage at the output of the ADC DAC. The figure is the equivalent to the
algorithm described in the flow chart of Figure 5 and it shows the process in terms of successive
approximation to the input voltage.
Start
Sample Vin, VD/A = 0, i=1
Vin > VD/A
bi = 1
VD/A à VD/A + Vref/2i+1
i à i+1
i >= N
Stop
VD/A à VD/A - Vref/2i+1
bi = 0
No
Yes
Yes
No
Figure 5 - Flow graph for the successive approximation algorithm.
7
0.6
0.3
0.75
1.2
Vo
ltag
e (V
)
1st bit = 1 2nd bit = 0 3rd bit = 0 4th bit = 1
Input voltage = 0.6V DAC voltage
Input voltage
Time
Figure 6 - evolution of DAC voltage for a 600 mV input signal in a 4 bit ADC.
8
9
SAR ADC Overview Chapter 3 -
3.1. Proposed Architecture
The SAR ADC proposed topology is represented in Figure 7. The ADC comprises two differential
capacitor networks, a dynamic comparator and the successive approximation control logic.
Figure 7 - Simplified SAR ADC architecture.
There are many ADC topologies that use several parallel paths to perform a conversion. These
architectures generally need only a clock cycle to complete the conversion operation. Such
characteristics are suitable for applications that require high sample rates and for example the flash
ADC is a good converter that meets those requirements. However, these kinds of characteristics
increase not only the chip area, but also the power consumption of the ADC. Besides that, the offset
error caused by multiple conversion paths is another problem.
On the other hand, the successive approximation architecture presents only a possible path for
the conversion algorithm, but requires multiple clock cycles to perform a conversion. These features
are suitable for applications that demand low to medium sampling rates.
Since the sensor devices require low power ADCs and do not need high sample rates, the SAR
ADC is the preferred architecture for such applications. Figure 8 shows some signals and phases
used in conversion process for the proposed SAR ADC
t
1st phase (reset)
2nd phase(Vin sampling)
3rd phase (1st bit comparison)
VCM generation signals
Comparator clock
Time Scale
Figure 8 - Some control signals during conversion process.
10 bit decision (high frequency clock)
10
To perform a conversion in a 10 bit ADC, at least 12 clock cycles are necessary, considering the
control signals illustrated in Figure 8. All control signals shown in figure, are generated by the control
logic unit. The sequence of the signals illustrated in figure is as follows. At first phase the signal reset
is used to reset all capacitors in DAC to a common mode voltage. After this phase, the sampling signal
(2nd
phase), is used to connect the capacitors to the input voltage and at last the VCM voltage is
connected to DAC capacitors (through control signals “VCM generation signals”) and the DAC
capacitors are set for the first bit estimation. This control signals are better explained at both sections
3.2.3 and 3.5.
3.2. DAC Switching Techniques
The conventional switching techniques are inefficient and much power consumption is wasted in
pre-charging of capacitors and possibly discharging them dependent on the bit decisions. Much of the
power consumed in an ADC (about 30%) is derived from the DAC. In order to reduce DAC
consumption, it is important to design carefully the DAC capacitors as well as developing efficient
capacitor switching techniques.
The order of the capacitors switching in the DAC is always made from the largest capacitance to
the smallest. As a consequence, most of the energy will be consumed in the first DAC switchings.
In general, the power consumption during the switching of a capacitor C for a given voltage Vref,
can be expressed as in (3.3) [6] [7]
In order to better understand the equation (3.3), it is assumed that for the instant time t = 0-, the
input voltage is sampled in DAC capacitors and at the instant time t=0, the capacitor bottom plates are
connected to Vref voltage. The energy associated with this switching can be obtained by
( )
(3.1)
∫ ( ) ∫ ( )
∫
∫
( )
( )
( ( ) ( )
(3.2)
The two equations above can be generalized to any case in which the current to charge the
capacitors is derived from Vref voltage. The equation (3.3) indicates the energy consumed during the
capacitor switching. That formula is obtained considering that ( ) ( ) and ( )
.
( ) (3.3)
11
3.2.1. Set-and-Down Technique
The Set-and-Down technique [3] obtains a half capacitance reduction and as a consequence there
are significant savings in switching energy. While in conventional switching methods, the necessary
MSB transition costs significant switching energy, the Set-and-Down technique avoids the up
transition of the MSB capacitor: the energy needed for the first bit settling is just the necessary to
charge bottom plates parasitic capacitances of DAC array.
The average power dissipation in a N-bit ADC with conventional switching techniques can be
derived as in equation (3.4) as in [5]
∑ ( )
(3.4)
With Set-and-Down technique, in an N-bit ADC is possible to reduce the average switching
energy as in equation (3.5). The equation is shown in [3]. For example for a 10 bit ADC, the proposed
technique in [5], consumes 1365.3CVref2 and the Set-and-Downs technique reduces the consumption
to 255.5 CVref2, which is a reduction of about 81%.
∑
(3.5)
At sampling phase, the top plates of the capacitors sample the input voltage and at the same
instant, the bottom plates of the capacitors are connected to Vref. Next, the comparator determines
which terminal has a higher voltage. During the conversion phase there are only transitions for ground,
not being necessary transitions for Vref voltage. Figure 9 illustrates a 3 bit example of a SAR ADC with
Set-and-Down scheme configuration. However, this procedure is sensitive to charge injection and
distortion resulting in non-linearities in the ADC characteristic such as the error gain, since the charge
injection is linearly dependent on the input sampled voltage. This effect will be analysed with further
detail in section 3.3.4. These effects are consequence of input sampling in capacitor top plates.
Figure 9 - 3-bit ADC example illustrating Set-and-down switching technique.
12
For a 10 bit resolution ADC, and considering equations (3.4) and (3.5), the conventional switching
technique consumes and in turn, the Set-and-down switching technique,
consumes .
3.2.2. VCM Switching Technique
The working principle of VCM Switching [4] is similar to the Set-and-Down technique. Both
techniques reduce the capacitance, that is, both techniques minimize the power consumed during the
largest capacitor transition. In VCM-Switching technique, the parasitic capacitances are charged to
half the reference voltage (VCM voltage) while in Set-and-Down technique, the parasitic capacitances
are charged to Vref.
With VCM-Switching technique, the corresponding capacitor to the most significant bit is not
considered in terms of power consumption. That means that, the DAC bits estimation is done using
just n-1 bits instead of using n bits like in conventional switching techniques, obtaining a half reduction
in capacitance and fewer transitions in capacitors.
The VCM-Switching technique has other advantages. The DAC capacitor transitions to Vref or to
ground are performed after the comparator determines the bit and not before. This does not require
pre-charging of the capacitors and possibly their discharging after the bit decision.
Besides the reduction of capacitance involved in switching process this procedure uses directly
the supply voltage as reference, avoiding the voltage generators during the bit-cycling.
The VCM-Switching technique performs the transitions to Vref or to ground after the comparator
determines which terminal has higher voltage and not before as in conventional techniques. As in Set-
and-down technique, the necessary energy for the first bit comparison is just the necessary to drive
the bottom plate parasitic capacitances which can be reduced by designing properly the DAC and a
good layout implementation. The larger capacitor is used for second most significant bit estimation
and the second most significant bit is used for the third bit estimation and so on.
Figure 10 shows a 2 bit DAC configuration for 2 most significant bits estimation.
Voutp
Voutn
VCM
2C
2C C C
C C
Voutp
Voutn
VCM
2C
2C
C C
C C
VREF
Gnd
1st bit estimation 2nd bit estimation
Figure 10 - 2 bit DAC configuration for 1st and 2nd bit estimation.
Figure 11 illustrates a comparison between the two techniques explained above, the VCM-
Switching technique and Set-and-Down technique. In most of transitions, the energy consumed in
VCM switching technique, corresponds to half of the energy consumed in Set-and-Down technique.
13
The VCM-Switching technique presents an important disadvantage - the technique still requires a
VCM buffer to generate the VCM voltage. This work presents a novel switching technique which
avoids the use of VCM buffer. The technique is based on VCM switching technique and is described in
detail in next section.
CC2C
2C
C C
Vref
Vp
Vn
Vp < Vn
CVref2
1/4CV ref2
3/4CVref
2
Vp < Vn
Vp > V
n
gnd
CC2C
2C C
C
Vp
Vn
gnd
C
C
2C
2C
C C
Vp
Vn
gnd
gnd
CC2C
2C C C
Vcm
Vp
Vn
CC
2C
2C
C C
Vcm
Vp
Vn
Vp < Vn
1/2CVref2
iVcm = 0
gnd
Vref
1/8CV ref2
Vp < Vn
5/8CVref
2V
p > Vn
iRef
C
2C
2C C
C
Vcm
Vp
Vn
gnd
Vref
C
C
2C
2C C
C
Vp
Vn
gnd
C
gnd
Vref
Vref
Vcm
VC
M S
wit
chin
gSe
t an
d D
ow
n
1st bit comparison 2nd bit comparison 3rd bit comparison
CC2C
2C C C
Vref
Vp
Vn
Vref
Vref
Figure 11 - 3 bit ADC example comparing VCM Switching technique and Set-and-down.
3.2.3. VCM Buffer-Free Switching Technique
The proposed solution is depicted in Figure 12.
There are two different phases to generate VCM voltage. At the first phase, C1 and C2 equal
capacitors are connected in series through switches 1 and 3. At this phase, the voltage at the node
between the two capacitors is VCM or VDD/2. At the phase 2, the switches 1 and 3 are opened and
14
simultaneously the switches 2, 4 and 5 are closed. At this phase, the C1 and C2 bottom plates are
connected to ground, while the top plates of both capacitors are connected to DAC capacitors bottom
plates. Figure 13 illustrates the capacitor configuration in both phases.
VDDVDD
GND
VDD
GND
GND
Comparator
Figure 12 - DAC with differential configuration and corresponding circuit to generate VCM.
Figure 13 - Steps for VCM generation.
Since the VCM generation circuit is not buffered, it can provide a very limited output current.
Therefore, the DAC switching scheme must be such that it sinks minimum current from VCM.
Figure 14 represents the 4 steps from the reset until 1st bit decision in the VCM buffer-free
switching technique. This technique requires one additional step to perform the reset in DAC
capacitors. As a consequence, N additional switches are necessary to initially reset all the capacitors
to a common-mode voltage in an N-bit ADC. In conventional VCM-Switching technique, the resetting
is done together with the input sampling because it is done against VCM.
C1
C2
1
2 3
4
5
VCM generator
Phase1 Phase 2
15
VDD
GND
VCMgenerator
Capacitors array
VDD
GND
VCMgenerator
Capacitors array
Vin+
Vin -
Step 1: Capacitors Reset Step 2: Sample input differentially with floating common mode
GND
VCM generator
Capacitors array
Step 3: Reconfigure left capacitors to hold VCM. Set arrays capacitors to VCM
Vout
Vout
+
-
GND
VCM generator
Capacitors array
Step 4: Set first bit (MSB) after comparator decision. Continue for second bit.
Vout
Vout
+
-
VDD
VCM
VCM
GND
Figure 14 - DAC and VCM capacitor configuration and steps using the proposed switching method.
The phases to generate the VCM voltage are represented in Figure 15. Initially the VCM
capacitors (C) are connected in series and the DAC is in sampling phase, resulting in a voltage in the
top plates of the DAC which is equal to Vin/2. At the phase 2, the common top plates of capacitors
CDACn and CDACp are disconnected and the voltage at these nodes remains at Vin/2, since the bottom
plates of the capacitors are still connected to Vin and to ground. At the next phase 3, the VCM
capacitors top plates connect to the DAC capacitors bottom plates. Considering the charge
redistribution and the charge conservation at the terminals of DAC capacitors, the CDACp top plate
voltage is VDD/2-Vin/2, while the CDACn top plate voltage is VDD/2+Vin/2
Ideally, without the parasitic capacitance Cp, the voltage generated by VCM capacitors would
remain constant (VDD/2) when the VCM capacitors connect to the DAC capacitors. However, the
parasitic capacitance of the bottom plates must not be neglected, since by layout extraction, the
parasitic capacitance of the unitary capacitance is about 30 fF. The VCM voltage can be given as in
(3.6)
=
(3.6)
16
Vin
CDACp
CDACn
Cp
Cp
Vdd
Vdd/2
Vin
Cp
Cp
Vin/2
Vin/2
Vin/2
Vin/2 Cp
CpVin
C
C
C
C
Vdd/2
Vdd/2
0Cp
CpVin+Vdd/2-Vin/2
Vdd/2
2Cp2C
Vdd/2-Vin/2
Ph
ase
1P
has
e 2
Ph
ase
3
CCC C
CDACp
CDACn
CDACn
CDACn
CDACp
CDACp
Figure 15 - Phases of VCM voltage generation and parasitic capacitance Cp influence.
In Figure 16 and in Figure 17 is illustrated the successive approximation algorithm using the VCM
Buffer-free switching technique. The input voltages are 300 mV and 800 mV respectively.
Figure 16 - SAR ADC algorithm convergence to VCM voltage (300 mV input signal).
VCM
VCM 1st bit 2
nd bit 3
rd bit 4
th bit 5
th bit 6
th bit 7
th bit 8
th bit 9
th bit 10
th bit
17
Figure 17 - SAR ADC algorithm convergence to VCM voltage (800 mV input signal).
For an input voltage of 300 mV, the DACn output voltage should be 750 mV while the output
voltage of the DACp should be 450 mV. The simulation results in a voltage of 738 mV and 445 mV at
the output of DACn and DACp, respectively. For an input voltage of 800 mV, ideally the output of
DACp and DACn should be 1V and 200 mV, respectively. The measured results are 987 mV and 205
mV.
The simulated values take into account the equation (3.6). The output values of the DAC at the
phase 3 inFigure 15 - Phases of VCM voltage generation and parasitic capacitance Cp
influence.Figure 15 do not consider the parasitic capacitance Cp. Thus, considering Cp, the DAC
output voltages can be rearranged as follows
(
)
(
)
(3.7)
As seen from previous equations, in order to get the ideal values at the DAC output (as in Figure
15) it is necessary to guarantee that the value of C is much higher than the Cp value.
3.3. Digital-to-Analog Converter design
3.3.1. DAC Design Constraints and Considerations
In a ADC, the capacitive DAC is used to generate precise analog voltages in the feedback path.
There are many considerations that must be taken when designing a digital-to-analog converter
for a SAR ADC. The capacitor size of the DAC is a function of various parameters such as the
smallest realizable capacitor (limitation imposed by the technology), thermal noise, mismatch of the
DAC capacitors, power consumption in capacitor DAC and even the settling time of the capacitors.
VCM
VCM 1st bit 2
nd bit 3
rd bit 4
th bit 5
th bit 6
th bit 7
th bit 8
th bit 9
th bit 10
th bit
18
The unit capacitor in the DAC must be kept as small as possible mainly for power consumption
saving. The minimum capacitor in the DAC is usually determined either by thermal noise or by
capacitor mismatch.
3.3.1.1. Noise Analysis
In a switched-capacitor SAR ADC a major contributor for noise is the thermal noise on the
switches that control the DAC capacitors. They form an RC lowpass filter with the capacitors.
It can be demonstrated that the thermal noise in such RC circuits depends only on the value of the
capacitance C according to
√
[VRms] (3.8)
Where k is the Boltzmann constant and T corresponds to the absolute temperature in Kelvin. The
noise contributed during both the sampling phase and the DAC Switching phases must be considered.
Another noise contributor is the comparator itself.
The total noise referred at the input of the comparator is given by equation (3.9).
[VRms] (3.9)
The sampling noise ( ), depends on the total DAC capacitance (CDAC).
[V] (3.10)
The 2nd
term, , corresponds to the DAC noise, where the DAC capacitors are floating and
the relevant capacitance is the parasitics to ground (Cp).
(
)
[V]
if (3.11)
At last, the comparator noise, is better explained in Section 3.4, where all the parameters
of the dynamic comparator are analysed in detail. The comparator is designed to have an input
referred noise of at most 1 mV in order to be much lower than a LSB.
Theoretically, the minimum sampling capacitor Cu is limited by the thermal noise of the sampling
capacitor array. Then, the requirement to design the unit capacitance is given by
19
√
(3.12)
Considering that CDAC is equal to 64Cu and one LSB corresponds to 2Vref/2N, the unitary
capacitance must be at least 0.05 fF. This value is not supported by technology and thus, it is used the
minimum capacitance provided by technology. As shown in equations (3.9) and (3.11), the ADC noise
depends not only on the DAC capacitance and comparator noise, but also on the parasitic
capacitances because the DAC is used in floating configuration.
It can be concluded from equation (3.11) that the DAC noise is much higher than sampling noise.
In order to reduce DAC noise, the capacitance must be increased. However, increasing Cp,
reduces the input voltage to the comparator, which is proportional to /( + ) and increases
consumption.
In [8] an additional capacitor CLPF is used as represented in Figure 18. With this approach, the
DAC noise is approximately reduced to KT/(Cp+CLPF) without degrading the input voltage to the
comparator.
To keep the DAC noise bellow 330 μVrms, and using equation (3.6) CLPF must be 38 fF.
Generally, the bottom plate parasitic capacitances have considerable values. By layout extraction,
these parasitic capacitances is approximately the required (38 fF) and no additional capacitance CLPF
is needed. Figure 18 shows the configuration of CLPF capacitor.
Vref+
Vref-ComparatorSwitch
on-resistance
CLPF
CP
CDAC
Low pass filter C
2C
CP
4C
CLPF
2CLPF
4CLPF
. .
.
Figure 18 - Proposed Filtered DAC in [8].
3.3.1.2. Capacitor Mismatch
In this project, the thermal noise constraint is considered to be dominant over the capacitor
mismatch when designing the unit capacitance. The DAC output is generated based on a
capacitances ratio. In order to get very precise voltages at the DAC output, a good matching of
capacitors is therefore a must, since the mismatch in DAC capacitor will result in non-linearities in the
ADC transfer function, reducing the dynamic range of the proposed ADC.
For a binary weighted DAC array, the worst case in differential nonlinearity (DNL) occurs at the
MSB transition code. So, the DNL analysis can be considered as follows in equations (3.13), (3.14)
and (3.15) [9].
20
√
(3.13)
N is the number of bits of ADC. From technology documentation and for a MIM capacitor (no data
on MOM capacitors was available and so data from a MIM capacitor is used instead) the capacitor
mismatch versus the capacitor area is given by (3.14)
(
)
√ (3.14)
In previous equation, the parameter is the matching coefficient and the parameter A is the area
of the capacitor. Besides that, considering that a given capacitor C is equal to its area multiplied by a
capacitor density coefficient ( ) and considering that to achieve the best possible match, we have to
maintain 3 0.5LSB, combining the previous equations, the unitary capacitance can be given
by equation (3.15)
( ) (3.15)
From technology documentation, the mixed mode capacitors have a matching of about 0.0095%
μm and a density of 1fF/ . From previous equations, the necessary unitary capacitance for the
required matching is 2 fF.
As mentioned before, the noise constraint is the limiting factor over the the mismatch constraints.
However, as the minimum MIM capacitance allowable for this technology is 17 fF, this value is taken
for schematic simulations.
As it will be referred later in report, for layout design limitations, the DAC array is designed with
MOM capacitors instead of MIM capacitors. However the results obtained for mismatch analysis are
considered valid for MOM capacitors, since the limiting factor is the noise constraint.
3.3.2. Binary Weighed Switched-Capacitor DAC
An N-bit binary weighed capacitor array consists basically of binary scaled capacitors, 2N-1
C, 2N-
2C...2C, C. The last capacitor (dummy capacitor) has an equal value to the LSB capacitor so that the
total value of the capacitors is 2NC
Figure 19 illustrates a 10 bit binary weighted array for a ADC. The capacitor correspondent to the
MSB has a value which is 512 times bigger than the smallest capacitor.
21
VDD
GND
Vin
CC21C22C23C24C25C26C27C28C29CDAC
output
Figure 19 - Binary weighted DAC array for an ADC with 10 bit.
3.3.3. Segmented Array DAC
One of the major limitations of the sampling rate in an architecture based on successive
approximation register is often related with the limitations imposed by the RC constant of the DAC
array capacitors.
In a binary weighted array, the capacitors size increases exponentially with the number of bits of
the ADC. This leads to a higher consumption and also to a higher voltage settling time in DAC
capacitors. To overcome this problem, the segmented array technique allows to reduce the total
capacitance in a DAC array. Figure 20 illustrates an example of a 6-bit SAR ADC with a segmented
array DAC.
The figure shows that there are two sub DAC arrays separated by an attenuation capacitor (Catten).
With this technique, the total capacitance is smaller than the total capacitance used in a binary
weighted DAC array. From Figure 20 is possible to get a ratio of 4C/C between the largest and the
smallest capacitance. With the same ADC, using a binary weighted DAC array, the ratio is much
higher (32C/C).
Equation (3.16) gives us the value of the attenuation capacitor [10]. The total capacitance of the
MSB array is equal to the capacitance of the LSB array less C.
(3.16)
C C 2C 4C
VREF
Vin
VCM
LSB array
Catten
4C2CC
MSB array
Figure 20 – 6 bit SAR ADC example with segmented array DAC.
22
Figure 21 depicts the proposed segmented DAC array with two 5-bit sub-DAC. In this work the
capacitance Catten has the value of the unitary capacitance C. Considering the equation (3.16) and the
proposed architecture in Figure 20, the attenuation capacitor has a value of (32/31)C. This
capacitance is difficult to implement in layout, resulting in poor matching between the two sub-DACs.
Therefore, the dummy unitary capacitor in the LSB array was removed, leading to unit capacitance for
the attenuation capacitor which provides best matching.
From Figure 21 the ratio between the largest and the smallest capacitor is now 16C/C while in a
binary weighted DAC the ratio was much higher – 512C/C.
The 5 least significant bits correspond to the left side array, while the 5 most significant bit
correspond to the right side array.
C 2C
4CVREFVin
VCM
4C2CC8C 8C 16C
C
16C
C 2C 4C
VREF
Vin
VCM
4C2CC8C 8C 16C
C
16C
+
-SAR Logic
Figure 21 - Proposed segmented DAC architecture with 2 5-bit sub-DACs.
The segmented DAC array is more vulnerable to parasitic capacitances than the binary weighted
array. Figure 22 depicts some critical nodes with parasitic capacitances Cp1 and Cp2. Generally, the
parasitic capacitance in node Vleft is larger than the capacitance Cp2. The layout of a segmented array
needs to be carefully designed in order to decrease as much as possible the parasitic capacitances
Cp1 and Cp2 and to decrease the non-linearities generated by those capacitances.
Assuming that the bottom plates of the capacitors in node Vleft are connected to voltage Vx, and
the voltage Vright is equal to 0 Volts and considering the voltage divider between left array capacitors
and Cp1, Cp2 and Catten, the voltage at the node Vleft can be given by (3.17) as in [11].
(3.17)
Then the charge contributed to node Vright is given for (3.18)
( ) ( )
(3.18)
As shown in two previous equations, the voltage contribution of the left sub-array depends on the
parasitic capacitances Cp1 and Cp2, which must be minimized in order to avoid non-linearities in ADC
23
C C 2C 4C
VREF
Vin
VCM
4C2CC8C 8CCp1
Cp2
Vout
Catten
VrightVleft
Figure 22 - Segmented DAC with parasitic capacitances in critical nodes.
Figure 23 compares the evolution of the voltages at the output of the DAC. Figure 23 (a)
represents the output voltage of the binary weighted DAC while Figure 23 (b) represents the evolution
of the voltage at the output of segmented array DAC. It is clear to see that as a consequence of the
largest capacitance in (a), the settling time is much bigger than in (b). Since the total capacitance in a
segmented array is much smaller, during the comparator clock rising edge, the glitches are more
visible at diagram (b) than in (a). This problem will be discussed later, in section that analyses the
comparator. The voltage variations in both diagrams are similar.
(a)
(b)
Figure 23 - Comparison between output DAC voltages in (a) - Binary weighed DAC and (b) - Segmented DAC.
24
3.3.4. DAC Switches Design and Charge Injection Effects
The capacitors bottom plate sampling switches have been implemented using transmission gates.
NMOS transistors cannot conduct for source voltages beyond Vdd-Vth, while PMOS transistors cannot
conduct for voltages below Vth. In order to overcome these limitations and to achieve a full range input
sampling, two transistors (NMOS and PMOS) are placed in parallel forming a transmission gate.
Generally, the sampling circuit (capacitor plus on-resistance of the transmission gate) is designed
to achieve a settling error of the input voltage, which is less than half of LSB, for an N-bit converter.
Then, considering the low pass filter formed by transmission gate and the sampling capacitors, the
equation (3.19) must be satisfied [12].
( )
(3.19)
Since in this design the ADC has a 10 bit resolution and the sampling frequency is 100 kHz, the
is about 243 kHz.
Considering a total input sampling capacitance of the ADC of around 0.5 pF, the transmission gate
switches must be designed to have an on-resistance less than 1.3 MΩ. Figure 24 illustrates the on-
resistance of a transmission gate (with minimum widths of the transistors) as a function of the input
voltage. As shown, the on-resistance is much lower than the required for all the range of the input
voltage. The switches to control the DAC switches are represented in Figure 25.
Figure 24 – Simulated Transmission Gate on-resistance as a function of the input voltage.
0 0.2 0.4 0.6 0.8 1 1.2 1.40
2
4
6
8
10
12
14x 10
6
Input Voltage (V)
Resis
tance (
Ohm
s)
PMOS resistance
NMOS resistance
Transmission gate resistance
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
1000
2000
3000
4000
5000
6000
7000
8000
9000
Input Voltage (V)
Resis
tance (
Ohm
s)
X: 0.55
Y: 1911
PMOS resistance
NMOS resistance
Transmission gate resistance
25
Vref+
Vref-
Vin
VCM
ph1
CDAC
nph1
ph2
reset
nph2
nph3
nph4
ph3
ph4
Figure 25 - Diagram with the necessary switches for each DAC capacitor.
With regard to the ADCs, the charge injection generated in the sampling switches results in an
error in the sampled input voltage. The charge injection effects can be minimized by either reducing as
much as possible the sizes of the switches or by having some clock signals slightly advanced with
respect to the remaining signals.
As mentioned in [13], the channel charge of an NMOS transistor can be given by:
( ) (3.20)
Figure 26 shows a sampling switch.
When the MOS switch is closed, the charge is injected onto the sampling capacitor and into Vin
source voltage. Since Vin node can be assumed as a low impedance node, the effect of the charge
injection can be neglected. However, the charge injected onto sampling capacitor, generates a voltage
variation across the capacitor. The voltage variation due to charge injection can be given as in (3.21).
CsampAC Vin
Vdd
Figure 26 - Charge injection and clock feedthrough effects in a sampling circuit.
( )
(3.21)
26
3.4. Dynamic Comparator
Comparators are a very important part of analog-to-digital converters. There are many important
factors that must be considered when designing a comparator, since the accuracy of an ADC depends
largely on the decisions taken by the comparator. For high speed and high resolution ADCs, they are
required to have low input referred offset and high speed operation. Either the input offset voltage or
the input referred noise is the two most critical parameters that must be optimized in a dynamic
comparator.
The dynamic comparator is a good solution for low power ADCs due to no static current
consumption, since there only is current flowing from supply to ground during the clock flanks.
However, these kinds of comparators are generally difficult to analyse, since they do not operate
around a static bias point. Both the noise and offset analysis are not straightforward to perform and so,
not only analytical expressions but also the test benches to simulate the response of the comparator
must be worked carefully.
The proposed dynamic comparator circuit is depicted in Figure 27. The operation principle is not
complicated and is described below. At the first stage clk is low, the comparator is in precharge phase
and both comparator outputs are set to ground. During this phase there is no current flowing from
supply voltage to ground, because transistor M1 is off. In the next phase, clk goes high and the
comparator is in comparison. During this phase, according to the voltage Vi+ and Vi-, the nodes A+ and
A- go to ground at different rates. This effect is reinforced by positive feedback created by transistors
M7 and M8. At the end of this phase, both nodes have different logic values.
The transistors M10 and M11 are necessary to reduce the kickback noise as it will be explained
later.
VDD
GND
Vcomp-Vcomp+
CLK
CLKCLK
Vi-Vi+
M1
M2 M3
M5
M9M8M7M6
M4
A+ A-
B+ B-
CLKCLK
GND GND
C1 C2M10 M11
Vcomp-
Vcomp+
Comp_ready
C+ C-
Figure 27 - Proposed dynamic comparator schematic.
27
3.4.1. Noise Analysis
The noise analysis in dynamic comparators is not easy to perform, since they have no static
biasing point. In comparators to be implemented in an ADC, a fundamental limitation on the available
resolution derives from the thermal noise. The input referred noise of dynamic comparators is
described in [14]. In this work, the author divided the noise analysis into three comparator operation
phases. The input referred noise in a dynamic comparator can be reduced by reducing its bandwidth,
increasing the input stage load capacitors.
Capacitors C1 and C2 are then used to set the input referred noise of the comparator below the
LSB. Due to clocked nature of the dynamic comparator, the noise must be obtained with transient
noise simulations.
Without the capacitors C1 and C2, the input referred noise of the comparator is about 3 mVrms,
which is higher than one LSB for this ADC (LSB = 2.34 mV) and therefore it was decided to reduce the
noise.
To get 1mVrms of input referred noise, the capacitors C1 and C2 were increased until the
probability of correct comparison is 84.1% with a 1mV input signal, which corresponds to the
probability of a gaussian variable going higher than its standard deviation. Figure 28 shows that it is
obtained for C1 and C2 a value of 190 fF to get a 1 mVrms of input referred noise, which is much below
the LSB value of the ADC.
0,4
0,45
0,5
0,55
0,6
0,65
0,7
0,75
0,8
0,85
0,9
0 1 2 3
pro
bab
ility
Differential input voltage (mV)
Probability of comparator right decision
0
(a)
0,45
0,55
0,65
0,75
0,85
0,95
20 70 120 170 220
pro
ba
bil
ity
Capacitance value (fF)
Probability of comparator right decision
0
0
(b)
2,8
0,84
Figure 28 - Probability of comparator correct decision as a function of C1 and C2 capacitance with 1 mV of input voltage.
3.4.2. Input referred offset Analysis
As previously referred, the dynamic comparators are very attractive, mainly because of their high
speed and low power consumption. However, the accuracy of such comparators is highly affected by
their input referred offset, resulting from mismatches in threshold voltage or in current factor β
(µCoxW/L) and also in parasitic capacitance mismatch in both branches of the dynamic comparator.
The offset in a comparator is therefore a parameter of high importance.
28
Offsets are classified into systematic offsets and random offsets. Systematic offsets can be
reduced by a symmetric design and a good layout. On the other hand, random offsets are the result of
random variations during the fabrication process, which may cause mismatches in factor β and in the
threshold voltage of the transistors.
The calculation of offset voltage in a comparator with static bias is well defined and easy to
perform, since all the transistors operation is known. However, in a dynamic comparator, the offset
analysis is not straightforward, since the gm of the transistors depends on the operation phase of the
comparator.
The offset voltage of the differential input stage can be approximated as expressed in equations
(3.22) and (3.23) as demonstrated in [15] and [16]. The transistors M2 and M3 are the most critical for
the offset voltage in dynamic comparator, since
√
( )
√
( )
(3.22)
√
[√
√
(
)
]
(3.23)
From the two previous equations and from [16] it is possible to get the approximation for the
comparator input offset as in equation (3.24), in which the capacitance C is the capacitance at the
source of both transistors M4 and M5
(
)
(
)
(
)
(3.24)
The random mismatch in threshold voltage Vth is given for (3.25), while the random mismatch in
current factor (β) is given for (3.26).
√ , W and L are in µm (3.25)
√ , W and L are in µm (3.26)
From three previous equations, the total input offset voltage increases proportionally to the
threshold voltage mismatch and to the current factor as well. Increasing the area of the transistors
leads to a lower random mismatch in threshold voltage and in current factor. In addition, increasing the
29
capacitances in nodes C+ and C-, reduces the input voltage offset as well. By equations (3.25) and
(3.26), if the area of the comparator is doubled, the offset will be reduced by a factor of √ .
The equation (3.24) is a good approximation to evaluate the offset voltage in dynamic
comparators, since both transistors M2 and M3 start to operate in saturation region during the
evaluation phase (input voltages comparison phase)
Figure 31 depictes an histogram of the final input referred offset of the proposed comparator. The
results were obtained from 1000 iterations of Monte Carlo transient simulations. As shown in the
figure, the standard offset deviation is aproximately 7.8 mV with a mean of -813 uV.
To obtain both the histograms of Figure 31 and Figure 30, it was performed a MonteCarlo
simulation with 1000 iterations. In each iteration it was obtained a similar result as in Figure 29. For
example, for the simulated result shown in the figure there was an offset of 60 mV.
It was necessary to create a good testbench to get accurate results and automatic and fast
simulations, since the output of the comparator just takes logical values, either 1 or 0. The offset
analysis simulation is not as easy as in case of comparators with static biasing in which the output can
generally take any value in range between ground and supply level.
To get an aproximation of the offset value in each iteration, it was applied to one input of the
comparator a ladder shaped signal (with 1mV steps) while in the other input it was applied a DC
voltage with a value of 600mV. For each iteration, the simulator applies a different mismatch in
transistors of the comparator, resulting in different offset values for each iteration. The iteration shown
in Figure 29 resulted in an offset of 60 mV for a given mismatch applied by simulator.
In order to get the histogram of the input reffered offset it was necessary to transform the
comparator output (red line in Figure 29) into a scalar value, so that the simulator can automatically
obtain the histogram of the input referred offset after 1000 MonteCarlo iterations with a transient of T
time. The scalar value of the offset was obtained by (3.27)
In the equation the parameter m corresponds to the slope of ladder signal, the parameter T is
the duration of the transient simulation and the parameter Vinitladder corresponds to the initial voltage
of the ladder signal (at the instant t = 0 µs).
(
∫
)
(3.27)
Figure 29 represents a ladder shapped input signal with 12 mV steps, although the simulation
to get the final offset value was performed with a ladder shapped signal with 1 mV steps to get more
accurate results.
30
Figure 29 - Example of a run in MonteCarlo simulation (for this run the obtained offset is 60 mV).
Figure 30 illustrates the obtained histogram with the minimum width values (W =160 nm), the
standard deviation is about 133 mV and the mean value is about 42 mV. The obtained values for the
input referred offset for a dynamic comparator to be implemented in an ADC are not acceptable, since
it results in an error of about 50 LSB for the ADC proposed in this work.
Therefore, to achieve the values represented in histogram of Figure 31 the widths of the more
critical transistors in terms of mismatch (M2, M3, M10 and M11 in Figure 27) were set to 9 µm. With
these new values, the error caused by the comparator offset is reduced to about 4 LSB, which is much
better.
After setting the widths of those transistors to have relatively large size, the sizes of the remaining
transistors were optimized for high speed, low offset and less power consumption.
31
Figure 30 - Histogram for comparator MonteCarlo simulation (with minimum widths of input pair transistors).
Figure 31 - Histogram for comparator MonteCarlo simulation (after redesigning widths of input pair transistors).
3.4.3. Kickback Noise
There is another source of errors in comparators which is the so called kickback noise. In order to
reduce as much as possible the input referred offset of the dynamic comparator, the widths of the
input pair transistors were increased. However, the larger the widths of the transistors M2 and M3 the
32
more the voltage variations in the internal nodes of the comparator are coupled to the input, disturbing
the input voltage.
When the decision phase starts, the cross coupled inverters make the output voltages go towards
0 or VDD. These large voltage variations are coupled to the input of the comparator through the
parasitic capacitances formed by transistors M2 and M3 which have large widths. This effect on the
input of the comparator may degrade the accuracy of the converter.
In Figure 32 is represented the effect of the Kickback noise at both inputs of the dynamic
comparator differential pair. In diagram (a) the output voltage nodes are coupled to the input through
the capacitances CM2 and CM3 which correspond to the gate-drain capacitance of the transistors M2
and M3 respectively. The input voltage variations (glitches) can be given by equation (3.28)
(3.28)
As mentioned back in DAC topologies analysis, the glitches at the comparator input depend on the
DAC capacitance as seen by equation (3.28). In Figure 23 is possible to see that the glitches are
attenuated using a binary weighted capacitor, which has a higher capacitance CDAC than the
segmented DAC array.
In diagram (b) the transistors M4 and M5 are introduced to reduce the effect of the kickback noise.
These two transistors isolate the large output voltage variations from the input of the dynamic
comparator. The kickback noise is then attenuated since the voltage variations at the drain of
transistors M2 and M3 are reduced by the introduction of two parasitic capacitances CM4 and CM5.
CM3
GND
CLK M1
M2 M3
DC
CDAC
CDAC
CM2
M4 M5
CLK CLK
Vout-Vout+
Vin-
Vin+
CM4 CM5
CM3
GND
CLK M1
M2 M3
DC
CDAC
CDAC
CM2
Vin+ Vin-
Vout+ Vout-
(a)(b)
Figure 32 - Kickback noise generation at the input of differential pair.(a) – Without kickback noise compensation, (b) – With kickback noise compensation.
To verify the real effect of the kickback noise, in Figure 33 are represented two different inputs
of the comparator. In diagram (a) there is no kickback noise compensation and as a consequence,
there is about a 10mV variation in the input voltage of the comparator at the rising edge of the first
comparator clock (corresponds to the first bit decision). That variation introduces in ADC an error of
33
about 5 LSB. With kickback noise compensation, the variation is much lower (about 0.5 mV), although
the glitches have higher amplitude.
Figure 33 - Simulated input of the comparator without kickback noise compensation (a) and with kickback noise compensation (b).
(a)
(b)
34
3.5. Asynchronous Control Logic
As previously mentioned, in this work the control is asynchronous to avoid high frequency clock
generators. Figure 34 represents the control logic block and some important signals that regulate the
entire conversion operation. The SAR ADC control is triggered by an external clock (External clk) with
a frequency of 100 kHz (this ADC was designed to run at a sample rate of 100 kSamples/s, but the
converter can operate at a maximum sampling rate of 1.2 MS/s)
The conversion of an input voltage starts at the rising edge of external clock and when the
conversion is ready the ADC remains idle until the next rising edge of the external clock triggers again
the control unit. That means that the ADC only consumes power during the conversion period. The
control unit is based on work presented in [17].
The external clock is the time reference for SAR ADC operations. However, internally there must
be a clock which must run at least 13 times faster than external clock, considering the reset cycle, the
sampling cycle, the VCM generation cycle and at last the 10-bit cycling.
Clk_delay
Reset
Comp_ready
Clk_comp
+
-
Delay Element
Clk cmpgenerator
EnableLogic and
SA Register
Conv_ready
Sample andReset
generator
Enable generator
Enable
Conv_ready
External clk
. . . . . .
. . . . . .Vin
10 b
Clk_delay
1 2 3 10
External clk
Enable
Clk_comp
Comp_ready
Sam
ple
Sample Time for DAC settling
Figure 34 - Block Diagram for asynchronous controller and respective control signals.
When the external clock goes high, it triggers the signal “Enable” which stays high during the entire
conversion process as shown in Figure 34. As soon as the signal “Enable” goes high, the signal
“sample” goes low. At this time, the converter stops the sampling of the input voltage by oppening the
input voltage sampling switches. As mentioned back in the chapter with the proposed DAC switching
35
technique, the next step after the sampling phase is to reset all DAC capacitors by rising the “reset”
signal. After the reseting, the VCM voltage is connected at the bottom plates of the DAC capacitors.
After the VCM voltage is settled in DAC capacitors (the time needed for capacitors settling is defined
by “delay element” block), the comparator takes the decision.
After the comparator decision, the signal “comp_ready” indicates that the comparator output is
ready. The block “Delay Element” generates a pulse with a duration defined by a monostable. Its
duration allows time for DAC settling and the falling edge of signal “Clk_delay” sequences the operation
of the sucessive approximation algorithm triggering again the block to that generates the clock for the
comparator.
“Clk_comp” clocks the comparator. It is triggered initially by “Enable” and thereafter by the falling
edge of “Clk_delay”. The signal “conv_ready” indicates that the conversion is done after all 10 bits are
decided. It sends the comparator to stand-by, outputs the conversion result and resets the “sample”
signal.
Figure 35 represents the simulated time sequence of the four main control signals for the
comparator. As described above, the figure shows that the rising edge of the signal “Enable” triggers all
the conversion process, initiated by comparator clock until delayed signal (Clk_delay) which defines the
time for DAC settling. The process is repeated until all ten bits are decided.
Figure 35 - Simulated control signals for comparator and for delay generator block.
The transmission gate based D flip flops are the preferred topology for this ADC. Comparing
this architecture with the traditional nand based D flip flop, it is possible to reduce the area of the flip
flop since it requires less transistors than in conventional D flip-flop
36
Basically to implement this topology, two level-sensitive latches are used in cascade. The first
stage tracks the D input when the clock is low and the second stage holds the previous output. Then,
in the rising edge of the clock, the first stage captures the input voltage and transfers it to the second
stage.
When clk is high, both TG1 and TG4 are turned off and TG2 and TG3 are turned on.
Considering that the reset is high, the D input is passed to the output Q at the rising edge of the clock.
On the other hand, when clock goes low, TG1 and TG4 turn on and TG2 and TG3 turn off and then
the value of D input circulates around the inverter and nand at the output Q.
reset
DQreset
nclk
clk
clkclk nclk
ncl
k
Qn
TG 1
TG 2
TG 3
TG 4
Figure 36 - Schematic of transmission gate based D Flip-Flop with reset.
Figure 37 represents the successive approximation register schematic, the logic block and the
main control signals that drive the DAC switches either to the VCM voltage or to Vref+/Vref
- . The first
array of the SAR register (shift register) controls the logic block through signals “s” and. For the
proposed switching technique, all the ten capacitors are connected either to VCM or to Vref+ or Vref
-
during the conversion process. The signal “clk” corresponds to the signal “Clk_delay” referred in
Figure 35. As explained before, this signal controls the timing for DAC capacitors settling.
The second array of Flip Flops (Bit Register) is controlled by signals “s” and “COMP”. These
flip flops are used to save the value of the decision of the comparator (signal COMP). The signal
“COMP” is generated by a Latch SR, which saves the value of the comparator output until the next
comparator decision. Figure 38 shows the timing sequence of the signals sw1 until sw10 used to
control the operation sequence in second array of flip flops.
It is important to guarantee non-overlapping in the signals generated by logic and by
successive approximation register block, since two different switches to same capacitor cannot be
closed at the same time resulting in errors during the conversion. The non-overlap between signals is
guaranteed by using inverters to delay the output signals of the shift register and logic block.
37
reset
clk
Q
Qn
Dreset
clk
Q
Qn
D
clk
Q
Qn
D
reset
clk
Q
Qn
Dreset
clk
Q
Qn
D
clk
Q
Qn
D
clk
Q
Qn
D
enable
COMP
clk
Q
Qn
Dbit1
nbit1
bit2
nbit2
bit9
nbit9
bit10
nbit10
s1 s2 s9 s10vdd
clk
s1 s2 s9 s10
s8
Shift Register
Bit Register
Logic Block
COMPS
R
Q
Qn
comparator
. .
.
.
s9
s10
s1
s2
b1 b2 b3 b4
nb1
nb2
nb9
nb10
Vref+
Vref-
b1
nb1
bit1C1
VCM
Vref+
Vref-
b2
nb2
bit2C2
Vref+
Vref-
b9
nb9
bit9C9
Vref+
Vref-
b10
nb10
bit10C10
. .
.
.
VCM
VCM
VCM
VCM_gen
VCM_gen
VCM_gen
VCM_gen
VCM1 nVCM1
VCM2 nVCM2
VCM9 nVCM9
VCM10 nVCM10
VCM1
VCM2
VCM9
VCM10
nVCM1
nVCM2
nVCM9
nVCM10
DAC switches and capacitors
Figure 37 - Successive Approximation Register, logic block and principal control signals.
38
Figure 38 - Control Signals generated by Successive approximation register block.
3.5.1. Monostable based Delay Element
It is very important to define the necessary time for DAC settling. If this time is too short, the
capacitors in DAC may not be completely charged when comparator starts the comparison, resulting
in incorrect decisions and in incorrect conversions as well.
On the other hand, if the time defined by delay block is too long (longest than the necessary time
for DAC settling), there is an unnecessary wasting of power, since the power consumption in a
monostable is proportional to the delay that it creates. Besides that, increasing the pulse duration of
the monostable delayed output signal, results in a longer conversion time and as a consequence, the
maximum allowable sampling rate of the ADC is lower.
Figure 39 represents the schematic of the monostable used in this work. The pulse duration of the
output signal is a function of the capacitor C (25 fF) and the equivalent resistor formed by transistor
M1, which is designed to have a large L (40 µm). Both transistors M1 and M2 operate as switches,
while transistors M3 and M4 correspond to the inverter1 and the transistors M5 and M6 correspond to
the inverter2.
39
L >>>
C
vdd
gnd
OU
T
R
IN
L >
L >
vdd
gnd
OU
T
L >IN
L >>>
CR
M1
M2
M3
M4 M5
M6
inv1
inv2
Figure 39 - Delay element based on a monostable circuit.
40
41
Pre-Layout Results and Simulations Chapter 4 -
The ADC´s dual functions, the quantization and the sampling, provide an efficient
transformation from the analog to digital world. However, both functions have consequences
with regard to the ADC´s performance.
The SNR or signal to noise ratio is a good metric to determine the performance of an ADC.
The SNR relates the power of the noise generated in ADC during a conversion and the RMS
full-scale signal. In an ideal ADC in which the quantization noise is the only contributor for
distortions, the SNR can be given by (4.1) in which N corresponds to the number of bits.
( ) (4.1)
The previous equation gives only the theoretical limit for a SNR in a N-bit converter. For this
work, considering equation (4.1) and with 10 bit resolution, it is possible to achieve at most a
SNR of 61.96 dB. Real converters do not provide this level of performance, mainly because of
the additional sources of noise as described in this report. However, formula (4.1) is a good
reference to judge the candidate ADC
Taking into account all the noise sources described throughout the report, the signal to
noise ratio of a non-ideal ADC is given by equation (4.2) in which the parameter VREF
corresponds to the reference voltage, Cp is the parasitic capacitance at the comparator input
and CDAC is the total DAC capacitance. The main sources of noise (in the denominator) are the
sampling noise, the DAC noise and comparator noise as described previously in report.
Reducing the noise generated from all sources by increasing either the DAC capacitance
or the decreasing comparator noise is therefore a must to achieve the maximum SNR.
(
)
(4.2)
The Test Bench Setup for measuring the ADC performance is depicted in Figure 40, in
which the designed ADC samples a sine wave at a sampling rate defined by signal clock. The
ideal DAC was implemented with Verilog-A code, which converts the 10-bit word from the ADC
into an analog voltage. The output of the ideal DAC is then exported to a csv file (comma
separated values file) which is after used in Matlab® software in order to obtain the
performance parameters of the ADC.
42
ADC under test
Ideal DAC
bit1
bit2
bit3
bit4
bit5
bit6
bit7
bit8
bit9
bit10
vdd
gnd
Vin+
Vin-
bit1
bit2
bit3
bit4
bit5
bit6
bit7
bit8
bit9
bit10
Co
nve
rsio
nre
ady
out_DAC
.csv file
Matlab
Co
nve
rsio
nre
ady
CADENCE environment
clo
ck
Figure 40 -Test Bench setup to measure ADC performance parameters.
Figure 43 represents the measured spectrum of a 8.984 kHz sine wave with amplitude and
a mean value of 600 mV. The signal was sampled at a sampling rate of 400 kS/s. The
measured SNDR is 58.9 dB.
Considering the equation to get the effective number of bits in the Chapter 2, which relates
the ENOB with the SNDR, for this ADC is obtained a 9.49 ENOB, which is around the design
specification (9.5 ENOB).
Figure 41 illustrates ADC output signal (red line) sampled at a frequency of 500 kHz. The
input signal is a sine wave with 1.2 V of amplitude and with a frequency of 12.5 kHz. The red
line was obtained with the ideal DAC as in Figure 40.
Figure 41 - ADC input signal with 12.5 kHz (black line) and ADC output signal (red line).
43
Figure 42 shows another simulation with the same input signal of the Figure 41 In this
simulation, the input signal was sampled at a sampling rate of 1 MS/s.
Figure 42 - ADC input signal with 12.5 kHz (black line) ADC output signal (red line).
Figure 43 - Measured FFT (1024-point FFT) at a sampling rate of 400 kHz and an input signal of 8.984 kHz.
20 40 60 80 100 120 140 160 180 200
-100
-80
-60
-40
-20
0
X: 9.002
Y: 0
Am
plit
ude (
dB
)
Frequency (kHz) Fs/2
44
Figure 44 - Measured FFT (256-point FFT) at a sampling rate of 200 kHz and an input signal of 10.9 kHz.
4.1. ADC Consumption
Figure 45 illustrates the consumption of the three main blocks of the ADC running at a
sampling rate of 100 kS/s: The comparator consumes almost half of the total consumption. The
capacitors at the input differential pair of the comparator are the main contributors for the
consumption in the dynamic comparator. The DAC consumption comes from the capacitors
switchings. The value is obtained when all the capacitors are connected to Vref+. At last, the
digital block (SAR Register and logic block) consumes about 37% of the total consumption. To
minimize the consumption of this block, the widths of the transistors are set to the minimum
allowed by technology.
Figure 45 - ADC consumption.
0 10 20 30 40 50 60 70 80 90 100-80
-60
-40
-20
0
20
40
X: 11.11
Y: 31.6
Frequency (kHz) Fs/2
Pow
er
(dB
)
SAR Register and logic block - 353.9
nA 37%
DAC - 162 nA 17%
Comparator- 435 nA
46%
ADC Overall Consumption
SAR Register and logicblock - 353.9 nADAC - 162 nA
Comparator- 435 nA
45
Most of the time, the comparator is in idle state and the power consumption depends
directly on the sampling rate. For higher sampling rates, the idle state is shorter and as a
consequence the average current consumption increases. Figure 46, relates the sampling
frequency with the current consumption. For sampling frequencies of 10 kHz the current driven
from supply can be as small as 200 nA. On the other side, for sampling frequencies of about 1
MHz, the consumption can reach up to almost 10 μA.
Figure 46 - Current consumption as a function of the sampling rate.
4.2. ADC Static DC Performance
Gain error is defined as the deviation between the last actual transition and the last ideal
transition. The last actual transition means the transition from 3FE to 3FF for a 10-bit ADC. In an
ideal case, the transition from 3FE to 3FF in a 10-bit ADC should occur when the input voltage
is equal to the full-scale voltage less 0.5 LSB.
On the other hand, the offset error is defined as the deviation between the first actual
transition and the first ideal transition.
Figure 47 shows an offset error of approximately 0.05 LSB, which corresponds to 117 µV
while the gain error is about 9.4 mV which corresponds to 4 LSB.
101
102
103
104
0
1
2
3
4
5
6
7
8
9
10
X: 100
Y: 0.912
Sampling Frequency (kHz)
Curr
ent
consum
ption (
uA
)
46
ADC input voltage (V)
0.05 LSB
4LSB1...111
1...110
1...000
1...001
1...010
1.2
Measured
Ideal 9.4 mV
gain error
offset error
ADC code output
=117 uV
Figure 47 - 10 bit ADC characteristics.
47
Layout and Post-Layout Results and Chapter 5 -
Simulations
5.1. Layout Design
The floorplan of the SAR ADC is illustrated in Figure 48. In this floorplan the capacitors for
VCM generation are not considered. The ADC layout configuration was planned to be
symmetric to avoid as much as possible offset errors and mismatches in the two main blocks of
the ADC – comparator and DAC:
Figure 48 - SAR ADC floorplan.
The two most critical blocks in terms of layout implementation are the comparator and the
two DAC sub-blocks. These three blocks must be carefully designed and must be symmetric in
order to avoid non-linearities due to an asymmetrical implementation. As previously referred, in
the comparator section, the input offset of the comparator (mainly the systematic offset) can be
highly affected if the comparator layout is not carefully designed.
Layout design techniques as common centroid are therefore a must, principally in input
differential pair of the comparator (which are the most critical transistors in terms of systematic
offset)
As in comparator, the capacitors in the two DAC sub-blocks are critical in terms of
mismatch caused by process variations. The implemented common centroid configuration is
illustrated in Figure 49. The left sub-array corresponds to the 5 LSB capacitors and the right sub
array corresponds to the 5 MSB capacitors. The DAC configuration is set not only to achieve a
good matching between the capacitors and also to minimize the parasitic capacitances between
the adjacent capacitors. Therefore, as shown in Figure 49, all capacitors are shielded by a layer
48
of ground (dashed line) in order to reduce the parasitic capacitance between capacitors.
Besides that, the configuration for the proposed common centroid for DAC capacitors minimizes
the routing of both bottom and top plates of the capacitors.
Dummy Capacitor
Unitary Capacitor (C) 16C Capacitor
4C Capacitor
8C Capacitor
2C Capacitor
Catten Capacitor (C)
Metal 5
Metal 4gnd
LSB
su
b-a
rray
MSB
su
b-a
rray
Figure 49 - Common centroid configuration of the DAC capacitors.
The design technology in this work (UMC 130 nm) provides two different types of
capacitors: MOM or metal-oxide-metal capacitors and MIM or metal-insulator-metal capacitors.
The ADC capacitors were firstly implemented with MIM capacitors which have the higher
capacitance density per μm2 (1 fF/ μm
2, accordingly to the technology documentation). Besides
that, since the MIM capacitors are designed above the last metal, they have minimum parasitic
capacitances to the substrate. On the other hand, the MOM capacitors have lower capacitance
density and higher parasitic capacitance to the substrate, since they are designed in the 5 lower
metals.
However, the technology layout design rules present some limitations in terms of spacing
between two adjacent MIM capacitors because they use top metal. For example the minimum
allowable distance between two adjacent top plates is 1 μm and routing lines are 3 μm wide.
Since the implementation of the DAC requires high capacitance density to reduce as much as
possible the dispersion between capacitors, this distance was not considered affordable.
Therefore, the MOM capacitors were the final choice over the MIM capacitors, since the
distance between two adjacent capacitors is only the allowed distance between two metals (0.2
μm), which is much smaller
The available MOM capacitors have a minimum capacitance of 25 fF, which was
considered high, given the noise and mismatch analysis performed previously in this work.
There was the necessity to reduce this capacitance to lower values and to design a capacitor
based on the MOM capacitor provided by technology. One of the main restrictions when laying
out a DAC is to guarantee that the ratios between DAC capacitors are maintained. Thus, the
precise value of the capacitor is not so relevant, provided that the noise requirements analysed
49
in Chapter 3 are guaranteed. By layout extraction, the designed capacitor has a value of
approximately 15 fF. The layout of the designed unitary capacitor is represented in Figure 50.
Figure 50 - Unitary capacitor designed for this work (based on MOM capacitors).
In Figure 51 illustrates the parasitic capacitances (red capacitors) after the layout
extraction. The ratios of DAC capacitances are maintained, and the unitary capacitor has a
value of around 15 fF. The parasitic capacitances at the top plates of both sub-DACs have a
value of around 28 fF and 19 fF for LSB array and MSB array, respectively. These capacitances
affect the voltage contribution from left sub-array to the right sub-array, which may degrade the
ADC performance.
The parasitic capacitances at the bottom plates of the DAC capacitors, don´t affect the
ADC performance, since those nodes are always connected to a voltage source. However, as
long as the capacitances at those nodes increase, the power consumption of DAC array
increases, as well. Besides that, these parasitic capacitances to ground can be used to reduce
the DAC noise as explained before in section 3.3.1.2.
15.2f 30.47f 60.94f 121.7f 243.4f 15.3f
15.2f
30.57f 60.9f 121.7f 243.2f
19.3f27.9f
12.7f 22.42f 39.84f 72.2f 145f 12.3f 41f 72.8f21.1f 145f
C 2C 4C 8C 16C
C
C 2C 4C 8C 16C
15.3f 30.49f 60.94f 121.8f 243.5f 15.2f
15.2f
30.59f 61f 121.8f 243.3f
19.2f27.7f
12.8f 22.41f 39.84f 72f 144f 12.2f 41f 72.85f21.1f 145f
C 2C 4C 8C 16C
C
C 2C 4C 8C 16C
-SAR Logic+
Figure 51 - DAC capacitances and parasitic capacitances after layout extraction.
The common centroid configuration for the input differential pair of the dynamic comparator
is illustrated in Figure 52. The 4 transistors have a width of 9 µm. In layout, each transistor is
50
divided into 12 small transistors with 760 nm of width. The complete layout of the comparator is
in Appendix.
D
C
C
D
GND
CLK
Vi-Vi+
CLKCLK
A B
C D
WB = 9 umWA = 9 um
WC = 9 um WD = 9 umC
D
D
C
A
B
A
A
B
B
A
C
D
D
C
C
D
D
C
A
B
B
A
B
A
A
B
D
C
C
D
D
C
C
D
B
A
A
B
B
A
A
B
B
Figure 52 - Common Centroid diagram for comparator input differential pair.
5.2. Post-Layout Simulations
The Figure 53 illustrates the successive approximation algorithm at the DAC output for an
input voltage of 800 mV. The simulation was performed after a RC layout extraction. Ideally, at
the phase “VCM”, the voltage at the output of the DACn should be around 1V (VCM+Vin/2) and
the output voltage at the DACp should be 200 mV (VCM –Vin/2). AS the figure shows, the DAC
output voltage is around 956 mV and 233 mV, for DACn and DACp, respectively. At the end of
the conversion (10th bit) the algorithm converges approximately to VCM.
Figure 53 - Successive approximation algorithm convergence at DAC output (Vin = 800 mV).
Figure 55 illustrates the measured spectrum of the sine wave (red line) in Figure 54 The
input signal (black line) has a frequency of 10.937 kHz with amplitude and a mean value of 600
mV. The signal was sampled at a sampling rate of 400 kS/s. The measured SNDR is 49.2 dB
giving an 8.87 ENOB. Comparing this value with the value obtained at the schematic level,
there was a reduction of about 1 ENOB. One of the causes is related with an increasing of the
VCM 1st bit 2
nd bit 3
rd bit 4
th bit 5
th bit 6
th bit 7
th bit 8
th bit 9
th bit 10
th bit
51
parasitic capacitance at the critical nodes such as at the comparator input and at the DAC
output which degrades the SNR.
Besides that, the ratios of the DAC capacitors implemented in layout may not have been
maintained as in schematic level. For example a large variation at the attenuation capacitor
value which is the most critical capacitor in DAC, may lead to a large error in the ADC
characteristic.
Figure 54 - ADC input signal with 10.937 kHz (black line) ADC output signal (red line).
Figure 55 - Measured FFT (512-point FFT) at a sampling rate of 400 kHz and an input signal of 10.156 kHz.
20 40 60 80 100 120 140 160 180 200
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
X: 10.2
Y: 0
Am
plit
ude (
dB
)
Frequency (kHz) Fs/2
52
1
53
Conclusions and Future Work Chapter 6 -
6.1. Conclusion
In this work an ultra-low-power ADC for micro-sensors to run at a sampling rate of 100 kS/s
is designed at transistor level and at layout level. The ADC utilizes a low power design strategy,
imposing maximum simplicity on ADC architecture, using low power consumption switching
schemes and a dynamic comparator which consumes only at the clock flanks.
The ADC achieves 9.49 ENOB with a power consumption of 0.9 μA at a sampling rate of
100 kS/s at the schematic level. The two main goals of this work were fully achieved: 9.5 ENOB
and a consumption below 1 μA. At the schematic level, the ADC has a FoM of 15 fJ/step.
At the layout level, the ADC achieves a 8.87 ENOB with a consumption of 1.7 μA. These
achievements result in a FoM of 43 fJ/step. The figure of merit considerably increased when
compared to the results obtained at schematic level. The effect of the parasitic capacitances in
the most critical blocks and nodes such as in comparator input and in DAC arrays has a great
influence on ADC performance, reducing the SNR and increasing the overall consumption,
which reduces the ADC FoM.
In this work is proposed a novel switching technique – the VCM buffer free switching
technique. The proposed technique is confirmed by a 10-bit split DAC based SAR ADC
designed in 130nm CMOS with 1.2V power supply
There are many switching capacitor techniques to use in a low power ADC. The most
common for these requirements are the Set-and-Down-Technique and the VCM switching
techniques. Both of these procedures have some limitations either by charge injection effects
due to the top plate sampling or by the necessity of a VCM voltage generator. The proposed
switching technique comes to overcome the mentioned problems.
In a data converter, the comparator is always a critical block. In this work, great efforts are
spent on the design of the comparator to reduce as much as possible the input referred noise
and the offset with minimal increase on the comparator consumption
To overcome layout limitations imposed by the technology, a new capacitor had to be
created, since the capacitance of the capacitor provided by technology was too large.
The realization of this dissertation allowed to verify the real differences between a layout
and a schematic level implementation.
6.2. Future Work
In a converter, the switches to drive the capacitors are fundamental for the overall
performance of the ADC. For example, the problems related with charge injection are one of the
main factors for linearity in a converter. The transmission gate is a good implementation for a
switch since it passes a full range input signal.
54
However, for some simulations with corners, and considering a variation of ±10% in the
supply voltage, the switches have a high threshold voltage of about 540 mV. This is a problem
for input voltages around 600 mV, which is an issue for the switches that generate the VCM
voltage and for the sampling switches as well.
To overcome this problem, the gate-bootstrapped sampling technique is required, since the
switches control voltage is added to the input voltage making the transistor VGS constant and
independent of the input signal.
The solution is to implement bootstrapped switches as represented in Figure 56. The circuit
is triggered by signal clk, which turns off and on the transistor M13. When clk is low, the gate of
transistor M13 is discharged to ground and simultaneously the voltage Vdd is applied across the
capacitor C3 by transistors M3 and M10.
At the next phase, (clk is high) the transistor M5 pulls down the gate of the transistor M7, and
then the charge from capacitor C3 flows to the gate of transistor M13. Thus, the gate source
voltage of transistor M11 (node G) is kept constant, regardless of the input signal, since the gate
voltage of M13 is boosted to approximately Vin+Vdd provided that M12 connects the voltage Vin to
the bottom plate of C3.
clk
clk
nclk
nclk
G
C1 C2 C3
Vin
Vout
M1
M2
M3
M4
M5
M7
M8 M9
M10
M11
M12 M13
Vdd
Figure 56 - Conventional NMOS bootstrap switch.
The expected results at the layout level were not fully achieved. It is also proposed as a
future work, to reduce both the power consumption, which has increased significantly when
compared to schematic values, and to improve the ENOB as well.
A further analysis in the implemented DAC layout block must be done in order to verify if
the correct ratios between the capacitors are maintain as in schematic level. The parasitic
capacitances after the layout extraction are the main factor for the reduction of the ADC
performance. For example, the lateral parasitic capacitances between a capacitor and the
grounded guard-ring increase the consumption. In layout the distance between the guard-ring
and a capacitor was set to be the minimum allowed by technology (0.2 μm). As a future work,
this distance must be increased in order to reduce the lateral capacitance between the guard-
ring and the capacitor at the expense of a slightly larger DAC.
The routing at the input of the comparator (top plates of DAC capacitors) must be analysed
and redesigned if necessary, since the parasitic capacitances at this node are critical for the
overall ADC performance.
55
At last, it is important to perform a further characterization of the complete ADC parameters
(after all optimizations in ADC layout).
It is also proposed to fabricate the ADC and to re-evaluate the ADC performance
parameters and compare them with the values measured at the layout level. This gives a good
insight in terms of the real differences between the simulator level and the fabricated chip.
56
57
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59
Appendix
Figure 57 - Comparator layout.
Capacitors for noise reduction
60
Figure 58 - SAR ADC layout.
SAR Register and logic
DACp
DACn
Bus and Switches
Comparator
VCM capacitors
VCM capacitors
C1 C1 C1 C1 C1
C1 C1 C1 C1
C2 C2 C2 C2
C2 C2 C2 C2 C2
61
Figure 59 - DAC layout.
LSB DAC array MSB DAC array
62
