Adder (Electronics) - Wikipedia, The Free Encyclopedia

Half adder logic diagram

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In electronics, an adder or summer is a digital circuit that performs addition of numbers. In manycomputers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also inother parts of the processor, where they are used to calculate addresses, table indices, and similar operations.

Although adders can be constructed for many numerical representations, such as binary-coded decimal orexcess-3, the most common adders operate on binary numbers. In cases where two's complement or ones'complement is being used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor. Other signed number representations require a more complex adder.

1 Half adder2 Full adder3 More complex adders

3.1 Ripple-carry adder3.2 Carry-lookahead adders3.3 Lookahead carry unit3.4 Carry-save Adders

4 3:2 compressors5 References6 External links

The half adder adds two single binary digits A and B. It has twooutputs, sum (S) and carry (C). The carry signal represents anoverflow into the next digit of a multi-digit addition. The value of thesum is 2C + S. The simplest half-adder design, pictured on the right,incorporates an XOR gate for S and an AND gate for C. With theaddition of an OR gate to combine their carry outputs, two half

adders can be combined to make a full adder.[1]

The half-adder adds two input bits and generate carry and sum whichare the two outputs of half-adder.

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adderadds three one-bit numbers, often written as A, B, and C

in; A and B are the operands, and C

in is a bit carried

in from the next less significant stage.[2] The full-adder is usually a component in a cascade of adders, whichadd 8, 16, 32, etc. bit wide binary numbers. The circuit produces a two-bit output, output carry and sumtypically represented by the signals C

out and S, where . The one-bit full adder's

truth table is:

Adder (electronics) - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/Full_adder#Full_adder

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Schematic symbol for a 1-bit full

adder with Cin

and Cout

drawn on

sides of block to emphasize their use

in a multi-bit adder

Full-adder logic diagram

4-bit adder with logic gates shown

Inputs Outputs

A B Cin

Cout S

0 0 0 0 0

1 0 0 0 1

0 1 0 0 1

1 1 0 1 0

0 0 1 0 1

1 0 1 1 0

0 1 1 1 0

1 1 1 1 1

A full adder can be implemented in many different ways such as witha custom transistor-level circuit or composed of other gates. Oneexample implementation is with and

.

In this implementation, the final OR gate before the carry-out outputmay be replaced by an XOR gate without altering the resulting logic.Using only two types of gates is convenient if the circuit is beingimplemented using simple IC chips which contain only one gate typeper chip. In this light, Cout can be implemented as .

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder,connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the

two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Cout could be made

the three-bit majority function of A, B, and Cin.

Ripple-carry adder

It is possible to create a logical circuit using multiple full adders toadd N-bit numbers. Each full adder inputs a Cin, which is the Cout of

the previous adder. This kind of adder is called a ripple-carry adder,since each carry bit "ripples" to the next full adder. Note that the first(and only the first) full adder may be replaced by a half adder.

The layout of a ripple-carry adder is simple, which allows for fastdesign time; however, the ripple-carry adder is relatively slow, sinceeach full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay caneasily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input tocarry in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays. A design with

alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.[3]

Carry-lookahead adders


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4-bit adder with carry lookahead

A 64-bit adder

Main article: Carry-lookahead adder

To reduce the computation time, engineers devised faster ways to addtwo binary numbers by using carry-lookahead adders. They work bycreating two signals (P and G) for each bit position, based onwhether a carry is propagated through from a less significant bitposition (at least one input is a '1'), generated in that bit position(both inputs are '1'), or killed in that bit position (both inputs are '0').In most cases, P is simply the sum output of a half-adder and G is thecarry output of the same adder. After P and G are generated thecarries for every bit position are created. Some advanced carry-lookahead architectures are the Manchester carry chain, Brent–Kungadder, and the Kogge–Stone adder.

Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of theseblocks based on the propagation delay of the circuits to optimize computation time. These block basedadders include the carry-skip (or carry-bypass) adder which will determine P and G values for each blockrather than each bit, and the carry select adder which pre-generates the sum and carry values for eitherpossible carry input (0 or 1) to the block, using multiplexers to select the appropriate result when the carrybit is known.

Other adder designs include the carry-select adder, conditional sum adder, carry-skip adder, and carry-complete adder.

Lookahead carry unit

By combining multiple carry lookahead adders even larger adderscan be created. This can be used at multiple levels to make evenlarger adders. For example, the following adder is a 64-bit adder thatuses four 16-bit CLAs with two levels of LCUs.

Carry-save Adders

Main article: Carry-save adder

If an adding circuit is to compute the sum of three or more numbersit can be advantageous to not propagate the carry result. Instead, three input adders are used, generating tworesults: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-numberadder without having to wait for propagation of a carry signal. After all stages of addition, however, aconventional adder (such as the ripple carry or the lookahead) must be used to combine the final sum andcarry results.

We can view a full adder as a 3:2 lossy compressor: it sums three one-bit inputs, and returns the result as asingle two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of101 results in an output of 1+0+1=10 (decimal number '2'). The carry-out represents bit one of the result,while the sum represents bit zero. Likewise, a half adder can be used as a 2:2 lossy compressor, compressingfour possible inputs into three possible outputs.

Such compressors can be used to speed up the summation of three or more addends. If the addends areexactly three, the layout is known as the carry-save adder. If the addends are four or more, more than onelayer of compressors is necessary and there are various possible design for the circuit: the most common are


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Dadda and Wallace trees. This kind of circuit is most notably used in multipliers, which is why these circuitsare also known as Dadda and Wallace multipliers.

^ Geoffrey A. Lancaster (2004). Excel HSC Software Design and Development (http://books.google.com/books?id=PZkDpS4m0fMC&pg=PA180). Pascal Press. p. 180. ISBN 9781741251753.

1.

^ M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall 1979, ISBN 0-13-21450-3 pp.119-1232.^ Burgess, N. (2011). "Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI" (http://ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F5991607%2F5992089%2F05992115.pdf%3Farnumber%3D5992115&authDecision=-203). 20th IEEE Symposium on Computer Arithmetic. pp. 103–111.

3.

Hardware algorithms for arithmetic modules (http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html), includes description of several adder layouts with figures.8-bit Full Adder and Subtractor (http://dev.code.ultimater.net/electronics/8-bit-full-adder-and-subtractor/), a demonstration of an interactive Full Adder built in JavaScript solely for learningpurposes.Interactive Full Adder Simulation (http://teahlab.com/Full_Adder/), Interactive Full Adder circuitconstructed with Teahlab's online circuit simulator.Interactive Half Adder Simulation (http://teahlab.com/Half_Adder/), Half Adder circuit built withTeahlab's circuit simulator.

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