Advanced Analog Integrated Circuits Operational ...boser/courses/240B/lectures/M06... · Advanced Analog Integrated Circuits ... 2-port analysis ignores the feedforward path and therefore

B. E. Boser 1

Advanced Analog Integrated Circuits

Operational Transconductance Amplifier I& Step Response

Bernhard E. BoserUniversity of California, Berkeley

[email protected]

Copyright © 2016 by Bernhard Boser

EE240B – OTA I: Step Response

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High-Level View

• Transistors are transconductors

• Some OTA designs consist of >40 transistors– Only few (typically 1 … 2) provide the transconductance in the signal path– The rest is support, e.g.

• increasing low frequency gain• output voltage range • biasing

• Hierarchical design strategies are imperative– Unless you like nodal equations for 40 transistors …


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Divide and Conquer


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In SC Circuit


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In SC Circuit


Amplifier is active only in 𝜙":

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Capacitive Feedback … Simulation

𝑅$% ≅ 20GΩ


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Small-Signal Model

Absorb Cgd, Cdb, etc. in Cf, CL, …


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Loop-Gain & Stability


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Model


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Loop-Gain Analysis


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Loop-Gain T(s)

𝑇 𝑠 = 𝛽𝑔1

𝑠 2 𝐶4565

Feedbackfactor𝛽 =𝑣%𝑣6=

𝐶C𝐶C + 𝐶$ + 𝐶%

≠1𝑎H6

EffectiveLoadCapacitance𝐶4565 = 𝐶4 + 1 − 𝛽 𝐶C


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Frequency Response of T(s)

𝑇 𝑠 =𝛽𝑔1

𝑠 2 𝐶4565


w

|T(jw)|

To

𝜔R =𝛽𝑔1𝐶4565

𝜔R𝑇6

-90o

0o w

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Closed-Loop Response


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Closed-Loop Analysis

Feedback-Only Model Generalized Model


Ref: P. Hurst, “A comparison of two approaches to feedback circuit analysis,” IEEE Trans. edu., Aug. 1992, pp. 253-261.

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Closed-Loop Transfer Function


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𝐴T


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𝑑


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Closed-Loop Gain

𝐴 𝑠 = 𝐴T𝑇 𝑠

1 + 𝑇 𝑠 +𝑑

1 + 𝑇 𝑠 = −𝐶$𝐶C

𝛽𝑔1𝑠 2 𝐶4565

1 + 𝛽𝑔1𝑠 2 𝐶4565

+𝛽 𝐶$𝐶4565

1 + 𝛽𝑔1𝑠 2 𝐶4565

= −𝐶$𝐶C

1 − 𝑠𝐶C𝑔1

1 + 𝑠 𝐶4565𝛽𝑔1

= −𝐶$𝐶C

1 − 𝑠𝑧1 − 𝑠

𝑝

𝑝 = −𝛽𝑔1𝐶4565

z = +𝑔1𝐶C


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Stability and T(s) with Simulator


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T(s) Verification with Simulator

• Infinite impedance point to break loop usually not accessible– E.g. inside transistor


[ Hspice manual ]

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Workaround (Don’t do this!)


Vo

1Gig¥

vreturn

vtestMockLoad

C1

C2

[ Drawing by B. Murmann ]

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General Problem

Any “single loop“ feedback circuit can be represented as:


gm×vx

vxZ1 Z2

Breakpoint at ideal source is not available.But there is a breakpoint “between finite impedances“

available breakpoint

21

21)(ZZZZgsT m +×

=

[ Drawing by B. Murmann ]

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Middlebrook Double Injection Method


Z1 Z2

iy

vxZ1 Z2 vy

vtest(ac)

itest(ac)

ix

1

22 ZZZgT

vv

mvx

y +×=º

2

11 ZZZgT

ii

mix

y +×=º

21

21

ZZZZgT m +

×=True Loop Gain:

Solving yields:

21++-

=iv

iv

TTTTT

• No “DC“ break in the loop, all loading effects covered.• Measure Tv and Ti, then calculate actual T• Variant implemented in many simulators, e.g. stb-analysis in Spectre

[ Middlebrook 75 ][ Drawing by B. Murmann ]

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SPICE


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Multiple Feedback Loops

• Break all loops at a single point

• If such a point does not exist: [Bode 45]

“If a circuit is stable when all its tubes have their nominal gains, thetotal number of clockwise and counterclockwise encirclements of thecritical point must be equal to each other in the series of Nyquist diagrams for the individual tubes obtained by beginning with all tubesdead and restoring the tubes successively in any order to theirnominal gains”

– Suggestion: take a controls class if your circuit depends on this!


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Nonlinearities

• Real circuits are nonlinear – frequency response depends on signal amplitude. Bode:

“... thus the circuit may sing when the tubes begin to lose their gainbecause of age, and it may also sing, instead of behaving as it should, when the gain increases from zero as power is supplied to the circuit ...“

• Always run a ”large signal” transient analysis for a complete stability check!– With realistic (large) signal amplitudes including overload– Power supply ramping. Is a special order required?


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Settling


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Step Response


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Closed-Loop Gain

• Use favorite analysis method, e.g. return-ratio analysis*, nodal analysis, …


𝐴 𝑠 =𝑉6(𝑠)𝑉\(𝑠)

= −𝐶$𝐶C


1 + 𝑠 𝐶4565𝛽𝑔1

= −𝐶$𝐶C

1 − 𝑠𝑧1 − 𝑠

𝑝

𝜔] =𝑔1𝐶C

*Note: 2-port analysis ignores the feedforward path and therefore does not get the zero

𝜔]𝜔^

=𝐶4565𝛽𝐶C

usually ≫ 1

𝜔^=𝛽𝑔1𝐶4565

≅ 𝜔defghij $ = 𝜔Rhik($)

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Dynamic Error (no zero)


Assume switch on-resistance contribution to settling is negligible

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Dynamic Settling Error


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Dynamic Settling Error (single pole)

𝜺𝒅 𝒕𝒔 𝝉⁄1% 4.6

0.1% 6.90.01% 9.2

10-6 13.8


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Amplifier Bandwidth versus fs


𝜀f 𝑓defg 𝑓$⁄1% 1.5

0.1% 2.20.01% 2.9

10-6 4.4

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Static Settling Error


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Example

𝐶$ = 4pF𝐶C = 1pF𝐶% = 1pF𝑔1𝑟6 = 6000


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Dynamic Error (with zero)

• Instant response to step determined by capacitive feed-forward

𝐴 𝑠 =𝑉6(𝑠)𝑉\(𝑠)

= −𝐶$𝐶C


1 + 𝑠 𝐶4565𝛽𝑔1

𝑧 = +𝑔1𝐶C𝑝 = −

𝛽𝑔1𝐶4565


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Step Response with Zero

𝑣6,$5x^ 𝑡 = −𝑉$5x^ 2 𝐺\ 1 − 1 −𝑝𝑧 𝑒d5 |⁄

1 −𝑝𝑧 =

1

1 − 𝛽𝐶C

𝐶C + 𝐶4

𝑡$ = −𝜏∙ln 𝜀f 1 − 𝛽𝐶C

𝐶C + 𝐶4


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Phase Margin


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Cascode


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Phase Margin


𝑓 " 𝑓R⁄ Phase Margin∞ 90o

5 ~80o

1/5 ~28o

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Step Response


0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.2

0

v s t 1,( )

v s t 3,( )

v s t 100,( )

1 e t--

100 t

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Relative Settling Error for 𝑓 " 𝑓R⁄ = 3


0 1 2 3 4 5 6 7 8 9 100

0.005

0.01

0.012

0

e s t 3,( )

e t-

100 t

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Settling Time versus 𝑓 " 𝑓R⁄


0 1 2 3 4 5 6 7 8 9 102

4

6

8

10

12

1415

3.508

t s e K,( )

ln e( )-

100.8 K𝑓 " 𝑓R⁄

𝜀f = 0.1%

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Noise


[ B. Murmann ]

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Design Example


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Design Example: Specification


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Design: Gain & Feedback Factor


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Design: Dynamic Range


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Design: Settling


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Design: Power Dissipation


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Could we go Faster?


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Gain Boosting


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Openloop Gain

𝑎H6 = 𝑔1𝑅6


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Openloop Gain

𝑎H6 = 𝑔1𝑅6


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Gain Boosting


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Gain Boosting

• Use feedback to boost low-frequency output resistance

• References– B. J. Hosticka, “Improvement of

the gain of MOS amplifiers,” JSSC, Dec. 1979 , pp. 1111-4.

– E. Sackinger and W. Guggenbuhl, “A high-swing high-impedance MOS cascode circuit”, JSSC, Feb. 1990, pp. 289-298.

– K. Bult, G. Geelen, “A fast-settling CMOS op-amp for SC circuits with 90-dB DC gain,” JSSC, Dec. 1990 , pp. 1379-84.


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High Frequency Analysis


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Overall Amplifier Response


Ref: M. Das, “Improved design criteria of gain boosted CMOS OTA with high-speed optimizations,” IEEE CAS II, March 2002, pp. 204-7.

𝜔]

𝜔6

𝑣6𝑣\

𝑓

Doublet

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Pole-Zero Doublets


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Pole-Zero Doublets

Ref: Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between frequency response and settling time of operational amplifiers,” IEEE J. Solid-State Circuits, pp. 347–352, Dec. 1974.


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Doublet Settling

• Amplifier model: replace Gmo with


p

zmom s

s

GsG

w

w

+

+=

1

1)(

Notation from Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between frequency response and settling time of operational amplifiers,” IEEE J. Solid-State Circuits, pp. 347–352, Dec. 1974.

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Doublet Settling

• Amplifier model: replace Gmo with

• Closed-loop response


p

zmom s

s

GsG

w

w

+

+=

1

1)(

( )

1 h wit1

of bandwidth is , 33

<<+=

=

= --

eeaaw

w

wbww

pz

dBdBp sT

with

( ) ÷÷÷÷

ø

ö

çççç

è

æ

+

+

+-@

+-=

- pp

z

dBm

Leffin

o

s

s

sc

sFGC

sc

VV

w

w

w1

1

11

1

3ppp

Leff

modB C

FG

ww

w

@

=-3with

Notation from Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between frequency response and settling time of operational amplifiers,” IEEE J. Solid-State Circuits, pp. 347–352, Dec. 1974.

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Doublet Step Response


( ) ( )ppdB ttstepstepo BeAecVtv ww -- ++-= -31,

21

1

bbe-

@

-@

B

Awith

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Doublet Example


0 1 2 3 4 5 6 7 8 9 10

0

0.5

11.1

0.1-

v s_no_doublet t( )

v s_doublet_ term t a, b,( )

v s_doublet t a, b,( )

100 t

9 10 11 12 13 14 15 16

0.005

0

0.005

0.01-

1 v s_no_doublet t( )-

1 v s_doublet t a, b,( )-

169 t

a = 1.5b = 0.3

B. E. Boser 65

Gain Boosting – Doublets


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Advanced Analog Integrated Circuits Operational ...boser/courses/240B/lectures/M06... · Advanced Analog Integrated Circuits ... 2-port analysis ignores the feedforward path and therefore