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12/3/2014
1
Erik Jonsson School of Engineering & Computer Science
Advanced Digital Calibration Techniques for Data Converters
Yun Chiu
Erik Jonsson Distinguished Professor
University of Texas at Dallas
EECT 7326, Fall 2014 - 2 - © Y. Chiu
Presentation Outline
• Principles of Multistep A/D Conversion
• Architectural Redundancy
• Error Mechanisms and Digital-Domain Calibration
• Error-Parameter Identification
– PRBS Test-Signal Injection (sub-ADC, sub-DAC, input)
– Two-ADC Equalization (ref.-ADC, split-ADC, ODC)
• Energy Efficiency and Trend
• Summary
12/3/2014
2
EECT 7326, Fall 2014 - 3 - © Y. Chiu
Presentation Outline
• Principles of Multistep A/D Conversion
• Architectural Redundancy
• Error Mechanisms and Digital-Domain Calibration
• Error-Parameter Identification
– PRBS Test-Signal Injection (sub-ADC, sub-DAC, input)
– Two-ADC Equalization (ref.-ADC, split-ADC, ODC)
• Energy Efficiency and Trend
• Summary
EECT 7326, Fall 2014 - 4 - © Y. Chiu
···
What is A/D Conversion?
,
s
in in sNFSoutN
FSt=nT
V t V nTVLSB = = D n = = 2
2 V
• Quantization = division + normalization + truncation
• VFS is the Full-Scale range of ADC determined by Vref.
CT, CA DT, DA
12/3/2014
3
EECT 7326, Fall 2014 - 5 - © Y. Chiu
Quantization Error (or Noise)
∆ ∆
- ε2 2
Dout
0
Vin
∆ 2∆ 3∆
1
3
5
0
2
4
6
7
VFS
2
-∆-2∆-3∆
VFS
2
"Random" quantization error is usually regarded as noise.
N = 3
∆ /2 2
2 2ε
-∆/2
1 ∆σ = ε dε =
∆ 12
Pε
0-∆/2 ∆/2ε
1/∆
• N is large
• Vin >> ∆, Vin is active
• ε is uniformly distributed
Ref. [1]
EECT 7326, Fall 2014 - 6 - © Y. Chiu
Flash ADC – Exhaustive Search
• Massive parallelism
• Very fast
• Reference ladder
consists of 2N equal
size resistors
• Input is compared
to 2N-1 reference
voltages
• Throughput = fs
• Complexity = 2N
… …
Enc
oder
VFS Vi
fs
Strobe
Dout
2N-1comparators
…
Do 0
Vi
∆
2∆
5∆
6∆
7∆
VFS
……
0
1
5
6
7
• Flash ADC is rarely used for beyond 6-8 bits due to complexity.
12/3/2014
4
EECT 7326, Fall 2014 - 7 - © Y. Chiu
Long Division (Decimal Case)
183
4 ) 735
4 (1×4=4)
33 (7−4=3)
32 (8×4=32)
15 (33−32=1)
12 (3×4=12)
3 (15−12=3)
1
400 ) 735
400
335
8
40 ) 335
320
15
3
4 ) 15
12
3
DivisorDividend Quotient Remainder
735 4 = 183 r 3
Step 1:
1st bit
Step 2:
2nd bit
Step 3:
3rd bit
EECT 7326, Fall 2014 - 8 - © Y. Chiu
Quantization (Binary Case)
Vin LSB QNDo
735 125 = 1,0,1 r 110
1
500 ) 735
500
235
0
250 ) 235
0
235
N = 3, FS = 1000, ∆ = 1000/8 = 125, Vin = 735
ino
VD =
• The procedure is also known as "binary search".
Step 1:
1st bit
Step 2:
2nd bit
Step 3:
3rd bit
12/3/2014
5
EECT 7326, Fall 2014 - 9 - © Y. Chiu
Successive-Approximation (SAR) ADC
SAR = 1 comparator + 1 DAC + digital logic
EECT 7326, Fall 2014 - 10 - © Y. Chiu
Sam
plin
g
......
Binary Search – MSB Cycle
N = 3, FS = 1 V, ∆ = 0.125 V, Vin = 0.735 V0.735V
0.5V
VX = Vi – 0.5V;
if VX > 0, MSB = 1, keep current VX VX;
otherwise, MSB = 0, restore VX VX + 0.5V;
12/3/2014
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EECT 7326, Fall 2014 - 11 - © Y. Chiu
Sam
plin
g
......
Binary Search – MSB-1 Cycle
N = 3, FS = 1 V, ∆ = 0.125 V, Vin = 0.735 V0.235V
0.25V
VX = VX – 0.25V;
if VX > 0, MSB-1 = 1, keep current VX VX;
otherwise, MSB-1 = 0, restore VX VX + 0.25V;
EECT 7326, Fall 2014 - 12 - © Y. Chiu
Sam
plin
g
......
Binary Search – MSB-2 Cycle
N = 3, FS = 1 V, ∆ = 0.125 V, Vin = 0.735 V0.235V
0.125V
VX = VX – 0.125V;
if VX > 0, MSB-2 = 1, keep current VX VX;
otherwise, MSB-2 = 0, restore VX VX + 0.125V;
12/3/2014
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EECT 7326, Fall 2014 - 13 - © Y. Chiu
Quantization (Binary) Modified…
Vin LSB QNDo
735 125 = 1,0,1 r 110
N = 3, FS = 1000, ∆ = 1000/8 = 125, Vin = 735
ino
VD =
Step 1:
1st bit
Step 2:
2nd bit
Step 3:
3rd bit
• Always use the same divisor but amplify the residue.
1
500 ) 940
500
440
EECT 7326, Fall 2014 - 14 - © Y. Chiu
Algorithmic (Cyclic) ADC
• Fixed comparison threshold (VFS/2) + 1-b DAC + Residue Amplifier
• Modified "Binary Search"
12/3/2014
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EECT 7326, Fall 2014 - 15 - © Y. Chiu
Bit Cycles
• Comparison if VX < VFS/2, then bj = 0; otherwise, bj = 1
• Residue generation Vo = 2·(VX - bj·VFS/2)
VX
Vo
VFS/20 VFS
VFSbj=0 bj=1
EECT 7326, Fall 2014 - 16 - © Y. Chiu
Pipelined ADC
• Algorithmic ADC loop unrolled pipeline enables high throughput
12/3/2014
9
EECT 7326, Fall 2014 - 17 - © Y. Chiu
Presentation Outline
• Principles of Multistep A/D Conversion
• Architectural Redundancy
• Error Mechanisms and Digital-Domain Calibration
• Error-Parameter Identification
– PRBS Test-Signal Injection (sub-ADC, sub-DAC, input)
– Two-ADC Equalization (ref.-ADC, split-ADC, ODC)
• Energy Efficiency and Trend
• Summary
EECT 7326, Fall 2014 - 18 - © Y. Chiu
What happens with circuit offsets?
Ideal RA offset CMP offset
Nearly zero tolerance on circuit offset errors!!
Vi
Vo
VFS/20 VFS
VFSb=0 b=1
Vi
Vo
VFS/20 VFS
VFSb=0 b=1
Vi
Vo
VFS/20 VFS
VFSb=0 b=1Vos
Vos
Vi
Do
VFS/20 VFS Vi
Do
VFS/20 VFS Vi
Do
VFS/20 VFS
12/3/2014
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EECT 7326, Fall 2014 - 19 - © Y. Chiu
Over-range & Under-range Comparators
Vi
Vo
VFS/20 VFS
VFSbj=0 bj=1
VFS/2
Bj+1=0
Bj+1=1
Vi
Do
VFS/20 VFS00
01
10
11
Vi
Vo
VFS/20 VFS
VFSbj=0 bj=1
VFS/2
Bj+1=0
Bj+1=1
Bj+1=-1
Bj+1=2
Vi
Do
VFS/20 VFS00
01
10
11
1 CMP 3 CMPs
EECT 7326, Fall 2014 - 20 - © Y. Chiu
Redundancy (a.k.a. DEC or RSD)
Original w/ Redundancy
• 4-level (2-bit) DAC required instead of 2-level (1-bit) DAC
12/3/2014
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EECT 7326, Fall 2014 - 21 - © Y. Chiu
Vi
Vo
VFS/20 VFS
VFSbj=0 bj=1
VFS/2
Bj+1=0
Bj+1=1
Bj+1=-1
Bj+1=2
Vi
Do
VFS/20 VFS00
01
10
11
Complementary Analog-Digital Information
• Max tolerance of comparator offset is ±VFS/4 simple comparators
• Key to understand redundancy:
FS oji
VV = +
2
Vb
2
1 bit
1 FS
o
j
Vb = 0
2
EECT 7326, Fall 2014 - 22 - © Y. Chiu
From 1-bit to 1.5-bit Architecture
1-bitNo redundancy
½ bit
½ FS
oVb = 0
2
12/3/2014
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EECT 7326, Fall 2014 - 23 - © Y. Chiu
oVb = 0
2
From 1-bit to 1.5-bit Architecture
½ bit
½ FS
oVb = 0
2
½ bit
½ FS
EECT 7326, Fall 2014 - 24 - © Y. Chiu
From 1-bit to 1.5-bit Architecture
• Center the two thresholds optimal symmetric offset tolerance
oVb = 0
2
oV
b = 02
12/3/2014
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EECT 7326, Fall 2014 - 25 - © Y. Chiu
The 1.5-bit Architecture
• 3 decision levels
→ ENOB = log23 = 1.58
• Max tolerance of comparator offset is ±VR/4
• An implementation of the Sweeny-Robertson-Tocher(SRT) division principle
• The conversion accuracy relies on the loop-gain error, i.e., the gain error and nonlinearity
• A 3-level DAC is required
Can the same technique be applied to SAR?
o i RV = 2 V - b -1 V
Ref. [2]
EECT 7326, Fall 2014 - 26 - © Y. Chiu
1.5-bit Multiplier DAC (MDAC)
• 2X gain + 3-level DAC + subtraction all integrated
• Can be generalized to n.5-bit architectures
R1
2i
1
21o V
C
C1bV
C
CCV
o i RV = 2 V - b -1 V
12/3/2014
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EECT 7326, Fall 2014 - 27 - © Y. Chiu
2.5-bit Multiplier DAC (MDAC)
• 4X gain + 7-level DAC + subtraction all integrated
o i RV = 4 V - b -3 V
b=1 b=3 b=5b=0 b=2 b=4 b=6
Vi
Vo
-5VR/8 VR/8
VR/2
-VR/2
0
-3VR/8 -VR/8 5VR/83VR/8-VR VR
VR
Vo
Vi
0
-VR
VR
Decoder
Φ1e
A
Φ2
VR6
VR1
6 CMP’s
Φ1 C1
Φ1 C2
Φ2
C3
C4
Φ1
Φ1
Φ2
Φ2
b
EECT 7326, Fall 2014 - 28 - © Y. Chiu
Residue Transfer Function (2.5b MDAC)
• Only half of the internal dynamic range is used under ideal condition!
overflowrange
underflowrange
normalrange
12/3/2014
15
EECT 7326, Fall 2014 - 29 - © Y. Chiu
With comparator offset
overflowrange
underflowrange
normalrange
EECT 7326, Fall 2014 - 30 - © Y. Chiu
Internal Redundancy
• Comparator and amplifier offsets tolerated by internal redundancy.
overflowrange
underflowrange
normalrange
12/3/2014
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EECT 7326, Fall 2014 - 31 - © Y. Chiu
How does Redundancy work in SAR?
• Binary search is efficient, but displays zero error tolerance.
EECT 7326, Fall 2014 - 32 - © Y. Chiu
+FS
t
0
-FS
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Vin
t
VX
0 0
1/2
1/4 3/8
1
0
1
1
Binary Search Revisited
• When everything is ideal…
12/3/2014
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EECT 7326, Fall 2014 - 33 - © Y. Chiu
+FS
t
0
-FS
1111
1110
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Vin
t
VX
0
1
0
1
1
1
0
0
1101
1/2
3/45/8
0
1/4 3/8
Binary Search w/ Dynamic Error
• Settling error, comparator hysteresis etc.
EECT 7326, Fall 2014 - 34 - © Y. Chiu
Overlapping Search Ranges
• Results indicate decision trajectory, no longer binary-coded.
+FS
t
0
-FS
1
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Vin
t
VX
1
10
0
01
1
00
1
12/3/2014
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EECT 7326, Fall 2014 - 35 - © Y. Chiu
Redundancy of Sub-binary Search
• Dynamic errors absorbed by redundancy.
+FS
t
0 0
-FS
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Vin
1
1
0
0 1
0
1
1 1
t
VX
11
00
1
1
0
1
EECT 7326, Fall 2014 - 36 - © Y. Chiu
SAR Redundancy
• Redundant conversion consumes more bit cycles, but
can recover intermediate decision errors.
• Redundancy can be exploited to expedite conversion
progress or to save power.
• DAC levels (matching) still need to be accurate.
(will come back to this later…)
12/3/2014
19
EECT 7326, Fall 2014 - 37 - © Y. Chiu
Presentation Outline
• Principles of Multistep A/D Conversion
• Architectural Redundancy
• Error Mechanisms and Digital-Domain Calibration
• Error-Parameter Identification
– PRBS Test-Signal Injection (sub-ADC, sub-DAC, input)
– Two-ADC Equalization (ref.-ADC, split-ADC, ODC)
• Energy Efficiency and Trend
• Summary
EECT 7326, Fall 2014 - 38 - © Y. Chiu
Pipelined ADC Errors (I)
• Capacitor mismatch
• Op-amp finite-gain error and nonlinearity
• Charge injection and clock feed-through (S/H)
• Settling error
o i RV = 2 V - d V
1 2 2So i/H R
1 2 1 21 1
o o
C C Ct f V
C C C CC C
VA
V
A
V
V
d
1.5b MDAC
12/3/2014
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EECT 7326, Fall 2014 - 39 - © Y. Chiu
Pipelined ADC Errors (II)
dj -3 -2 -1 0 1 2 3
dj,1 -1 -1 -1 -1 -1 0 1
dj,2 -1 -1 -1 0 1 1 1
dj,3 -1 0 1 1 1 1 1
DAC bit-encoding scheme
dj = dj,1 + dj,2 + dj,3
...
43j,
j+1
j r1 j,2 j,3 j2
11
+
VV V
C + C ACC C+ += +
C C CVd d
Cd
2.5b MDAC
EECT 7326, Fall 2014 - 40 - © Y. Chiu
RA Gain Error and Nonlinearity
-VR/4 VR/4
0
VR/2
-VR/2
Vi
-VR
VR
VR
b=0 b=2b=1
Vo
0Vi-VR VR
Do
12/3/2014
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EECT 7326, Fall 2014 - 41 - © Y. Chiu
RA Gain Error and Nonlinearity
-VR/4 VR/4
0
VR/2
-VR/2
Vi
-VR
VR
VR
b=0 b=2b=1
Vo
0Vi-VR VR
Do
• Raw accuracy is usually limited to 10-12 bits w/o error correction.
EECT 7326, Fall 2014 - 42 - © Y. Chiu
-VR/4 VR/4
0
VR/2
-VR/2
Vi
-VR
VR
VR
b=0 b=2b=1
Vo
RA Gain Error and Nonlinearity
• Raw accuracy is usually limited to 10-12 bits w/o error correction.
0Vi-VR VR
Do
12/3/2014
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EECT 7326, Fall 2014 - 43 - © Y. Chiu
Digital
Computation
The Basic Idea of Digital Calibration
ADC
UnknownSystem
SystemInversion
1o
2i
V 1- 1
βA-
C
CV
• match C1 and C2
• make βA very large
Digital soln:
• any constant C1 and C2
• any constant A is fine
Analog soln:e.g., SC amplifier:
Calibration = efficient digital processing to undo certain analog errors
EECT 7326, Fall 2014 - 44 - © Y. Chiu
Two Essential Components of Dig. Cal.
1. A digital-domain technique (e.g. equation) to recover accurate analog information from raw digital output– Treat analog precision or linearity only
– Neglect small consequence on SNR
2. An algorithm to identify the error parameters– Foreground vs. Background techniques
1
2CL
1C
CA 1-
βA- = #
12/3/2014
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EECT 7326, Fall 2014 - 45 - © Y. Chiu
Linear MDAC Correction
j,1 j,2 j,3j r j+
31 21
4CC C C + C A+ += +
C C CV V Vd d
Cd
ideal residue function
j,1 j,2 j,3
3j j+1
r
1 2
r
4CC C C + C A+ += +
C C Cd d
V V
V V Cd
j,1 j,2 j,j 3 j
j,
,1 j,2 j,3j j+1
j,k j+k jk
1
β + β + β= + α
=
d d dD D
β D+ αd
Digital representation:
j jj,1 j,2 j,
+1 j+1
r r
3 jr
V V V
V V
1 1 1 1+ += + = +
Vd d
4 4d d
4 4
Analog residue function:
Normalized residue function:
error parameters: { αj, βj,k }
EECT 7326, Fall 2014 - 46 - © Y. Chiu
Bit-Weight (Radix) Correction
...
...
1 in
j j j+1 j+1 j+2 j+2 j+1 j j-1
j j+1 j+j j+1 j+22
D =D
=...+ d β + d β + d β +... α α α
=...+d +d +d +γ γ γ weighted sum of ALL bits!(bit weight or radix error)
segmental offset
For 1-b or 1.5-b MDAC:
...
...
1 in
j j+1 j+2
j j+1 j+j j+1 j+2
j j j+1 j+1 j+2 j+2
2
j j+1 j+2
j j+1 j+2
D =D
d d d=...+ + + +
2 2 2d + d + d +
=.
1+∆ 1+∆ 1+∆
d ∆ d ∆ d ∆..+ + + +
2 2 2
Alternatively,
12/3/2014
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EECT 7326, Fall 2014 - 47 - © Y. Chiu
Bit-Weight (Radix) Correction
Vi-VR VR
Do
Vi-VR VR
Do
Vi-VR VR
Do
radix error:needs multiplication
segmental offset:addition only
d1=-1 d1=1d1=0 d1=-1 d1=1d1=0 d1=-1 d1=1d1=0
1.5b MDACresidue nonlinearity
EECT 7326, Fall 2014 - 48 - © Y. Chiu
Nonlinear MDAC Correction
43j,
j+1
j r1 j,2 j,3 j2
11
+
VV V
C + C ACC C+ += +
C C CVd d
Cd
431 2j,1 j,2 j,3
j+1j j+1
r r
C + C ACd d
C C+ += +
C
VV V
V Vd
C C C
j,1 j,2 j,3j,1 j,2 j,3j j+1
jm
j,k,k j+1 j,mk m
d β + β + β= + f
β + α
d dD D
d D
Digital representation:
Analog representation:
Normalized analog representation:
error parameters: { αj,m, βj,k }
Next problem: how to determine {αj,m, βj,k} precisely?
12/3/2014
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EECT 7326, Fall 2014 - 49 - © Y. Chiu
Let’s try to push this…
-70 dBFS
"Give me a place to stand on, and I will move the Earth…"
Corrected w/ 9th-order power series
LDrawn
0.15μm
VDD
1.2V
Correcting nonlinearity:
Archimedes, 200 BC
EECT 7326, Fall 2014 - 50 - © Y. Chiu
On nonlinear correction
• Memory-less polynomial computation is efficient– A few coefficients fits/predicts full-range nonlinearity
(requiring digital multipliers and adders mostly)
– Caveat 1: coefficients depend on signal statistics!
– Caveat 2: coefficients depend on PVT variations!
• Piecewise-linear or lookup table can be useful– Memory, digital power, and cost
– Complexity and convergence time (esp. tracking speed in background mode)
Solution needs to be practical after all…
12/3/2014
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EECT 7326, Fall 2014 - 51 - © Y. Chiu
0 3/8 1/8 9/32 3/8
10 6 3.5 2 1
1.6 1.67 1.71 1.75 2
+FS
t
-FS
Vin
SAR Redundancy Forms (I)
• Unit-Element DAC
• Best matching
• Arbitrary decision threshold arbitrary radix
• Redundancy @ each bit
• DAC resolution slightly higher
• Binary-to-Thermo encoder (slow)
Radix:Ref. [3]
EECT 7326, Fall 2014 - 52 - © Y. Chiu
0 1/2 1/4 1/2 3/8
8 4 4 2 1
2 2 1 2 2
+FS
t
-FS
Vin
SAR Redundancy Forms (II)
• Binary DAC
• Good matching
• Periodic redundancy non-uniform radix
• Redundancy @ selective bits
• SAR logic slightly more complex
• Can also use UE DAC
Radix:Ref. [4]
12/3/2014
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EECT 7326, Fall 2014 - 53 - © Y. Chiu
0 ... ... ... ...
1.864 1.863 1.862 1.86 1
1.86 1.86 1.86 1.86 1.86
+FS
t
-FS
Vin
SAR Redundancy Forms (III)
• Sub-binary DAC
• Poor matching
• Uniform redundancy uniform radix
• Redundancy @ each bit
• Simple layout, simple SAR logic (fast)
• Cannot use UE DAC
• Must calibrate DAC
Radix:Ref. [5]
EECT 7326, Fall 2014 - 54 - © Y. Chiu
Sub-binary DAC – Construction
Vi
...DAC Do
VDAC
VX
...
d0
dN-1
C0·1.86N-1
CN-1
C0·1.86N-2
CN-2
C0·1.86N-3
CN-3
C0·1.86N-4
CN-4 …
• Hard-coded in analog form
• No B2T encoder
• Simple layout
e.g., Radix = 1.86
Ref. [5]
12/3/2014
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EECT 7326, Fall 2014 - 55 - © Y. Chiu
Sub-binary DAC – Transfer Function
N = 14
= 011…1 VH
= 100…0 VL
Note: only one transition
edge shows up
VL VHVi
Redundant region
1
Do
2
2N
2N-1
0 FS
MSB = 1
MSB = 0
Do
EECT 7326, Fall 2014 - 56 - © Y. Chiu
Sub-binary DAC – Quantization
Vi
...DAC Do
VDAC
VX
...
d0
dN-1
j
j
≈ 2d -1
2d -1
io
FS
N-1j
j=0 j
jj
N-1
=0
Vd =
V
=
C
C
w
C0·1.863
C3
C0·1.862
C2
C0·1.86
C1
C0
C0
d3 = 1d2 = 0
d1 = 0d0 = 1
3
DAC R jj=0
3
ij=0
j
j
Q = V 2d -1
≈ CV
C
+ + +
Radix = 1.86
Ref. [5]
12/3/2014
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EECT 7326, Fall 2014 - 57 - © Y. Chiu
Do
d o
Sub-binary DAC – Digital Correction
jw = bit weights
Nraw = 14 Nnet = 12
j2d -1N-1
io
j=0j
FS
wV
d = =V
Next problem: how to determine {wj} precisely?
EECT 7326, Fall 2014 - 58 - © Y. Chiu
Presentation Outline
• Principles of Multistep A/D Conversion
• Architectural Redundancy
• Error Mechanisms and Digital-Domain Calibration
• Error-Parameter Identification
– PRBS Test-Signal Injection (sub-ADC, sub-DAC, input)
– Two-ADC Equalization (ref.-ADC, split-ADC, ODC)
• Energy Efficiency and Trend
• Summary
12/3/2014
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EECT 7326, Fall 2014 - 59 - © Y. Chiu
Error-Parameter Identification Techniques (BG)
• With PRBS test-signal injection (dither)– Sub-ADC injection (comparator dither)
– Sub-DAC injection (DAC dither)
– Input injection (Independent Component Analysis)
• With two-ADC equalization (test signal free)– Reference-ADC equalization (training sequence)
– Split-ADC equalization (blind)
– Offset double conversion (ODC) (blind, single ADC)
Parameter extraction is what the game is all about…
EECT 7326, Fall 2014 - 60 - © Y. Chiu
Recent BG Digital Calibration Techniques
ADC2 x2(n) y2(n)
e(n)Vin
Lewis [11], Chiu [12], McNeill [13]…
ADCAdaptive
DPP
x(n)
y(n)e(n)
T(n)
Vin
Temes [6,7], Lewis [8], Galton [9,10]…
Two-ADCequalization
PRBS injection(Dither)
x1(n)
Adaptive DPP
ADC1Adaptive
DPP
y1(n)
12/3/2014
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EECT 7326, Fall 2014 - 61 - © Y. Chiu
PRBS Test-Signal Injection
EECT 7326, Fall 2014 - 62 - © Y. Chiu
Comparison of PRBS Injection Techniques
• Sub-ADC injection
– considered as dynamic comparator offset, no removal needed
– higher sub-ADC resolution (injection and ADC matching not req’d)
– works only with busy input
• Sub-DAC injection
– needs to be removed in digital output
– higher sub-DAC resolution (injection and DAC matching req’d)
– can work with quiet input
• Input injection (sub-DAC + sub-ADC)
– needs to be removed in digital output
– No impact on sub-ADC or sub-DAC resolution
– works only with busy input
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PRBS Test-Signal Injection(Sub-ADC Injection)
EECT 7326, Fall 2014 - 64 - © Y. Chiu
Sub-ADC Injection – Comparator Dither
• In steady state, analog gain (G1) and digital gain (G1-1) cancel exactly.
• 2-k ≤ ¼ to avoid overflow in residue output.
• No need to match injection scaling factor (2-k) to the sub-ADC thresholds.
residuepath
Converge@
1D T = 0
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Sub-ADC Injection – Comparator Dither
• In steady state, analog gain (G1) and digital gain (G1-1) cancel exactly.
• 2-k ≤ ¼ to avoid overflow in residue output.
• No need to match injection scaling factor (2-k) to the sub-ADC thresholds.
Converge@
1D T = 0
-VR/2
0
d1=1 d1=2
-VR
VR/2
VR
¼ bit½ bit
...
...
typ. k = 2
EECT 7326, Fall 2014 - 66 - © Y. Chiu
Exploiting Internal Redundancy
• Input falling in shaded region randomly sees one of two RTF’s dithering.
• Decision threshold needs not to be accurate or matched to each other.
• Digitization outcome is independent of PRBS when ADC is ideal !!
Ref. [14]
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Identifying Residue Gain Error
1 1 ideal 1 ideal 1If V { region 1 } and T = +1, D =D ; if T = -1, D =D -δ
1 2 31 1 1
1 1 1Segmental offset : D = + d + d +...d +d δ
4 8 16
1 1 ideal 1 1 idealIf V { region 2} and T = +1, D =D +δ ; if T = -1, D =D
EECT 7326, Fall 2014 - 68 - © Y. Chiu
Identifying Residue Gain Error
1 1 1δ = δ +μ D Tn+1 n n n
1 1 1ideal idealideal 1 ideal 1
1 11 1
1 1
1 1D T = Pr V { region 1 } Pr V { region 2 }D - -DD -δ D +δ
2 21 1
= δ Pr δ PrV { region 1 } V { region 2 }2 21
= δ Pr V { region 1 or 2 }2
1 1D T 0δ removed
Calculating correlation:
LMS learning:
• Correlation reveals information about segmental offset.
• Exact size of shaded region is not important (only affects Pr(.)).
• Key observation: if ADC is ideal, D1 must be uncorrelated to T.
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PRBS Test-Signal Injection(Sub-DAC Injection)
EECT 7326, Fall 2014 - 70 - © Y. Chiu
2D
Sub-DAC Injection – DAC Dither
Converge@
2D T = 0
• In steady state, analog gain (G1) and digital gain (G1-1) cancel exactly.
• 2-k ≤ ¼ to avoid overflow in residue output, DAC adds 2 bits minimum.
• Injection bit scaling factor (2-k) must match to the sub-DAC unit elements.
residuepath
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2D
Sub-DAC Injection – DAC Dither
Converge@
2D T = 0
-VR/2
0
d1=1 d1=2
-VR
VR/2
VR
¼ bit½ bit
...
...
typ. k = 2
• In steady state, analog gain (G1) and digital gain (G1-1) cancel exactly.
• 2-k ≤ ¼ to avoid overflow in residue output, DAC adds 2 bits minimum.
• Injection bit scaling factor (2-k) must match to the sub-DAC unit elements.
EECT 7326, Fall 2014 - 72 - © Y. Chiu
Signal-Dependent DAC Dither
Vj (VR) T = +1 T = -1
-1 -⅜ 0 0
-⅜ -⅛ 0 VR
-⅛ ⅛ -½ VR ½ VR
⅛ ⅜ -VR 0
⅜ 1 0 0
PRBS Injection Table
• PRBS only injected when input falls within the shaded region.
• Extra comparators needed to instrument the SD dither.Ref. [15]
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Opportunistic DAC Dither
Vin/VR
2x rangeres in RV = 4V - V D
res in RV = 4V - V D + PN
in R inr
Res
th
in
4V - V D'+PN , V V
4V - V D, o.w.V =
Vre
s/V
R
0-1 11
-1
0
Vre
s/V
R
1
-1
0
1
-1
0
-2
2
Vin/VR
Vre
s/V
R
2x range
0-1 1
Vth Vth Vth
0-1 1
GapGap
• When redundancy is not ample, blind injection requires large DR.
• Without additional comparators, detecting Vth vicinity is difficult.
EECT 7326, Fall 2014 - 74 - © Y. Chiu
Exploiting Comparator Metastability
Q+
, Q-
Q+
, Q-
Vin-Vthsmall
Vin-Vth large
• Comparator resolving time indicates proximity of input.
• Proximity detector also functions as metastabilty detector/resolver.
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12b 160MS/s CMOS Prototype (40nm)
• (5b + 8b) synchronous two-step pipelined SAR architecture.
• First-stage capacitor weights identified w/ opportunistic DAC dither.
EECT 7326, Fall 2014 - 76 - © Y. Chiu
Die Photo
40nm low-leakage CMOS process(active area = 0.042mm2)
Integrator+
DAC
MDAC1 MDAC2 MDAC3 MDAC4
Sub-ADC1
Sub-ADC2
Sub-ADC3
Sub-ADC4
Sub-ADC5
Clock&
PN Gen.
300μm
139μ
m
Ref. [16]
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Measured ADC Dynamic Performance
10 80 30055
60
65
70
75
80
85
90
Fin [MHz]
dB
Fin = 80MHz
SNDRSFDR
100 160 20055
60
65
70
75
80
85
90
Fs [MHz]
dB
Fs = 160MHz
SNDRSFDR
Fs = 160MHz after cal. Fin = 25MHz after cal.
EECT 7326, Fall 2014 - 78 - © Y. Chiu
Power Consumption
Analog 1.1V2.8mW(53.6%)
Digital 1.1V2.2mW(42.2%)
• Total power is 4.96mW at 160MS/s operation.
Ref. [16]
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PRBS Test-Signal Injection(Input Injection)
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Direct Input Injection
• Algorithm works reliant on the independence b/t input and T.
• Multi-parameter extraction is possible by Independent Component Analysis.
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Independent Component Analysis (ICA)
o 1 2D = α D +β D -k T
n+1 n α 1 o 2
n+1 n β 2 o 1
α = α -μ g D g T
β =β -μ g D g T
Hérault-Jutten (HJ) stochastic de-correlation:
In our simulation, we picked g1(x) = x and g2(x) = x3.
Only two parameters need to be identified.
Ref. [17]
EECT 7326, Fall 2014 - 82 - © Y. Chiu
Simulation Results
1 1.1 1.2 1.3 1.4 1.51
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
/2
0 0.1 0.2 0.3 0.4-120
-100
-80
-60
-40
-20
0
ENOB=3.32
0 0.1 0.2 0.3 0.4-120
-100
-80
-60
-40
-20
0ENOB=11.99
H-J Learning TrajectoryBefore After
• Typical learning pattern of the H-J algorithm
• Steady-state coefficient fluctuation causing low-level spurs
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ICA extended to nonlinear treatment
2 3o i 0 1 i 2 i 3 iV = f V a +a V +a V +a V +...
jj j j ob n+1 = b n -μ D n T n j =1,...,5
Error model:
Update equations:
Ref. [17]
EECT 7326, Fall 2014 - 84 - © Y. Chiu
An ICA Approach for SAR Calibration
ˆ id T
d̂
Digital Post-Processing
• ICA recovers 2X speed at the cost of slower convergence.
• ALL bit weights {wj} are learned simultaneously!
T: PRBS
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Prototype SAR ADC w/ ICA
Sub-binary DACRef. [18]
EECT 7326, Fall 2014 - 86 - © Y. Chiu
Prototype SAR ADC w/ ICA
ICA
90nm CMOS, 0.05mm2
• 12b, 50MS/s in BG mode
• (3.3+1.4)mW power (45fJ/step)
• CICC Best Paper Award
Ref. [18]
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Measurement Results
Learning Curve
Dynamic Performance
• Gear shifting helps stabilize the steady-state fluctuations.
EN
OB
[bit]
0 10 20 30 40 50 6050
55
60
65
70
75
80
85
90
fin [MHz]
SF
DR
/ S
ND
R [d
B]
SFDR w/ cal. SNDR w/ cal. SFDR w/o cal.SNDR w/o cal.
EECT 7326, Fall 2014 - 88 - © Y. Chiu
Two-ADC Equalization
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Two-ADC Equalization Techniques
• Reference-ADC equalization
– Slow-Fast two-ADC architecture to accomplish accuracy and throughput simultaneously using adaptive equalization
– Two (different) ADC’s needed, subject to skew error without SHA
• Split-ADC equalization
– Two almost identical ADC’s employed for blind equalization
– Two ADC’s needed, subject to skew error without SHA
• Offset double conversion (ODC)
– Self-equalization by digitizing every sample twice with opposite DC offsets injected to the input
– Single ADC with modified timing in background mode
– Conversion throughput halved in background mode
EECT 7326, Fall 2014 - 90 - © Y. Chiu
Two-ADC Equalization(Reference-ADC)
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Reference-ADC Equalization
• Concept inspired by adaptive equalization in digital comm. receivers
• Divide-and-conquer approach to achieve analog speed and
accuracy
Ref. [11,12]
EECT 7326, Fall 2014 - 92 - © Y. Chiu
EQZ of Time-Interleaved ADC Array
• ALL paths are aligned to the unique ref. ADC after equalization.
Ф
Φ1
tnov
Фr
Φ2
Φ10
1 21002
1
2
11002
1002
ADC1
T/H
Ref.ADC
ADC10
ADF1
ADF10
D1
DLL
Ф1
Vin
1X
1X
D10
Dr
Ф10
Ф1
Ф10
Фr
Ф
Ф′
Digital
Cal.
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Prototype 10-way TI-ADC Array
Performance Comparison(@ time of publication)
Time CMOS Process
Speed[MS/s]
SFDR[dB]
FoM[fJ/step]
ISSCC06 0.13µm 600 43 220
ISSCC08 0.13µm 1250 48 480
VLSI08 65nm 800 58 280
ISSCC09 0.13µm 600 65 210
Die photo
• The 2009 DAC/ISSCC Student Design Contest Award
Ref. [5]
EECT 7326, Fall 2014 - 94 - © Y. Chiu
0 100 200 300-90
-80
-70
-60
-50
-40
-30
-20
-10
0
frequency [MHz]0 100 200 300
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
frequency [MHz]0 100 200 300
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
frequency [kHz]
SNDR=31.2dBSFDR=33.0dB
SNDR=46.7dBSFDR=65.2dB
SNDR=42.2dBSFDR=60.5dB
3fs/10
2fs/10 4fs/10
fs/10
HD3
HD3 HD3
SNDR=31.2 dBSFDR=33.0 dB
SNDR=42.2 dBSFDR=60.5 dB
SNDR=46.7 dBSFDR=65.2 dB
ADC Array EQZ – Measured Spectra
(fs = 600MS/s, fin = 7.8MHz, Ain = 0.9FS, 16k samples)
Ref. ADCAfter Cal.
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Two-ADC Equalization(Split-ADC)
EECT 7326, Fall 2014 - 96 - © Y. Chiu
Split-ADC Equalization
Vi
Vo
ADCA
Vi
Vo
ADCB
• Blind equalization w/o reference possible by offsetting the RTFs
• Fast convergence due to zero-forcing equalization
Ref. [13]
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Vin
dB
dA
Zero Forcing
Radix correction Zero-forcing EQZError observation
Vin
dB
dA
ε = 0
ε = dB−dA
EECT 7326, Fall 2014 - 98 - © Y. Chiu
Two-ADC Equalization(Offset Double Conversion)
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Offset Double Conversion (ODC) for SAR
• ODC enables zero-forcing self-equalization.
• ALL bit weights {wj} are learned simultaneously!
Digital Post-Processing
EECT 7326, Fall 2014 - 100 - © Y. Chiu
How to determine Bit Weights?
Is the transfer curve shift-invariant?
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How to determine Bit Weights?
Is the transfer curve shift-invariant?
EECT 7326, Fall 2014 - 102 - © Y. Chiu
How to determine Bit Weights?
Is the transfer curve shift-invariant?
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How to determine Bit Weights?
• Shift-invariant ONLY when the transfer curve is completely linear!
• Non-constant difference b/t D+ and D− reveals bit weight information.
EECT 7326, Fall 2014 - 104 - © Y. Chiu
Prototype SAR ADC w/ ODC
Sub-binary DAC ODC Aux. DAC
0.13µm CMOS, 0.06mm2
• 12b, 45MS/s in FG mode
• 3mW power (36.3 fJ/step)
• Most read JSSC article Nov. 2011
C0C1C13
SAR Logic
–VR
d0d1d13
CMPp
+VR
VX
C0
Vin
C13,d C6,dC∆
ReadyCMPn
CLKCLK
ACLK
Ref. [19]
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Measurement ADC Spectra (BG Mode)
0 5 10-120
-100
-80
-60
-40
-20
0d
B
Freq [MHz]0 5 10
-120
-100
-80
-60
-40
-20
0
dB
Freq [MHz]
After Cal.Before Cal.
SNDR = 60.2dB
SFDR = 66.4dB
THD = -61.7dB
SNDR = 70.7dB
SFDR = 94.6dB
THD = -89.1dB
EECT 7326, Fall 2014 - 106 - © Y. Chiu
Convergence Time (BG Mode)
0 1 2 3 4 5 6
x 104
-5
0
5
10
e [L
SB
]
Number for samples
0 1 2 3 4 5 6
x 104
-5
0
5
10
e [L
SB
]
Number for samples
0 1 2 3 4 5 6
x 104
-5
0
5
10
e [L
SB
]
Number for samples
22000 samples @ 22.5MS/s ≈ 1ms
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Comparison with 12b ADCs
2000 2002 2004 2006 2008 201010
-2
10-1
100
101
Year
Fo
M (
pJ/
con
v. s
tep
)
2000 2002 2004 2006 2008 201010
-2
10-1
100
101
102
Year
Act
ive
area
(m
m2 )
0.06mm2
46fJ/step @ 22.5MS/s31fJ/step @ 45MS/s
Total Power: 3.0mW
(@ time of publication)
EECT 7326, Fall 2014 - 108 - © Y. Chiu
Summary of Dig. BG Cal. Techniques
Method Parameter Test signal Injection point Reference†
DNC + GEC { βj,k, αj,m } multi PRBS sub-DAC [9,10,20-24]
Split capacitor { ∆j } 1 PRBS sub-DAC [25,26]
Sig.-dep. dither { γj } 1 PRBS sub-DAC [15,16]
GEC + SA { γj } 2 PRBS sub-ADC [27,28]
Statistics { αj,m } 1 PRBS sub-ADC [29,30]
Fast GEC { γj } 1 PRBS sub-ADC [31]
ICA { γj }, { αj,m } 1 PRBS input [17,18,32,33]
Ref. ADC { βj,k, αj,m } n/a n/a [5,11,12,34-36]
Virtual ADC { βj,k, αj,m } offset sub-DAC [37,38]
Split ADC{ αj,m } n/a n/a [13,39]
{ βj,k, αj,m } n/a n/a [40]
ODC{ γj } offset input [19]
{ βj,k, αj,m } offset input [41]
† References are furnished at the end of the slides.
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Presentation Outline
• Principles of Multistep A/D Conversion
• Architectural Redundancy
• Error Mechanisms and Digital-Domain Calibration
• Error-Parameter Identification
– PRBS Test-Signal Injection (sub-ADC, sub-DAC, input)
– Two-ADC Equalization (ref.-ADC, split-ADC, ODC)
• Energy Efficiency and Trend
• Summary
EECT 7326, Fall 2014 - 110 - © Y. Chiu
ADC Figure-of-Merit (FoM)
W ENOB
P JouleFoM
2 BW 2 Conversion -Step
BW: min{fs/2, ERBW}
ERBW: effective resolution BW
"Energy Efficiency"
P: power consumption
ENOB: effective number of bits
Walden FoM:
ENOB
S 10
2 BW 4FoM 10log dB
PSchreier FoM:
• Walden FoM is intuitive but penalizes noise/matching-limited designs.
• Schreier FoM is more fair to high dynamic range designs.
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Performance, Efficiency, and Power
α/2αENOBPerforman = 2 BW Hz pce Ste
Performance = Speed × SNR
α/2αENOB
P J
2 BW SteEnergy Eff n
picie cy
αα
ENOBENOB
P= 2 BW =
2 B
Performance Efficie
W
ncy
Power
Note: α = 2 - 4
EECT 7326, Fall 2014 - 112 - © Y. Chiu
Performance–Efficiency (PE) Chart
1E+09
1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E+16
1E+17
1E-18 1E-17 1E-16 1E-15 1E-14 1E-13 1E-12
Energy Efficiency = Power/(2·BW·3ENOB)
Per
form
ance
= 2
·BW
·3E
NO
B
Constant performance
Co
nst
ant
effi
cien
cy
(log scale)
(lo
g s
cale
)
X·Y = Power
α = 3
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PE Chart: Pipelined ADC (<2005)
1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
Pipeline (<2005)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
EECT 7326, Fall 2014 - 114 - © Y. Chiu
1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
Pipeline (<2005)
Pipeline (2005-2010)
PE Chart: Pipelined ADC (2005-2010)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
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1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
Pipeline (<2005)
Pipeline (2005-2010)
Pipeline (2010-2013)
PE Chart: Pipelined ADC (2010-2013)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
EECT 7326, Fall 2014 - 116 - © Y. Chiu
PE Chart: SAR ADC (<2005)
1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
SAR (<2005)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
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1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
SAR (<2005)
SAR (2005-2010)
PE Chart: SAR ADC (2005-2010)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
EECT 7326, Fall 2014 - 118 - © Y. Chiu
1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
SAR (<2005)
SAR (2005-2010)
SAR (2010-2013)
PE Chart: SAR ADC (2010-2013)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
12b,160MS/s5mW
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1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
Pipeline (<2005)Pipeline (2005-2010)Pipeline (2010-2013)SAR (<2005)SAR (2005-2010)SAR (2010-2013)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
PE Chart: Both ADCs (<2014)
IndustryADCs
UniversityADCs
EECT 7326, Fall 2014 - 120 - © Y. Chiu
1E+10
1E+11
1E+12
1E+13
1E+14
1E+15
1E-16 1E-15 1E-14 1E-13 1E-12 1E-11
Pipeline (<2005)Pipeline (2005-2010)Pipeline (2010-2013)SAR (<2005)SAR (2005-2010)SAR (2010-2013)
ISSCC & VLSI data
100mW
1W
10mW1mW100μW10μW
Efficiency
Per
form
ance
10W
EUT
PE Chart: Both ADCs (<2014)
OSU
IMEC
NCKU
NCTUMichigan
MIT
Panasonic
OSUFujitsu
ADI TI Agilent
ADI
AKM
BCMKENET
NSC
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Bibliography
1. W. R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., vol. 27, pp. 446-472, Jul. 1948.
2. S. H. Lewis et al., "A 10-b 20-MS/s analog-to-digital converter," JSSC, vol. 27, Mar. 1992.
3. F. Kuttner, "A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS," in ISSCC, 2002.
4. C. C. Liu et al., "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," in ISSCC, 2010.
5. W. Liu et al., "A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization," in ISSCC, 2009.
6. T. Sun, A. Wiesbauer, and G. C. Temes, "Adaptive compensation of analog circuit imperfections for cascaded delta-sigma ADCs," in ISCAS, 1998.
7. P. Kiss et al., "Adaptive digital correction of analog errors in MASH ADC’s—Part II: Correction using test-signal injection," TCAS2, vol. 47, Jul. 2000.
8. D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital back-ground calibration technique for time-interleaved analog-to-digital converters," JSSC, vol. 33, Dec. 1998.
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