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Advanced Digital DesignAdvanced Digital DesignMetastabilityMetastability
by A. Steininger and M. DelvaiVienna University of Technology
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 2
OutlineOutline
What is metastabilityWhat is metastability
Effects and ThreatsEffects and Threats
The unavoidabilityThe unavoidability
MTBU estimationMTBU estimation
CountermeasuresCountermeasures
TrendsTrends
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 3
Digital LogicDigital Logic
The output of a digital logic gate The output of a digital logic gate always assumes a defined logic levelalways assumes a defined logic level
The undefined („forbidden“) voltage The undefined („forbidden“) voltage range in between is assumed onlyrange in between is assumed only during transition (very shortly)during transition (very shortly) for undefined input levels (!)for undefined input levels (!)
„1“
„0“
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 4
Important RemarksImportant Remarks Specified behavior of a component can Specified behavior of a component can
be expected only on condition of its be expected only on condition of its environmentenvironment behaving as specified. behaving as specified.
Digital levels are represented by Digital levels are represented by analoganalog voltages. Also the transistors voltages. Also the transistors inside the gates are inherently inside the gates are inherently analoganalog elements. We just use a digital elements. We just use a digital abstractionabstraction, since the gates are , since the gates are specified for a digital environment.specified for a digital environment.
Once generated, undefined logic levels Once generated, undefined logic levels have the potential to have the potential to propagatepropagate
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 5
Inverter ExampleInverter Example
analog transfer analog transfer characteristicscharacteristics
undefined input undefined input level may lead to level may lead to undefined output undefined output levellevel
propagation of propagation of undefined levelundefined level
uin
uoutInverter-characteristics
BUT: No „generation“ of undefined levels BUT: No „generation“ of undefined levels
(for defined inputs)(for defined inputs)
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 6
Observation:Observation: An input transition during the An input transition during the decision window leads to an (unbounded) decision window leads to an (unbounded) increase of clock-to-output delay increase of clock-to-output delay
tclk2out
tclk2out,nom
tclk2datatsetup thold0
CLK
D
Response Time of a FFResponse Time of a FF
off
-spec
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 7
Behavior during DelayBehavior during Delay
A data transition during the setup/hold A data transition during the setup/hold window violates the environment speci-window violates the environment speci-fications. Consequently the output does fications. Consequently the output does not behave as specified. Possibilitiesnot behave as specified. Possibilities
delayed but proper transitiondelayed but proper transition may cause timing problemsmay cause timing problems
creeping through undefined rangecreeping through undefined range generates long undefined levelgenerates long undefined level
oscillationoscillation generates erroneous transitionsgenerates erroneous transitions
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 8
Metastability: CreepingMetastability: Creeping
1
2
3
4
5
1 2 3 4 5
1
1
Inv 1
Inv 2
ue,2 = ua,1
ue,1 = ua,2
stable (HI)
stable (LO)
metastablemetastable
A
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 9
CLK
D
Q
D Q1
1
1
Why a Setup/Hold Time?Why a Setup/Hold Time?
When swiching a When swiching a latch from latch from „transparent“ to „transparent“ to „hold“ the „hold“ the feedback path feedback path must be stable.must be stable.
Otherwise we Otherwise we capture a capture a transition, thus transition, thus generating a generating a lasting undefined lasting undefined levellevel
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 10
Physical EquivalentPhysical Equivalent
Ball may remain on top („metastable“) for Ball may remain on top („metastable“) for unbounded timeunbounded time
A small disturbance causes the ball to fall in A small disturbance causes the ball to fall in either directioneither direction
normal operation: sufficient impulse rolls ball over hill
problem case: insufficient impulse
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 11
Why voilate Setup/Hold?Why voilate Setup/Hold?
in a closed synchronous system no in a closed synchronous system no violations will occurviolations will occur
BUT: no system is really closedBUT: no system is really closed non-synchronous interfacesnon-synchronous interfaces clock domain boundariesclock domain boundaries fault effects fault effects (single-event upsets)(single-event upsets) off-spec operation off-spec operation (temp, VCC, frequency)(temp, VCC, frequency)
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 12
asynchronous event
setup/hold
clock period Tclk
dec. win. T0
probability of setup/hold violation
Asynchronous InputsAsynchronous Inputs
00 clk
violate T
TP
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 13
CLK 1 (Ref)
CLK 2
A
Multiple Clock DomainsMultiple Clock Domains
arbitrary „phase“ relation setup/hold violation inevitable
(fundamentally!)
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 14
Metastability: ThreadMetastability: Thread
propagationpropagation undefined logic level at input may undefined logic level at input may
produce undefined outputproduce undefined output „„Byzantine“ InterpretationByzantine“ Interpretation
thresholds of different inputs are thresholds of different inputs are different (type variations)different (type variations)
marginal input level may be marginal input level may be interpreted differentlyinterpreted differently
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 15
D
CLK
X
Metastab.
Xdata
clkuin
uout
Combinational gates as well as the Combinational gates as well as the inverters inside the FF map metastable inverters inside the FF map metastable inputs to metastable outputsinputs to metastable outputs
Inverter-characteristics
A
Metastability PropagationMetastability Propagation
D
CLK
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 16
Inconsistent PerceptionInconsistent Perception
D
CLK
D
CLK
X
0
1
Metastab.
The metastable state may be regarded as The metastable state may be regarded as „1“ by one FF and as „0“ by another„1“ by one FF and as „0“ by another
CMOS 3V
0.8V
2.0V
0.0V0.4V
2.4V
3.3V
D
CLKX
threshold A
A
Btreshold B
A
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 17
Why use the D-Flipflop?Why use the D-Flipflop?
Metastability is not restriced to Metastability is not restriced to D-FFs, it is encountered withD-FFs, it is encountered with
SR-latch, JK-Flipflop, Muller C-Gate,…SR-latch, JK-Flipflop, Muller C-Gate,…
basic issue:basic issue: Even with perfect input level runts may Even with perfect input level runts may
emerge from looped-back outputs under emerge from looped-back outputs under unfavorable timing conditionsunfavorable timing conditions
Basically all biststable Basically all biststable elements can become elements can become metastablemetastable min min
max
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 18
Metastability ProofsMetastability Proofs
Formal proofs exist thatFormal proofs exist that no upper bound on the duration of no upper bound on the duration of
metastable state can be givenmetastable state can be given metastability can in principle not be metastability can in principle not be
avoided („Buridan‘s Principle“)avoided („Buridan‘s Principle“) Fundamental issueFundamental issue
Mapping from a continuous space to a Mapping from a continuous space to a discrete space involves a decision that discrete space involves a decision that may take unbounded time (namely in may take unbounded time (namely in borderline cases)borderline cases)
RuntsRunts create such borderline cases create such borderline cases
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 19
Mitigating MetastabilityMitigating Metastability
Metastability cannot be eliminatedMetastability cannot be eliminated in practice systems still work because in practice systems still work because
metastability is very improbable metastability is very improbable it can be made it can be made
more or lessmore or lessprobable by probable by design techniquesdesign techniques
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 20
c
res
clkdat
t
fTfMTBU
exp
1
0
Quantifying the Risk of MSQuantifying the Risk of MS
„„Upset“Upset“ metastable output is captured by metastable output is captured by
subsequent FF after subsequent FF after ttrr
Mean Time Between Upset (MTBU)Mean Time Between Upset (MTBU) expected value (statistics!) for interval expected value (statistics!) for interval
between two subsequent upsetsbetween two subsequent upsets
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 21
Resolution TimeResolution Time
clk
asyn
syntclk2out
tcomb tSUtres
SUcombclkres ttTt
D
CLK
D
CLK
asyn
clk
syn comb. logic
normal operation:
tclk2out < tr
upset:
tclk2out > tr
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 22
ParametersParameters
Resolution timeResolution time t tresres interval available for output to settle after interval available for output to settle after
active clock edge active clock edge
Flip-Flop parameters Flip-Flop parameters c c ,,TT00
experimentally determinedexperimentally determined time constant time constant cc dep. on transit frequ. dep. on transit frequ.
TT00 from effective width of decision window from effective width of decision window
Clock period of FF Clock period of FF TTclkclk = 1/= 1/ffclkclk
Average rate of change Average rate of change ffdatdat
average data rate at FF data inputaverage data rate at FF data input
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 23
Simple Metastability ModelSimple Metastability Model
model bistable model bistable element by element by inverter pairinverter pair
use use linear modellinear model for inverter, around for inverter, around midpoint of midpoint of transfer function transfer function („balance point“)(„balance point“)
consider „homo-consider „homo-genuous“ case, i.e. genuous“ case, i.e. closed loopclosed loopuin
uoutInverter-characteristics
uout = -A*uin
u1 u2
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 24
Introducing DynamicsIntroducing Dynamics
1st order 1st order approximation of approximation of dynamic behavior: dynamic behavior: RC elementRC element
assume symmetry assume symmetry (same A, RC for (same A, RC for both inverters) for both inverters) for simplicitysimplicity
assume symmetric assume symmetric supply supply (+VCC/-VCC) (+VCC/-VCC)
against GNDagainst GND
-A
-ARC =
RC = u1 u2
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 25
Differential EquationsDifferential Equations
Basics:Basics:
forward path:forward path:
backward path:backward path:
Laplace:Laplace:
time-domain solution:time-domain solution:
RR iRu dt
duCi C
C
dt
duCRuAu 2
12
dt
duCRuAu 1
21
0)()(
usUsdt
tduL
02212 uUsUAU
01121 uUsUAU
t
Auut
Auutu
1
exp2
1exp
2)(
01
02
01
02
2
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 26
The SolutionThe Solution
uu2200-u-u11
00 … difference of initial voltages … difference of initial voltages (charges on Cs); zero at balance point(charges on Cs); zero at balance point
… … RC constant, RC constant, bandwidth = 1/RCbandwidth = 1/RC
A … inverter gain at balance pointA … inverter gain at balance point A/A/ … gain bandwidth product of inverter … gain bandwidth product of inverter
starting from the initial difference ustarting from the initial difference u22 rises rises exponentially with timeexponentially with time towards the towards the positive or negative supply voltagepositive or negative supply voltage
t
Auutu
1
exp2
)(01
02
2
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 27
Plot of uPlot of u22 over Time over Time
-500
-250
0
250
500
0 1 2 3
-25
-20
-15
-10
-5
0
5
10
15
20
25
For a given For a given tt we can project „forbidden“ input range back we can project „forbidden“ input range back to a „forbidden“ range of the initial voltage differenceto a „forbidden“ range of the initial voltage difference
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 28
Forbidden Initial RangeForbidden Initial Range
t
Auutu
1
exp2
)(01
02
2
uu00
resborderoutrborder t
AUtu
1
exp)( ,,0
The forbidden output voltage range relates to a The forbidden output voltage range relates to a forbidden range of initial difference voltage (i.e. just forbidden range of initial difference voltage (i.e. just after sampling). This range becomes exponentially after sampling). This range becomes exponentially smaller for smaller for high resolution time high resolution time ttresres and and high gain-high gain-bandwidth product bandwidth product AA//..
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 29
Aperture Window Aperture Window TTAWAW
How long does it take for the input How long does it take for the input voltage difference to cross the voltage difference to cross the forbidden range? forbidden range?
Depends on feedback voltage slopeDepends on feedback voltage slope(and probably on input voltage!)(and probably on input voltage!)
+u0,border
u0,borderTAW
udiff(t), slope S
S
uT border
AW,02
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 30
Calibrating Calibrating TTAWAW
TTAWAW depends on depends on uu0,0,border border , , which in turn depends on which in turn depends on ttresres
for immediate use of the output:for immediate use of the output:
thusthus
res
borderborderAW t
A
S
U
S
uT
1
exp22 ,0,0
0,02
)0( Wborder
resAW TS
UtT
resWAW t
ATT
1
exp0
technology parameter
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 31
Hitting the ApertureHitting the Aperture
with exponentially distributed inter-arrival with exponentially distributed inter-arrival time of input events (rate time of input events (rate datdat) and sampling ) and sampling with period with period TTclkclk (i.e. window (i.e. window TTAWAW is repeated) is repeated) the upset rate can be calculated asthe upset rate can be calculated as
Hence the MTBU becomesHence the MTBU becomes
clk
AWdatupset T
T
AW
clk
datupset T
TMTBU
11
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 32
Putting it all togetherPutting it all together
AW
clk
datupset T
TMTBU
11
resWAW t
ATT
1
exp0
res
W
clk
dat
tA
T
TMTBU
1
exp1
0
T0 C
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 33
The widely used equationThe widely used equation
c
r
clkdat
t
TffMTBU
exp
1
0
rate (!) of input events
sampling frequency
technology parameters
expected time between upsets (statistical!)
available resolution time
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 34
Provoking MetastabilityProvoking Metastability
asynchronous inputsasynchronous inputs multiple clock domainsmultiple clock domains clock divider (uncontrolled delay)clock divider (uncontrolled delay)
low timing marginslow timing margins slow technology (gain/BW prod)slow technology (gain/BW prod) supply drop (excessive delay)supply drop (excessive delay) heatingheating
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 35
Claim: „Metastability is a non-issue Claim: „Metastability is a non-issue in modern technologies“ in modern technologies“
log MTBU[s]
tres
6
12
5
1996 (XC4005)
2002 (XC2VP4)
BUT: clock rates have increased by a factor of 16 during that period –
and timing margins have shrunk in the same way!
Metastability – TrendsMetastability – Trends
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 36
Mitigating MetastabilityMitigating Metastability
avoid/minimize non synchronous IFsavoid/minimize non synchronous IFs leave sufficient timing marginsleave sufficient timing margins use fast technology (gain/BW prod)use fast technology (gain/BW prod) ensure proper perating conditions ensure proper perating conditions
(stable power supply, cooling,…)(stable power supply, cooling,…)
basic principle of synchronizers:basic principle of synchronizers:
trade performance for increased trade performance for increased timing margins (ttiming margins (tresres))
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 37
SynchronizerSynchronizer Example: Cascade of Example: Cascade of nn Input-FFs Input-FFs
D
CLK
asyn
clk
syn
D
CLK
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 38
Assumptions made so farAssumptions made so far
linear inverter slope linear inverter slope (1st order model)(1st order model) load independent gainload independent gain dominating RC const. dominating RC const. (1st order model)(1st order model) full symmetry full symmetry (RCs, inverter properties, (RCs, inverter properties,
rising/falling slopes,…)rising/falling slopes,…) decreasing exp term neglecteddecreasing exp term neglected homogenuous case homogenuous case (MUX switching and (MUX switching and
input signal shape neglected)input signal shape neglected) equally distributed voltage levelsequally distributed voltage levels exponentially distributed input eventsexponentially distributed input events
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 39
A More general MS ModelA More general MS Model
ideal amplifier
gain -A
pure delay
delay
slope limiter
time constant RC slope S
GBWP = A/RC determines dynamics (decay of metastable state)
oscillation for > RC/A
creeping otherwise