ADVANCED GERMANIUM COMPLEMENTARY-METAL ... On Chui...credit are the most valuable characteristics for me to learn from. In addition, I would like to thank the members of my reading

ADVANCED GERMANIUM COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR

TECHNOLOGIES

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Chi On Chui

August 2004

ii

© Copyright by Chi On Chui 2004

All Rights Reserved

iii

I certify that I have read this dissertation and that, in my opinion, it

is fully adequate in scope and quality as a dissertation for the

degree of Doctor of Philosophy.

__________________________________________

Krishna C. Saraswat (Principal Advisor)




__________________________________________

Yoshio Nishi




__________________________________________

Paul C. McIntyre

Approved for the University Committee on Graduate Studies

__________________________________________

iv

This thesis is dedicated to

my family

v

Abstract

Drive current saturation in scaled Si MOSFETs is fundamentally limiting the

prospect of future scaling. To overcome this scaling bottleneck and allow further

improvements on short-channel MOSFET drive current, Ge MOSFET channel with high

carrier mobility and source injection velocity should be incorporated. However, the

unstable Ge native oxide for gate insulation and field isolation, together with the high

diffusivity and low solubility of n-type Ge dopants for source and drain junction

formation are the two classical problems that have obstructed CMOS device realization in

Ge for four decades.

In this work, three types of nanoscale gate dielectric for Ge MOS applications are

investigated. The scalability and stability of native Ge oxynitrides are first examined

followed by a seminal investigation and demonstration of integration of the more scalable

and stable high-κ metal oxides for Ge MOS applications. The effects of different Ge

surface cleaning and passivation strategies are discussed, leading to the demonstration of

sub-1.0 nm equivalent SiO 2 thickness dielectric stack on Ge.

Additionally, two techniques to form shallow junctions for Ge MOSFET source

and drain applications are studied. The corresponding activation and diffusion of various

p-type and n-type dopants in Ge are analyzed after either the ion implantation or solid

source diffusion doping. Through monitoring the thermal stability of the out-diffused

dopants, phosphorus deactivation in Ge is observed for the first time.

Finally, two low thermal budget processes to fabricate Ge MOSFETs are

developed using the above dielectric and junction technologies. Metal gate high-κ Ge p-

MOSFETs are fabricated without exceeding 400 °C that demonstrate effective hole

mobility enhancement over the silicon universal mobility model. On the other hand,

functional metal gate high-κ Ge n-MOSFETs are built using an innovative self-aligned

gate-last process, which could be used as a technology vehicle to expedite the evaluation

of numerous novel materials integration for advanced MOSFET applications.

vi

Acknowledgements

The accomplishment of this Ph.D. would never be possible without the supports

from many individuals. First and foremost, I would like to express my sincere gratitude

to my principal advisor, Professor Krishna C. Saraswat, fo r all his guidance and support

in my last 4 years in the group. I am particularly impressed by his deep insights on many

apparently general problems as well as his vision on numerous future potential research

areas of interest. His liberal style in supervising students and his unselfishness in sharing

credit are the most valuable characteristics for me to learn from. In addition, I would like

to thank the members of my reading and orals committee including Professor Yoshio

Nishi for his useful advice and continuous encouragement, Professor Paul C. McIntyre

for making possible my collaboration with his group on high-κ dielectric issues, and

Professor Piero A. Pianetta for enabling my interaction with his team on synchrotron

radiation photoemission studies.

The invaluable consultation from a number of experts is another key to success.

Above all, I would like to pay my tribute to Dr. James P. McVittie, whose significant

contributions are usually ignored as an un-named hero, for his hands-on experimental

assistance. Secondly, I would like to acknowledge Dr. Baylor B. Triplett for his initial

help on the high-κ dielectric on Ge feasibility study and spreading his expertise on SiO2

on Si interfaces. Thirdly, I am extremely grateful to Prof. Eugene E. Haller (from UC

Berkeley) for our numerous phone discussions to check out his career-long experience on

Ge. Also, other specialists’ advices from Dr. Michael Deal, Prof. Robert Dutton, Dr.

Peter Griffin, Dr. Christoph Jungemann, Dr. Ann Marshall, Prof. James Meindl (from

Georgia Tech) and Prof. James Plummer are undoubtedly gratefully acknowledged.

Additionally, I would like to greet the prompt and fruitful collaborations with

Stanford insiders like David Chi, Kailash Gopalakrishnan, Fumitoshi Ito, Hyoungsub

Kim, Hai Lan, Dong-Ick Lee, Yang Liu, Eric Pop, Shriram Ramanathan, Andy Singh,

and Shiyu Sun, as well as outsiders like Muhannad Bakir from Georgia Tech and

Jungwoo Oh from UT Austin.

vii

Due to the inherent experimental nature of this work, the helps from many SNF

lab members should not be forgotten. Dr. Eric Perozziello, Pat Castle and Hector

Cavazos have been my life-savers for years. Moreover, my processing time would not

have been such enjoyable and productive without the presence of Cesar Baxter, Len

Booth, Dick Crane, Elmer Enriquez, Carl Faulkner, Dan Grupp, Jim Haydon, Sameer

Jain, Paul Jerabek, Eun-ha Kim, Robin King, Nancy Latta, Frankie Liu, Yaocheng Liu,

Mahnaz Mansourpour, Mike Martinez, Chang-man Park, Henry Phan, Gladys Sarmiento,

John Shott, Maurice Stevens, Yayoi Takamura, Mario Vilanova, Dunwei Wang, and

many others. Also, I would thank Tom Carver of the Ginzton Lab for running literally

hundreds of metal evaporations for me.

Throughout these years residing in CIS, I have gotten many times help from staff

including Dr. Richard Dasher, Maureen Rochford, and Carmen Mriaflor. Besides, I am

very grateful to numerous members of Prof. Saraswat’s group, past and present, who

have provided me with help and advice including Amol Joshi, Rohit Shenoy, Albert

Wang, Dan Connelly, Ting-Yen Chiang, Marci Liao, Ali Okyay, Ammar Nayfeh, and

Abhijit Pethe. Thanks especially to Irene Sweeney for her prompt and untiring

administrative assistance on my behalf.

Last but not least, thanks go to my wonderful family for sharing their endless love

and support with me. Thanks go to my parents and brother for their care and for being

there whenever I need them. Thanks to my wife, Hoi Yan, for her creativity and skill in

preparing delicious dishes, her love and smile, and always being a good listener to me. I

pray for their happiness and good health, and I dedicate my work to them in the most

sincere way I can think of.

viii

Table of Contents Abstract......................................................................................................... v

Acknowledgments....................................................................................... vi

Table of Contents...................................................................................... viii

List of Tables............................................................................................... xi

List of Figures............................................................................................. xii

Chapter 1. Introduction............................................................................... 1

1.1 Drive Current Saturation in Scaled Si MOSFETs............................................... 1

1.2 Demand for Germanium Channel MOSFETs...................................................... 5

1.2.1 Physical and Historical Facts about Germanium...................................... 5

1.2.2 CMOS Performance Boost with Germanium............................................ 9

1.3 Thesis Objective and Organization.................................................................... 13

Chapter 2. Nanoscale Ge MOS Gate Dielectrics: From native GeOxNy to

high-κ MOx.............................................................................. 15

2.1 Introduction........................................................................................................ 15

2.2 Native Germanium MOS Dielectrics................................................................. 18

2.2.1 Germanium Oxidations........................................................................... 18

2.2.2 The Rapid Thermal Processing System................................................... 20

2.2.3 Germanium Oxynitride Synthesis........................................................... 21

2.2.4 Scaling and Electrical Characterizations of Oxynitride.......................... 23

2.2.5 Effects and Degree of Nitridation in Oxynitride..................................... 28

2.2.6 Oxynitride-Germanium Interface Trapped Charge................................. 29

2.3 High-κ Dielectrics by Atomic Layer Deposition............................................... 31

2.3.1 High-κ Dielectric Motivation and Selection........................................... 31

2.3.2 Atomic Layer Deposition Process for High-κ Dielectric........................ 35

2.3.3 Atomic Layer Epitaxy of Zirconium Oxide on Germanium................... 36

ix

2.3.4 Atomic Layer Deposited Zirconium Oxide on Differently Prepared

Germanium Surfaces............................................................................... 40

2.3.5 Atomic Layer Deposited Hafnium Oxide on Differently Prepared


2.4 High-κ Dielectrics by Ultraviolet Ozone Oxidation.......................................... 52

2.4.1 Ultraviolet Ozone Oxidation Process for High-κ Dielectric................... 52

2.4.2 Ultraviolet Ozone Oxidized Zirconium Oxide on Differently Prepared


2.4.3 Zirconium Oxide-Germanium Interfacial Layer Identification............... 57

2.5 Benchmarking Nanoscale Ge MOS Gate Dielectrics........................................ 64

2.6 Summary............................................................................................................ 66

Chapter 3. Shallow Junction Formations in Ge by Ion Implantation and

SSD Doping.............................................................................. 69

3.1 Introduction........................................................................................................ 69

3.2 Shallow Junctions by Ion Implantation Doping................................................. 72

3.2.1 P-type Junction Activation with Furnace Anneal................................... 72

3.2.2 Complementary Junctions Activation with Rapid Thermal Anneal....... 76

3.2.3 N-type Dopant Diffusion......................................................................... 81

3.3 Shallow Junctions by Solid Source Diffusion Doping...................................... 84

3.3.1 N-type Junction Activation and Diffusion............................................... 84

3.3.2 Dopant Deactivation within Activated Junctions.................................... 88

3.4 Summary............................................................................................................ 91

Chapter 4. Low Thermal Budget Ge MOSFET Fabrication Processes 93

4.1 Introduction........................................................................................................ 93

4.2 The Sub-400 °C Metal Gate High-κ P-MOSFET Process................................ 95

4.2.1 Structural Design..................................................................................... 95

4.2.2 Process Flow............................................................................................ 98

4.2.3 Device Characterizations....................................................................... 100

4.3 The Novel Self-Aligned Gate-Last Metal Gate High-κ MOSFET Process..... 103

x

4.3.1 Structural Design................................................................................... 103

4.3.2 Process Flow.......................................................................................... 105

4.3.3 Device Characterizations....................................................................... 107

4.3.4 Advantages and Extensions of The Novel Process............................... 110

4.4 Summary.......................................................................................................... 112

Chapter 5. Conclusions............................................................................ 113

5.1 Summary.......................................................................................................... 113

5.2 Contributions and Impacts of This Work......................................................... 115

5.3 Recommendations for Future Work................................................................. 116

Bibliography............................................................................................. 119

xi

List of Tables Table 1.1 Physical properties of Ge and Si at 300 K [10].

Table 1.2 Ballisticity extracted from p- and n-MOSFETs with conducting channel

orthogonal to Si<100>, Ge<100>, and Ge<111> surfaces [8]. The Si data

were adopted from Ref. [35].

Table 2.1 Different Ge pre-oxidation treatments and surface oxidations.

Table 2.2 Key comparisons of the three nanoscale Ge MOS dielectrics.

Table 3.1 Extracted diffusion coefficients and the associated model for various n-type

dopants in Ge [18].

Table 4.1 Different series of ring MOSFET layout.

xii

List of Figures Figure 1.1 Normalized planar bulk Si MOSFET performance trend in the 30-40 year

span [1].

Figure 1.2 Recently reported IDsat’s with respect to the channel length reduction by

IBM, TI, Bell Labs, Intel, and AMD [2].

Figure 1.3 (a) Conduction subband edge versus position from the source to the drain

of a nanoscale MOSFET under high gate and drain bias. Also shown are

the thermal injection fluxes from the source and drain. (b) Illustration of

carrier backscattering in a MOSFET under high drain bias. If a carrier

backscatters beyond the critical distance l from the beginning of the

channel, then it is likely to exit from the drain and unlikely to return to the

source [4].

Figure 1.4 Quantum leaps in new materials [9].

Figure 1.5 Absorption coefficients for Si, Ge, and selected III-V compound

semiconductor materials in the visible and near- infrared spectral region

[11].

Figure 1.6 Normalized (a) cosmic and (b) earth abundances of va rious elements with

respect to Si.

Figure 1.7 (a) Bardeen and Brattain’s point-contact semiconductor amplifier with the

n-type polycrystalline Ge and two line-contacts of gold affixed to the

polystyrene wedge [12]. (b) Schematic of semi-conductor triode [13].

Figure 1.8 The first integrated circuit, a phase shift oscillator fabricated in Ge,

invented by Jack Kilby [15].

Figure 1.9 Schematic diagrams of the different sub-band energy levels in (a) bulk

semiconductor and (b) ultrathin GOI. Both the energy differences (E1-E0

and E’0-E0) increase due to carrier confinement effect [32].

Figure 1.10 Ultimate IDsat-Vg characteristics under a limit of zero nm EOT [32].

xiii

Figure 1.11 The double-gate MOSFET structure used for MC device simulation with

Ge channel [8]. Device geometry and dimension were chosen mostly

according to ITRS.

Figure 1.12 Full band MC simulation of the transfer characteristics at VDS = VDD = 0.4

V on both Ge DG p- and n-MOSFETs. Both ballistic and scattering

transports were simulated along both [010]⊥<100> and [1 1 0] ⊥<111>

channel directions [8].

Figure 1.13 Achievable Ge DG n-MOSFET drain currents with varying source and

drain doping. Drain bias was set equal to VDD. Ballistic transports were

simulated along the [010]⊥<100> channel direction.

Figure 2.1 (a) Ge 3d core- level spectra as a function of temperature in the case of

chemical oxide on Ge(100) surface [2] and (b) Oxygen (O) 1s spectra of (i)

Ge(111) exposed to clean air for 5 hr, and (ii) after rinsing in warm water

[3].

Figure 2.2 The band diagram at flat bands condition for the Au/GeO2/Ge system [5].

Figure 2.3 Ge 3d core-level (left) and O 1s (right) spectra on differently prepared Ge

surface oxides: (i) thermal oxide, (ii) native oxide, (iii) H2O2 chemical

oxide, and (iv) HNO3 oxide. The Ge surfaces were HF cleaned prior to

oxidation (except on sample (ii)).

Figure 2.4 (a) Schematic of the AG Associates Heatpulse® 4108 rapid thermal

processing (RTP) system, (b) the quartz reaction chamber tube, and (c) the

quartz wafer tray and wafer position mechanism [42].

Figure 2.5 The AG Associates Heatpulse® 4108 lamp temperature control feedback

system block diagram [42].

Figure 2.6 (a) GeOxNy film thickness and (b) refractive index estimated using optical

ellipsometry after various rapid thermal processes.

Figure 2.7 The XPS intensity ratio of N 1s to O 1s signals as a function of the

photoelectron take-off angle on a typical GeOxNy film. The intensity ratio

increases with take-off angle which suggests a higher nitrogen content

xiv

within the GeOxNy film near the bottom interface. The insets show the N

1s and O 1s XPS spectra from different take-off angles [44].

Figure 2.8 (a) Multi- frequency gate capacitance-voltage characteristics measured from

an as-deposited W/GeOxNy/n-Ge capacitor stack (solid symbols) and after

300 °C anneal in N2 and then in forming gas (open symbols), and (b) the

corresponding gate leakage-voltage measurements [44].

Figure 2.9 Change of W/GeOxNy/n-Ge capacitor (with 3.0-5.0 nm EOT) VFB after

subsequent anneals in either N2 or forming gas ambient at either 300 or 400

°C for 30 min. Solid and open symbols respectively represent GeOxNy

samples without and with O2 PDA prior to W deposition. The ideal VFB

(assuming zero Qf) and the theoretical VFB (assuming and EOT of 4.0 nm

and Qf of 1012 C/cm2) are also included [44].

Figure 2.10 W/GeOxNy/Ge capacitor gate leakage density as a function of EOT

normalized at 1 V above flat-band voltage. All the data were taken on n-

type Ge substrates. As a reference the leakage current level from thin SiO 2

on Si MOSFET is also included [44].

Figure 2.11 Measured W-gate Ge MOS capacitance normalized to the maximum

accumulation Cox for (a) GeO2 dielectric, and (b) GeOxNy dielectrics with

different degree of nitridation. C-V was measured on as-deposited samples

at 10 kHz small-signal frequency.

Figure 2.12 (a) and (b) show the quasi-static and high-frequency (1 MHz) C-V

characteristics measured on GeOxNy MOS capacitors with n- and p-type Ge

substrates. The GeOxNy was identically grown on both substrates. (c) and

(d) illustrate the extracted interface trap level densities (before and after a

forming gas anneal) as a function of Ge surface potential using the

combined low-high frequency capacitance method [51]. The sampled

surface potential span was limited to flat-band-to-2? B.

xv

Figure 2.13 High performance logic technology EOT target and the corresponding gate

leakage density limit as a function of technology generation specified in the

ITRS 2003 Edition [52].

Figure 2.14 Binary phase diagrams for (a) Y2O3-GeO2 and (b) La2O3-GeO2 systems

[56].

Figure 2.15 Calculated Zr-Ge-O ternary phase diagram at 600 K [57].

Figure 2.16 Energy band diagrams of the (left) Ge/HfO 2 and (right) Ge/GeOx/HfO2

structures inferred from the IPE experiments. The measurement error of

the barrier height determination is ±0.1 eV [59].

Figure 2.17 (a) Schematic diagram of the ALD system, and (b) the ALD reaction

mechanism [57].

Figure 2.18 Cross-sectional HR-TEM micrographs along the <110> zone-axis of (a)

Pt/5.5 nm ZrO2/Ge(100), and (b) 6.8 nm ZrO2/Ge(111) [61].

Figure 2.19 Schematic diagram showing the epitaxial relationship and the interfacial

dislocations for the sample illustrated in Fig. 2.18 (a) [57].

Figure 2.20 (a) Bright-field plan-view image of the 5.5 nm ZrO2/Ge(100), and (b)

selective area diffraction pattern showing the corresponding epitaxial

relationship. (c) Bright- field plan-view image of the 6.8 nm ZrO2/Ge(111),

and (b) selective area diffraction pattern showing the corresponding

epitaxial relationship [57, 61].

Figure 2.21 Multi- frequency gate capacitance-voltage characteristics measured from (a)

a Pt/ZrO2/n-Ge(100) capacitor after forming gas anneal and (b) an as-

deposited Pt/ZrO2/n-Ge(111) capacitor, and (c) their corresponding gate

leakage-voltage measurements [57, 61].

Figure 2.22 Ge surface Rrms from AFM as a function of DI water rinse time [65]. The

Rrms values from both epitaxial and Czochralski Si wafers were also

included.

Figure 2.23 Multi- frequency gate capacitance-voltage characteristics measured from

post-forming gas anneal Pt/5.5 nm ZrO2/n-Ge(100) capacitors with various

xvi

starting Ge surfaces: (a) HF vapor etched, (b) DI water rinsed, and (c)

chemical oxide kept.

Figure 2.24 Gate leakage-voltage measurements from Pt/5.5 nm ZrO2/n-Ge capacitors

with different Ge surface preparations. Also included is the leakage

reference from a Pt/5.5 nm ZrO2/chemical oxide/Si capacitor [57].

Figure 2.25 Cross-sectional HR-TEM images of ~ 4.5 nm ALD HfO 2 on (a) CHF

cleaned, (b) chemical oxide kept, and (c) thin GeOxNy Ge surfaces.

Figure 2.26 EOT with respect to SiO 2 and normalized hysteresis estimated from bi-

directional C-V sweep from Pt/HfO 2/n-Ge with various surface

preparations prior to ALD [65]. The series resistance correction [69] was

applied before parameter extractions using both the 100 kHz and 800 kHz

scan data. The C-V hystereses were normalized to the same EOT value of

the thin GeOxNy sample.

Figure 2.27 Gate leakage-voltage measurements from Pt/4.5 nm HfO2/n-Ge capacitors

with different Ge surface preparation [65]. Solid and open symbols are

used for non-hydroxylated and hydroxylated surfaces respectively.

Figure 2.28 Multi- frequency gate capacitance-voltage characteristics measured from (a)

Pt/HfO2/GeOxNy/p-Ge and (b) Pt/HfO 2/GeOxNy/n-Ge capacitors [65].

Figure 2.29 Multi- frequency gate capacitance-voltage characteristics measured from as-

deposited Pt/HfO 2/GeOxNy/p-Ge capacitors with the GeOxNy grown at (a)

600 °C and (b) 700 °C for 1 min apiece. (c) and (d) are the measurements

after a forming gas anneal at 300 °C for 30 min. (e) shows the

corresponding gate leakage-voltage measurements.

Figure 2.30 (a) Ge 3d XPS spectra, (b) N 1s XPS spectra, and (c) relative N atomic

concentration from the GeOxNy films as a function of RTN temperature.

Figure 2.31 Ge 3d (left) and N 1s (right) XPS spectra on the GeOxNy film grown at 600

°C after either an H2O or HF etch.

Figure 2.32 MEIS spectra with the simulation curves and the corresponding model

structure of (a) HfO 2 on Ge substrate with chemical oxide kept and (b)

xvii

HfO2 on CHF cleaned Ge substrate followed by RTN at 600 °C for 1 min

in NH3 [72].

Figure 2.33 Schematic diagram of the UHV metal sputtering chamber with in-situ

ultraviolet ozone oxidation capability to form MOx.

Figure 2.34 Multi- frequency gate capacitance-voltage characteristics measured from

post-forming gas anneal Pt/ZrO2/n-Ge(100) capacitors with various starting

Ge surfaces: (a) chemical oxide kept, (b) DI water rinsed, and (c) HF vapor

etched [76]. All the EOT values are quoted before any quantum

mechanical correction.

Figure 2.35 Gate leakage-voltage measurements from Pt/ZrO2/n-Ge capacitors with

different Ge surface preparation [76]. Open and solid symbols are used for

chemical oxide kept and oxide stripped surfaces respectively.

Figure 2.36 Cross-sectional HR-TEM images of Pt/ZrO2/Ge capacitors with different

starting Ge surfaces: (a) DI water rinsed and (b) HF vapor etched [76].

Figure 2.37 Schematic diagram of the SR-PES system. A hemispherical analyzer is

mounted at the magic angle (54°44’) with respect to the incoming photon

beam. LEED optics, thermal couple, Cs doser are also available for other

analysis [81].

Figure 2.38 ZrO2/Ge sample surface Rrms from AFM as a function of 100:1 HF solution

etch time [82].

Figure 2.39 Sub-shell photoelectron cross-sections of (a) Ge and (b) Zr [83].

Figure 2.40 (a) Ensemble evolution SR-PES spectra as a function of ZrO2/Ge etch time

including both core-level and VB spectra taken at photon energy of 100 eV.

(b) Magnified valence band spectra of (a) [84].

Figure 2.41 Peak-fitted SR-PES spectra of the ZrO2/Ge after 16-18 sec of etch with

both the elemental and oxidized Ge peaks assigned [84].

Figure 2.42 Fitted core- level Ge 3d peak areas as a function of etch time [84]. Cross-

sectional schematics of the stack are also included to illustrate the etching

progress.

xviii

Figure 2.43 Illustrations of escape depth calculation on the photoelectrons from Ge

substrate at two different time points: (a) right after complete ZrO2 removal,

and (b) right after complete GeOx removal [84].

Figure 2.44 Benchmarking the gate leakage from Ge MOS capacitors with nanoscale

dielectric. All data from native GeOxNy and high-κ/Ge with and without

interfacial layer (IL) were taken on n-type Ge substrates.

Figure 3.1 (a) Diffusivity of various impurities in Ge, and (b) schematic diagram

showing the method used for locating the p-n junction on Ge samples [2].

Figure 3.2 Solid solubility values for various dopants in germanium. The Ga, As, and

Sb data (solid lines) were taken in 1960 [4] and the scattered solubilities

(Ga (? ), P ( ¦ ), As (?), and Sb (? )) were summarized in 1990 [5].

Figure 3.3 (a) Sheet resistance and (b) activated dose measured from surface

implanted p+ layers on n-type Ge substrate as a function of furnace anneal

temperature. These Hall effect measurements were carried out at room

temperature after the capping SiO 2 removal. The values extracted from the

as-implanted sample and sample right after SiO 2 deposition are also

included [15].

Figure 3.4 Schematic of a SRP analysis, where metal probes step down the surface of

a beveled sample and measure the resistance between the probes at each tip

[16].

Figure 3.5 (a) Resistivity and (b) electrical concentration measured on two BF2

implanted Ge samples with one annealed at 400 °C for 30 min in N2 and

the other first annealed at 400 °C for 30 min in N2 and then in forming gas

(FGA) [15]. The SPR measurements were carried out at room temperature

after the capping SiO 2 removal.

Figure 3.6 Electrical concentration measured on BF2, P, As, and Sb implanted Ge

samples after various RTA [18]. The SPR measurements were carried out

at room temperature with the capping SiO 2 on top.

xix

Figure 3.7 Plot of the fractional activation of various n-type dopant implants as a

function of anneal temperature for two isochronal anneals (solid symbols

for 10 sec and open symbols for 5 sec).

Figure 3.8 SIMS and SRP depth profiles of B and P before and after an RTA at 650

°C for 10 sec. BF2 and P were implanted at 20 and 18 keV, respectively, at

a dose of 4×1015 cm-2 [18]. Both SIMS and SPR measurements were

carried out with the capping SiO 2 on top.

Figure 3.9 SRP profiles of various n-type dopants in Ge after two different RTA

treatments (675 °C for 5 sec and 650 °C for 60 sec) [18].

Figure 3.10 Experimental SRP profiles and the corresponding T-SUPREMTM

simulation fits for ion implanted P in Ge after 10 sec of RTA at 600 °C and

700 °C [18].

Figure 3.11 SRP depth profiles of the out-diffused P into p-type Ge substrate as a

function of RTP soak time at 850 °C in N2 ambient [26].

Figure 3.12 Metallurgical junction depths versus the square root of RTP soak time

extracted from the out-diffused junctions at 850 °C and 900 °C.

Figure 3.13 Arrhenius plot of the extracted intrinsic diffusivity of P in Ge together with

the reference data from Ref [2].

Figure 3.14 (a) Temperature dependence of the intrinsic diffusion coefficient of P in Ge

[2] and Si [3], and (b) the same intrinsic diffusivity dependence normalized

to the corresponding crystal melting point in K.

Figure 3.15 SRP depth profiles of the junction first formed by out-diffusion from PSG

at 850 °C for 10 sec (estimated) in N2 and those subsequently annealed

with different thermal budgets and in different ambient.

Figure 3.16 SIMS depth profiles of the junction first formed by out-diffusion from PSG

at 850 °C for 10 sec in N2 and that subsequently annealed at 600 °C for 60

sec in NH3 ambient.

Figure 4.1 Steps in the fabrication of a metal replacement gate transistor [3].

Figure 4.2 Damascene gate transistor fabrication process [4].

xx

Figure 4.3 Top view of the ring MOSFET structure (left) and cross-sectional view of

A-B (right) [5].

Figure 4.4 Effective channel width extraction by applying the gradual channel

approximation on a long-channel ring MOSFET [5].

Figure 4.5 Cross-section HR-TEM image taken from a fully processed Pt/ZrO2/Ge p-

MOSFET with DI water rinsed Ge surface [5].

Figure 4.6 Output characteristics of Pt/ZrO2/Ge p-MOSFET with (a) DI water rinsed

and (b) HF vapor etched Ge surfaces prior to ZrO2 deposition [5].

Figure 4.7 Inversion capacitance measured at 400 kHz from a Pt/ZrO2/Ge p-MOSFET

[5].

Figure 4.8 Effective hole mobility versus effective E-field extracted from Pt/ZrO2/Ge

p-MOSFETs with either DI water rinsed or HF vapor etched Ge surfaces

prior to ZrO2 deposition. Mobility from the Si universal model [8] and a

high-κ/Si p-MOSFET [9] are also included.

Figure 4.9 The simple and novel low thermal budget self-aligned gate- last fabrication

process for integrating metal gate and high-κ dielectric into Ge (and Si)

MOSFETs [12-13].

Figure 4.10 Source and drain to substrate diode I-V characteristics measured from a

Pt/HfO2/GeOxNy/Ge n-MOSFET.

Figure 4.11 Inversion capacitance measured at 400 kHz from a Pt/HfO 2/GeOxNy/Ge n-

MOSFET [12].

Figure 4.12 Output characteristics of (a) Pt/ZrO2/GeOxNy/Ge n-MOSFET and (b)

Pt/HfO2/GeOxNy/Ge n-MOSFET with 1-2 µm of channel length [12].

Figure 4.13 FIB XS-SEM Diagnostics.

Figure 4.14 Extension of the novel process to incorporate LDD structures [12].

Figure 4.15 Extension of the novel process to fabrication complementary channel

MOSFETs [12].

xxi

Figure 4.16 Elevated source and drain junctions could be employed upon the

replacement of the insulating solid dopant source with a doped Si1-xGex

alloy [12].

Figure 5.1 Snapshot of the emerging research device chapter from the 2003 version of

ITRS [1].

xxii

Chapter 1. Introduction

1

Chapter 1 Introduction 1.1 Drive Current Saturation in Scaled Si MOSFETs

Looking into the past 15-20 years, the scaling of planar bulk silicon (Si) metal-

oxide-semiconductor field-effect transistors (MOSFETs) had been very successful that

guaranteed a roughly 17% device performance enhancement per year as shown in Fig.

1985 1995 2005 2015 20250.1

1

10

Historical Trend (17% per year)

IEDM Benchmark Technologies

ITRS Projections Bulk Si Transport

Properties

No

rmal

ized

Per

form

ance

Year

Figure 1.1 Normalized planar bulk Si MOSFET performance trend in the 30-40 year span [1].


2

1.1 [1]. In the coming 15-20 years, the International Technology Roadmap for

Semiconductors (ITRS) projects the future device performance to closely follow this

historical trend. However, theoretical calculations suggest that by simply maintaining the

same planar bulk geometry and/or Si channel the MOSFETs may not be able to keep up

with the required performance beyond the year of 2010.

The saturation of bulk Si MOSFET drive current (IDsat) upon dimension shrinkage

is limiting the prospect of future scaling as illustrated in Fig. 1.2. By reading the x-axis

backward, the IDsat from both n-MOSFETs and p-MOSFETs stop to improve beyond a

drawn gate length of 0.25 µm. In this analysis the off current was kept constant. To

understand this saturation phenomenon, numerous theoretical and experimental analyses

were carried out [3-7]. First of all, the IDsat (and transconductance) in very short-channel

MOSFETs is believed to be limited by carrier injection from the source into the channel

[3]. In order words, the source injection velocity (vsrc) saturates during scaling and that

its limit is set by thermal injection velocity (vinj) [4] as depicted in Fig. 1.3 (a). Also, the

carrier density at the top of the source to channel barrier is fixed by MOS electrostatics

and the scattering in a short region near the beginning of the channel limits the IDsat (Fig.

1.3(b)). In deeply scaled MOSFETs, vsrc was experimentally shown to be at most 40% of

vinj [5].

Figure 1.2 Recently reported IDsat’s with respect to the channel length reduction by IBM, TI, Bell Labs, Intel, and AMD [2].

Drawn Gate Length (µm)

Sat

ura

ted

Dra

in C

urr

ent (

µA/µ

m)

NMOS

PMOS

Drawn Gate Length (µm)

Sat

ura

ted

Dra

in C

urr

ent (

µA/µ

m)

NMOS

PMOS


3

By corroborating measured velocity and mobility dependencies on deeply scaled

MOSFETs, the carrier velocity was shown to have a direct proportionality with the low-

field effective inversion- layer mobility [6]. Unfortunately, mobility is not a well-defined

quantity in a nanoscale MOSFET under high drain bias where off-equilibrium transport

dominates; however in Ref. [3], it was demonstrated that the drain current of a nanoscale

MOSFET is directly related to the near-equilibrium mean-free-path for backscattering,

which can be deduced from measurements on a corresponding long-channel MOSFET

for which the mobility is well defined. In brief, these results suggested that mobility

continues to be of crucial importance to saturated transconductance and IDsat as channel

lengths decrease below ~ 100 nm [7].

Moreover, the common performance metrics, MOSFET drive current and logic

gate delay, when expressed in terms of vinj [8], respectively reveals a direct and indirect

proportionality:

injinvDsat vQWI ××= and (1.1)

( ) injthDD

DD

Dsat

DDLOAD

vVVVL

IVC

×−×

= (1.2)

Figure 1.3 (a) Conduction subband edge versus position from the source to the drain of a nanoscale MOSFET under high gate and drain bias. Also shown are the thermal injection fluxes from the source and drain. (b) Illustration of carrier backscattering in a MOSFET under high drain bias. If a carrier backscatters beyond the critical distance l from the beginning of the channel, then it is likely to exit from the drain and unlikely to return to the source [4].

(a) (b)


4

where W is the MOSFET channel width, Qinv is the inversion charge density, CLOAD is the

load capacitance, VDD is the supply voltage, L is the MOSFET gate length, and Vth is the

threshold voltage. Therefore, by coupling these simple relationships with the above

theoretical and experimental analyses, one can easily identify the advantage of

incorporating an alternative MOSFET channel material with higher carrier mobility (and

vinj) to allow further improvements on MOSFET IDsat versus technology scaling.

In fact, in order to continue the historical progress in information processing and

transmission, different classes of new materials have been introducing to Si-based

microelectronics for the last few decades (Fig. 1.4). Metal silicides, metals for

interconnection, metal gate electrodes, high-permittivity (high-κ) gate dielectrics,

ferroelectric materials, as well as low-permittivity interlayer dielectrics were brought in

before [9]. To enhance transport property, strain has also been applied to the Si channel

[1]. In the present research, the use of new semiconductor channel materials is being

pursued.

Figure 1.4 Quantum leaps in new materials [9].


5

1.2 Demand for Germanium Channel MOSFETs 1.2.1 Physical and Historical Facts about Germanium

Germanium (Ge) belongs to the same group in the Periodic Table as Si, and offers

several attractive physical properties over Si as excerpted in Table 1.1 [10]. In Ge, the

lower electron transverse and light hole (and heavy) effective masses are primarily

responsible, respectively, for the higher electron and hole drift mobility. This property is

most advantageous over Si for deeply scaled MOSFET applications as previously

discussed regardless of the higher Si saturation velocity. The more symmetric electron

and hole mobility in Ge would reduce the real estate of p-MOSFETs, and hence would

permit more compact complementary-MOS (CMOS) logic gates. Moreover, its smaller

bandgap is more compliant with the supply voltage scaling as specified in ITRS [1]; at

the same time, this also broadens the optical absorption spectrum (Fig. 1.5) to cover

telecommunication wavelengths (1.3 and 1.55 µm) allowing opto-electronic integration

Properties Symbols Ge Si Units

Bandgap at 300 K Eg 0.66 1.12 eV

Breakdown E-field EBD ~ 105 ~ 3×105 V/cm

Dielectric permittivity κ 16.0 11.9 ?

Drift mobility (electron) µe 3900 1500 cm2/V-s

Drift mobility (hole) µh 1900 450 cm2/V-s

Effective mass (electron longitudinal) mle* 1.64 0.98 ?

Effective mass (electron transverse) mte* 0.082 0.19 ?

Effective mass (heavy hole) mhh* 0.044 0.16 ?

Effective mass (light hole) mlh* 0.28 0.49 ?

Intrinsic carrier concentration ni 2.4×1013 1.45×1010 cm-3

Melting point ? 937 1415 °C

Saturation velocity vsat 6×106 1×107 cm/s

Thermal conductivity at 300 K kth 0.6 1.5 W/cm-°C

Table 1.1 Physical properties of Ge and Si at 300 K [10].


6

to enhance CMOS functionality. Furthermore, its lower melting point reflects a

possibility to fabricate Ge MOSFETs with much lower thermal budget processes while

relaxing some stringent thermal stability requirements in integrating novel materials like

metal gate electrode and high-κ dielectric into advanced transistors.

On the other hand, some of the nice Si properties would have to be compromised.

For example, the lower breakdown E-field could be a concern for deeply scaled or high

voltage Ge devices, plus the higher dielectric permittivity would cause the Ge MOSFETs

to be more susceptible to short-channel effects. Additionally, the higher intrinsic carrier

concentration of Ge makes itself less suitable for high temperature device operation, and

its lower thermal conductivity may worsen the problems in today’s already very hot

integrated-circuits. Also, the much less cosmic and earth abundances of Ge (Fig. 1.6)

could eventually limit the manufacturing of Ge devices in large quantity. Nevertheless,

some of these shortcomings can be alleviated by employing innovative device structures

that will be elaborated in the next section.

Figure 1.5 Absorption coefficients for Si, Ge, and selected III-V compound semiconductor materials in the visible and near- infrared spectral region [11].


7

Historically, Ge was the most important semiconductor for decades. On

December 16, 1947, the first transistor action was experimentally observed in Bell Labs

by John Bardeen and Walter Brattain in n-type polycrystalline Ge as a result of the

judicious placement of gold-plated probe tips in nearby single crystal grains of the

0 10 20 30 40 50 60 70 80 9010-8

10-6

1x10 -4

10-2

100

102

104

106

No

rmal

ized

Co

smic

Ab

un

dan

ce

Atomic Number

Ge

OSi

Figure 1.6 Normalized (a) cosmic and (b) earth abundances of various elements with respect to Si [scattered data collected from the Internet].

0 10 20 30 40 50 60 70 80 9010-10

10-8

10-6

1x10-4

10-2

100

102

No

rmal

ized

Ear

th A

bu

nd

ance

Atomic Number

Ge

OSi

(a) (b)

Figure 1.7 (a) Bardeen and Brattain’s point-contact semiconductor amplifier with the n-type polycrystalline Ge and two line-contacts of gold affixed to the polystyrene wedge [12]. (b) Schematic of semi-conductor triode [13].

(a)

(b)


8

polycrystalline material (i.e. the point-contact semiconductor amplifier, often referred to

as the point-contact transistor (Fig. 1.7(a)) [12-15]. The device configuration (Fig.

1.7(b)) exploited the inversion layer as the channel through which most of the emitted

(minority) carriers were presumed to be transported from the emitter to the collector.

Later on, both Bardeen and Brattain were awarded the Nobel Prize in physics in 1956

“for their researches on semiconductors and their discovery of the transistor effect”; this

prize was also shared with William Shockley, who had seminal contributions on injection

over barrier, p-n junction theory, and p-n junction transistor [16].

On September 12, 1958, Jack Kilby proved the concept of fabricating all

necessary components of the desired circuit, both active and passive, in a single piece of

semiconductor and their interconnection in-situ. The first working integrated circuit

model was a phase shift oscillator with about ten components in Ge and wire bonding

was utilized to interconnect the components within the chip (Fig. 1.8). Afterward, he was

also honored with the Nobel Prize in physics in 2000 “for basic work in information and

communication technology and for this part in the invention of the integrated circuit”

The water soluble nature of the Ge oxide was one of the key properties that led to

the success of the point-contact transistor [17], yet it cannot become a high quality gate

Figure 1.8 The first integrated circuit, a phase shift oscillator fabricated in Ge, invented by Jack Kilby [15].


9

dielectric for Ge MOSFET applications. The first Ge n-MOSFET demonstration

archived in literature could be dated back in 1965 with pyrolytically decomposed silicon

dioxide (SiO 2) gate dielectric and antimony (Sb) out-diffused junctions [18]. In contrast,

the first Ge p-MOSFET was realized in 1975 using chemical vapor deposited (CVD)

SiO2 gate dielectric and boron ion implanted source and drain [19]. Subsequently,

several Ge n-MOSFETs [20-25] and p-MOSFETs [23-31] were fabricated using various

MOS gate dielectric and junction fo rmation technologies, which are summarized in the

next two chapters. Even so, none of those technologies would be applicable for deeply

scaled MOSFETs. This mandates the development and evaluation of more advanced Ge

CMOS technologies as the goal of this dissertation.

1.2.2 CMOS Performance Boost with Germanium

In order to scale MOSFETs into the sub-20 nm regime, the use of high mobility

channel (like Ge) together with ultrathin body device structures would be most desirable.

The rationale behind this combination is to maximize the MOSFET IDsat and

simultaneously circumvent the poor electrostatic control to suppress short-channel effects

aforementioned. Recently, an added advantage of utilizing ultrathin body has also been

pointed out to enhance vinj in ultra-short-channel MOSFETs [32].

E1

E0

2-fold valleys (1st ladder)

4-fold valleys (2nd ladder)

E’0

E1

E0

E’0

1st ladder 2nd ladder

Figure 1.9 Schematic diagrams of the different sub-band energy levels in (a) bulk semiconductor and (b) ultrathin GOI. Both the energy differences (E1-E0 and E’0-E0) increase due to carrier confinement effect [32].

(a) (b)


10

By reducing the ultrathin body thickness (germanium-on- insulator (GOI)

thickness in this case), the energy sub-band structures (Fig. 1.9(a)) could be modulated to

increase the sub-band energies of both the second ladder and higher sub-bands in the first

ladder (Fig. 1.9(b)). This consequence then increases the electron occupancy of the

lowest sub-band (E0) within the first ladder, where electrons have the lowest effective

mass and valley degeneracy, and therefore leads to the resultant enhancement of vinj.

When the GOI and silicon-on- insulator (SOI) MOSFET IDsat-Vg were calculated using the

ultimate limit of zero gate dielectric thickness with respect to SiO 2 (EOT), thickness

confined GOI devices certainly out-performed the thickness confined SOI counterparts

(Fig. 1.10).

S D

G

G

10 nm 10 nm 10 nm5 nm 5 nm

5 nm

Undoped GeNo S/D overlap

Abrupt junction

15 nm

Uniformly doped Ge

EOT = 1 nm

Figure 1.11 The double-gate MOSFET structure used for MC device simulation with Ge channel [8]. Device geometry and dimension were chosen mostly according to ITRS.

Figure 1.10 Ultimate IDsat-Vg characteristics under a limit of zero nm EOT [32].


11

With the aim of understanding carrier transport within the ultrathin Ge channel in

the presence of source and drain, full band Monte Carlo (MC) device simulations were

performed [8] using DAMOCLESTM [33]. An ultrathin body double-gate (DG)

MOSFET structure (Fig. 1.11) was chosen to guarantee good electrostatics with

dimensions required by the high-performance logic technology at the end of ITRS for the

year 2016 [1]. The Ge body thickness was selected as 5 nm but not thinner to avoid any

carrier confinement effect [32] within the channel which could not be captured by

DAMOCLESTM. The channel length was rounded off to 10 nm (instead of 9 nm) for

convenient grid placement during simulation and the upper bound of EOT range (0.9-1.0

nm) was conservatively picked assuming technology immaturity. Due to the noisy nature

of any MC methods, the MOSFET sub-threshold behavior with low current (and

threshold voltage) was instead seized by drift-diffusion simulation. Next, the MOSFET

off-state current was fixed at 20 µA/µm (for DG MOSFETs) in every device by tuning

the threshold voltage through the gate electrode workfunction. Both the ballistic and

scattering transports were then simulated using 1000 carriers assuming zero gate leakage.

In the scattering simulations, phonon scattering, impurity scattering, and impact

ionization were included while ignoring any carrier-carrier scattering, alloy scattering,

and incomplete dopant ionization.

0.0 0.1 0.2 0.3 0.40

1000

2000

3000

4000

5000

ITRSSpec. [1]

n-MOSFETs

Ge<111> ballistic Ge<111> scattering Ge<100> ballistic Ge<100> scattering

Dra

in C

urr

ent

(µA

/µm

)

Gate Voltage (V)-0.4 -0.3 -0.2 -0.1 0.00

-1000

-2000

-3000

-4000

-5000

p-MOSFETs

Ge<111> ballistic Ge<111> scattering Ge<100> ballistic Ge<100> scattering

Dra

in C

urr

ent

(µA

/µm

)

Gate Voltage (V)

(a)

Figure 1.12 Full band MC simulation of the transfer characteristics at VDS = VDD = 0.4 V on both Ge DG p- and n-MOSFETs. Both ballistic and scattering transports were simulated along both [010]⊥<100> and [110] ⊥<111> channel directions [8].

(b)


12

Ge DG MOSFET transfer characteristics were plotted in Fig. 1.12 for both p- and

n-channel devices assuming a 1020 cm-3 source and drain doping and zero contact

resistance. Carrier transports along the channel direction orthogonal to the Ge

crystallographic orientation (or “surface”) investigated included [010]⊥<100> and [110]

⊥<111>. Obviously, the ballistic drain currents are always higher than scattering

transports at the same off-state current and all the devices meet the ITRS drive current

specification [1]. In addition, the channels along [1 1 0]⊥<111> deliver substantial

improvements over the [010]⊥<100> counterparts for both holes and electrons. The

enhancement in electron transport could be attributed to a lower effective mass and valley

degeneracy [32, 34] while the reason for hole transport improvement remains unknown

owing to the complex valence band structures.

Compared to the DAMOCLESTM simulation on Si DG MOSFETs with identical

device geometry and dimensions [35], both the Ge DG p- and n-MOSFET drain currents

are somewhat higher provided that a much higher drain bias (1.0 V) was used in the Si

simulations. The ballisticity, defined as the ratio of ballistic current to scattering current

with both the gate and drain biased to the supply voltage (0.4 V), are tabulated in Table

1.2 for different conducting channels. To summarize, deeply scaled Ge MOSFETs have

a higher ballistic current (ballistic limit) over Si devices; in addition, the practical

scattering Ge MOSFETs could be operated closer to their individual ballistic mode than

the Si counterparts.

Moreover, since the p-type doping level of 1020 cm-3 could be experimentally

obtained (Section 3.2.2), this assumption on p-MOSFET source and drain concentration

needs no refinement. However, the highest achievable n-type doping level is relatively

Si <100> Ge <100> Ge <111> p-MOSFET 0.48 0.70 0.56 n-MOSFET 0.68 0.78 0.76

Table 1.2 Ballisticity extracted from p- and n-MOSFETs with conducting channel orthogonal to Si<100>, Ge<100>, and Ge<111> surfaces [8]. The Si data were adopted from Ref. [35].


13

lower and the impact on n-MOSFET drive current deserves more attention. As depicted

in Fig. 1.13, the simulated MC drain current decreases with decreasing source and drain

doping and saturates at low concentration (~ 1019 cm-3). Nevertheless, even though n-

type Ge doping in excess of 1020 cm-3 may never be technologically possible, the

resultant MOSFET drive currents could still surpass the ITRS requirement.

1.3 Thesis Objective and Organization

The objective of this work is to develop and evaluate various advanced

technologies to fabricate high-performance Ge CMOS devices while establishing the

baseline processes to allow the realization of deeply scale Ge MOSFETs in the future.

This thesis is organized in 5 chapters. Chapter 2 discusses the investigation of

three types of nanoscale gate dielectric for Ge MOS applications including native Ge

oxynitrides, high-permittivity (high-κ) dielectrics grown by atomic layer deposition, and

high-κ dielectrics grown by ultraviolet ozone oxidation process. Their syntheses together

with various Ge surface preparations are first discussed. These dielectrics are then

physically and electrically characterized, and their performances are benchmarked

together.

1019 1020 10210

1000

2000

3000

4000

5000

ITRSSpec. [1]

n-MOSFETs

VGS

= 0.4 V V

GS = 0.3 V

VGS = 0.2 V

Dra

in C

urr

ent

(µA

/µm

)

Source and Drain Doping (cm-3)

Figure 1.13 Achievable Ge DG n-MOSFET drain currents with varying source and drain doping. Drain bias was set equal to VDD. Ballistic transports were simulated along the [010]⊥<100> channel direction.


14

Chapter 3 discusses the investigation of two techniques to form shallow junction

for Ge MOSFET applications including ion implantation and solid source diffusion

doping. Both furnace anneal and rapid thermal anneal are described to activate

incorporated dopants. The activation and diffusion of various p-type and n-type dopants

in Ge are studied together with the thermal stability of the activated dopants. Phosphorus

deactivation in Ge is observed for the first time and a possible mechanism is therefore

proposed.

Chapter 4 discusses the investigation of two low thermal budget processes to

fabricate Ge MOSFETs including a sub-400 °C metal gate high-κ p-MOSFET process

and a novel self-aligned gate- last metal gate high-κ MOSFET process. Both processes

are developed using the dielectric and junction technologies from the previous two

chapters. Their individual structural design and process flow are proposed and the

resultant devices are characterized by electrical measurements.

Finally, Chapter 5 summarizes the conclusions and contributions of this work and

recommends possible future areas of investigation.

Chapter 2. Nanoscale Ge MOS Gate Dielectrics: From native GeOxNy to high-κ MOx

15

Chapter 2 Nanoscale Ge MOS Gate Dielectrics: From Native Ge Oxynitrides to High-κ Metal Oxides 2.1 Introduction Silicon (Si) has been the most important semiconductor material in the modern

electronic industry since 1960s primarily attributed to its very high quality native oxide

for surface passivation. After over forty years of research, the scaling of classical bulk Si

metal-oxide-semiconductor field-effect transistors (MOSFETs) is approaching many

fundamental limits which mandate integration of novel materials and innovative device

structures to continue the historic progress in information processing and transmission.

Germanium (Ge) is a promising MOSFET channel material candidate with

numerous advantages over Si, however, lacks a stable native oxide for MOSFET gate

insulation and integrated-circuit (IC) field isolation. For instance, a mixture of Ge oxides

(GeOx and GeO2) would form on the Ge surface upon air exposure with the former

desorbs at moderate temperatures while the latter dissolves in water (H2O).


16

In order to illustrate these physical properties, many photoemission spectroscopy

(PES) studies were carried out [1-3]. On the Ge oxides prepared by reacting the Ge

surface with concentrated hydrogen peroxide (H2O2), synchrotron radiation

photoemission spectra (SR-PES) were taken as a function of thermal anneal temperature

in ultrahigh vacuum (UHV) as shown in Fig. 2.1(a). The oxidized Ge 3d core- level peak

(composite of GeOx and GeO2 signals) shifted towards lower binding energy with

increasing anneal temperature due to a gradual reduction of GeO2 to GeOx [2]. All the

GeOx completely desorbed at 430°C and led to the formation of a clean Ge surface.

Similarly, ultraviolet photoemission spectra (UPS) were recorded on Ge oxides formed

by exposing the wafer to clean room air (Fig. 2.1(b)). The GeO2 component was clearly

removed after rinsing the sample in warm water [3], a clear confirmation that the

commonly formed GeO2 has the water soluble hexagonal or quartz- like phase rather than

the insoluble tetragonal phase [1, 3-4].

Figure 2.1 (a) Ge 3d core- level spectra as a function of temperature in the case of chemical oxide on Ge(100) surface [2] and (b) Oxygen (O) 1s spectra of (i) Ge(111) exposed to clean air for 5 hr, and (ii) after rinsing in warm water [3].

(i)

(ii)

(a) (b)

420 (°C) RT


17

In addition to their thermodynamic instability, the Ge oxides are not electrically

robust for the continuous MOSFET scaling. In the energy band diagram estimated from

a gold (Au) electroded-GeO2/Ge system [5] where the GeO2 was formed by thermal

evaporation, the GeO2 bandgap was shown to be 3.98 eV, and its conduction band offset

(∆EC) and valence band offset (∆EV) with Ge are 1.41 eV and 1.90 eV respectively.

Depending on the stoichiometry and micro-structure, GeOx with bandgap as large as 5.95

eV has been synthesized [6], however, with a consistently small valance band offset of

about 2 eV. Both the small bandgap and band offset severely limit the applicability of

native germanium oxides as a scalable gate dielectric required in the advanced MOSFETs.

In order to obtain a stable dielectric with good electrical integrity for Ge

MOSFET applications, a variety of native and deposited dielectric materials have been

engineered during the last four decades. Gate quality native GeO2 dielectrics have been

grown by wet chemical oxidation [7], thermal oxidation [8-10], electron cyclotron

resonance plasma (ECR) oxidation [10], vacuum ultraviolet-assisted (VUV) oxidation

[11], as well as remote plasma oxidation [12]. To improve their thermal and chemical

stability, either thermal nitridation [13-19] or plasma anodic nitridation [20] was applied

to transform these Ge oxides to native Ge oxynitrides (GeOxNy). Alternatively, several

different deposited dielectrics for Ge MOS devices have been attempted including silicon

dioxide (SiO 2) [21-30], SiO2 on a thin Si cap [27, 30-36], silicon nitride (Si3N4) [26, 28],

Figure 2.2 The band diagram at flat bands condition for the Au/GeO2/Ge system [5].

EC

EV


18

GeO2 [28], germanium nitride (Ge3N4) [28, 37], aluminum oxide (Al2O3) [38-40], and

aluminum-phosphorus oxide (AlP xOy) [41].

In this chapter, a fundamental investigation of the scalability and stability issues

on native GeOxNy MOS dielectrics is first presented. Various physical and electrical

characterizations have been carried out to understand the GeOxNy bulk and GeOxNy-Ge

interface properties. In addition, we have studied the feasibility and then demonstrated

the incorporation of the more scalable and stable high-permittivity (high-κ) metal oxide

dielectrics for Ge MOSFET applications. The two techniques employed for high-κ

deposition are atomic layer deposition (ALD) of metal oxides and ultraviolet ozone

oxidation (UVO) of metal films. Various surface preparations prior to high-κ integration

were also examined for electrical behaviors. Lastly, the dielectric performance of both

the native GeOxNy and deposited high-κ metal oxides are benchmarked together with the

highly scaled dielectrics on Si.

2.2 Native Germanium MOS Dielectrics 2.2.1 Germanium Oxidations

Amongst all the stable native dielectric approaches listed in Section 2.1, thermal

nitridation of the intentionally grown Ge oxides is apparently the most promising and

accessible technique in our laboratory at this time. As the first step towards GeOxNy

formation, different methods for Ge surface oxidation were studied as listed in Table 2.1.

Table 2.1 Different Ge pre-oxidation treatments and surface oxidations. No. Pre-oxidation treatment Surface oxidation

(i) 50:1 HF, 30 sec Thermal oxidation in dry O2, 500°C, 8 min (ii) None Native (iii) 50:1 HF, 30 sec Chemical oxidation in 30% H2O2, room

temperature, 1 min (iv) 50:1 HF, 30 sec Chemical oxidation in conc. HNO3, room

temperature, 1 min


19

Ge 3d core-level and O 1s x-ray photoemission spectra (XPS) were taken on

different Ge oxides as plotted in Fig. 2.3. In order to analyze the chemical bonding

nature and stoichiometry of these oxides, the Ge 3d signals were further peak-fitted

assuming the existence of Ge, GeOx, and/or GeO2 configurations. Since the thermal

oxide (a) was relatively thick, the substrate elemental Ge peak (with binding energy ~ 30

eV) was absent due to its small photoelectron escape depth; on the other hand, the

elemental Ge peak was observed on samples (b) to (d) as these chemical oxidations are

usually self- limiting. Nonetheless, from both the Ge 3d and O 1s spectra, the bulk of the

thermal oxide (a) was mainly composed of stoichiometric GeO2 while the other

components consisted of a mixture of GeOx and GeO2. Moreover, the relative intensity

ratio of GeOx to GeO2 is higher for the chemical oxides prepared with either hydrogen

peroxide (H2O2) (c) or nitric acid (HNO3) (d), whose sub-stoichiometry may lead to the

creation of a high density of interface states for charge trapping and de-trapping as well

as channel mobility degradation in Ge MOSFET applications. The thermal oxide was

thereby chosen for subsequent nitridation to engineer the stable native GeOxNy, with both

processes carried out in an RTP system.

Figure 2.3 Ge 3d core-level (left) and O 1s (right) spectra on differently prepared Ge surface oxides: (i) thermal oxide, (ii) native oxide, (iii) H2O2 chemical oxide, and (iv) HNO3 oxide. The Ge surfaces were HF cleaned prior to oxidation (except on sample (ii)).

536 534 532 530 528

Inte

nsi

ty (a

.u.)

Binding Energy (eV)

(i)

(ii)

(iii)

(iv)

O(1s)

37 36 35 34 33 32 31 30 29 28 27

Inte

nsity

(a.

u.)

Binding Energy (eV)

GeOx

(i)

(ii)

(iii)

(iv)

GeO2

Ge

Ge(3d)


20

2.2.2 The Rapid Thermal Processing System

The rapid thermal processing (RTP) system is becoming a key piece of equipment

in modern semiconductor industry for fabricating advanced MOSFETs with very thin

gate dielectrics and ultra-shallow source and drain junctions. Our commercial AG

Associates Heatpulse® 4108 RTP system uses a bank of lamps that rapidly heat a single

wafer resting on sharp pins [42]. Fig. 2.4 (a) schematically illustrates this machine. The

heating occurs by optical energy transfer between the radiating lamps and the process

wafer, so that the transparent (quartz) walls of the reaction chamber (Fig. 2.4 (b)) may

remain relatively cool during short time processing. The process wafer temperature is

measured through the optical pyrometer located at the bottom of the reaction chamber,

(a)

(b)

(c)

Figure 2.4 (a) Schematic of the AG Associates Heatpulse® 4108 rapid thermal processing (RTP) system, (b) the quartz reaction chamber tube, and (c) the quartz wafer tray and wafer position mechanism [42].


21

which captures the wafer backside emissivity. The lamp temperature is then controlled

through a feedback system (Fig. 2.5).

2.2.3 Germanium Oxynitride Synthesis

The starting substrates used to synthesize GeOxNy were (100) oriented n-type and

p-type Ge wafers, with a net background doping concentration of ~ 7 × 1015 cm-3 and ~ 3

× 1017 cm-3, respectively at room temperature. The substrates were first cleaned by cyclic

rinsing between deionized (DI) water and hydrofluoric acid (HF), a technique originally

developed by Deegan and Hughes [43] for effective surface oxide removal. The HF

concentration employed was 50:1 and the rinse time was modified to 15 sec in each

chemical for a total duration of 150 sec. This cyclic HF (CHF) clean was finished with a

10 sec DI water rinse for chemical safety reasons. The cleaned Ge substrates were then

blown dry with nitrogen gas (N2) and immediately loaded into the RTP system.

Figure 2.5 The AG Associates Heatpulse® 4108 lamp temperature control feedback system block diagram [42].


22

The oxynitride formation recipe [44] consists of an initial rapid thermal oxidation

(RTO) at 500-600 °C with 5-120 sec soak time in dry oxygen (O2) to form germanium

oxides followed by in-situ rapid thermal nitridation (RTN) at 600 °C with 60-300 sec

soak time in ammonia (NH3) ambient to convert the oxides into oxynitrides. NH3 was

chosen as the nitriding agent due to its ability to incorporate more nitrogen (N) into the

oxynitride film over other species like nitrous oxide (N2O) or nitric oxide (NO), as

inferred from their behavior on Si oxides [45]. During the oxynitridation, the rapid

thermal ramp rates were set to 100 °C/sec for both RTO and RTN and the wafer

temperature was brought down to room temperature prior to RTN. On selected samples,

an in-situ post-deposition anneal (PDA) at 600 °C for 10 sec in dry O2 was performed.

The change in GeOxNy film thickness and refractive index during the entire process was

monitored using optical ellipsometry. For example, as shown in Fig. 2.6, the GeOxNy

film thickness decreased while the refractive index increased after the RTN treatment

following the initial 5 sec RTO step. Both phenomena could be explained by the

increased coordination between Ge and O atoms through the N incorporation, with longer

RTN soak time giving denser coordination that resembles the Si oxynitridation

experience [46]. The optional PDA thickened the GeOxNy by additional surface Ge

oxidation, diluted the N concentration within the GeOxNy film, and thereby reduced the

Ge and O atom coordination.

8

9

10

11

12

13 RTO 5 sec + RTN 120 sec + PDA RTO 5 sec + RTN 90 sec + PDA

PDA at 600ºCfor 10 sec

RTO at600ºC

RTN at600ºC

GeO

xNy F

ilm T

hic

knes

s (n

m)

1.2

1.3

1.4

1.5

1.6 RTO 5 sec + RTN 120 sec + PDA RTO 5 sec + RTN 90 sec + PDA

PDA at 600ºCfor 10 sec

RTO at600ºC

RTN at600ºC

GeO

xNy R

efra

ctiv

e In

dex

Figure 2.6 (a) GeOxNy film thickness and (b) refractive index estimated using optical ellipsometry after various rapid thermal processes.

(a) (b)


23

2.2.4 Scaling and Electrical Characterizations of Oxynitride

Angle-resolved x-ray photoemission spectroscopy (AR-XPS) was employed to

qualitatively depth profile the N content within the GeOxNy layer [44]. Illustrated in Fig.

2.7 is one such profile examining a typical GeOxNy film (grown by RTO at 600 °C for 5

sec followed by RTN at 600 °C for 2 min and without PDA). The XPS signals were first

peak-fitted around the N 1s and O 1s binding energies and the extracted intensities were

normalized by their corresponding sensitivity factors. In this film, the N-to-O XPS signal

intensity ratio increases with increasing photoelectron take-off angle. In other words,

more N is piled up near the bottom GeOxNy/Ge interface (rather than near the top surface)

and raises the local dielectric permittivity. Inspired by this phenomenon, we adopted a

general scaling strategy to reduce the initial thermal oxide thickness and thus to trim

down the resultant lower-κ top surface portion of GeOxNy. A secondary approach to

scale this dielectric was to increase the degree of nitridation by lengthening the RTN soak

time.

30 40 50 60 70 80 900.0

0.1

0.2

0.3

0.4

Ge oxynitride(GeO

xN

y)

N(1

s)/O

(1s)

Inte

nsity

Rat

io

Photoelectron Take-off Angle (degrees)

Figure 2.7 The XPS intensity ratio of N 1s to O 1s signals as a function of the photoelectron take-off angle on a typical GeOxNy film. The intensity ratio increases with take-off angle which suggests a higher nitrogen content within the GeOxNy film near the bottom interface. The insets show the N 1s and O 1s XPS spectra from different take-off angles [44].

531 532 533 534 535

O(1s) Inten

sity (a.u.)

Binding Energy (eV)397 398 399 400 401

N(1s)

30º35º

60º

90º

Inte

nsi

ty (

a.u

.)

Binding Energy (eV)


24

MOS capacitors were subsequently fabricated using these GeOxNy films by

electron beam evaporation of about 50 nm tungsten (W) through a shadow mask to form

gate electrodes of various sizes. Aluminum (Al) was then evaporated on the wafer

backside to reduce the sample contact (and series) resistance. Finally, on the completed

W/GeOxNy/Ge capacitor stacks, thermal anneals were carried out in either dry N2 or

forming gas (H2/N2) ambient for 30 min at either 300 °C or 400 °C to investigate their

effect on the capacitor electrical properties.

-2 -1 0 1 20.0

0.4

0.8

1.2

(VFB = 0.395 V)

(VFB

= -0.389 V)After N

2 300ºC

+ FGA 300ºCAs-Deposited

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)

As-Dep (10 kHz) As-Dep (100 kHz) As-Dep (1 MHz) FGA300 (10 kHz) FGA300 (100 kHz) FGA300 (1 MHz)

Figure 2.8 (a) Multi- frequency gate capacitance-voltage characteristics measured from an as-deposited W/GeOxNy/n-Ge capacitor stack (solid symbols) and after 300 °C anneal in N2 and then in forming gas (open symbols), and (b) the corresponding gate leakage-voltage measurements [44].

-3 -2 -1 0 1 2 310-10

10-8

10-6

1x10-4

10-2

100

As-Deposited

Leak

age

Cur

rent

(A

/cm

2 )

Gate Voltage (V)

After N2 300ºC

+ FGA 300ºC

(a)

(b)


25

Capacitance-voltage (C-V) characteristics were measured on these GeOxNy MOS

capacitors using the HP4275A multi- frequency LCR meter. Since for most of these

samples the amount of frequency dispersion in accumulation was negligible, we extracted

the equivalent capacitance-based SiO 2 thickness (EOT) from the 100 kHz C-V data. Fig.

2.8(a) shows the bi-directional C-V measurements on a typical W/GeOxNy/n-Ge capacitor

(grown by RTO at 600 °C for 5 sec followed by RTN at 600 °C for 2 min and without

PDA) before and after thermal anneals. After the thermal anneals at 300 °C (in N2 and

then in forming gas for 30 min each), both the EOT and C-V hysteresis (beginning at

inversion) increased slightly from 3.25 nm to 3.45 nm and 25 mV to 35 mV respectively;

the interface trap level density, Dit, determined using the Terman method [47] was shown

to reduce from 8 × 1012 cm-2 eV-1 to 3 × 1012 cm-2 eV-1. The kinks that showed up near

inversion in lower frequency scans suggest the presence of slow interface states even

after various thermal anneals. Moreover, a distinct positive flat-band voltage (VFB) shift

of about 0.8 V can be seen which will be further discussed in the later sections. Through

the measurements on all the MOS capacitors, we have demonstrated that this GeOxNy

could in fact be scaled from an EOT of 11.6 nm to 1.9 nm without suffering from the gate

leakage induced C-V distortion [48].

Also shown in Fig. 2.8(b) is the corresponding gate leakage density as a function

of voltage bias for both gate and substrate injections measured using the HP4155A

semiconductor parameter analyzer. The reduction in gate leakage could be attributed to

the modification of the Dit level after the thermal anneals. In addition, the accumulation

leakage level (at positive gate voltage bias) is comparable to the inversion leakage (at

negative gate voltage bias), a symmetric leakage behavior that contrasts the experience

on Si MOS capacitors in which the inefficient carrier generation in inversion usually

gives a substantially lower leakage than in accumulation. This behavior could be

explained by the three order of magnitude higher intrinsic carrier concentration, ni, in Ge

than in Si. Enough carriers for inversion gate leakage could then be provided by thermal

generation within the depletion region. Finally, the reason fo r the symmetric leakage is

governed by the similar gate tunneling probability in both biasing polarities.


26

To further investigate the effects of thermal anneals on capacitor VFB shift, after

each annealing treatment we recorded the VFB on many capacitors which are summarized

in Fig. 2.9. For reference purposes, the ideal VFB (assuming zero oxide fixed charge

density, Qf) and the theoretical VFB (assuming an arbitrary EOT of 4.0 nm and Qf of 1012

C/cm2) are also included.

On the as-deposited capacitors, a positive VFB shift of 0.6-0.8 V could be

measured after an initial 300 °C anneal in N2. On these treated samples, a subsequent

forming gas anneal at 300 °C only increased the VFB minimally; however, a succeeding

anneal at 400 °C in forming gas conversely raised the VFB by an extra 0.2-0.3 V. We

noticed that the theoretical VFB with small amount of oxide fixed charge (e.g. 1012 C/cm2)

was achieved experimentally only after thermal anneals at 300 °C or above. This could

be ascribed to the elimination of radiation- induced oxide trapped charges (Qot)

accumulated during W electron beam evaporation. On the annealed capacitors, we

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

Theoretical VFB

Ideal VFB

+ FGA

at 40

0ºC+ FGA

at 30

0ºC+ N2

at 30

0ºCAs-

Depos

ited

G

e M

OS

Cap

acit

ors

VFB

(V)

Without PDA With 600ºC PDA in O

2

Figure 2.9 Change of W/GeOxNy/n-Ge capacitor (with 3.0-5.0 nm EOT) VFB after subsequent anneals in either N2 or forming gas ambient at either 300 or 400 °C for 30 min. Solid and open symbols respectively represent GeOxNy samples without and with O2 PDA prior to W deposition. The ideal VFB (assuming zero Qf) and the theoretical VFB (assuming and EOT of 4.0 nm and Qf of 1012 C/cm2) are also included [44].


27

observe the characteristic positive VFB shift from the ideal value due to positive Qf

generation during RTN. Meanwhile, the O2 PDA at 600 °C was shown to reduce the

amount of Qf inside the GeOxNy layer, but that would also increase the dielectric EOT.

In order to evaluate the performance of these native GeOxNy dielectrics more

representatively, we have plotted in Fig. 2.10 their gate leakage density (normalized at 1

V above VFB) as a function of EOT. As a reference, the gate leakage current for thin SiO 2

on Si MOSFET [49] is also included. From both the as-deposited and annealed GeOxNy

dielectrics on Ge, an expected exponential increase of gate leakage with decreasing EOT

could be observed. In contrast to the apparently higher gate leakage (Fig. 2.8(b)) owing

to the negatively shifted VFB of the as-deposited samples (discussed in Fig. 2.9), the

normalized gate leakage shown in Fig. 2.10 of the annealed samples is in fact higher than

that of the as-deposited case with a possibly different leakage mechanism. For the sake

of future comparisons, only the normalized gate leakage of the annealed samples should

be chosen due to their acceptable VFB with a small amount of oxide fixed charge.

0 1 2 3 4 510 -9

10 -6

10 -3

100

103

GeOxN

y/Ge

(Annealed)

(As-Deposited)GeO

xN

y/Ge

SiO2/Si

Lea

kag

e C

urr

ent

@V

FB+1

V (

A/c

m2)

Equivalent SiO2 Thickness (nm)

Figure 2.10 W/GeOxNy/Ge capacitor gate leakage density as a function of EOT normalized at 1 V above flat-band voltage. All the data were taken on n-type Ge substrates. As a reference the leakage current level from thin SiO2 on Si MOSFET is also included [44].


28

2.2.5 Effects and Degree of Nitridation in Oxynitride

With the above solid understanding of the baseline GeOxNy dielectric, we have

further examined the effects of the degree of nitridation on the GeOxNy characteristics.

Fig. 2.11 depicts the normalized C-V characteristics of W-gate Ge MOS

capacitors with either GeO2 (grown by RTO at 600 °C for 30 sec) or GeOxNy dielectrics

(first formed by RTO at 600 °C for 5 sec followed by RTN at 600 °C for 2, 3, or 5 min

and without PDA). The drastic reduction in C-V hysteresis after the nitridation in

GeOxNy (from both Fig. 2.8(a) and Fig. 2.11(b)) proves its effectiveness to lower the

amount of interfacial electron trapping over the inferior quality GeO2 (Fig. 2.11(a)).

However, the degree of nitridation in GeOxNy should be well optimized before the real

benefit can be discerned. In an experiment where we began with an identical initial RTO,

we varied the degree of nitridation by changing the RTN soak time while keeping the

reaction temperature and NH3 flow rate the same. Fig. 2.11(b) captures the as-deposited

C-V characteristics measured at 10 kHz. By increasing the RTN soak time from 2 to 3

min, the kink near inversion shrank and the VFB shifted slightly towards the positive

direction. When the soak time was further extended to 5 min the inversion capacitance

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.50.0

0.2

0.4

0.6

0.8

1.0

W/GeO2/Ge

No

rmal

ized

Cap

acit

ance

C/C

ox

Gate Voltage (V)

RTO at 600ºC for 30 sec

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.2

0.4

0.6

0.8

1.0

W/GeOxN

y/Ge

No

rmal

ized

Cap

acit

ance

C/C

oxGate Voltage (V)

RTN 2 min RTN 3 min RTN 5 min

Figure 2.11 Measured W-gate Ge MOS capacitance normalized to the maximum accumulation Cox for (a) GeO2 dielectric, and (b) GeOxNy dielectrics with different degree of nitridation. C-V was measured on as-deposited samples at 10 kHz small-signal frequency.

(a) (b)


29

shot up to about half of the accumulation capacitance (Cox), an indication of efficient

carrier generation near the excessively nitrided GeOxNy/Ge interface. In addition, this

over-nitridation also led to increased interfacial charge trapping and positive oxide fixed

charge formation which may ultimately degrade channel mobility.

2.2.6 Oxynitride-Germanium Interface Trapped Charge

-1.0 -0.5 0.0 0.5 1.00.0

0.2

0.4

0.6

W/GeOxN

y/n-Ge

After FGA 300ºC

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)

Quasi-static C-V High-frequency C-V

-1.0 -0.5 0.0 0.5 1.00.0

0.2

0.4

0.6

W/GeOxN

y/p-Ge

After FGA 300ºC

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)

Quasi-static C-V High-frequency C-V

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.31011

1012

1013

1014

Ei

After FGA 300ºC

As-Deposited

EV

EC

W/GeOxN

y/n-Ge

Inte

rfac

e T

rap

Lev

el D

ensi

ty (

cm-2eV

-1)

Surface Potential (V)-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3

1011

1012

1013

1014

Ei

After FGA 300ºC

As-Deposited

EV

EC

W/GeOxN

y/p-Ge

Inte

rfac

e T

rap

Lev

el D

ensi

ty (

cm-2eV

-1)

Surface Potential (V)

Figure 2.12 (a) and (b) show the quasi-static and high-frequency (1 MHz) C-V characteristics measured on GeOxNy MOS capacitors with n- and p-type Ge substrates. The GeOxNy was identically grown on both substrates. (c) and (d) illustrate the extracted interface trap level densities (before and after a forming gas anneal) as a function of Ge surface potential using the combined low-high frequency capacitance method [51]. The sampled surface potential span was limited to flat-band-to-2? B.

(a) (b)

(c) (d)


30

The interface trap properties can be analyzed using a variety of capacitance

measurements. Among the classical techniques [50], the combined low-high frequency

capacitance method [51] is particularly simple as it eliminates the need for a theoretical

computation of the semiconductor surface capacitance and for a measurement of the

doping profile of the device. In order to extract Dit, both the n- and p-type Ge substrates

were identically cleaned and the GeOxNy was grown with the same recipe: RTO at 600

°C for 10 sec followed by RTN at 600 °C for 5 min and without PDA. On these

W/GeOxNy/Ge capacitors, quasi-static C-V measurement was carried out using the

HP4140B pA meter/DC voltage source through this relation

tV

ICQS ∂∂

= (2.1)

where CQS is the quasi-static capacitance, I is the measured current value, and tV ∂∂ is

the gate biasing voltage ramp rate; a biasing ramp rate of 0.1 V/sec was employed. The

uni-directional quasi-static and high-frequency (1 MHz) C-V characteristics are plotted

together in Fig. 2.12(a) and (b) from both n- and p-type Ge substrates. Without the loss

of generality, only the post- forming gas annealed data are shown. The more stretched-

out C-Vs on p-type Ge were primarily due to its substantially higher substrate dopant

concentration rather than an intrinsically higher Dit. By combining both the quasi-static

and high-frequency C-V measurements, Dit could be computed with

−−

−=

oxhf

oxhf

oxQS

oxQSoxit CC

CC

CC

CC

qC

D11

(2.2)

where q is the electronic charge and Chf is the high-frequency capacitance. Eq. (2.2)

gives Dit over only a limited range of the bandgap, typically from the semiconductor flat-

band condition to the onset of inversion (2? B).

Fig. 2.12(c) and (d) extracted Dit as a function of Ge surface potential before and

after a forming gas anneal at 300 °C for 30 min. The surface potential axes (x-axes) were

labeled with the convention that 0.0 V represents the mid-gap (Ei) position, a positive

potential samples the upper-half of the bandgap towards the conduction band edge (EC),

and a negative value explores the lower-half of the bandgap towards the valence band


31

edge (EV). The surface potential span plotted was in fact less than the Ge bandgap as we

were not mapping the Dit near both the EC and EV edges. The as-deposited Dit is about 3

× 1012 cm-2 eV-1 on both n- and p-type Ge substrates with relatively symmetric

distribution in both upper and lower-halves of the bandgap. After the forming gas anneal,

the Dit dropped by about a factor of three to roughly 1 × 1012 cm-2 eV-1 on both substrates.

On n-type Ge, the lowest Dit value obtained was 8.4 × 1011 cm-2 eV-1 and the

spread of the Dit level in both halves of the bandgap was rather even (Fig. 2.12(c)). On

the other hand, the post-annealed Dit map on p-Ge indicated a clear asymmetry that has a

considerably higher level within the upper-half (Fig. 2.12(d)). This important

observation may help to explain the asymmetric electron and hole mobility degradation in

Ge n- and p-channel MOSFETs with GeOxNy gate dielectric [18-19]. In the MOSFET

on-state, the surface inversion would govern the Fermi level to reside within the upper

half of the bandgap in p-type Ge for n-channel MOSFET (lower-half of the bandgap in n-

type Ge for p-channel MOSFET). Therefore, the n-channel carriers (electrons) mobility

would tend to degrade more due to Coulomb scattering [19] from the higher Dit near EC

on p-Ge (compared to the lower Dit near EV on n-Ge for hole scattering in p-channel

MOSFET).

2.3 High-κ Dielectrics by Atomic Layer Deposition 2.3.1 High-κ Dielectric Motivation and Selection

Even though the GeOxNy has been shown to be a stable and scalable dielectric

down to an EOT of 1.9 nm, a sub-1.0 nm EOT solution should still be sought for Ge

MOSFETs to advance beyond the 32 nm technology node [52]. Inspired by the recent

research successes to scale down the EOT in Si MOS devices with the use of high-κ

metal oxides [53-54], we have investigated the possibility of applying these high-κ

candidates to Ge as well [55]. Moreover, such integrations in Si usually inherit a lower-κ

SiOx interfacial layer between the high-κ film and Si substrate [54], which is currently the


32

major bottleneck to scale the EOT thinner than ~ 1.3 nm (Fig. 2.13). On the contrary, the

thermodynamic instability of GeOx may permit a true high-κ gate stack on Ge without the

performance limiting lower-κ interfacial layer and thus break through the EOT scaling

bottleneck.

2003 2006 2009 2012 2015 20180.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

EO

T w

.r.t.

SiO

2 (n

m)

Year of Production(HP Physical Gate Length)

102

103

104

No known solution

(7nm)(10nm)(14nm)(20nm)(28nm)(45nm)

Gate L

eakage L

imit (A

/cm2)

Figure 2.13 High performance logic technology EOT target and the corresponding gate leakage density limit as a function of technology generation specified in the ITRS 2003 Edition [52].

Figure 2.14 Binary phase diagrams for (a) Y2O3-GeO2 and (b) La2O3-GeO2 systems [56].

(a) (b)


33

Various high-κ material candidates including metal germanates (MGexOy) and

metal oxides (MOx) were considered from the perspective of their thermodynamic

stability in contact with Ge. Several stable MGexOy were first identified from the binary

phase diagrams on different two-metal-oxide systems [56]. For instance, stable yttrium

germanate (Y4GeO8, Y2GeO5, and Y2Ge2O7) as well as lanthanum germanate (La2Ge3O9

and La2Ge2O7) phases could respectively be found from the yttrium oxide-germanium

oxide (Y2O3-GeO2) and lanthanum oxide-germanium oxide (La2O3-GeO2) systems (Fig.

2.14). Nonetheless, due to their inaccessibility in our laboratory, we then limited our

study on the common MOx high-κ candidates for Si and their application to Ge. Based

on the thermodynamic analysis using a pseudo-ternary phase diagram, the

thermodynamic stability of zirconium oxide (ZrO2) and hafnium oxide (HfO 2) with

respect to solid state reaction with Ge was predicted [57] as illustrated in Fig. 2.15.

This thermodynamic calculation was done at the normal ALD reaction

temperature and the existence of a tie line in Fig. 2.15 between ZrO2 and Ge resulted

from the large formation energy of ZrO2. Therefore, it is theoretically viable to obtain an

interfacial layer- free ZrO2 on Ge gate stack with the conditions that ALD could occur on

a native oxide-free Ge surface and there should not be any significant Ge oxidation

during the ALD reaction. Likewise, a similar thermal stability of HfO 2 on Ge was

predicted on an Hf-Ge-O ternary system at the same ALD reaction temperature.

Ge Zr

O

ZrO2 GeO2

ZrGe ZrGe2 Zr2Ge

ZrGeO4

Figure 2.15 Calculated Zr-Ge-O ternary phase diagram at 600 K [57].


34

To be the successful MOS dielectric candidates, their electrical robustness also

needs to be guaranteed. First, their κ-values were extracted by measuring the EOT from

a series of Si MOS capacitors with different MOx physical thickness [58]. The high

dielectric permittivity of ALD ZrO2 (κ = 29) and ALD HfO 2 (κ = 17) is responsible for

their effective leakage suppression over SiO2 at the same EOT. Next, the energy band

alignment at the MOx/Ge interface was determined using internal photoemission (IPE).

On the HfO2 prepared by metallo-organic chemical vapor deposition (MOCVD) on NH3

treated Ge surfaces followed by an optional PDA in O2, internal photoemission of

electrons and holes from Ge into HfO 2 was applied [59] to construct the interface energy

band diagram as excerpted in Fig. 2.16. On the sample without PDA, the ∆EC and ∆EV at

the interface were respectively found to be 2.0 and 3.0 eV, which promise a good

dielectric performance of HfO 2 on Ge. However, the ∆EV is reduced by ~1 eV after the

optional PDA, suggesting that GeOx formation should be prevented during high-κ gate

stack formation. In the same study, the HfO 2/Si interface ∆EC was estimated to be

around 2.0 eV as well [59]. To summarize, both ZrO2 and HfO2, as high-κ candidates for

futuristic Si MOS applications, should also be attractive and applicable to Ge devices

from both thermodynamic and electrical perspectives.

Figure 2.16 Energy band diagrams of the (left) Ge/HfO 2 and (right) Ge/GeOx/HfO2 structures inferred from the IPE experiments. The measurement error of the barrier height determination is ±0.1 eV [59].


35

2.3.2 Atomic Layer Deposition Process for High-κ Dielectric

The high-κ dielectric materials used in this study were deposited in a home-built

cold-wall high vacuum base pressure ALD system (Fig. 2.17(a)) [57]. Among high-κ

deposition techniques, ALD is particularly attractive as a method for preparing ultrathin

MOx layers with excellent electrical characteristics and near-perfect film conformality

because of the layer-by- layer nature of the deposition kinetics [60]. The typical ALD

process was performed at 300 °C, using alternating surface-saturating reactions of H2O

Turbo Pump

Rotary Pump

Turbo Pump

Diaphram Pump

ZrC

l4

HfC

l4

Pump

Throttle Valve

Loadlock

Main Chamber

Carrier Gas (N2)

MF

C

Exhaust

H2O

MF

C

MF

C

MFC

Turbo Pump

Rotary Pump

Turbo Pump

Diaphram Pump

ZrC

l4

HfC

l4

Pump

Throttle Valve

Loadlock

Main Chamber

Carrier Gas (N2)

MF

CM

FC

Exhaust

H2O

MF

C

MF

CM

FC

MFC

MFC

Figure 2.17 (a) Schematic diagram of the ALD system, and (b) the ALD reaction mechanism [57].

ZrCl4/HfCl4 (g)

Substrate

ZrCl4/HfCl4 (g)

Substrate Substrate

Saturated adsorption

Substrate

Saturated adsorption

Substrate

H2O (g)HCl (g)

Substrate

H2O (g)HCl (g)

Substrate

ZrO2/HfO2 (s)

Substrate

ZrO2/HfO2 (s)

(a) -

(b)


36

and metal tetrachloride (MCl4) [57]. Each precursor was pulsed for 2 sec and N2 purging

was followed for 30 and 60 min after each H2O and MCl4 pulse, respectively. The base

pressure of the system was around 5 × 10-8 Torr and the process pressure was maintained

at 0.5 Torr during ALD.

2.3.3 Atomic Layer Epitaxy of Zirconium Oxide on Germanium

The starting substrates used for ALD of ZrO2 were (100) and (111) oriented n-

type Ge wafers with a net background dopant concentration of ~ 7 × 1015 cm-3 at room

temperature. The substrates were first cleaned by HF vapor exposure, evaporated from a

concentrated (49%) HF acid, for 1 min to remove the native oxides and immedia tely

loaded into the ALD system.

Contrary to the ALD experience on Si, ALD of ZrO2 films on both Ge(100) and

Ge(111) exhibited local epitaxial growth without a distinct interfacial layer [61], as

shown in the cross-sectional high-resolution transmission electron micrographs (HR-

TEM) from Fig. 2.18(a) and (b). This absence of interfacial oxides was also confirmed

with sputtered depth profile XPS analysis [57, 61]. The thermodynamic stability for this

interfacial layer- free ZrO2 on Ge substrate is plausible because of the more negative

Gibbs free energy of ZrO2 formation (-1135 kJ/mol at 600 K) compared to that of GeO2

ALD-ZrO2

Ge (111)

(c)

ALD-ZrO2

Ge (100)

Pt

Figure 2.18 Cross-sectional HR-TEM micrographs along the <110> zone-axis of (a) Pt/5.5 nm ZrO2/Ge(100), and (b) 6.8 nm ZrO2/Ge(111) [61].

(a) (b)


37

(-610 kJ/mol at 600 K) as discussed in Section 2.3.1. Even though the reformation of

GeOx on HF-treated Ge surface prior to the ALD process is largely possible (as in the

case of ALD of MOx on Si), it could be easily dissociated and/or dissolved in H2O during

the subsequent ALD steps. Owing to the large lattice mismatch (~ 10%) between the

tetragonal ZrO2 and Ge, a significant areal density of interfacial dislocations can be seen

in the cross-sectional image in Fig. 2.18. This phenomenon is schematically illustrated in

Fig. 2.19 where there exists an extra atomic plane out every other ten within the ZrO2

layer.

The epitaxial relationship between the ZrO2 film and Ge substrate was further

verified using electron diffraction analysis and plan-viewing TEM imaging (Fig. 2.20).

Indexing of electron diffraction patterns obtained during electron microscopy indicates

that the ALD grown ZrO2 film is quite likely to be in tetragonal phase [57, 61]. Due to

the large lattice mismatch, local epitaxial growth generated numerous distorted Moiré

fringes, as shown in the plan-view images (Fig. 2.20(a) and (c)). The mosaic spread of

the epitaxial film orientation also manifests itself in a distortion of diffraction spots seen

in the electron diffraction patterns (Fig. 2.20(b) and (d)). The (100) Ge // (100) ZrO2 and

[100] Ge // [100] ZrO2 epitaxial relationship is observed and the existence of an extra

ZrO2

<110> <001>

Ge

Interfacial dislocations

ZrO2

<110> <001>

Ge

Interfacial dislocations

Figure 2.19 Schematic diagram showing the epitaxial relationship and the interfacial dislocations for the sample illustrated in Fig. 2.18 (a) [57].


38

ZrO2 (111) atomic plane per every ten planes (Fig. 2.18(a)) hints that the compressive

misfit strain of the ZrO2 film is almost fully relaxed by these misfit dislocations. On Ge

(111) substrate, a similar (111) Ge // (111) ZrO2 and [111] Ge // [111] ZrO2 epitaxial

correlation was obtained as well.

MOS capacitors were subsequently fabricated on these epitaxial ZrO2 films by

electron beam evaporation of about 50 nm platinum (Pt) through a shadow mask to form

gate electrodes of various sizes. Al was then evaporated on the substrate backside to

reduce the sample contact (and series) resistance. An optional forming gas anneal was

carried out for 30 min at 400 °C on the completed Pt/ZrO2/Ge capacitors.

(a)

(c)

Figure 2.20 (a) Bright- field plan-view image of the 5.5 nm ZrO2/Ge(100), and (b) selective area diffraction pattern showing the corresponding epitaxial relationship. (c) Bright- field plan-view image of the 6.8 nm ZrO2/Ge(111), and (b) selective area diffraction pattern showing the corresponding epitaxial relationship [57, 61].

Cross-sectional HR-TEM micrograph along the <110> zone-axis, and (d) bright- field

(b)

(d)


39

C-V characteristics were measured on these ZrO2 MOS capacitors using the

HP4284A precision LCR meter. As depicted in Fig. 2.21(a) and (b), a significant amount

of frequency dispersion and C-V hysteresis were observed on both Ge (100) and Ge (111)

substrates. As indicated by the positive C-V shift upon sweeping from inversion to

accumulation and back to inversion, there exists a substantial interfacial trapping of

electrons injected from the n-type Ge substrates on the order of ~ 3 × 1012 cm-2. Both the

frequency dispersion and electron trapping are believed to originate from either the large

areal density of interfacial dislocations (~ 7 × 1012 cm-2) due to the relatively large lattice

-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

2.5

3.0

(EOT @ 10 kHz = 1.28 nm)Pt/5.5 nm ZrO

2/Ge(100)

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)

10 kHz 100 kHz 800 kHz

-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

2.5

3.0

(EOT @ 10 kHz = 1.90 nm)Pt/6.8 nm ZrO

2/Ge(111)

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)


(a) (b)

Figure 2.21 Multi- frequency gate capacitance-voltage characteristics measured from (a) a Pt/ZrO2/n-Ge(100) capacitor after forming gas anneal and (b) an as-deposited Pt/ZrO2/n-Ge(111) capacitor, and (c) their corresponding gate leakage-voltage measurements [57, 61].

-3 -2 -1 0 1 2 310-10

10-8

10-6

1x10 -4

10-2

100

Pt/5.5 nm ZrO2/Ge(100)

Pt/6.8 nm ZrO2/Ge(111)

Leak

age

Cur

rent

(A/c

m2 )

Gate Voltage (V)

(c)


40

mismatch or a very high Dit owing to the intrinsic differences in bonding coordination

across the chemically-abrupt ZrO2/Ge interface. In addition, the inversion capacitance

goes up in lower frequency scans, which could be explained either by an excessive

impurity diffusion from or through the ZrO2 film into Ge substrate (in the absence of an

interfacial barrier) or by carrier generation from the slow states due to interfacial

dislocations. Better engineering of the interface is certainly required to reduce the

interfacial dislocation density and thus to improve MOS electrical properties.

Also shown in Fig. 2.21(c) is the corresponding gate leakage density as a function

of voltage bias for both gate and substrate injections measured using the Keithley 230

programmable voltage source and 6512 programmable electrome ter. Even with the

presence of large number of interface defects and grain boundaries, the measured gate

leakage on the Ge samples is very low, a level that is equivalent to a ZrO2 on Si gate

stack having a much larger EOT and similar physical ZrO2 thickness. This remarkably

low leakage characteristic suggests that other crystalline MOx with closer lattice match to

Ge could be employed for high-κ epitaxy on Ge for MOS applications. For instance,

candidates including epitaxial CeO2 [62] and crystalline BaTiO 3 [63] have been

experimentally demonstrated on Ge.

2.3.4 Atomic Layer Deposited Zirconium Oxide on Differently

Prepared Germanium Surfaces

The ALD reaction on differently prepared substrate surfaces could yield high-κ

films with various microstructures and qualities. For example, the uneven nucleation of

ALD high-κ on non-hydroxylated surfaces like HF-last Ge (as discussed in Section 2.3.3)

and HF-last Si [64] could give poor electrical properties. Different Ge surface

passivations were prepared prior to the ALD of ZrO2 in this experiment to study the

respective effects and electrical characteristics.

The ALD of ZrO2 on Ge was first studied on three different types of surface: (i)

HF vapor etched, (ii) DI water rinsed, and (iii) chemical oxide kept. The former two

preparations were largely intended to produce a non-hydroxylated Ge surface while the


41

latter one was designed to provide surface hydroxylation for the ALD reaction. The HF

vapor etch was the same as described in Section 2.3.3 while the chemical oxides were

those remaining on the surface after chemical treatments from the wafer vendor. DI

water rinsing was used to dissolve the solub le native oxide that was examined to be the

dominant species on as-received wafers by XPS. To optimize the dwell time in DI water

for minimum resultant surface roughness, atomic force microscopy (AFM) was used to

track the root-mean-square roughness (Rrms) as highlighted in Fig. 2.22 [65].

Starting with the as-received bare substrate, the initial peak in Rrms (0-60 sec) was

due to partial and then complete removal of the soluble native oxide. Inferred from the

experience on Si [66-68], the dissociative adsorption of H2O at room temperature on the

Ge surface is believed to preferentially form a GeOH surface intermediate, which could

lead to increased oxidation (and Rrms) with increasing rinse time (> 60 sec). The optimal

DI water dwell time employed in the subsequent experiments is 1 min.

MOS capacitors were fabricated on (100) oriented n-type Ge wafers with a net

background doping concentration of ~ 7 × 1015 cm-3 at room temperature. The three

different surface preparations aforementioned were applied prior to the ALD of ~ 5.5 nm

ZrO2. Various sizes of 50 nm thick Pt gate electrode were formed by electron beam

evaporation through a shadow mask, and subsequently, Al was evaporated on the wafer

1 10 100 10000.0

0.1

0.2

0.3

0.4

CZ Si [66]

Epi Si [66]

Bare

RM

S R

ough

ness

(nm

)

Rinse Time (sec)

Figure 2.22 Ge surface Rrms from AFM as a function of DI water rinse time [65]. The Rrms values from both epitaxial and Czochralski Si wafers were also included.


42

backside to reduce the sample contact (and series) resistance. Finally, a forming gas

anneal was carried out for 30 min at 400 °C on the completed Pt/ZrO2/Ge capacitors.

The measured C-V characteristics, from the HP4284A, of ALD ZrO2 on both non-

hydroxylated (solid symbols in Fig. 2.23(a) and (b)) and hydroxylated (open symbols in

Fig. 2.23(c)) Ge surfaces are mostly similar with huge frequency dispersion, large C-V

hysteresis, and abnormal inversion behavior. The primary reasons for the electrical

inferiorities are believed to stem from the poor interfacial bonding configuration (with

lots of dangling bonds) and/or the diffusion of metal impurities from or through the ZrO2

film into Ge substrate (in the absence of an interfacial barrier).

-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

2.5

3.0

(EOT @ 10 kHz = 1.51 nm)Pt/ZrO

2/Chem Ox-Ge

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)


-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

2.5

3.0


2/HF Vapor-Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)


-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

2.5

3.0


2/DI Water-Ge

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)


(a) (b)

Figure 2.23 Multi- frequency gate capacitance-voltage characteristics measured from post- forming gas anneal Pt/5.5 nm ZrO2/n-Ge(100) capacitors with various starting Ge surfaces: (a) HF vapor etched, (b) DI water rinsed, and (c) chemical oxide kept.

(c)


43

The HF vapor etched sample delivers the smallest EOT amongst the identically

deposited samples, which suggests its effectiveness in removing the surface (interfacial)

oxide. On the DI water rinsed samples with different physical thickness of ALD ZrO2,

cross-sectional TEM images disclosed no apparent epitaxial relationship [57], a result

that could be attributed to the inefficacy of DI water rinsing in a complete GeOx removal

prior to the ALD reaction. This also explains the larger EOT value on the DI water

rinsed sample (Fig. 2.23(b)) than the HF vapor etched counterpart (Fig. 2.23(a)).

Additionally, the sample with chemical oxide kept (Fig. 2.23(c)) should in principle have

an even larger EOT. Perhaps due to its relatively unstable nature, this chemical oxide

may be largely removed during the subsequent ALD steps, producing similar behavior to

that of the DI water rinsed sample.

Fig. 2.24 shows the gate leakage density of these ZrO2/Ge capacitors as a function

of voltage bias for both gate and substrate injections using the Keithley 230 and 6512.

Among the Ge capacitors, the leakage measured from the non-hydroxylated samples

(solid symbols) scales with the corresponding EOT value. The hydroxylated sample

(open square symbol) shows a higher leakage even with a larger EOT, which could be

attributed to the relatively poor electrical quality GeOx interfacial layer. Compared to the

G

-3 -2 -1 0 1 2 310-10

10-8

10-6

1x10 -4

10-2

100

Pt/ZrO2/HF Vapor-Ge

Pt/ZrO2/DI Water-Ge

Pt/ZrO2/Chem Ox-Ge

Pt/ZrO2/Chem Ox-Si

Leak

age

Cur

rent

(A/c

m2 )

Gate Voltage (V)

Figure 2.24 Gate leakage-voltage measurements from Pt/5.5 nm ZrO2/n-Ge capacitors with different Ge surface preparations. Also included is the leakage reference from a Pt/5.5 nm ZrO2/chemical oxide/Si capacitor [57].


44

Si reference with an identical ZrO2 physical thickness (open triangle symbol), a slightly

higher leakage is observed in the Ge chemical oxide sample (open square symbol) that

again indicates the importance of a good quality interfacial layer. Nonetheless, the

notably low leakage at small EOT from these Ge capacitors reveals the promise of high-κ

dielectric incorporation in MOS applications.

2.3.5 Atomic Layer Deposited Hafnium Oxide on Differently Prepared

Germanium Surfaces

As another leading high-κ dielectric candidate, we also studied the ALD HfO 2

reaction and resulting film quality on assorted Ge surfaces with and without

hydroxylation. From the ALD ZrO2 on Ge results presented in the last section, we

learned that GeOx alone may not be a stable surface during the ALD process employed in

this research. Inspired by the high quality GeOxNy/Ge interface discussed in Section 2.2,

we have investigated the possibility of applying GeOxNy surface hydroxylation prior to

the ALD of HfO 2 on Ge.

The ALD of HfO2 on Ge was examined on five different types of surface: (i) CHF

cleaned (as described in Section 2.2.3), (ii) DI water rinsed, (iii) chemical oxide kept, (iv)

thick GeOxNy, and (v) thin GeOxNy. The first two Ge surfaces are hydrophobic while the

last three are hydrophilic. The thick GeOxNy was prepared by conventional furnace

oxidation of CHF cleaned Ge at 500 °C for 2 min followed by RTN at 600 °C with 1 min

soak time in NH3. The thin GeOxNy was prepared by RTN of CHF cleaned Ge at 600 °C

with 1 min soak time in NH3.

Figure 2.25 Cross-sectional HR-TEM images of ~ 4.5 nm ALD HfO 2 on (a) CHF

cleaned, (b) chemical oxide kept, and (c) thin GeOxNy Ge surfaces.

HfO2

Ge

GeOxNy HfO2

Ge

HfO2

Ge

GeOx

(a) (b) (c)


45

Interfacial microstructures on selected ALD HfO 2 on Ge samples were inspected

using TEM (Fig. 2.25). The ALD HfO 2/CHF cleaned Ge surface has negligible

interfacial oxide (Fig. 2.25(a)) similar to the ALD ZrO2 experience described in Section

2.3.4. The chemical oxide kept sample (Fig. 2.25(b)) contains thinner interfacial GeOx (~

0.8 nm) than the usual interfacial SiO x in high-κ/Si gate stack [57], with greater

interfacial roughness possibly associated with either an uneven dissociation of GeOx or a

partial reaction between HfO 2 and GeOx during the ALD process. From Fig. 2.25(c), the

thin interfacial GeOxNy is found to be quite uniform with thickness of ~ 1.1 nm.

MOS capacitors were fabricated on (100) oriented n-type and p-type Ge

substrates, with a net background concentration of ~ 7 × 1015 cm-3 and ~ 3 × 1017 cm-3,

respectively at room temperature. Surface treatments including CHF cleaning (i), DI

water rinsing (ii), as well as Ge oxynitridations (iv) and (v) were employed prior to ALD

of ~ 4.5 nm HfO2. Various sizes of 50 nm thick Pt gate electrode were formed by

electron beam evaporation through a shadow mask, and subsequently, Al was evaporated

on the wafer backside to reduce the sample contact (and series) resistance.

2.5

2.7

2.9

3.1

3.3

3.5

EO

T w

.r.t.

SiO

2 (n

m)

0

40

80

120

160

ThinGeOxNy

ThickGeO

xN

y

DI waterrinsed

CHFcleaned

No

rmalized

C-V

Hysteresis (m

V)

Figure 2.26 EOT with respect to SiO 2 and normalized hysteresis estimated from bi-directional C-V sweep from Pt/HfO 2/n-Ge with various surface preparations prior to ALD [65]. The series resistance correction [69] was applied before parameter extractions using both the 100 kHz and 800 kHz scan data. The C-V hystereses were normalized to the same EOT value of the thin GeOxNy sample.


46

Multi- frequency C-V characteristics were measured using the HP4284A on the

Pt/HfO2/n-Ge capacitors with various surface preparations prior to ALD reaction. Since

the HfO2 film on different samples were identically deposited at the same time with the

same number of ALD cycles, the variation in deposition conditions was minimized.

Presented in Fig. 2.26 are the EOT and the normalized C-V hysteresis beginning at

inversion. The series resistance correction [69] was first applied before the parameter

extractions. The corresponding hysteresis from each sample was normalized to the same

EOT value of the thin GeOxNy sample to account for the apparently smaller hysteresis on

thinner EOT sample. Among the surface hydroxylated samples, the inclusion of a thicker

GeOxNy interfacial layer intuitively produces a larger EOT value than a thinner one. On

those non-hydroxylated surfaces, the CHF cleaned sample offers a smaller EOT

compared to the DI water rinsed sample, indirectly suggesting that the combination of HF

and DI water cleaning is more effective to remove GeOx than DI water alone. On the

other hand, the C-V hysteresis obtained from different starting surface represents another

scenario. The incorporation of a GeOxNy interfacial layer delivers a reduction in the

amount of charge trapping (and thus hysteresis) versus ALD directly onto non-

hydroxylated Ge surfaces. The improvement may be attributed to improved ALD

nucleation on stable hydroxylated surfaces over the atomically clean Ge, which allows

locally epitaxial growth with a different microstructure [61].

-3 -2 -1 0 1 2 310-10

10-8

10-6

1x10 -4

10-2

100

Pt/HfO2/CHF cleaned-Ge

Pt/HfO2/DI Water rinsed-Ge

Pt/HfO2/Thick GeO

xN

y-Ge

Pt/HfO2/Thin GeO

xN

y-Ge

Leak

age

Cur

rent

(A/c

m2 )

Gate Voltage (V)

Figure 2.27 Gate leakage-voltage measurements from Pt/4.5 nm HfO2/n-Ge capacitors with different Ge surface preparation [65]. Solid and open symbols are used for non-hydroxylated and hydroxylated surfaces respectively.


47

Illustrated in Fig. 2.27 is the gate leakage density of these HfO 2/Ge capacitors as a

function of voltage bias using Keithley 230 and 6512. With either a gate or substrate

injection, the gate leakage for all the samples was similarly low. The sample with a thick

GeOxNy interfacial layer gave the lowest leakage, which is expected because of its larger

EOT. Compared to SiO 2 on Si in the same EOT range [70], the leakage current obtained

from the high-κ Ge MOS capacitors demonstrated about 103 to 105 times reduction.

Combining the accumulation EOT, C-V hysteresis, and gate leakage data, we found that

the optimal Ge MOS gate dielectric stack, for the processing methods investigated in this

work, was composed of ALD HfO 2 on a thin GeOxNy interfacial layer to generate

acceptable capacitors (Fig. 2.28). On both p- and n-type Ge substrates, the kinks that

showed up near inversion in lower frequency scans again suggest the presence of slow

interface states as observed in GeOxNy/Ge capacitors (Section 2.2.4). However, the

observed inversion capacitance increase in n-type Ge in lower frequency scans may be

due to excess carrier generation over that in p-type Ge. Alternatively, the presence of

negative Qf within the HfO 2/GeOxNy dielectric stack that causes n-type surface depletion

(except the capacitor active area) and supplies positive carriers for capacitor channel

inversion (depending upon the capacitor area) could cause the same effect [50].

To optimize the hydroxylation conditions for ALD of HfO 2 onto Ge, the

Pt/HfO2/GeOxNy/p-Ge capacitor electrical characteristics with different GeOxNy RTN

temperature were examined before and after a forming gas anneal (Fig. 2.29).

-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

(EOT = 2.03 nm)Pt/HfO

2/GeO

xN

y/p-Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)


-1.0 -0.5 0.0 0.5 1.0 1.50.0

0.4

0.8

1.2

1.6

(EOT = 2.66 nm)Pt/HfO

2/GeO

xN

y/n-Ge

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)


(a) (b)

Figure 2.28 Multi- frequency C-V characteristics measured from (a) Pt/HfO2/GeOxNy/p-Ge and (b) Pt/HfO 2/GeOxNy/n-Ge capacitors [65].


48

When the as-deposited C-V curves are compared (Fig. 2.29(a) and (b)), the 600

°C grown GeOxNy interfacial layers revealed almost no hys teresis and frequency

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

(EOT = 2.0 nm)As-Dep Pt/HfO

2/GeO

xN

y/Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)


RTN at 700°C

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

(EOT = 2.0 nm)As-Dep Pt/HfO

2/GeO

xN

y/Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)


(a)

Figure 2.29 Multi- frequency gate capacitance-voltage characteristics measured from as-deposited Pt/HfO2/GeOxNy/p-Ge capacitors with the GeOxNy grown at (a) 600 °C and (b) 700 °C for 1 min apiece. (c) and (d) are the measurements after a forming gas anneal at 300 °C for 30 min. (e) shows the corresponding gate leakage-voltage measurements.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

(EOT = 2.0 nm)FGA300 Pt/HfO

2/GeO

xN

y/Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)


-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

(EOT = 1.9 nm)FGA300 Pt/HfO

2/GeO

xN

y/Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)


RTN at 600°C

RTN at 600°C

(c)

(b)

RTN at 700°C

(d)

-3 -2 -1 0 1 2 310-10

10-8

10-6

1x10 -4

10-2

100

RTN at 600ºC (As-Dep) RTN at 700ºC (As-Dep) RTN at 600ºC (FGA300) RTN at 700ºC (FGA300)

Leak

age

Cur

rent

(A/c

m2 )

Gate Voltage (V)

(e)


49

dispersion compared to the 700 °C case. The higher RTN temperature degraded the

interfacial quality and triggered an inversion capacitance increase. This phenomenon is

the characteristic over-nitridation previously observed (Section 2.2.5) and is

fundamentally different from the abnormal inversion behavior due to metal impurity in-

diffusions (Section 2.3.3-3.3.4), which will shortly be discussed further. After a forming

gas anneal at 300 °C for 30 min, both the 600 °C and 700 °C capacitors showed increased

interfacial hole trapping (Fig. 2.29(c) and (d)) because of a possible de-passivation of the

weak Ge-H bonds formed during the NH3 nitridation. Contrary to the benign function of

hydrogen in passivating most of the SiO 2/Si interfacial dangling bonds, a balance should

be struck on its application to Ge MOS systems to maximize its benefits. The gate

leakage current densities of these HfO 2/GeOxNy/Ge capacitors are recorded with both

gate and substrate injections (Fig. 2.29(e)). Even though major differences were

identified in their C-V characteristics, the gate leakage for all the samples was similarly

low and relatively independent of the nitridation condition.

Lastly, some physical characterizations of the GeOxNy films were carried out to

inspect their N content, chemical stability, and the impurity diffusion blocking capability.

XPS (Fig. 2.30(a) and (b)) was employed to calculate the N atomic concentration

in GeOxNy films grown on CHF cleaned Ge at various temperatures for 1 min. Fig.

38 36 34 32 30 28 26

Inte

nsi

ty (

a.u

.)

Binding Energy (eV)

Gen+

∆=3eV

Ge0+

700ºC

600ºC

500ºC

Ge(3d)

402 400 398 396 394

Inte

nsity

(a.u

.)

Binding Energy (eV)

700ºC

600ºC

500ºC

N(1s)

N

400 500 600 700 8000

10

20

30

40RTN in NH

3 for 60 sec

N/(N

+O+C

) (%

)

RTN Temperature (ºC)

(a) (b)

Figure 2.30 (a) Ge 3d XPS spectra, (b) N 1s XPS spectra, and (c) relative N atomic concentration from the GeOxNy films as a function of RTN temperature.

(c)


50

2.30(c) shows the relative concentration of N within the films including the surface

hydrocarbon layer formed during sample transfer in the air ambient. The relative N

content with respect to the sum of N plus carbon (C) and O was between 10 to 30% and

increased with the RTN temperature. In addition, the oxidized Ge 3d peak (Gen+ in Fig.

2.30(a)) shifted towards lower binding energy with increasing RTN temperature, which

suggests a gradual modification of the Ge bonding configuration.

Next, the chemical stability of the GeOxNy films was studied by dipping the

GeOxNy sample in either H2O for 2 min or 20:1 HF for 1 min (Fig. 2.31). After the N

incorporation into GeOx, the resultant GeOxNy film demonstrates a drastically reduced

solubility in H2O and enhanced chemical stability. On the other hand, this stabilized

GeOxNy film could be etched in HF solution − the standard SiO 2 etchant.

Analogous to the experience with silicon oxynitride (SiO xNy), the nitrogen

incorporation into the GeOxNy interfacial layer is expected to block the metal impurities

within the metal gate electrode/high-κ dielectric stack from diffusing into Ge substrate.

Medium energy ion scattering (MEIS) was chosen for such as investigation, which is a

lower energy version of Rutherford backscattering (RBS) in which the energy and

angular distributions of scattered ions are used to obtain detailed information about

atomic structure and composition within the top 5-20 nm of the sample [71]. About 4 nm

of HfO2 was deposited by ALD on two different Ge (100) surfaces: (i) chemical oxide

38 36 34 32 30 28 26

Inte

nsi

ty (a

.u.)

Binding Energy (eV)

20:1 HF etch

H2O etch

Ge(3d)

402 400 398 396 394

Inte

nsi

ty (a

.u.)

Binding Energy (eV)

20:1 HF etch

H2O etch

N(1s)

Figure 2.31 Ge 3d (left) and N 1s (right) XPS spectra on the GeOxNy film grown at 600 °C after either an H2O or HF etch.


51

kept and (ii) CHF cleaned followed by RTN at 600 °C with 1 min soak time in NH3.

MEIS analysis was then performed with a 100 keV proton beam in a double alignment so

as to reduce the contributions from the crystalline Ge substrate, allowing de-convolution

of spectra into contributions from the HfO 2 layer and Ge-containing underlayer and

substrate [72]. The incident ions were directed along the (111) plane and the scattered

ions were along the (100) plane with a scattering angle of ~ 125°. Quantitative depth

profiles for different species were extracted with a resolution of less than 0.5 nm in the

near-surface region.

Fig. 2.32 depicts the measured MEIS spectra and the ion scattering simulation

results from both samples. The overall shapes of both spectra were similar except for a

difference in the lower energy edge of the Hf signal as shown in the figure insets, which

corresponds to the interfacial layer under the HfO 2 film. On the chemical oxide kept

sample, a marked shoulder was observed which is likely due to an intermixing between

Hf and GeOx or large interface roughness even without under-going any post-deposition

80 85 90 95 1000

300

600

900

1200

Raw data fitting data

Energy (keV)

Ion

Yie

ld (

Co

un

ts)

80 85 90 95 1000

300

600

900

1200 Raw data fitting data

Ion

Yie

ld (

Co

un

ts)

Energy (keV)

94.5 95.0 95.5 96.0 96.5 97.0 97.5 98.00

100

200

300

400

500

600

Ion

Yie

ld (C

ou

nts

)

Energy (keV)

O Ge

Hf

94.5 95.0 95.5 96.0 96.5 97.0 97.5 98.00

100

200

300

400

500

600

Energy (keV)

Ion

Yie

ld (C

ount

s)

O Ge

Hf (a) (b)

HfO2

Ge(Hf)Ox

Ge

HfO2

GeOxNy

Ge

Figure 2.32 MEIS spectra with the simulation curves and the corresponding model structure of (a) HfO 2 on Ge substrate with chemical oxide kept and (b) HfO2 on CHF cleaned Ge substrate followed by RTN at 600 °C for 1 min in NH3 [72].


52

thermal treatment. In contrast, no significant amount of Hf atoms could be found inside

the interfacial GeOxNy within the MEIS detection limit (< 5 at.%), which is consistent

with the expected effectiveness of the GeOxNy interfacial layer in blocking Hf out-

diffusion from the HfO 2 dielectric into Ge substrates.

Combining both the electrical and physical characterization data, the insertion of a

GeOxNy interfacial layer is advantageous for producing high quality ALD high-κ

dielectric stacks on Ge for MOS applications, consistent with other reported high-κ

deposition results on Ge including MOCVD of HfO 2 [73]. Nevertheless, in order to offer

a sub-1.0 nm EOT using this technology, the scaling of the thin GeOxNy interfacial layer

has to be carefully studied [65].

2.4 High-κ Dielectrics by Ultraviolet Ozone Oxidation 2.4.1 Ultraviolet Ozone Oxidation Process for High-κ Dielectric

As an alternative high-κ dielectric deposition technique, the UVO process offers

advantages including very low processing temperature, low contamination levels, as well

as an in-situ gate electrode capping capability. In this technique, a thin metal (e.g. Zr)

film is first deposited by UHV direct current (DC) magnetron sputtering on the wafer

sample. The sample is then transferred and exposed to an in-situ oxidation chamber (Fig.

Figure 2.33 Schematic diagram of the UHV metal sputtering chamber with in-situ ultraviolet ozone oxidation capability to form MOx.

UHV sputtering chamber

UVO oxidation chamber


53

2.33) where high-purity oxygen (99.999%) and ultraviolet light from a mercury vapor

lamp (254 and 185 nm wavelengths) are introduced [74]. Interaction between the oxygen

and ultraviolet radiation produce atomic oxygen and ozone, both highly reactive species

that enhance oxidation kinetics of certain materials [75]. The oxidation was allowed to

proceed at 600 Torr O2 partial pressure and low temperature (~ 50 °C) for 60 min,

whereupon the ultraviolet lamp was turned off and the oxidation chamber was pumped

down and then vented. Due to the reactive nature of the metal precursor and the surface

GeOx instability, interfacial layer-free high-κ growth on Ge can possibly be achieved

using this technique as well.

2.4.2 Ultraviolet Ozone Oxidized Zirconium Oxide on Differently

Prepared Germanium Surfaces

The UVO process on differently prepared substrate surfaces yields high-κ films

with different microstructure and quality. The UVO of ZrO2 on Ge was studied on three

different types of surface: (i) chemical oxide kept, (ii) DI water rinsed, and (iii) HF vapor

etched. The surface GeOx on the first sample was intentionally kept while those on the

last two were stripped to compare their reactions with the precursor metals during the

UVO process. The DI water rinse and HF vapor etch were the same as described in

Section 2.3.4 and 3.3.3 respectively.

MOS capacitors were fabricated on (100) oriented n-type Ge substrates with a net

background concentration of ~ 7 × 1015 cm-3 at room temperature. The three different

aforementioned surface preparations were applied prior to UHV sputtering of ~ 2-3 nm

thick Zr films. The samples were then transferred to the loadlock and oxidized in-situ by

the room temperature ultraviolet ozone technique. Subsequently, the samples were

transferred back to the main chamber for UHV sputtering of ~ 50 nm Pt as the top

electrode layer. Various sizes of circular capacitor structure were then defined by optical

lithography and argon (Ar) ion sputter etch. No wafer backside Al was applied to this set

of experiments. Finally, a forming gas anneal was carried out for 30 min at 410 °C on

the completed Pt/ZrO2/Ge capacitors.


54

Multi- frequency C-V characteristics were measured using HP4275A on the

Pt/ZrO2/n-Ge capacitors with various surface preparations prior to UVO. On the

chemical oxide kept sample (Fig. 2.34(a)), a large C-V hysteresis (~ 0.3 V), slight

frequency dispersion, and relatively larger EOT were obtained. A possible source of

these artifacts is the inferior interfacial quality between the ZrO2 film and Ge substrate,

even though any remaining amount of unstable GeOx would be minimal due to the very

high oxygen solubility of the Zr precursor sputtered initially. Conversely, almost

negligible hysteresis, minimal frequency dispersions, as well as sub-1.0 nm EOTs were

achieved on those samples with the surface GeOx stripped intentionally (Fig. 2.34(b) and

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

2.0

4.0

6.0

8.0

(EOT @ 1 MHz = 0.48 nm)Pt/ZrO

2/HF Vapor-Ge

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)

100 kHz 1 MHz

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

2.0

2.5

3.0

(EOT @ 1 MHz = 1.49 nm)Pt/ZrO2/Chem Ox-Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)

100 kHz 1 MHz

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.0

1.0

2.0

3.0

4.0

5.0

(EOT @ 1 MHz = 0.84 nm)Pt/ZrO

2/DI Water-Ge

Gat

e C

apac

itan

ce (

µF/c

m2 )

Gate Voltage (V)

100 kHz 1 MHz

(a)

(b)

Figure 2.34 Multi- frequency gate capacitance-voltage characteristics measured from post- forming gas anneal Pt/ZrO2/n-Ge(100) capacitors with various starting Ge surfaces: (a) chemical oxide kept, (b) DI water rinsed, and (c) HF vapor etched [76]. All the EOT values are quoted before any quantum mechanical correction.

(c)


55

(c)). Among the two GeOx stripped samples, the HF vapor etched surface offers a

smaller EOT compared to the DI water rinsed surface which hints at the higher efficacy

of HF vapor over DI water in removing GeOx, a conclusion that is consistent with the

ALD ZrO2 on Ge (Section 2.3.4) and ALD HfO 2 on Ge (Section 2.3.5) experiences.

Also illustrated in Fig. 2.35 is the gate leakage density of these ZrO2/Ge

capacitors as a function of voltage bias for both gate and substrate injections using the

HP4155A. The chemical oxide kept sample (open symbol) gives the highest leakage

even with the largest EOT that implies the detrimental effect with the presence of

interfacial GeOx layer. The leakage measured from the oxide stripped samples (solid

symbols) however scales with their individual EOT level.

Nonetheless, for these ultrathin gate dielectrics, a precise electrical EOT

extraction is difficult due to the inherently high gate leakage. The EOTs reported here

were extracted directly from the measured accumulation capacitance without any

quantum mechanical (QM) correction [77] owing to the inaccessibility of a Ge model.

Attempts have been made to do some C-V modeling but none of them seem to be

appropriate for these Ge MOS capacitors. As an alternative measure, a combination of

physical and electrical EOT extraction was employed. The physical EOT was estimated

from the physical thickness of the dielectric stack (Fig. 2.36) using the approximate κ

value.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510 -4

10 -2

100

102

Pt/ZrO2/Chem Ox-Ge

Pt/ZrO2/DI Water-Ge

Pt/ZrO2/HF Vapor-GeLe

akag

e C

urre

nt (A

/cm

2 )

Gate Voltage (V)Figure 2.35 Gate leakage-voltage measurements from Pt/ZrO2/n-Ge capacitors with

different Ge surface preparation [76]. Open and solid symbols are used for chemical oxide kept and oxide stripped surfaces respectively.


56

From the cross-sectional HR-TEM image of the HF vapor surface etched sample,

the physical ZrO2 thickness is roughly 3.6 nm with an atomically flat ZrO2/Ge interface

(Fig. 2.36 (b)). Although these HR-TEM images are relatively insensitive to local

composition variations, the uniform image contrast between the Ge substrate and Pt

electrode suggests that the high-κ dielectric stack is free of any significant interfacial

GeOx layer between the ZrO2 film and Ge substrate. Compared with previous

observations of well-defined polycrystallinity in ZrO2 on SiO2 [78-79], the ZrO2 film

grown directly on Ge has an amorphous or, at most, partially microcrystalline nature.

Taking the κ value to be ~ 25 from the reported bulk value for the monoclinic phase of

ZrO2 [54], the calculated physical EOT is 0.56 nm. Combining both the electrical (Fig.

2.34(c)) and physical extractions together with the anticipated QM correction, the

representative EOT of the HF vapor etched sample is about 0.5-0.7 nm. Similar

extraction on the DI water rinsed sample reveals a thicker EOT of 0.6-1.0 nm attributed

to a possible non-uniform removal of GeOx prior to the UVO process; this is also the

primary cause of a rougher ZrO2/Ge interface (Fig. 2.36(a)) even though this die lectric

stack is interfacial layer- free as well.

Correlating the previous thermodynamic calculation (Section 2.3.1), the sub-1.0

nm EOTs and very low C-V hystereses measured on the interfacial layer-free samples,

one could deduce that the absence of GeOx interfacial layer improves the MOS device

performance substantially. The implication of the electrical data is that improved

performance for high-κ on Ge can be obtained by complete elimination of the poor

Pt

ZrO2

Ge 30Å

Figure 2.36 Cross-sectional HR-TEM images of Pt/ZrO2/Ge capacitors with different starting Ge surfaces: (a) DI water rinsed and (b) HF vapor etched [76].

Pt

ZrO2

Ge 30Å

(a) (b)


57

quality and readily removed GeOx interfacial layer, followed by direct high-κ growth on

Ge.

Finally, the Ge MOS capacitor reliability and process variation on the HF vapor

etched sample have been evaluated [80]. Upon constant-current stressing for 200 sec

with about 664 C/cm2 of charges are being injected from the Ge substrate, only a small

VFB shift of 1.24 mV is observed. Device-to-device variation across the wafer die is

almost negligible from electrical measurements and device yield is close to 100%.

2.4.3 Zirconium Oxide-Germanium Interfacial Layer Identification

In order to explore the ultimate scalability of high-κ gate stacks on Ge, we would

like to understand whether it is technologically feasible to achieve an interfacial layer-

free high-κ film growth on Ge. For instance, the HR-TEM image from Fig. 2.36(b)

indicated apparently no interfacial layer between the UVO grown ZrO2 and HF vapor

etched Ge surface. However, conventional TEM is not well suited for identifying a GeOx

layer in this system due to the closeness in atomic number (Z) of Zr and Ge resulting in

poor image contrast. Instead we have employed synchrotron radiation photoemission

spectroscopy (SR-PES) to track the compositional variation within the dielectric stack

along the depth dimension using layer-by- layer removal technique.

The SR-PES technique used in this study shares the same basic physics as XPS

except that XPS uses x-rays from Al kα and magnesium (Mg) kα x-ray tubes as the light

source. The synchrotron radiation source is provided by the Stanford Positron Electron

Asymmetric Ring (SPEAR) located at the Stanford Synchrotron Radiation Laboratory

(SSRL). While the SPEAR storage ring was originally designed as a high-energy physics

colliding beam facility, it has been an important and effective source for synchrotron

radiation experiments. In brief, synchrotron radiation is a bright and collimated light

source. Radiation emitted from bending magnets and wigglers have a continuous energy

range from the infra-red to the hard x-ray portion of the spectrum. A monochromator

must be used to select light of certain photon energy, making synchrotron radiation a

widely tunable source [81].


58

The experiments were performed at Beam Line 8-1 (photon monochromator

energy range of 20-180 eV and photon flux spot size of 5 mm × 5 mm) at SSRL with the

analytical chamber base pressure kept at ~ 5 × 10-11 Torr (Fig. 2.37). The photoemission

spectra were measured with a PHI model 10-360 hemispheric capacitor electron energy

analyzer with the Omni Focus III small area lens mounted to the chamber with an angle

of 54°44’ (magic angle) with respect to the incoming photon beam direction [81]. The

analyzer has a multi-channel detector that allows a detectable kinetic energy (KE) range

of 0-1000 eV with energy resolution of 0.05 eV. The photoelectron take-off angle is set

normal to the sample surface to maximize the depth information.

The sample analyzed by SR-PES is the same UVO grown ZrO2 on HF vapor

etched Ge surface sample, as described in Section 2.4.2, yet without the in-situ sputtered

Pt electrode layer. The physical thickness of the ZrO2 film is expected to be around 3.5

nm (similar to the sample shown in Fig. 2.36(b)). This ultrathin ZrO2 film was then

etched in a layer-by-layer fashion with wet chemistry while numerous SR-PES spectra

Load Lock

hυ

Sample

LEED

Cs doser

Thermocouple

Ar

Leak Valve for O2

Analyzer

Load Lock

hυ

Sample

LEED

Cs doser

Thermocouple

Ar

Leak Valve for O2

Analyzer

Figure 2.37 Schematic diagram of the SR-PES system. A hemispherical analyzer is mounted at the magic angle (54°44’) with respect to the incoming photon beam. LEED optics, thermal couple, Cs doser are also available for other analysis [81].


59

were taken between the etches. This layer-by- layer etch was carried out inside the Ar

purged glove bag attached to the analytic chamber loadlock (Fig. 2.37) using 100:1 HF

solution. In order to guarantee the wet etched ZrO2 surfaces are smooth and free of

pinholes, AFM was used [82] to monitor surface morphology after each HF etch and

extracted the Rrms values as a function of etch time (Fig. 2.38). The Rrms level had been

maintained around 0.15 nm (< half of a monolayer) roughly before the entire ZrO2 layer

was removed, beyond which the roughness raised up owing to the HF induced Ge surface

roughening. These results indicate that this wet etching technique could provide pinhole-

free surfaces throughout the layer-by- layer removal.

0 5 10 15 20 250.0

0.1

0.2

0.3

RM

S R

ough

ness

(nm

)

Etch Time (sec)

Figure 2.38 ZrO2/Ge sample surface Rrms from AFM as a function of 100:1 HF solution etch time [82].

Figure 2.39 Sub-shell photoelectron cross-sections of (a) Ge and (b) Zr [83].

101

100

10-1

10-2

200 4000

Cro

ss S

ecti

on

(M

bars

)

Photon Energy (eV)

Ge 3d

Ge 3p

101

100

10-1

10-2

200 4000

Cro

ss S

ecti

on

(M

bars

)

Photon Energy (eV)

Ge 3d

Ge 3p

101

100

10-1

10-2

200 4000

Cro

ss S

ecti

on

(M

bar

s)

Photon Energy (eV)

Zr 4p

Zr 4s

101

100

10-1

10-2

200 4000

Cro

ss S

ecti

on

(M

bar

s)

Photon Energy (eV)

Zr 4p

Zr 4s

(a) (b)


60

In order to maximize the SR-PES signals from the sample, the desired core- level

Ge peaks should be picked for inspection based on system capability while avoiding any

possible interference with Zr peaks. The system photon monochromator energy range

determines the detectable binding energy (BE) peaks to be either the Ge 3d (BE of 29.2-

29.8 eV) or Ge 3p (BE of 120.8-124.9 eV) peaks. After that, these sub-shell

photoelectron cross-sections were compared [83]. Between the Ge 3d and Ge 3p sub-

shell photoelectrons, the former has much larger cross-sections (Fig. 2.39(a)) and was

therefore chosen. Unfortunately, the Zr 4p peak also has a similar BE (27.1-28.5 eV) as

the Ge 3d peak whose PES signals would interfere with each other. Subsequently, their

photoelectron cross-sections were cross compared (Fig. 2.39(a) and (b)) which reveal an

acceptable order of magnitude larger photoelectron cross-section from the Ge 3d over the

Zr 4p for our purpose.

(a)

(b)

50 60 70 80 90 100

Inte

nsity

(a.

u.)

Kinetic Energy (eV)

0s

2~3s5~6s9~10s

10~12s

12~14s

16~18s

22~24s

Bare Ge

Etch time50 60 70 80 90 100

80 85 90 95

Inten

sity (a.u.)

Kinetic Energy (eV)

Inte

nsity

(a.u

.)

KE (eV)

Heat Cleaned Ge

Figure 2.40 (a) Ensemble evolution SR-PES spectra as a function of ZrO2/Ge etch time including both core- level and VB spectra taken at photon energy of 100 eV. (b) Magnified valence band spectra of (a) [84].

Core-Level

Valence Band


61

Capturing the ZrO2/Ge surface evolution throughout the layer-by- layer removal

process, numerous SR-PES of both core- level and valence band (VB) peaks were

performed [84] and the ensemble spectra are shown in Fig. 2.40(a). Since the etch

duration on the order of seconds is difficult to control, the data from two samples are

interleaved together without compromising the general trend. With input photon energy

of 100 eV, the core- level elemental Ge 3d (Ge0+) peaks showed up around KE of 65.6 eV

owing to energy offset of ~ 5 eV from the PES system. Qualitatively, the VB spectra

(KE of ~ 83-92 eV) could be utilized as species identifiers during the layer-by- layer

removal (Fig. 2.40(b)). Beginning with 0 sec etch time, the VB peak at KE of 90 eV

represents some un-oxidized surface features probably originated from surface

contaminants rather than un-oxidized Zr precursor. After an initial ZrO2 etch for 2-3 sec,

the surface was cleaned and gave rise to the characteristic ZrOx VB peak which is

relatively broad (KE of 86-88 eV) and more rectangular [85]. The ZrOx signature

remains about the same until after 9-10 sec of etch, beyond which an addition of GeOx

identity on top of ZrOx signals is discerned from the much sharper peak at about the same

energy. This is a clear evidence of the existence of bonding configuration other than

elemental Ge, which could either come from an interfacial GeOx layer or a Zr-O-Ge

interfacial bonding. With the progressive etches, the GeOx VB peak intensity reduces

and finally disappears. Furthermore, these VB qualitative mappings could be correlated

with the core-level spectra (Fig. 2.40(a)) as well. The weak and broad (KE of ~ 62-67 eV)

core-level Zr 4p signals are visible within the first 10 sec of etches. Starting after when

the sharper and well-defined core- level Ge 3d peaks arise and dominate, corresponding

well to the VB identifications.

With the purpose of quantifying the interfacial GeOx layer thickness, the

ensemble core-level PES spectra were first normalized to the photon beam current (I0) to

eliminate any real-time fluctuation in SR flux. Errors in such a computation were further

minimized by performing quantification only on one single sample rather than on both.

Extensive peak fittings were then carried out [86] by assigning the core- level Ge 3d

signals with all possible oxidation states. Rigorous fitting requirements were imposed by


62

fixing the doublet peak splitting amount and branching ratio according to physics, the

Gaussian and Lorentzian line widths, and the peak energy positions, while freeing only

the peak areas to obtain the best possible fits. If necessary, the Zr 4p peaks were also

allocated. Fig. 2.41 depicts one such fitting of the PES spectra after 16-18 sec of etch

with both the elemental (Ge0+) and oxidized (Gen+ where 1 = n = 4) peaks assigned [84].

60 62 64 66 68 70

Inte

nsi

ty (

a.u

.)

Kinetic Energy (eV)

Ge0+

Ge1+

Ge2+

Ge3+

Ge4+

Figure 2.41 Peak-fitted SR-PES spectra of the ZrO2/Ge after 16-18 sec of etch with both the elemental and oxidized Ge peaks assigned [84].

Figure 2.42 Fitted core- level Ge 3d peak areas as a function of etch time [84]. Cross-sectional schematics of the stack are also included to illustrate the etching progress.

0 5 10 15 20 25

InterfacialGeO

x

Etch Time (sec)

Fit

ted

Pea

k A

reas

(a.u

.)

Ge0+

Ge1+

Ge2+

Ge3+

Ge4+

ZrO2

GeOx

Ge

ZrO2 GeOx

Ge

GeOx

Ge Ge

(a) (b) (c) (d)


63

Plotted in Fig. 2.42 are areas of the fitted core- level Ge 3d peaks as a function of

etch time. To illustrate the etching progress, cross-sectional schematics of the stack are

also included. First of all, a sanity check on the overall fitting validity could be done by

monitoring the elemental peak (Ge0+) evolution. The fitted peak area increases with etch

time which is consistent with the theoretical prediction that elemental signals from Ge

substrate should attenuate less with a thinner overlayer on top (e.g. ZrO2 and/or GeOx)

upon etching. Next, the evolution of the oxidized Ge peaks was focused. Within the first

few seconds of etch (Fig. 2.42(a)), all oxidized signals were absent as any interfacial

GeOx layer would be buried by the relatively thick ZrO2 film above. When the ZrO2 film

got sufficiently thin (Fig. 2.42(b)), the more oxidized Ge signals (Gen+ where n = 2)

began to rise and reach maximum just when the entire ZrO2 film was removed. Further

etches would start to consume the GeOx layer (Fig. 2.42(c)) and cause the more oxidized

Ge signal intensity to fall back down. Once all GeOx were removed (Fig. 2.42(d)), the

oxidized Ge signals slightly went up again with the least oxidized peak (Ge1+) dominated.

This phenomenon is possibly due to re-oxidation right after a complete GeOx removal

inside the Ar purged glove bag and forms sub-stoichiometric surface oxides.

Next, the extraction of interfacial GeOx thickness was done by first computing the

escape depth of photoelectrons from Ge substrate as illustrated in Fig. 2.43. Judicious

selection of time points throughout the evolution for extraction was then made to largely

simplify the calculation process: (i) right after complete ZrO2 removal, and (ii) right after

Ge

GeOxs

z signal

Ge

zsignal

etching

Ge

GeOxs

z signal

Ge

GeOxss

z signal

Ge

zsignal

Ge

zsignal

etchingetching

Figure 2.43 Illustrations of escape depth calculation on the photoelectrons from Ge substrate at two different time points: (a) right after complete ZrO2 removal, and (b) right after complete GeOx removal [84].

(a) (b)


64

complete GeOx removal [84]. Thus, the fitted peak area right after ZrO2 removal, NGe(i),

could be expressed with

( )GexGeOGexGeO

ss

Ges

zs

Ge eedzeeN λλλλλ

−−∞ −−

=∝ ∫i (2.3)

and the fitted peak area right after GeOx removal, NGe(ii), could be related using

( ) Ge

z

Ge dzeN Ge λλ =∝ ∫∞ −

0ii (2.4)

where s is the GeOx thickness, and λGeOxand λGe are the electron inelastic mean-free-paths

(IMFPs) in GeOx and Ge respectively. By substituting Eq. (2.4) into Eq. (2.3), the GeOx

thickness could thus be extracted using

( )

( )

+=

i

iilnGe

Ge

GeOGe

GeOGe

N

Ns

x

x

λλ

λλ (2.5)

The λGeis estimated to be about 0.44 nm and λGeO could range between 0.4-0.8 nm

[87]. Taking into account any possible errors in peak fitting and uncertainty in λGeO, the

interfacial GeOx thickness should be around 0.22-0.29 nm. Since the thickness is

substantially less than a complete monolayer, we therefore attribute this oxidized Ge

signature to a possible Zr-O-Ge interfacial bonding configuration. When this ultrathin

interfacial layer in high-κ/Ge gate stack is compared to the usually thicker interfacial

SiOx in high-κ/Si gate stack [57], a better scalability in high-κ/Ge MOS systems could be

predicted which will be elaborated in the next section.

2.5 Benchmarking Nanoscale Ge MOS Gate Dielectrics

From both the performance and scalability perspectives, objective assessments of

all nanoscale Ge MOS gate dielectrics discussed in this Chapter are educational and

indispensable. First, we have re-classified these dielectrics into three categories: (i)

native GeOxNy/Ge, (ii) high-κ/Ge with interfacial layer, and (iii) high-κ/Ge without

xGeOλ Geλ

GeλxGeOλ

xGeOλ


65

interfacial layer. The last category sorts out those high-κ/Ge gate stacks without a

distinct interfacial layer from cross-sectional HR-TEM (e.g. epitaxial ALD ZrO2 on Ge

from Fig. 2.18(a) and UVO ZrO2 on surface GeOx stripped Ge from Fig. 2.36). All data

in category (i) and (iii) were adopted from previous sections but the data in category (ii)

came from both previous sections and published literatures [73, 88] to improve the

generality of any resultant trends. As one of the most accepted benchmarking strategy,

we have plotted in Fig. 2.44 the gate leakage density (normalized at 1 V above VFB) as a

function of EOT for all three categories.

All these data were taken on n-type Ge substrates to make fair comparisons even

though the different metal gate electrode workfunctions might inevitably introduce errors

in this benchmarking exercise. When the native GeOxNy/Ge dielectrics are compared to

high-κ/Ge stacks, about 4-5 order of magnitude higher gate leakage could be observed

[44], which is the first exhibition of effective gate leakage suppression at a given EOT

value upon replacing GeOxNy with high-κ dielectrics in Ge MOS devices. Among the

two high-κ curves, the one without interfacial layer has a steeper slope and lower leakage

demonstrating a better scalability. Moreover, when both the GeOxNy and high-κ with

0 1 2 3 4 510-9

10-6

10-3

100

103

High-κ/Ge(no IL)

GeOxN

y/Ge

High-κ/Ge(with IL)

Lea

kag

e C

urr

ent @

VFB

+1V

(A

/cm

2 )

Equivalent SiO2 Thickness (nm)

Figure 2.44 Benchmarking the gate leakage from Ge MOS capacitors with nanoscale dielectric. All data from native GeOxNy and high-κ/Ge with and without interfacial layer (IL) were taken on n-type Ge substrates.


66

interfacial layer curves are extrapolated backwards, they would intersect at a very low

EOT value as the interfacial layer thickness. This may imply that the GeOxNy, which

acted as a sub-1.0 nm interfacial layer in high-κ gate stack on Ge [65, 73], should allow

the scaling of certain high-κ dielectric stacks on Ge more than high-κ on Si. Recently, a

similar projection has also been made on better EOT scalability of reactive sputtered

HfO2 on Ge systems over the Si counterpart [89]. Lastly, the key comparisons of the

three nanoscale Ge MOS gate dielectrics are summarized in Table 2.2.

2.6 Summary

In this chapter, we have investigated three types of nanoscale gate dielectric for

Ge MOS applications including native GeOxNy, high-κ dielectrics grown by ALD

reaction, and high-κ dielectrics grown by UVO process. Their synthesizing mechanisms

and tools were first discussed. Prior to their formation on Ge substrates, various surface

preparations were also examined. Physical characterizations of these dielectrics were

carried out using XPS, optical ellipsometry, HR-TEM, electron diffraction analysis, AFM,

MEIS, and SR-PES. Moreover, their electrical qualities were evaluated by building MOS

capacitor structures followed by subsequent C-V and gate leakage measurements before

and after thermal anneals.

Interface Trap Density

Frequency Dispersion

Film Leakage

C-V Hysteresis

GeOxNy High ~ 0 High Very Low

ALD high-k (without interfacial layer) High Huge Low Large

ALD high-k (with GeOxNy interfacial layer)

Medium to high ~ 0 Low ~ 0

UVO high-k (without interfacial layer)

Medium to high

Little Low Very low

Table 2.2 Key comparisons of the three nanoscale Ge MOS dielectrics.


67

Even though the GeOxNy is relatively stable and could be scaled down to an EOT

of 1.9 nm, a sub-1.0 nm EOT solution should still be sought. From both thermodynamic

and electrical considerations, a sub-1.0 nm EOT interfacial layer- free high-κ on Ge gate

stack using either ZrO2 or HfO2 should be plausible. Although interfacial layer- free

epitaxial growth of ALD high-κ was demonstrated, an interfacial GeOxNy layer is

necessary to produce high quality Ge MOS capacitors with ALD high-κ, which in turn

compromises future scalability. Next, viable interfacial layer- free UVO high-k growth

on Ge was studied due to the reactive nature of metal precursors and surface GeOx

instability. Experimental results suggested that sub-1.0 nm EOT high-κ/Ge gate stacks

with interfacial layer thickness as thin as 0.2-0.3 nm and excellent electrical

characteristics could be demonstrated using a room-temperature UVO high-κ process,

surpassing the high-κ/Si gate stack EOT scalability bottleneck. Finally, when these

GeOxNy/Ge and high-κ/Ge dielectrics are benchmarked with each other, about 4-5 order

of magnitude gate leakage reduction could be obtained upon the replacement of GeOxNy

with high-κ as a promising technology in future Ge MOS applications.


68

Chapter 3. Shallow Junction Formations in Ge by Ion Implantation and SSD Doping

69

Chapter 3 Shallow Junction Formations in Ge by Ion Implantation and Solid Source Diffusion Doping 3.1 Introduction For advanced metal-oxide-semiconductor field-effect transistor (MOSFET)

applications, shallow source and drain junctions with high dopant activation level are

mandated to simultaneously suppress short-channel effects and minimize parasitic

resistances. In the past decades, tremendous theoretical and technological progresses

have been made in both understanding and making shallow junctions in silicon (Si).

From the experience on Si, we can identify two determining factors in forming shallow

junctions with low sheet resistance: low dopant diffusivity and high dopant solid

solubility.

For germanium (Ge) to be a successful candidate for transport-enhanced FET

channel material specified in the ITRS [1], similar technology should exist to allow

fabrication of heavily doped shallow junctions in Ge. As a historically important


70

semiconductor material, many basic physical properties of Ge including impurity

diffusivity and solid solubility were archived during the mid 1950s.

Diffusivities of various impurities in Ge are shown in Fig. 3.1(a), which were

obtained in 1954 by the observation of the p-n junctions formed as the diffusing

impurities penetrate the specimen [2]. Figure 3.1(b) shows the setup to locate the p-n

junction where the test probe was mounted on a micromanipulator originally designed for

work with point-contact transistors. When these values are compared to those of the

same impurities in Si [3], a few orders of magnitude higher diffusivities could be found in

Ge. In addition, the common p-type dopant (boron (B)) diffuses much slower than n-type

dopants (phosphorus (P), arsenic (As), and antimony (Sb)), a phenomenon that is exactly

opposite to the much faster p-type dopant diffusion than n-type dopants diffusion in Si.

Moreover, a systematic investigation [4] on the solid solubility of various

impurities in Ge was performed in 1960; however, the solubility of common dopants like

B and P in Ge was not available. These solubilities are plotted in Fig. 3.2 together with

some scattered data that were documented in a later report [5].

Figure 3.1 (a) Diffusivity of various impurities in Ge, and (b) schematic diagram showing the method used for locating the p-n junction on Ge samples [2].

(a)

(b)


71

Compared to the data from the same dopants in Si [4], about an order of

magnitude lower solid solubility is discerned for n-type dopants (P, As, and Sb) in Ge

(Fig. 3.2) with the exception of Ga (a p-type dopant) showing an order of magnitude

higher solubility in Ge.

After the brief review of both dopant diffusivity and solid solubility, one could

imagine the formation of heavily doped shallow p+ junctions in Ge to be much less

challenging than the n+ junction fabrication. Also, even though the higher p-type dopant

diffusivity and solid solubility in Ge may compensate with each other and lead to

comparable p+ junctions as in Si, the higher n-type dopant diffusivity and lower solid

solubility in Ge (over Si) would literally double the hindrance in shallow n+ junction

construction. Nevertheless, there would still be a slight chance for the resultant n+ layer

to be less resistive primarily owing to the higher intrinsic carrier mobility in Ge [6].

In order to obtain decent junctions for radiation detector and MOSFET

applications, various Ge doping experiments were carried out during the last three

decades. For p-type dopant incorporation, implantation of 11B+ ions was studied [7-10] at

a dose range of 5×1011 to 6×1017 cm-2 and energy spanning from 20 to 100 keV; these

Figure 3.2 Solid solubility values for various dopants in germanium. The Ga, As, and Sb data (solid lines) were taken in 1960 [4] and the scattered solubilities (Ga (? ), P (¦ ), As (?), and Sb (? )) were summarized in 1990 [5].

400 500 600 700 800 900 10001018

1019

1020

1021

P

Sb

As

Ga

So

lid S

olu

bili

ty (

ato

m/c

m3 )

Temperature (ºC)


72

implants were then anneal activated at temperatures of 200-850 °C for 30-60 min. Also,

implantation of 5×1011 to 1×1014 cm-2 of boron difluoride ions (49BF2

+) at 100 keV was

employed [9] followed by thermal anneals at temperature as high as 550 °C for 30 min.

All these experiments, however, utilized conventional furnace for activation anneals

which may have limited applicability for making shallow junctions.

For n-type doping in Ge, implantations of 31P+, 75As+, and 121Sb+ ions were

examined with a dose and energy range of 1×1012 to 1×1015 cm-2 and 20-700 keV

respectively [11-13], and were anneal activated at 200-650 °C for 20-80 min.

Nonetheless, either a too low dose or too high implant energy was used in any single

study together with furnace anneals. As implant activation was further inspected with

both furnace anneal and rapid thermal anneal (RTA) at temperatures 430-650 °C [14].

Although, the more practical implant energy (50 keV) was used for our purpose, the

implant dose range (8×1012 to 1×1014 cm-2) and resultant level of activation (< 1019 cm-3)

were low for futuristic device applications.

In this chapter, the activation and diffusion of various p-type and n-type dopants

in Ge are thoroughly studied. Two techniques employed in dopant incorporation are ion

implantation and solid source diffusion (SSD). The incorporated dopants were activated

mostly using RTA to minimize their diffusion and occasionally with furnace anneal to

update the literature. Through the examination of thermal stability on the activated

dopants, their deactivation is observed for the first time. Lastly, a possible mechanism

for such a deactivation process is proposed.

3.2 Shallow Junctions by Ion Implantation Doping 3.2.1 P-type Junction Activation with Furnace Anneal

The starting substrates used to fabricate p+ junctions were (100) oriented n-type

Ge wafers with a net background concentration of ~ 7×1015 cm-3 at room temperature.

No special Ge surface preparation or cleaning was performed before ion implantation.


73

49BF2+ ions were implanted with dose and energy of 4×1015 cm-2 and 35 keV, respectively,

at room temperature. These implantation conditions were calculated to produce junctions

with depth of about 100 nm and hence the ion beam was also tilted by 7° to the substrate

surface normal to minimize channeling effect. These implanted samples were first

degreased in PRS1000 (positive resist stripper) and then loaded into a hot-wall low-

pressure chemical vapor deposition (LPCVD) furnace to deposit roughly 30-50 nm of

silicon dioxide (SiO 2) at 300 °C. Activation anneals were carried out in a conventional

furnace at 325-700 °C for 30 min in nitrogen gas (N2), a choice over RTA that was

primarily picked to monitor the dopant activation levels rather than to obtain shallow

junctions. Finally, the surface capping SiO 2 was removed in 50:1 hydrofluoric acid (HF)

prior to the subsequent electrical measurements.

Hall effect measurement can be utilized to directly reveal the resistivity of the

material, the dominant carrier type, and thus the electrically active doping concentration.

On these BF2 implanted n-type Ge samples, room temperature Hall effect

measurements [15] were applied to extract both sheet resistance (ρs) and activated dose

from the surface p+ layers (Fig. 3.3). In Fig. 3.3(a), the low as-implanted ρs is probably

300 400 500 600 7000

50

100

150

200

250

300

As-implanted

After 300ºC SiO2 Dep

Sh

eet

Res

ista

nce

(Ω

/ )

Anneal Temperature (ºC)

Figure 3.3 (a) Sheet resistance and (b) activated dose measured from surface implanted p+ layers on n-type Ge substrate as a function of furnace anneal temperature. These Hall effect measurements were carried out at room temperature after the capping SiO 2 removal. The values extracted from the as- implanted sample and sample right after SiO 2 deposition are also included [15].

300 400 500 600 7001014

1015

1016

Implanted BF2 Dose

= 4x1015 cm-2

As-implanted

After 300ºC SiO2 Dep

Act

ivat

ed D

ose

(cm

-2)


(a)

(b)


74

originated from implant damage-related acceptor centers [9] rather than the as- implanted

substitutionally active p-type doping by B implantation, also discussed in the same report.

After the SiO 2 capping at 300 °C, some of the implant damages began to be repaired but

the boron had not been substitutionally active and led to an increase in ρs. A furnace

anneal at 325 °C after SiO2 capping (at 300 °C) only slightly lowered the ρs; however, a

more dramatic ρs reduction could be observed if the anneal was executed at 400 °C. This

could be explained by both the effectiveness of the 400 °C anneal to completely

recrystallize Ge surface layers (amorphized by ion implantation with dose of less than

6×1015 cm-2 [7]) giving rise to high carrier mobility, and the substitutional B

incorporations into Ge crystal lattice providing sufficient carriers for current conduction.

When the anneal temperature was further raised to 500-700 °C, no significant change in

ρs was perceived, hypothesizing that once the B atoms have substitutionally incorporated

into Ge lattice, they do not tend to redistribute and diffuse.

Similarly, the activated dose illustrated in Fig. 3.3(b) follows the same activation

temperature dependence. For instance, the activated dose increases with the anneal

temperature rise from 325 °C to 400 °C reinforcing the idea of increased substitutional B

incorporations aforementioned; but none of those higher temperature anneals improve the

activated dose any further. As these Hall effect measurements indicate, one can

effectively activate p-type dopant in Ge at a temperature as low as 400 °C with about

31% of the total implanted dose activated [15].

Next, spreading resistance probe (SRP) analysis was chosen to measure the

electrical concentration depth profiles and study dopant diffusion. In brief, SRP analysis

provides an electrical measurement of the active concentration using a pair of fine metal

probes to step down the beveled surface of a sample as shown in Fig. 3.4 [16]. The raw

data captured are first compared against calibration standards to generate resistivity plots,

which are then computed together with published carrier mobility values to obtain the

carrier concentration as a function of sample depth. Extra caution should be exercised in

analyzing Ge samples including the use of softer probes owing to the softer substrate and

the employment of Ge mobility numbers for data conversion.


75

Fig. 3.5 depicts the SRP data on the 400 °C furnace annealed sample discussed in

Fig. 3.3. To study the dopant diffusion behavior, part of the sample was further annealed

at 400 °C for 30 min in forming gas. The resistivity plots in Fig. 3.5(a) were used to

Figure 3.4 Schematic of a SRP analysis, where metal probes step down the surface of a beveled sample and measure the resistance between the probes at each tip [16].

0 50 100 150 20010-3

10-2

10-1

100

101

400ºC, 30min, N2

400ºC, 30min, N2 +

400ºC, 30min, FGA

Res

istiv

ity (Ω

-cm

)

Depth (nm)

0 50 100 150 2001016

1017

1018

1019

1020

1021

400ºC, 30min, N2

400ºC, 30min, N2 +

400ºC, 30min, FGA

Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)

(a) (b)

Figure 3.5 (a) Resistivity and (b) electrical concentration measured on two BF2 implanted Ge samples with one annealed at 400 °C for 30 min in N2 and the other first annealed at 400 °C for 30 min in N2 and then in forming gas (FGA) [15]. The SPR measurements were carried out at room temperature after the capping SiO 2 removal.


76

calculate the electrically active dopant concentrations in Fig. 3.5(b), where both of them

indicate a negligible amount of dopant redistribution or diffusion after the additional

forming gas anneal. This phenomenon is coherent with the extremely low B diffusivity

at 400 °C shown in Fig. 3.1.

Additionally, the peak and surface electrical concentrations are 3.3×1019 cm-3 and

~ 2×1019 cm-3 respectively exhibiting decent p+-n junctions in Ge (Fig. 3.5(b)). However,

the integrated electrically active dose from SRP (1.6×1014 cm-2) is about an order of

magnitude lower than the activated Hall dose extracted previously. This big discrepancy

is possibly originated from the lack of an experimentally calibrated standard sample for

both SRP analysis and Hall correction factor adjustment. Nevertheless, by using

conventional ion implantation doping followed by RTA, shallow p+ junction in Ge with

surface concentration exceeding 1×1020 cm-3 is readily demonstrated as will be discussed

together with n-type junction activation in the next section.

3.2.2 Complementary Junctions Activation with Rapid Thermal Anneal

Highly activated p+ and n+ junctions are the utmost important components in

building complementary MOS (CMOS) logic, which is also the major focus of this

section. The starting substrates used to fabricate complementary junctions were (100)

oriented n-type and p-type Ge wafers with a net background concentration at room

temperature of ~ 6×1015 and ~ 2×1014 cm-3, respectively. No special Ge surface

preparation or cleaning was performed before ion implantation. Room temperature

implantations of various common ionic species at a fixed dose of 4×1015 cm-2 were

carried out at energies [17] corresponding to a similar projected range (Rp). 49BF2+ ions

with 20 keV were used to form p+ junctions in n-type Ge, while 18 keV of 31P+, 30 keV

of 75As+, and 45 keV of 121Sb+ ion were employed to make n+ junctions in p-type Ge.

The ion beam was tilted by 7° to the substrate surface normal to minimize channeling

effect. These implanted samples were first degreased in PRS1000 and then deposited

with about 30-50 nm of SiO 2 at 300 °C in a LPCVD furnace. RTA was then performed


77

at temperatures of 600-850 °C with 1-300 sec soak time in N2 ambient to activate dopants

and remove the implantation damage while minimizing non-equilibrium diffusion effects

such as transient enhanced diffusion (TED). Without removing the capping SiO 2, SRP

analysis was applied to track the electrically active dopant depth profiles.

0 100 200 300 4001015

1016

1017

1018

1019

1020

1021

1022

B (p-type)

700ºC, 1 sec 700ºC, 5 sec 700ºC, 10 sec


Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)

Figure 3.6 Electrical concentration measured on BF2, P, As, and Sb implanted Ge samples after various RTA [18]. The SPR measurements were carried out at room temperature with the capping SiO 2 on top.

0 100 200 300 4001015

1016

1017

1018

1019

1020

1021

1022

P (n-type)

675ºC, 5 sec 700ºC, 1 sec 700ºC, 5 sec 700ºC, 10 sec


Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)

0 100 200 300 4001015

1016

1017

1018

1019

1020

1021

1022

As (n-type)



Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)

0 100 200 300 4001015

1016

1017

1018

1019

1020

1021

1022

Sb (n-type)

650ºC, 10 sec 650ºC, 60 sec 675ºC, 5 sec 700ºC, 5 sec 700ºC, 10 sec

Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)


78

As illustrated in Fig. 3.6, the ion implanted B can be activated to produce shallow

p+ junctions with no substantial B diffusion for the RTA thermal budgets of interest [18].

Surface electrical concentrations on the order of 1×1020 cm-3 could be obtained with

about 2.9-5.9% of the implanted dose activated, which might also reflect its solid

solubility level at these temperatures. On the other hand, RTA of ion implanted n-type

dopants causes significant diffusions and delivers not as high surface concentrations.

From all n-type doping profiles, the peak concentrations were never shown to occur at the

surface which could be attributed to dopant out-diffusion from Ge substrate and

segregation into the SiO2/Ge interface. Among the three n-type dopant candidates, P

apparently gives the highest peak and surface concentration of ~ 8.5×1019 cm-3 and ~

2×1019 cm-3 respectively after an RTA at 650 °C for 10 sec. In addition, all profiles

exhibit an abrupt edge near the metallurgical n+-p junctions except for P that has tails

extending into bulk Ge (Fig. 3.6), consistent with the discussion in Ref. [11]. These tails

are related to defects at the original implant- induced amorphous/crystalline interface

referred to as end-of-range (EOR) defects. They occur because there is a large amount of

damage which is just below the threshold of amorphization beyond the

amorphous/crystalline interface, where the maximum possible amount of damage can

exist in the crystal without itself being amorphous. After all, these EOR defects could

only be annealed out with larger thermal budgets as will be elaborated next.

600 625 650 675 7000

5

10

15

20

25 10 sec 5 sec

P

As

Sb

Fra

ctio

n A

ctiv

e (%

)


Figure 3.7 Plot of the fractional activation of various n-type dopant implants as a function of anneal temperature for two isochronal anneals (solid symbols for 10 sec and open symbols for 5 sec).


79

As demonstrates a slightly lower activation level than P but this is still an order of

magnitude higher than that of Sb. The SRP peak concentration of these three elements in

Ge when compared to the solid solubility shown in Fig. 3.2, obeys the same order (P >

As > Sb). Fig. 3.7 plots the fractional activation of the three n-type dopant implants as a

function of anneal temperature for two RTA soak times. Regardless of the low Sb

fractional activation, the experimental peak concentration matches the solid solubility,

hinting any lower resistivity n+ layer would not be feasible owing to a fundamental limit.

Contrarily, the experimental P and As peak concentrations are a few times lower than

their respective solid solubilities while their fractional activations are far from unity,

leaving room for further improvement. A probable explanation of such a discrepancy is

the ability for Sb to completely amorphize Ge but only partial amorphization is possible

with either P or As at the same implant dose. Even though the dose of 4×1015 cm-2 in our

experiment is above the usual amorphization threshold (~ 1×1015 cm-2) in Si, the larger

lattice constant in Ge may require an even higher threshold for some lighter ions. From

the experience on Si, it is much more difficult to anneal a sample that has only been

partially damaged at levels below the amorphization threshold [19]. This difficult regime

is where secondary damage forms that has a more complex annealing behavior. Usually

when this happens, a gradual increase in fractional activation with anneal temperature

would be discerned (like from medium dose P implants into Si [19]); now, similar

behaviors are also found in P and As implants into Ge (Fig. 3.7). In principle, a higher

activation level could thus be achieved at higher anneal temperature. However, the

accelerated dopant diffusion at these temperatures compromises shallow junction

formation, which instead mandates a more careful selection of implant doses.

In all commercial CMOS integrated-circuit (IC) fabrications, both p+ and n+

junctions are simultaneously activated with the same thermal anneal budget. Therefore,

we should also compile with this requirement for Ge CMOS applications by selecting the

most symmetric pair of junctions from the above complementary junctions activation

experiment. Besides using SRP to monitor electrical depth profiles, secondary ion mass

spectroscopy (SIMS) is also employed for chemical concentration profiling.


80

Fig. 3.8 shows the depth profiles of B and P both as- implanted and after an RTA

at 650 °C for 10 sec [18]. Only SIMS data is shown for the as- implanted samples and

both SIMS and SRP results are presented for the post-RTA case. Negligible B diffusion

is again confirmed by the overlapping of the as- implanted and post-RTA SIMS profiles.

Conversely, P diffuses substantially even after a very low thermal budget anneal.

Electrically, the resultant p+-n junction has a depth of ~ 150 nm and a peak active

concentration of ~ 1.5×1020 cm-3 (with a corresponding sheet resistance of 210 Ω/ð)

while those from the n+-p junction are ~ 280 nm and ~ 8.5×1019 cm-3 (sheet resistance of

42 Ω/ð), respectively. It is worth noting that the electrical active concentration of P in

Ge after RTA from SRP shows a higher value than the chemical concentration from

SIMS. This apparent contradiction could be attributed to the inaccuracy in raw data

conversion, due to the lack of some well-calibrated standards in Ge. To summarize,

symmetrically high levels of electrical activation of both p-type and n-type dopants in Ge

are plausible and have been demonstrated at concentrations directly applicable to

advanced CMOS devices.

0 50 100 150 2001016

1018

1020

1022

B (p-type)

SIMS - as-implanted SIMS - 650ºC, 10 sec SRP - 650ºC, 10 sec

Con

cent

ratio

n (c

m-3)

Depth (nm)

Figure 3.8 SIMS and SRP depth profiles of B and P before and after an RTA at 650 °C for 10 sec. BF2 and P were implanted at 20 and 18 keV, respectively, at a dose of 4×1015 cm-2 [18]. Both SIMS and SPR measurements were carried out with the capping SiO 2 on top.

0 50 100 150 2001016

1018

1020

1022

P (n-type)

SIMS - as-implanted SIMS - 650ºC, 10 sec SRP - 650ºC, 10 sec

Con

cent

ratio

n (c

m-3)

Depth (nm)


81

3.2.3 N-type Dopant Diffusion

Since the ion implanted B profiles discussed previously showed negligible

diffusion at all temperatures of interest, its diffusion will not be studied in this section.

Alternatively, the fast diffusion of ion implanted n-type dopants in Ge requires more

attention when building shallow junctions. First of all, we qualitatively compare their

diffusion behavior [18]. Fig. 3.9 illustrates various n-type SRP profiles of P, As, and Sb

after two different RTA treatments (675 °C for 5 sec and 650 °C for 60 sec) excerpted

from Fig. 3.6. The 650 °C for 60 sec RTA treatment had certainly a larger thermal

budget that produced lower peak concentrations and deeper junctions than the 675 °C for

5 sec RTA for all three dopants. Within the same RTA treatment, the ion implanted As

tends to diffuse the most followed by P and then Sb, a trend that is different from their

intrinsic diffusivity order (As > Sb > P) as shown in Fig. 3.1(a).

In order to understand this inconsistency in ordering, we have fitted the

experimental dopant profiles with those simulated using T-SUPREMTM for P, As, and Sb.

Two representative simulation fits with post-RTA ion implanted P profiles in Ge are

shown in Fig. 3.10.

Figure 3.9 SRP profiles of various n-type dopants in Ge after two different RTA treatments (675 °C for 5 sec and 650 °C for 60 sec) [18].

0 100 200 300 400 500 6001015

1016

1017

1018

1019

1020

Sb

AsAs

PP

Sb

650ºC60 sec675ºC

5 sec

Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)


82

Through these simulation fittings, we have extracted the dopant diffusion

coefficients in Ge and simultaneous ly studied the related diffusion models and

mechanisms [18]. In the simulations, the implant profiles were assumed to have a simple

two moment model (comprising Rp and straggle (∆Rp)) in the cases where SIMS data of

the as- implanted profile was not available. In all cases, the implanted profiles were

scaled so that they would match the total active dose from SRP (since SRP instead of

SIMS profiles were used in the dopant diffusion simulation and modeling). These

simulations did not include implant damage and therefore would not capture effects like

transient enhanced diffusivity (TED). Extensive simulations were done with the neutral

interstitial, single negatively charged interstitial, and doubly negatively charged

interstitial models in order to match the diffused profiles. Only a dose corresponding to

the active dose measured by SRP was presumed to diffuse.

From the SRP profiles shown in Fig. 3.9 (and Fig. 3.6), both P, As, and Sb

exhibited box-shaped characteristics that is indicative of concentration dependent

diffusion [3]. The best fits to SRP data suggested that concentration dependent

diffusivity models using an (n/n i)2 dependency gave the best fit for P and As while (n/n i)

Figure 3.10 Experimental SRP profiles and the corresponding T-SUPREMTM simulation fits for ion implanted P in Ge after 10 sec of RTA at 600 °C and 700 °C [18].

0 100 200 300 4001017

1018

1019

1020

1021

700ºC10 sec

600ºC10 sec

SRP T-SUPREMTM

Con

cent

ratio

n (c

m-3)

Depth (nm)


83

provided the best fits for Sb. The intrinsic carrier density, ni, used in our extractions is

given by [20]

( ) TkTEVCi

BgeNNn 2/−= (3.1)

where NC and NC are the effective densities of states in the conduction and valence bands,

respectively, kB is the Boltzmann’s constant, T is the absolute temperature, and Eg(T) is

the temperature dependent energy bandgap. The bandgap narrowing effect on increasing

temperature illustrated in Ref. [20] could be fitted empirically with these expressions

( )( ) TTEg4

Ge 10775.47437.0 −×−= for Ge, and (3.2)

( )( ) TTEg4

Si 1015.3170.1 −×−= for Si (3.3)

at temperature range of interest (600-850 °C). The dopant diffusion coefficients were

first simulated assuming the Si ni values. The extracted prefactors, D0, were then

adjusted with the Ge ni using

( ) ( )( )2GeSi

0Si

0Ge ii nnDD ×= for P and As, and (3.4)

( ) ( )( )GeSi0Si

0Ge ii nnDD ×= for Sb (3.5)

The activation energies, EA, which were also modified accordingly, are shown together in

Table 3.1. For P, the fits were good at high doping concentrations, but the simulations

did not model the end of range (EOR) defect tails in the doping profiles (< 1×1017 cm-3).

The diffusion coefficients differ slightly from the values reported in literature [21]

because of the different concentration dependencies observed in these experiments and

the narrow range of temperatures over which the studies were carried out for some

dopants. We believe that this may be caused by the fact that the simulations did not

include full coupling between dopants and defects and its impact on diffusion.

Dopants Model EA (eV) D0 (cm2/sec) P (n/ni)2 2.07 4.38×10-2 As (n/ni)2 3.32 1.45×106 Sb (n/ni) 2.28 1.19×101

Table 3.1 Extracted diffusion coefficients and the associated model for various n-type dopants in Ge [18].


84

From these concentration dependent diffusion results together with previous

investigations on the effect of pressure on ion implanted As diffusion in Ge [22], we

could conclude that the diffusion of Groups III, IV, and V elements is not entirely

mediated by vacancies. Otherwise, the vacancy formation volume must be unexpectedly

low or the energy of vacancy migration must be unexpectedly high. In a later report [23],

Ge vacancies with the charge states 0 and 2- were shown to be the diffusion vehicles

responsible for As migration in Ge without contribution from the singly charged vacancy.

Nevertheless, in order to allow fabrication of futuristic ultra-shallow junctions in Ge by

ion implantation, further research on these dopant-defect interactions especially for n-

type dopants are undoubtedly indispensable.

3.3 Shallow Junctions by Solid Source Diffusion Doping 3.3.1 N-type Junction Activation and Diffusion

Since the ion implantation doping results in fast diffusion in Ge especially for n-

type dopants, its efficacy to form shallow junctions might eventually be limited. As an

alternative doping technology, solid source diffusion (SSD) doping is free from problems

such as channeling effects, TED, and extended defect formation, even at very low

implant energies [24]. In addition to these advantages, shallow junctions with low sheet

resistance have been achieved in silicon using SSD [24-25]. In an attempt to obtain

shallow junctions in Ge via diffusion from doped SiO 2, we have studied the SSD doping

in Ge. Rapid thermal processing (RTP) was utilized to maximize the activation level of

the out-diffused dopants and minimize their redistribution.

The starting substrates used to fabricate n+ junctions were (100) oriented p-type

Ge wafers with a net background concentration of ~ 3×1017 cm-3 at room temperature.

The surfaces were first cleaned by cyclic rinsing between deionized (DI) water and

hydrofluoric acid (HF). The HF concentration employed was 50:1 and the rinse time was

15 sec in each chemical for a total duration of 150 sec (elucidated in Section 2.2.3). This


85

cyclic HF clean was finished with a 10 sec DI water rinse for chemical safety reasons.

The cleaned Ge substrates were then blown dry with N2 and immediately loaded into a

LPCVD furnace to deposit about 200 nm of 8 wt.% phosphosilicate glass (PSG) as the

solid dopant source from a mixture of silane (SiH4) and phosphine (PH3) gases at 400 °C.

This choice of PSG concentration was intended to maximize the P amount while

preventing the film from becoming hygroscopic. The SSD doping was subsequently

carried out in a commercial RTP system (described in Section 2.2.2) at 600-900 °C with

5-300 sec soak time in N2 ambient. The RTP ramp rate was 100 °C/sec. Without

removing the capping SiO 2, SRP analysis was applied to track the electrically active

dopant depth profiles.

Fig. 3.11 shows the electrically active depth profiles of the out-diffused P into p-

type substrate as a function of the RTP soak time at 850 °C in N2 ambient [26]. These

resultant n+-p junctions always showed the peak concentration at the surface of about

1×1019 cm-3. This highest achievable peak concentration depends on several factors

including the P concentration and diffusivity within the PSG layer, the P segregation at

the PSG/Ge interface, as well as the P solid solubility in Ge. For the 8 wt.% PSG that we

Figure 3.11 SRP depth profiles of the out-diffused P into p-type Ge substrate as a function of RTP soak time at 850 °C in N2 ambient [26].

0 500 1000 1500 20001017

1018

1019

1020

P in Ge


Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)


86

used in our experiment, no appreciable out-diffusion was observed below 800 °C, which

could be attributed to the low diffusivity of P within the PSG layer at such low

temperatures. In order to simultaneously lower the out-diffusion temperature and raise

the surface peak concentration, a solid source with either higher dopant concentration or

diffusivity could be employed.

Before the extraction of intrinsic dopant diffusivity, a constant-source diffusion

behavior has to be verified by examining the out-diffused junction profiles. The

junctions formed by out-diffusion at 800 °C did not produce the same surface peak

concentration with different RTP soak times which represents non- ideal constant-source

diffusion. A true constant-source diffusion regime was instead visible after SSD at 850

°C and 900 °C. By plotting the resultant junction depth versus the square root of

diffusion time, a linear relationship could be observed as illustrated in Fig. 3.12.

The diffusion coefficient, D, could then be estimated from the complementary

error- function for constant-source diffusion

×= −

0

12NN

erfcDtx Bj (3.6)

0 5 10 15 200

300

600

900

1200

1500

1800

850oC

900oC

Jun

ctio

n D

epth

(n

m)

Diffusion Time0.5 (sec0.5)Figure 3.12 Metallurgical junction depths versus the square root of RTP soak time

extracted from the out-diffused junctions at 850 °C and 900 °C.


87

where xj is the junction depth, t is the RTP soak time, NB is the p-type Ge substrate

concentration, and N0 is the n+ Ge surface peak concentration. Assuming most of the

commonly known extrinsic diffusion mechanisms were absent during the SSD process,

the diffusion coefficients extracted from Eq. (3.6) and Fig. 3.12 should represent the

intrinsic diffusivities of P in Ge.

When these intrinsic diffusivities are plotted as a function of temperature as

shown in Fig. 3.13, they follow the Arrhenius relationship

−

=kTE

DD Aexp0 (3.7)

where D0 is the diffusivity pre-factor, EA is the activation energy for diffusion, k is the

Boltzmann’s constant, and T is the absolute temperature. Also included in Fig. 3.13 are

the P diffusion coefficients in Ge from Ref. [2], which indicates a very good match with

the experimental data in the present study; the extracted EA is 2.45 eV and D0 is 2.05

cm2/sec for such an intrinsic SSD.

In order to compare the intrinsic diffusivity of P in both Ge and Si and thus to find

out which material would ultimately permit shallower junctions, their temperature

dependences were plotted together in Fig. 3.14(a).

0.8 0.9 1.0 1.110-13

10-12

10-11

1x10-10

1x10-9

Ref [2]

Dif

fusi

on

Co

eff.

(cm

2 /sec

)

1000/T (K-1)Figure 3.13 Arrhenius plot of the extracted intrinsic diffusivity of P in Ge together

with the reference data from Ref [2].


88

However, because of their large difference in melting point, a more objective

assessment could only be made by normalizing the same intrinsic diffusivity dependence

with respect to their individual melting point (Fig. 3.14(b)). Still, P in Ge is found to be

more diffusive than in Si. Together with its lower solid solubility (Section 3.1), the

shallow n+ junction formation in Ge would be relatively more challenging.

To sum up, shallow n+ junctions in Ge have been demonstrated through

controlled SSD doping with low thermal budget RTP. In addition to the insulating solid

dopant source aforementioned, the use of in-situ p-type and n-type doped silicon

germanium (SixGe1-x) alloys as solid sources have also been attempted. The initial results

suggest their suitability by enabling p+-n and n+-p diodes with ideality factor close to

unity, and such idea should deserve more research effort to show further promises.

3.3.2 Dopant Deactivation within Activated Junctions

Being able to maintain the high level of dopant activation during the subsequent

thermal steps in a MOS transistor fabrication process is crucial to guarantee good device

Figure 3.14 (a) Temperature dependence of the intrinsic diffusion coefficient of P in Ge [2] and Si [3], and (b) the same intrinsic diffusivity dependence normalized to the corresponding crystal melting point in K.

850 1000 1150 1300 145010-20

10-18

1x10-16

1x10-14

1x10-12

1x10-10

P in Si [3]

P in Ge [2]

Diff

usio

n C

oeff

icie

nt (c

m2 /s

ec)

Temperature (K)

0.5 0.6 0.7 0.8 0.9 1.010-20

10-18

1x10-16

1x10-14

1x10-12

1x10-10

P in Si [3]

P in Ge [2]

Diff

usio

n C

oeff

icie

nt (c

m2 /s

ec)

Fraction of Melting Point (K/K)

(a) (b)


89

performance. Working towards this goal, we have studied the activation level of the out-

diffused dopants after various thermal anneals. On the same n+-p junction out-diffused

from PSG at 850 °C for 10 sec, RTA were individually carried out at either 500 °C in N2,

600 °C in N2, or 600 °C in ammonia (NH3) [26]. Fig. 3.15 depicts their measured

electrically active depth profiles together with the estimated as-out-diffused junction

profile.

After either one of these subsequent thermal anneals, the electrically activated n-

type dopants were distinctly observed to be deactivated for the first time. Comparing the

thermal anneals in N2 ambient, the 600 °C treatment caused more severe deactivation

then the 500 °C case. When the treatments were carried out at the same 600 °C, the

anneal in NH3 deactivated dopants more than in N2. On the other hand, the surface

dopant concentration dropped after anneals in N2 but not in NH3. This phenomenon

indicates that the PSG/Ge interfacial NH3 nitridation might help to suppress surface

deactivation or to minimize surface dose loss, possibly due to a similar nitridation-

retarded surface P diffusion observed in Si [27].

Figure 3.15 SRP depth profiles of the junction first formed by out-diffusion from PSG at 850 °C for 10 sec (estimated) in N2 and those subsequently annealed with different thermal budgets and in different ambient.

0 100 200 300 4001017

1018

1019

1020

P in Ge

Est. As Out-Diff. (O/D) O/D + 500ºC, 60 sec, N2

O/D + 600ºC, 60 sec, N2

O/D + 600ºC, 60 sec, NH3

Ele

ctri

cal C

once

ntra

tion

(cm

-3)

Depth (nm)


90

In order to propose a plausible deactivation mechanism, we examined the change

in P chemical concentration profiles with SIMS on these junctions before and after the

deactivation anneal at 600 °C in NH3 (Fig. 3.16). Prior to the SIMS analysis on each

sample, the PSG layer on Ge surface was removed in 50:1 HF to avoid any interference

between the out-diffused dopants inside Ge, and those within the PSG layer which were

present in a very high concentration. This PSG stripping was not necessary in previous

SRP measurements because the dopants within the PSG layer are not electrically active.

After the deactivation anneal, no significant chemical dopant redistribution was

observed in Fig. 3.16. The slight reduction in junction depth could either due to dopant

diffusion and segregation at the PSG/Ge interface (which was unfortunately not captured

owing to PSG removal) or merely be an error in SIMS craters height measurement for

depth calibration. When these chemical SIMS profiles are compared to the electrically

active SRP profiles in Fig. 3.15, we notice that only the electrical activation level

dropped after the 600 °C anneal in NH3 while the chemical concentration stayed about

the same. Combining these experimental facts together, we suggest that activated P in Ge

deactivates through the formation of small inactive dopant-defect clusters [28], which

Figure 3.16 SIMS depth profiles of the junction first formed by out-diffusion from PSG at 850 °C for 10 sec in N2 and that subsequently annealed at 600 °C for 60 sec in NH3 ambient.

0 100 200 300 4001017

1018

1019

1020

P in Ge

850ºC, 10 sec, N2

850ºC, 10 sec, N2 +

600ºC, 60 sec, NH3

Che

mic

al C

once

ntra

tion

(cm

-3)

Depth (nm)


91

also indirectly indicates the existence of an appreciable amount of point defects even in a

crystalline Ge substrate. On the contrary, deactivation through precipitation is less likely

as it usually occurs only after significant dopant diffusion [28], an observation that is

missing from the SIMS data after such a short anneal for 60 sec. More systematic studies

into these mechanisms would be timely and essential as such a deactivation behavior

would not only increase the MOS transistor source and drain sheet resistance, but more

importantly degrade the contact resistivity which is currently the major bottleneck in the

development of advanced transistors.

3.4 Summary

In this chapter, we have investigated two techniques to form shallow junction for

Ge MOSFET contact applications including ion implantation and SSD doping. The

incorporated dopants were activated using furnace anneal and RTA. The activation and

diffusion of various p-type and n-type dopants in Ge were studied using Hall effect

measurement, SRP, and SIMS.

Ion implanted p-type dopant in Ge can effectively be activated with negligible

diffusion at temperature as low as 400 °C using furnace anneal. However, the higher

temperature required to activate ion implanted n-type dopants would inherently cause fast

extrinsic diffusion. RTA was then employed to circumvent the problem and led to the

demonstration of symmetrically high levels of both p-type and n-type dopant activation at

concentrations directly applicable to advanced CMOS devices. In addition, RTP was

utilized together with SSD doping to obtain shallow n+-p junctions in Ge. By examining

the thermal stability of the out-diffused dopants, we observed P deactivation in Ge for the

first time, possibly through the formation of small inactive dopant-defect clusters.


92

Chapter 4. Low Thermal Budget Ge MOSFET Fabrication Processes

93

Chapter 4 Low Thermal Budget Ge MOSFET Fabrication Processes 4.1 Introduction In conventional silicon (Si) metal-oxide-semiconductor field-effect transistor

(MOSFET) fabrication processes, the source and drain junctions or shallow extensions

are self-aligned to the gate by ion implantation followed by a thermal anneal to activate

dopants and repair implant damage at temperatures as high as 1000 °C. This high

temperature step may impose many stringent thermal stability requirements on the

integration of advanced metal gate and high-permittivity (high-κ) dielectric materials.

For instance, phase separation in metal silicate high-κ systems [1] and metal impurity

diffusion through the dielectric into Si substrate may occur at moderately high

temperatures.

In order to circumvent these technological difficulties, several self-aligned gate-

last processes have been developed [2-4] in which all high temperature steps are

performed prior to the formation of gate dielectric and metal gate electrode. The


94

pioneering technique was the replacement gate process [2] in which the source and drain

regions are self- registered to a dummy polycrystalline Si (poly-Si) gate that is

subsequently replaced by the metal gate electrode. The self-registration is achieved using

a two step process: (i) after the poly-Si gate definition and source and drain implantation,

a back-end-of- line (BEOL) oxide layer is first deposited; (ii) the chemical-mechanical

polishing (CMP) is then applied to uncover the top of the dummy gates followed by a wet

etch to remove the poly-Si. The first prototype had the dummy poly-Si/silicon dioxide

(SiO2) gate stack replaced by a metal/silicon oxynitride (SiO xNy) stack with either

aluminum (Al)/titanium nitride (TiN) or tungsten (W)/TiN as the metal gate [2]. The

second generation [3] replaced the same dummy stack with a metal gate/high-κ dielectric

stack (W/TiN/Tantalum Pentoxide (Ta2O5)/SiO2) as illustrated in Fig. 4.1.

Figure 4.1 Steps in the fabrication of a metal replacement gate transistor [3].

Figure 4.2 Damascene gate transistor fabrication process [4].

a) b) c)

d) e)


95

The radiation damage incurred during reactive ion etches (RIE) of metal gate and

high-κ dielectric in the above processes may deteriorate the gate oxide reliability and

influence the channel dopant profile. A novel damascene gate process [4] was therefore

developed by substituting the metal gate/high-κ etch step with a CMP planarization as

shown in Fig. 4.2.

Since p-type dopant in Ge could be activated at a temperature as low as 400 °C as

discussed in Section 3.2.1, the demand for a gate- last process for p-channel metal-oxide-

semiconductor field-effect transistor (p-MOSFET) fabrication is relatively low. The 600-

850 °C activation temperature (Section 3.2.2 and Section 3.3.1) for n-type dopants in Ge

conversely mandates a low thermal budget gate-last n-MOSFET process. However,

employment of the aforementioned replacement gate process or damascene gate process

for Ge MOSFET fabrication is not always practical in many situations.

In this chapter, two low thermal budget Ge MOSFET fabrication processes are

proposed and developed using the dielectric and junction techno logies investigated in

previous chapters. The first one is a sub-400 °C p-MOSFET process and the second one

is a novel self-aligned gate-last MOSFET process; both incorporate metal gates and high-

κ dielectrics. Their individual structural design, process flow, and device characteristics

have been examined. Lastly, many derivatives of the novel process are proposed for

some advanced applications.

4.2 The Sub-400 °C Metal Gate High-κ P-MOSFET Process 4.2.1 Structural Design

Since standard device isolation technology has yet to be established to fabricate

Ge MOSFETs in an integrated fashion, adopting a self- isolated transistor structure would

certainly help to expedite the technology evaluation process. A simple ring MOSFET

structure is therefore chosen for our purpose (Fig. 4.3). Self- isolation is achieved by


96

tying the source ring potential to ground and additional electrical isolation could be

obtained by biasing the outermost isolation ring as well for some device applications.

The device operation of a ring MOSFET is identical to that of a conventional

rectangular MOSFET, however, the effective channel width, Weff, needs to be re-defined

for a long-channel ring MOSFET (Fig. 4.4). Like in any 1-D MOSFET model, the

gradual channel approximation is first applied to reduce Possion’s equation to the 1-D

form that is valid for most of the channel regions except beyond the pinch-off point [6].

Since the total drain-to-source current, Ids, is the same at any point along the channel, the

hole current flux pointing inward the drain dot at a point (x, r) is

Figure 4.3 Top view of the ring MOSFET structure (left) and cross-sectional view of A-B (right) [5].

Isolation ring

Source ring

Gate ring

Drain Dot

A

B

Isolation ring

Source ring

Gate ring

Drain Dot

A

B

Dielectrics

A B

Gate

Drain Source

Metal Contacts

Dielectrics

A B

Gate

Drain Source

Metal Contacts

Weff

xi(r)

S G D G S

rx

w

r2r1

L

Ids

Weff

xi(r)

S G D G S

rx

w

rx

w

r2r1

L

Ids

Figure 4.4 Effective channel width extraction by applying the gradual channel approximation on a long-channel ring MOSFET [5].


97

( ) ( )dr

rdVrxpqrxJ pp

)(,, µ−≅ (4.1)

where q is the electronic charge, µp is the hole mobility, p(x, r) is the hole density in the

channel, and V(r) is the quasi-Fermi potential. By taking the circular symmetry, the total

current at a point r along the channel is then expressed by

( ) ( ) ( )( )

dxdr

rdVrxprqrIrx

pds

i

∫××=0

,2 µπ (4.2)

where xi(r) is the inversion layer thickness. We can also assume the µp can be taken

outside the integral by defining effective carrier mobility, µeff, at some average gate and

drain fields. The hole density is then integrated over the inversion layer giving the

inversion charge per unit gate area,

( ) ( )( )

dxrxpqrQrx

inv

i

∫×=0

, (4.3)

Eq. (4.2) becomes

( ) ( ) ( )VQdrdVrrQ

drdVrrI inveffinveffds ×××=×××= πµπµ 22 (4.4)

Multiplying both sides of Eq. (4.4) by dr/2πr and integrating from r1 to r2 (drain to source)

yield

( ) ( )∫∫ =

=

dsV

inveffds

r

r

ds dVVQrrIdr

rrI

01

2ln22

2

1

µππ

(4.5)

where Vds is the drain-to-source voltage. In the linear region,

( ) ( )VVVCVQ thgsoxinv −−= (4.6)

where Cox is the gate oxide capacitance, Vgs is the gate-to-source voltage, and Vth is the

threshold voltage. Therefore, the drain-to-source channel current is

( )

−−

= 2

1

221

ln21

dsdsthgsoxeff

ds VVVV

rr

CI

π

µ (4.7)


98

where the denominator represents the ratio of channel length, L, to Weff and Weff could be

expressed as

( )( )( )12

12

12 ln2

ln2

rrrr

rrLWeff

−== ππ (4.8)

Three different series of ring MOSFET structure have been designed and the

layout is listed in Table 4.1.

In the same mask set, MOS capacitor structures and various process test structures

(including four-point probe, van der Pauw, contact chains, six-point Kelvin contact,

transmission line tap resistor, cross-sectional scanning electron microscopy (XS-SEM)

structures) were also inserted to aid debugging if necessary.

4.2.2 Process Flow

The process flow for the fabrication of the metal gate high-κ p-MOSFETs below

400 °C is summarized here:

(i) Starting substrates

(a) 4”, (100) oriented, ~ 1×1016 cm-3 n-type Ge wafers

(ii) Surface cleaning (Section 2.3.3-2.3.4)

(a) Deionized (DI) water rinse or hydrofluoric acid (HF) vapor etch

(iii) High-κ dielectric deposition (Section 2.4.2)

(a) ~ 3.5-5.0 nm of zirconium oxide (ZrO2) formed by the ultraviolet ozone

oxidation (UVO) process at room temperature

(iv) Metal gate definition

(a) Optical lithography #1 for photoresist liftoff

(b) ~ 50 nm of platinum (Pt) deposited by electron beam evaporation

Series r1 (µm) r2 (µm) L (µm) Weff (µm) (i) 50 75-250 25-200 387-781 (ii) 50-225 250 25-200 781-1491 (iii) 25-100 125-200 100 390-907

Table 4.1 Different series of ring MOSFET layout.


99

(c) Photoresist liftoff of Pt in acetone

(v) Self-aligned source and drain implantation and activation (Section 3.2.1)

(a) 4×1015 cm-2 of 49BF2+ ions implanted at 35 keV and 7° tilt

(b) Organic clean in PRS1000

(c) Furnace anneal at 400 °C for 30 min in nitrogen (N2) ambient

(vi) Contact holes etch and metallization

(a) Optical lithography #2 for photoresist masking and liftoff

(b) Contact hole ZrO2 dry etch with chlorine-based chemistry

(c) ~ 75 nm of titanium (Ti) and ~ 100 nm of aluminum (Al) deposited by

electron beam evaporation as contact metals

(d) Photoresist liftoff of Al/Ti in acetone

(vii) Post-metallization anneal

(a) Organic clean in PRS1000

(b) Furnace anneal at 300 °C for 30 min in forming gas (H2/N2) ambient

As a minor note, the Pt gate electrode is not defined using dry etch due to the lack

of a selective etch recipe. Moreover, since no BEOL oxide layer is employed in this

simple process, the contact metal is self-aligned to the contact holes by photoresist liftoff.

From the cross-sectional high-resolution transmission electron micrographs (HR-TEM)

taken from a Pt/ZrO2/Ge p-MOSFET fabricated entirely below 400 °C (Fig. 4.5), no

degradation of the metal gate high-κ gate stack could be observed as compared to the

standalone MOS capacitors illustrated in Fig. 2.36.

Figure 4.5 Cross-section HR-TEM image taken from a fully processed Pt/ZrO2/Ge p-MOSFET with DI water rinsed Ge surface [5].

Pt

ZrO2

Ge


100

4.2.3 Device Characterizations

Output characteristics were measured on these Pt/ZrO2/Ge p-MOSFETs using the

HP4155A semiconductor parameter analyze r. Devices with drawn channel length of 2-

200 µm were all working and two typical measurements are shown in Fig. 4.6. The 2 µm

channel length device with 5.0 nm of ZrO2 deposited on HF vapor etched Ge surface (Fig.

4.6(a)) exhibits a reasonable turn-on behavior and relatively high Ids exceeding 100

µA/µm at 1 V of gate overdrive (Vgs-Vth). However, when the gate overdrive is reduced

to zero, a complete transistor turn-off becomes difficult. While the gate leakage current

was confirmed to be only a minor contribution, the transistor off-state leakage current

could also be supplied by the parasitic substrate bipolar transistor in parallel with the

MOSFET channel. In addition, the smaller bandgap and higher permittivity substrate

may make Ge to be more susceptible to short-channel effects like drain- induced barrier

lowering (DIBL) and Vth roll-off.

On the other hand, the 10 µm channel length device with 3.5 nm of ZrO2

deposited on DI water rinsed Ge surface (Fig. 4.6(b)) displays a slightly different

behavior. While the on-state drive current is still respectable, the non-zero crossing of Ids

at zero drain voltage hints the presence of substantial amount of gate leakage, which is

also responsible for the off-state leakage at zero overdrive. Apart from the physically

-2.0 -1.5 -1.0 -0.5 0.00

-10

-20

-30

-40

-50

Weff/L = 344.6 µm/10 µm

Vgs-Vth = 0 to -2.0 V

Pt/3.5 nm ZrO2/DI Water-Ge

Dra

in C

urr

ent

(µA

/µm

)

Drain Voltage (V)-2.5 -2.0 -1.5 -1.0 -0.5 0.00

-40

-80

-120

-160

Weff/L = 320.4 µm/2 µm

Vgs

-Vth

= 0 to -2.0 V

Pt/5.0 nm ZrO2/HF Vapor-Ge

Dra

in C

urr

ent

(µA

/µm

)

Drain Voltage (V)

(a)

Figure 4.6 Output characteristics of Pt/ZrO2/Ge p-MOSFET with (a) DI water rinsed and (b) HF vapor etched Ge surfaces prior to ZrO2 deposition [5].

(b)


101

thinner ZrO2 compared to that on the 2 µm channel length device, the larger gate

electrode area would be more prone to having pinholes in the ZrO2 layer and translate

into higher gate leakage.

Moreover, the un-optimized Vth (+0.5 V) for this batch of Ge p-MOSFETs causes

a high voltage stress to build up across the thin dielectric especially near the drain end.

For instance, a gate voltage of +0.5 V is required to deliver zero gate overdrive. Even at

drain bias of as low as -0.5 V, a potential difference of 1 V is instantly exercised across

the gate and drain terminals. This configuration may trigger un-desirable effects like

gate-induced drain leakage (GIDL) to compromise MOSFET off-state leakage.

Nevertheless, a much better turn-off would be expected with proper device scaling, i.e. a

thicker gate dielectric on a long-channel length device or a very thin dielectric on a sub-

micron gate length transistor, both with the correct Vth.

In order to estimate the effective hole mobility from these Pt/ZrO2/Ge p-

MOSFETs, Qinv was first computed by measuring the inversion capacitance (Cinv) from

the MOSFET structure using the HP4275A multi- frequency LCR meter (Fig. 4.7). The

relationship between µeff and effective electrical field (Eeff), however, could not be

extracted using the split capacitance-voltage (C-V) method [7] due to the poor turn-off

characteristics. Instead, by biasing the device into the deep linear regime (|Vgs| » |Vds|),

effective hole mobility could be approximated from Eq. (4.7)

-2 -1 00.0

0.5

1.0

1.5

2.0

2.5

Weff

/L = 387.4 µm/25 µmPt/5.0 nm ZrO

2/HF Vapor-Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)

Figure 4.7 Inversion capacitance measured at 400 kHz from a Pt/ZrO2/Ge p-MOSFET [5].


102

( ) dsthgsoxeff

dseff VVVCW

LI−

≈µ (4.9)

where Cox is conservatively chosen as the respective maximum Cinv (as in Fig. 4.7). Eeff

could be expressed as

+= invdep

Geeff QQE

311

ε (4.10)

with the depletion charge density

=

i

aBaGedep n

NTkNQ ln4ε (4.11)

where εGe is the Ge permittivity, Na is the substrate doping concentration, kB is the

Boltzmann’s constant, T is the absolute temperature, and ni is the intrinsic carrier

concentration.

To further minimize errors introduced by the gate leakage to the pure Ids

measurements for accurate µeff extraction, these Pt/ZrO2/Ge p-MOSFETs were operated

at gate and drain biases where the gate leakage is negligibly small (< 1%) compared to

either the measured drain current (ID) or source current (IS). Finally, µeff as a function of

Eeff from Pt/ZrO2/Ge p-MOSFETs with different Ge surface cleaning are calculated as

plotted in Fig. 4.8.

0.2 0.3 0.4 0.5 0.60

100

200

300

400

Si hi-κ pFET

25µm Ge hi-κ pFET (HFV) 25µm Ge hi-κ pFET (DIW) 30µm Ge hi-κ pFET (DIW) 100µm Ge hi-κ pFET (DIW)

Si UniversalMobility

Eff

ecti

ve M

ob

ility

(cm

2 /V-s

)

Effective Field (MV/cm)

Figure 4.8 Effective hole mobility versus effective E-field extracted from Pt/ZrO2/Ge p-MOSFETs with either DI water rinsed or HF vapor etched Ge surfaces prior to ZrO2 deposition. Mobility from the Si universal model [8] and a high-κ/Si p-MOSFET [9] are also included.


103

Since the effective hole mobility extracted from a limited number of devices

exhibits a slight distribution, no gate length dependence and no single preferential Ge

surface cleaning prior to high-κ dielectric formation could be identified. Even with the

same DI water rinsing methodology, mobility extracted from devices with different

channel length disperses a little. In any case, these Pt/ZrO2/Ge p-MOSFETs reveal

roughly 2-fold enhancement in hole mobility over the silicon universal mobility model

[8] and about 3 times higher mobility than that of high-κ/Si p-MOSFETs [9], both at low

E-field. With proper optimization of the device structure and fabrication process, it

should be possible to attain even higher effective mobility and lower leakage. For

instance, thin gate spacers together with source and drain extensions could be employed

to bring the metal contacts much closer to the channel to minimize parasitic resistances.

Recently, variants of this high-κ on Ge concept have been subsequently demonstrated in

Ge p-MOSFETs by other groups [10-11] showing similar results.

4.3 The Novel Self-Aligned Gate-Last Metal Gate High-κ

MOSFET Process 4.3.1 Structural Design

The choice of a simple self- isolated ring MOSFET structure (Section 4.2.1) could

provide us with a quick feedback on the performance of a new technology. Yet, a very-

large-scale- integrated (VLSI) like planar device configuration would be necessary to

show further feasibility from an integrated-circuit (IC) perspective. Very often, a direct

duplication of the Si process flow to integrate new materials may be difficult due to

various thermal and equipment compatibility issues.

For the sake of integrating metal gate and high-κ dielectric into Ge (and Si)

MOSFETs, a simple and novel low thermal budget self-aligned gate-last fabrication

process is therefore developed with features including planar geometry and field isolation

[12-13]. The key idea of this process is to selectively place a solid dopant source layer


104

above the MOSFET source and drain regions but not on top of the channel. Instead of

the conventional gate self-alignment by ion implantation, a source and drain self-

registration is now pursued by performing dopant out-diffusion from the solid source

layer. The schematic views of various process steps are captured in Fig. 4.9 and will be

discussed in greater details in the next section.

Ge Substrate

FOX

PSGLTO

FOX

PSGLTO

P-Well

ILD ILDMetal Metal

Ge Substrate

FOX

PSGLTO

FOX

PSGLTO

P-Well

Ge Substrate

FOX

PSGLTO

FOX

PSGLTO

P-Well

• Channel region screen oxidation to prevent auto-doping

• S/D formation by PSG out-diffusion using RTP

• RTN in NH3 at 600°C

• Conformal ALD of high-κ dielectric

• Metal gate formed by photoresist liftoff

• LTO deposited as the BEOL isolation ILD

• Contact hole etching (including LTO, PSG, & high-κ)

• Contact metallization

(c)

(d)

(e)

Ge Substrate

FOX

PSGLTO

FOX

PSGLTO

P-Well

Ge Substrate

FOX FOX

P-Well

(a)

• LTO/PSG deposition

• S/D definition using dry (90%) + wet (10%) oxide etching

• Field isolation (RTN + LTO)

• Screen oxidation

• P-Well implant

(b)

Figure 4.9 The simple and novel low thermal budget self-aligned gate- last fabrication process for integrating metal gate and high-κ dielectric into Ge (and Si) MOSFETs [12-13].


105

The resultant device structure is almost identical to the baseline planar Si

MOSFET in our laboratory; a major re-design of the existing mask set is not necessary.

The smallest geometry device in the layout has a drawn channel length of 1 µm.

4.3.2 Process Flow

The novel self-aligned gate- last MOSFET process flow for the fabrication of the

metal gate high-κ n-MOSFETs is summarized here:

(i) Starting substrates

(a) 3”, (100) oriented, ~ 2×1014 cm-3 p-type Ge wafers

(ii) Surface cleaning (Section 3.2.3)

(a) Cyclic rinsing between DI water and 50:1 HF acid (CHF)

(b) DI water rinse

(iii) Field isolation (Fig. 4.9(a))

(a) Ge oxynitride (GeOxNy) grown by rapid thermal nitridation (RTN) at

600 °C with 1 min soak time in ammonia (NH3) ambient (Section 2.3.5)

(b) ~ 500 nm of silicon dioxide (SiO2) deposited by low-pressure chemical

vapor deposition (LPCVD) at 400 °C (also known as LTO)

(iv) Active area definition and P-well formation

(a) Optical lithography #1 for photoresist masking

(b) SiO2/GeOxNy wet etch in 6:1 buffered HF solution

(c) Photoresist strip, organic clean in PRS1000, and CHF

(d) ~ 20 nm of screening germanium dioxide (GeO2) grown by thermal

oxidation at 550 °C in dry oxygen (O2) ambient

(e) 5×1012 cm-2 of 11B+ ions implanted at 150 keV and 0° tilt

(f) Organic clean in PRS1000 and screening GeO2 wet etch in CHF

(v) Source and drain definition (Fig. 4.9(b) and Fig. 4.9(c))

(a) ~ 200 nm of 8 wt.% phosphosilicate glass (PSG) and ~ 100 nm of SiO2

deposited by LPCVD at 400 °C


106

(b) Optical lithography #2 for photoresist masking

(c) SiO2/PSG dry etch in O2 plasma (90%) and then wet etch in 6:1 buffered

HF solution (10%)

(d) Photoresist strip, organic clean in PRS1000, and CHF

(e) ~ 5 nm of screening GeO2 grown by thermal oxidation at 500 °C in O2

ambient

(f) Source and drain doping by out-diffusion from the PSG layer using rapid

thermal processing (RTP) at 850 °C with 10 sec soak time in N2 ambient

(Section 3.3.1)

(g) Screening GeO2 wet etch in CHF

(vi) High-κ dielectric stack formation (Fig. 4.9(d)) (Section 2.3.5)

(a) GeOxNy grown by RTN at 600 °C with 1 min soak time in NH3 ambient

(b) ~ 4.5 nm ZrO2 and hafnium oxide (HfO 2) deposited by atomic layer

deposition (ALD) reaction at 300 °C

(vii) Self-aligned metal gate definition

(a) Optical lithography #3 for photoresist liftoff

(c) ~ 50 nm of platinum (Pt) deposited by electron beam evaporation

(b) Photoresist liftoff of Pt in acetone

(viii) Contact hole definition (Fig. 4.9(e))


(b) ~ 250 nm of SiO 2 deposited by LPCVD at 400 °C as the BEOL isolation

interlayer dielectric (ILD)

(c) Optical lithography #4 for photoresist masking

(d) Contact hole ILD/high-κ/SiO2/PSG dry etch in O2 plasma

(e) Photoresist ash in O2 plasma

(ix) Contact metallization


(b) ~ 500 nm of Al (with 1% Si) deposited by DC magnetron sputtering

(c) Optical lithography #5 for photoresist masking


107

(d) Al wet etch in Al etchant and Si freckle etch in sulfur hexafluoride (SF6)

plasma

(e) Photoresist strip

(x) Post-metallization anneal


(b) Furnace anneal at 400 °C for 45 min in H2/N2 ambient

This tailored 5- lithography level process was developed entirely using the Si

mainline equipment set in the Stanford Nanofabrication Facility (SNF), except the high-κ

ALD step, which was done in the Stanford Geballe Laboratory for Advanced Materials

(GLAM). The rationales behind some of the above process steps could however be quite

subtle. For instance, inserting the GeOxNy layer for field isolation (Step (iii)(a)) improves

the SiO2/Ge interfacial quality and suppresses device edge leakage, while depositing the

undoped SiO 2 above the PSG layer (Step (v)(a)) prevents auto-doping of the channel by

phosphorus (P) out-diffusion from the top surface. In addition, two screening Ge

oxidations are employed to either absorb the P-well implant damages (Step (iv)(d)) or

further prevent channel auto-doping from the PSG sidewall (Fig. 4.9(c)) during source

and drain formation (Step (v)(e)). No separate P-well dopant activation anneal is

required as this low dose implant (Step (iv)(e)) could well be activated during the

subsequent SiO 2/PSG deposition at 400 °C (Section 3.2.1). Moreover, a combination of

dry and wet etch of the solid dopant source layer (Step (iv)(e)) is intended to preserve the

channel length and simultaneously minimize any damage to the channel surface.

Furthermore, the Pt gate electrode is not patterned by dry etch (Step (vii)) due to the non-

existence of a selective etch whereas its alignment to the previous layer would not be

critical if sufficient overlapping to the source and drain fixtures (Fig. 4.9 (d)) is allowed.

4.3.3 Device Characterizations

Proof-of-concept Ge n-MOSFETs having either ZrO2 or HfO2 gate dielectric

together with Pt gate electrode were fabricated using this novel self-aligned gate-last


108

process [12]. Current-voltage (I-V) characteristics were measured on the MOSFET

source and drain to substrate diodes using the HP4155A semiconductor parameter

analyzer as illustrated in Fig. 4.10. Decent diode characteristics could be obtained even

though the associated on-and-off ratio is slightly less than that of the ion implanted n+-p

diodes [14], which could be attributed to the deactivation (RTN at 600 °C) of activated

dopants (RTP at 850 °C) within the junction (Section 3.3.2).

Reasonable P-well surface inversion is observed in n-MOSFETs from C-V

characteristics measured using the HP4275A multi- frequency LCR meter (Fig. 4.11).

The equivalent capacitance-based SiO 2 thickness (EOT) in inversion is extracted to be ~

2.2 nm, which is similar to the accumulation EOT obtained from the standalone MOS

-2 -1 0 1 210-8

10-6

1x10-4

10-2

100

W/L = 2 µm/2 µmPt/HfO2/GeOxNy/Ge

Source-to-Sub Diode Drain-to-Sub Diode

Dio

de C

urre

nt (A

)

Bias Voltage (V)

Figure 4.10 Source and drain to substrate diode I-V characteristics measured from a Pt/HfO2/GeOxNy/Ge n-MOSFET.

0.2 0.6 1.0 1.40.0

0.5

1.0

1.5

2.0

W/L = 20 µm/20 µmPt/HfO

2/GeO

xN

y/Ge

Gat

e C

apac

itan

ce (µ

F/c

m2 )

Gate Voltage (V)

Figure 4.11 Inversion capacitance measured at 400 kHz from a Pt/HfO2/GeOxNy/Ge n-MOSFET [12].


109

capacitor with an identical dielectric stack (Section 2.3.5). The slight discrepancy would

not stem from the typical poly-Si gate depletion effect as a metal gate is used, but due to

process variation between experiments. The feasibility of the novel process has been

confirmed with the functional metal gate Ge n-MOSFETs having channel length down to

1-2 µm (Fig. 4.12) with either ZrO2 or HfO2 dielectrics. The IS is displayed instead of ID

as the later appear to include a small amount of reverse-biased drain-to-substrate diode

leakage. The Vth are slightly different for the two devices owing to either a different

amount of fixed charge or some short-channel related effects.

0.00 0.25 0.50 0.75 1.000

2

4

6

8

W/L = 2 µm/2 µm

Vgs

= 0 to 1.5 V

Pt/HfO2/GeOxNy/Ge

So

urc

e C

urr

ent

(µA

/µm

)

Drain Voltage (V)0.00 0.25 0.50 0.75 1.000

2

4

6

8

W/L = 1.5 µm/1 µm

Vgs

= 0 to 1.5 V

Pt/ZrO2/GeO

xN

y/Ge

So

urc

e C

urr

ent

(µA

/µm

)

Drain Voltage (V)

(a)

Figure 4.12 Output characteristics of (a) Pt/ZrO2/GeOxNy/Ge n-MOSFET and (b) Pt/HfO2/GeOxNy/Ge n-MOSFET with 1-2 µm of channel length [12].

(b)

AlAl

nn++––GeGeGe channelGe channel

Pt gatePt gate

Figure 4.13 FIB XS-SEM Diagnostics.


110

The non-linearity of the output characteristics at low drain voltage indicates the

presence of a Schottky source and drain contact, which could be explained either by the

junction Al spiking, the poor coverage of Pt gate electrode near the channel edges, or the

loss of ohmicity due to dopant deactivation (Section 3.3.2), together with the presence of

high density of interface states (Section 2.2.6). Diagnostics were carried out by

dissecting the MOSFET using focused ion beam (FIB) followed by XS-SEM as shown in

Fig. 4.13. These images suggest that junction Al spiking is highly unlikely even though

this phenomenon is probabilistic in nature. Conversely, the Pt gate electrode is disclosed

to be lifted up near the channel edge possibly after the BEOL isolation ILD deposition,

and a better gate electrode metal should easily solve this problem. Together with a lower

thermal budget GeOxNy formation process prior to ALD of high-κ deposition, the dopant

deactivation issue could also be eliminated and lead to the real performance advantage of

metal gate high-κ Ge n-MOSFETs.

4.3.4 Advantages and Extensions of The Novel Process

With this simple low thermal budget self-aligned gate- last MOSFET process, the

stringent thermal stability requirement on the metal gate/high-κ dielectric stack during

dopant activation is relaxed, while serving the same purpose as the more- involved

replacement gate (Fig. 4.1) or damascene gate (Fig. 4.2) process. In addition, highly

selective etches of (i) the gate electrode metal versus the high-κ dielectric and (ii) the

high-κ dielectric versus the Ge substrate are no longer essential due to the presence of a

thick LTO/PSG buffer layer underneath (Fig. 4.9 (d)).

Figure 4.14 Extension of the novel process to incorporate LDD structures [12].

Ge Substrate

FOX

PSGLTO

FOX

PSGLTO

P-Well

LDDLower wt.% PSG inward spacer


111

Many useful device structures could also be derived by extending this innovative

process. For example, by incorporating a pair of lower wt.% PSG spacer inside the

channel opening region (Fig. 4.14) and performing the out-diffusion altogether, the

lightly doped drain (LDD) or shallow source and drain extensions could be formed self-

aligned to the deeper source and drain junctions. Additionally, complementary channel

MOSFETs could be realized by removing the PSG film from the p-MOSFET areas

followed by a blanket borosilicate glass (BSG) and then LTO layer deposition (Fig. 4.15).

Thus, complementary junctions for both n-MOSFET and p-MOSFET are readily formed

with a single RTP out-diffusion step.

Moreover, heavily-doped polycrystalline silicon germanium (Si1-xGex) alloys

could be employed instead of the insulating doped glasses as the solid source; out-

diffusion doping is carried out as usual. The resultant device structure would

automatically contain the doped Si1-xGex layer as the benign elevated source and drain

junctions (Fig. 4.16). However, a highly selective etch of the heavily-doped Si1-xGex

alloy versus the lightly-doped Ge channel substrate would then be required.

P-WellN-Ge Substrate

FOX

PSG

FOX

PSGBSGLTO

BSGLTO

N-MOSFET

N-Ge Substrate

FOX

BSGLTO

FOX

BSGLTO

P-MOSFET

Figure 4.15 Extension of the novel process to fabrication complementary channel MOSFETs [12].

Ge Substrate

FOX FOX

P-Well

Doped Si1-xGexDoped Si1 -xGex

Metal MetalILD ILD

Figure 4.16 Elevated source and drain junctions could be employed upon the replacement of the insulating solid dopant source with a doped Si1-xGex alloy [12].


112

Lastly, this versatile self-aligned gate- last process was also utilized to fabricate

metal gate Si MOSFETs to compare the candidate high-κ dielectrics from both the gate

leakage and MOSFET drive current perspectives [13].

4.4 Summary

In this chapter, we have investigated two low thermal budget processes to

fabricate Ge MOSFETs including a sub-400 °C metal gate high-κ p-MOSFET process

and a novel self-aligned gate- last metal gate high-κ MOSFET process. Both processes

were developed using the dielectric and junction technologies from the previous chapters.

Their individual structural design and process flow were proposed and the resultant

devices were characterized by C-V and I-V electrical measurements.

Since p-type dopant in Ge can be activated below 400 °C, metal gate high-κ Ge p-

MOSFETs can also be fabricated below 400 °C and demonstrate effective hole mobility

enhancement over the silicon universal mobility model and high-κ/Si p-MOSFETs. On

the other hand, functional metal gate high-κ Ge n-MOSFETs were built using the

innovative self-aligned gate- last process, which could be used as a technology vehicle to

expedite the evaluation of numerous novel materials integration for advanced MOSFET

applications.

Chapter 5. Conclusions

113

Chapter 5 Conclusions 5.1 Summary Drive current saturation in scaled Si MOSFETs is fundamentally limiting the

prospect of future scaling, which is believed to be limited by carrier injection velocity

from the source into the channel and carrier scattering in a short region near the

beginning of the channel. To overcome this scaling bottleneck and allow further

improvements on short-channel MOSFET drive current, an alternative MOSFET channel

material with high carrier mobility (and source injection velocity) should be incorporated.

As a material candidate that resides in the same group within the periodic table as Si, Ge

offers higher and more symmetric electron and hole mobility. In addition, its smaller

bandgap for supply voltage scaling together with lower processing temperature are highly

desirable. However, the unstable Ge native oxide for gate insulation and field isolation,

together with the high diffusivity and low solubility of n-type Ge dopants for source and

drain junction formation are the two classical problems that have obstructed CMOS

device realization in Ge for four decades.


114

First of all, three types of nanoscale gate dielectric for Ge MOS applications were

investigated including native Ge oxynitride, high-κ dielectrics formed by atomic layer

deposition, and high-κ dielectrics grown by ultraviolet ozone oxidation process. Their

synthesis together with various Ge surface preparations was first discussed. These

dielectrics were then physically and electrically characterized. Even though the Ge

oxynitride is relatively stable and could be scaled down to an equivalent SiO 2 thickness

of 1.9 nm, a sub-1.0 nm solution should still be necessary. Insertion of an interfacial Ge

oxynitride layer prior to high-κ ALD produces high quality Ge MOS capacitors with

however compromised scalability. Instead, sub-1.0 nm EOT high-κ/Ge gate stacks with

interfacial layer thickness as thin as 0.2-0.3 nm and excellent electrical characteristics

were demonstrated using a room-temperature UVO high-κ process, surpassing the high-

κ/Si gate stack EOT scalability bottleneck. When all these dielectrics were benchmarked

together, about 4-5 order of magnitude gate leakage reduction was obtained upon the

replacement of Ge oxynitrides and high-κ.

Moreover, two techniques to form shallow junction for Ge MOSFET applications

were investigated including ion implantation and solid source diffusion doping. Both

furnace anneal and rapid thermal anneal were studied to activate incorporated dopants.

Also, the activation and diffusion of various p-type and n-type dopants in Ge were

studied. Ion implanted p-type dopant in Ge can effectively be activated with negligible

diffusion at a temperature as low as 400 °C but the higher temperatures required to

activate ion- implanted n-type dopants would inherently cause fast extrinsic diffusion.

RTA was then employed to circumvent the problem and led to the demonstration of

symmetrically high activation level for both dopant types. In addition, rapid thermal

processing was utilized together with SSD doping to obtain shallow n+-p junctions in Ge.

By examining the thermal stability of the out-diffused dopants, phosphorus deactivation

in Ge was observed for the first time, possibly through the formation of small inactive

dopant-defect clusters.

Furthermore, two low thermal budget processes to fabricate Ge MOSFETs were

investigated including a sub-400 °C metal gate high-κ p-MOSFET process and a novel


115

self-aligned gate- last metal gate high-κ process. Both processes were developed using

the above dielectric and junction technologies. Their individual structural design and

process flow were proposed and the resultant devices were characterized by electrical

measurements. Metal gate high-κ Ge p-MOSFETs could be fabricated below 400 °C that

demonstrated effective hole mobility enhancement over the silicon universal mobility

model and high-κ/Si p-MOSFETs. On the other hand, functional metal gate high-κ Ge n-

MOSFETs were built using the innovative self-aligned gate-last process, which could be

used as a technology vehicle to expedite the evaluation of numerous novel materials

integration for advanced MOSFET applications.

5.2 Contributions and Impacts of This Work

Among others, many significant contributions were made throughout this work

including:

• Study of the scalability and stability of native Ge oxynitride dielectrics and the

effects of different Ge surface cleaning and passivation

• Seminal incorporation of high-κ gate dielectrics into Ge MOS devices

• 1st examination of high-κ/Ge interface using synchrotron radiation photo-

emission spectroscopy

• 1st benchmarking of native Ge oxynitrides with high-κ dielectrics

• 1st observation of dopant deactivation in activated Ge junctions

• Development of a novel self-aligned gate- last MOSFET fabrication process

• 1st demonstration of Ge p- and n-MOSFETs with metal gate electrode and

high-k dielectric down to 1-2 µm channel length

• Evaluation of the theoretical performance of futuristic MOSFETs using full

band Monte Carlo simulations


116

After this pioneering works on Ge surface passivation with high-κ dielectrics and

demonstration of mobility enhanced Ge p-MOSFETs was published, enormous industrial

and scientific interest was initiated in this area. In the emerging research device chapter

from the 2003 version of ITRS, Ge has been now identified as a material candidate for

the transport-enhanced FETs for high performance CMOS applications by citing our

work [1].

Simultaneously, this work has an equally profound impact on the international

scientific communities as revealed by the large number of archival publications that

referenced this work. These researches cover a broad spectrum of activities from

theoretical analyses [2-7] to experimental investigations [8-25].

5.3 Recommendations for Future Work

This work explores, demonstrates, and evaluates various advanced technologies

for high-performance Ge MOSFETs fabrication. In order to reveal the full performance

advantage in employing Ge into deeply scaled MOSFET structures, further research is

need in the following areas:

Figure 5.1 Snapshot of the emerging research device chapter from the 2003 version of ITRS [1].


117

• Low-cost Ge surface substrate development : ? Due to the much less

abundance of Ge and the brittle nature of Ge wafers, a low-cost and high-

quality Ge surface on Si substrate technology would be necessary to continue

the success of Ge-based devices and circuits. Ge epitaxial growth on Si using

techniques like compositional grading with Si1-xGex alloy [26] or

heteroepitaxial Ge growth followed by high temperature anneals [27] have

shown some initial promises; further research is required to better characterize

and perfect these layers.

• High-quality Ge-on- insulator (GOI) technology exploration: ? In order to

attain the confinement advantage while maintaining a good electrostatic

control over the MOSFET channel, a crystalline Ge thin film on insulator

technology is strongly desired. Budding technologies comprise Ge epitaxial

necking through SiO 2 via on Si [28], Ge epitaxial layer overgrowth by

molecular beam epitaxy [29], Ge condensation from Si1-xGex thin films on

insulator [30], liquid-phase epitaxy of Ge from Si seed holes [16], and various

Ge layer transfer techniques. Nonetheless, the demonstrated defect density

requires further suppression that mandates future research towards this

direction.

• Ge surface cleaning and preparation prior to gate dielectric formation: ?

Even though decent MOS capacitors have been demonstrated in this work, a

more systematic and Si CMOS compatible pre-gate cleaning recipe should be

developed with components like organic removal and surface metal gettering.

• Schottky source and drain contacts for Ge n-MOSFETs: ? Perhaps future

technological breakthroughs could allow fabrication of shallow n+ junctions in

Ge, the fundamentally lower n-type dopant solubility and higher diffusivity

may pose an ultimate limit. To circumvent the issue, future research to

employ Schottky source and drain contacts could be an alternate route over

the diffused approach.


118

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