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Aerospace and Defence
Forum 2016An Industry Event Hosted by National Instruments
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CI NIDays Europe150 day report out
New Technologies for Software Defined Radio
Aerospace and Defence
Forum 2016An Industry Event Hosted by National Instruments
3ni.com
SDR Target Markets & Applications
Utilities & Infrastructure
Medical Devices &
Internet of Things
Aerospace &
Defense
Automotive &
Car to Car
Communications & RF Identification
Primary Applications
Spectral Monitoring
Spectral Analysis
Signals Intelligence
Surveillance
Custom Radios
Communications Research
Land Mobile &
Safety Radio
Satellite Comms & Navigation
Education
4ni.com
SDR Architecture
CPU
GPP
FPGA
DSP
D/A
D/A
A/D
A/D
VCO
PLL
VCO
PLL
90
0
90
0
Host ConnectionDetermines Streaming Bandwidth
Ex. Gigabit E-net, PCIe
Multi-Processor SubsystemReal-time signal processor
• Physical Layer (PHY)
• ex FPGA, DSP
Host processor
• Medium Access Control (MAC) –Rx/Txcontrol
• ex. Host GPP, multi-core CPU
Baseband
Converters
RF Front End• General Purpose RF
• Dual LOs
• Contiguous Frequency Range
5ni.com
System Architecture
Windows MacOS LinuxEmbedded
Linux
Application
LabVIEW Custom GNURadioPython / GRC
The Mathworks ™
USRP N210
RF Board (WBX)
UHD DriverPortability Across Hardware, Interface, OS, and Dev. Environment
HardwareMotherboard
(FPGA, host connection)
RF board
Antenna
AntennaVERT400
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Software
7ni.com
Programming Approaches
Built-in Libraries
Deployment Targets
A Highly Productive Graphical Development Environment for Engineers and Scientists
Hardware APIs Custom User Interfaces
Technology Abstractions
8ni.com
Example: Spectrum Monitor
• NI-USRP LabVIEW Driver for Windows OS
• Modulation Toolkit & MathScript RT
• USRP2/ N200/N210 & all daughter boards
• Examples
• 8x8 MIMO OFDM link
• RF direction finding
• GPS simulation
• Spectrum monitoring
• Record & playback
9ni.com
LabVIEW Communications System Design SuiteThe Revolution in Rapid Prototyping
Hardware Software
Hardware Aware Design
Environment
Algorithm
Design
Languages
Design Exploration
In Product
Learning
Learning
10ni.com
LabVIEW CommunicationsOne continuous design flow that unifies the disparate design teams
Single, Cohesive Toolchain
System Mapping System ImplementationAlgorithm Development
Collaborative Design Team
Iterative
Modeling
Rapid
hardware
mapping
exploration
11ni.com
• History
• Experiment with ATSC Decoding in
Software
• Impetus for USRP – low cost
hardware
• Ettus Research – A Leading
Contributor
• Free and Open Source
• 1000’s of users
• Mailing List
• gnuradio.org
• Annual conference
GNU Radio Introduction
12ni.com
tb = gr.top_block()
src1 = gr.sig_source_f(32000, gr.GR_SIN_WAVE, 350,
.5, 0)
src2 = gr.sig_source_f(32000, gr.GR_SIN_WAVE, 440,
.5, 0)
adder = gr.add_ff()
sink = audio.sink(32000)
tb.connect(src1, (adder, 0))
tb.connect(src2, (adder, 1))
tb.connect(adder, sink)
tb.run()
GNU Radio Companion (optional)
int gr_add_ff::work(int noutput_items,
gr_vector_const_void_star &input_items,
gr_vector_void_star &output_items)
{
float *out = (float *) output_items[0];
int noi = d_vlen*noutput_items;
memcpy(out, input_items[0], noi*sizeof(float));
volk_32f_x2_add_32f_a(out, out, (const float*)input_items[i],
noi);
return noutput_items;
}
DSP Block – C++ Work Function
• Blocks
• Large library of existing IP -> Mod/demod,
filters, USRP I/O, GUI features, etc.
• Write custom blocks – C++ or Python
• GNU Radio Companion (optional)
• Import blocks
• Connect blocks
• Generate python source code for flowgraph
• Python Flow-Graph
• Generate from GRC and/or hand-write
• Simplifies block connectivity
Python Flow-Graph
GNU Radio Design Flow
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Applications
15ni.com
RECORD ANALYZE SIMULATE
1.Record and store up to 160 MHz of real signals
and impairments.
2.Play back and analyze
real-world spectrum for repeatable results.
3.Simulate all GNSS satellites
to test corner cases and future events.
Averna RP-6100 A Complete Validation Solution
for GNSS Receivers
17ni.com
Passive RADAR
Transceiver for Satellite Downlink
• Passive RADAR: DVB-T, UMTS
• Tow USRP N210s in MIMO Config.
• Tracking of ships and other vehicles
“Unlike other off-the-shelf options, the USRP family represents a
complete and versatile solution with software support that
accelerates development.”
Amerigo Capria, Lead Researcher
18ni.com
Tracking WiFi Signals to Passively See Through
Walls
The Challenge The Solution
Using NI USRP to lock onto a WiFi router, whilstsimultaneously monitoring the same WiFi signalsas they reflect off visually obscured moving targets.
Enabling undetectable surveillance, by monitoringmovement through walls, using the wireless signalsthat already swamp our urban airways.
19ni.com
Satellite Communication: ISEE-3 Rebooted After 36 Years
Launch: Aug 12, 1978
Contact: May 29, 2014Source: spacecollege.org
20ni.com
USRP Family
Bus
B2xx
Embedded
E3xx
Networked
N2xx
High Performance
X3xx
Frequency (Hz) 70 M – 6 G 70 M – 6 G DC-30M & 10M–6G DC-30M & 10M–6G
Bandwidth 56MHz (32 MHz in 2x2) 56MHz (32 MHz in 2x2) 40 MHz 160 MHz
Channels 2 Tx, 2 Rx 2 Tx, 2 Rx
w/ filter banks
1 Tx, 1 Rx 2 Tx, 2 Rx
RF Performance Good Good Better Best
Architecture Integrated RF Integrated RF RF Daughterboard RF Daughterboards
Communication USB Embedded 1GbE 10GbE or PCIe
MIMO Capability 2x2 2x2 Up to 2x2 2x2 to 256x256
LabVIEW Support Yes No Yes Yes
FPGA/CPU Spartan 6 Kintex 7 & ARM A9 Spartan 6 Kintex 7
NI Version USRP-290x None USRP-292x
USRP-293x
USRP-294x
USRP295x
S/W Ecosystem GNU Radio
C++
MatLab
Xilinx ISE
GNU Radio
C++
Xilinx Vivado
C Coder
HDL Coder
GNU Radio
C++
MatLab
Xilinx ISE
GNU Radio
C++
MatLab
Xilinx Vivado
Simulink
C Coder
HDL Coder*Same Daughterboard in each slot
21ni.com
SDR Architecture – Desktop
CPU
GPP
FPGA
DSP
D/A
D/A
A/D
A/D
VCO
PLL
VCO
PLL
90
0
90
0
Host ConnectionDetermines Streaming Bandwidth
Ex. Gigabit E-net, PCIe
Multi-Processor SubsystemReal-time signal processor
• Physical Layer (PHY)
• ex FPGA, DSP
Host processor
• Medium Access Control (MAC) –Rx/Txcontrol
• ex. Host GPP, multi-core CPU
Baseband
Converters
RF Front End• General Purpose RF
• Dual LOs
• Contiguous Frequency Range
Desktop
22ni.com
X Series•Two wideband RF daughterboard slots (2x2 MIMO)
•Up 160 MHz bandwidth per channel
•Selection covers DC to 6 GHz
•ADC – 200 Ms/s, 14 bit resolution
•DAC – 800 Ms/s, 16 bit resolution
•Large, customizable Kintex-7 FPGA
•USRP X300 - XC7K325T
•USRP X310 – XC7K410T
•UHD architecture provides compatibility:
•GNURadio
•C++ API/Python
•Other third-party frameworks & applications
•Multiple high-speed interfaces
•Dual SFP(+) ports for 1/10 Gigabit Ethernet
•PCIe x4
•Flexible clocking architecture
•Configurable sample clock
•Optional GPS-disciplined OCXO
•Coherent operation with 10 MHz/1 PPS
•Compact and rugged half-wide 1U form factor
USRP X-Series
Front
Back
Applications• Advanced Wireless Prototyping
• Massive MIMO Applications
• Passive RADAR
• Signals Intelligence
23ni.com
UBX
• 10 MHz to 6 GHz
• Full duplex transceiver
• Synthesizer synchronization for phase aligned applications
• 40 MHz on N200, 160 MHz on X300
• Full shield, high dynamic range
• Excellent performance – 8dB NF @ +5dBm IP3
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Twin RXPre-Release Information
25ni.com
What is the Twin RX?
• Frequency coverage from 10 MHz to 6 GHz
• 80 MHz of instantaneous bandwidth on two channels
• In a single X300 or X310 you can accommodate 2 TwinRX modules, giving 4 channels of phase coherent
measurements for DF
• Ettus’ first superheterodyne design with residual spurious performance better than -100 dBm
Target Applications:
• Direction Finding
• Spectrum Monitoring
• SIGINT/COMINT
• Time Difference of Arrival (TDOA)
27ni.com
2 TwinRX Daughtercards inside X310
4 RX channels total with LO Sharing
28ni.com
SDR Architecture – Embedded/Deployed
CPU
GPP
FPGA
DSP
D/A
D/A
A/D
A/D
VCO
PLL
VCO
PLL
90
0
90
0
Host ConnectionDetermines Streaming Bandwidth
Ex. Gigabit E-net, PCIe
Multi-Processor SubsystemReal-time signal processor
• Physical Layer (PHY)
• ex FPGA, DSP
Host processor
• Medium Access Control (MAC) –Rx/Txcontrol
• ex. Host GPP, multi-core CPU
Baseband
Converters
RF Front End• General Purpose RF
• Dual LOs
• Contiguous Frequency Range
Embedded
29ni.com
Specs
• Frequency Range: 70MHz - 6 GHz, 10dBm power output
• 2x2 MIMO standard configuration
• ~ 50 MHz BW / channel
• Xilinx Zynq-7020
• ARM Dual-Core Cortex A9 @ 667MHz
• 1GB MB Processor RAM
• 512 MB FPGA RAM
• 120x90x50 mm, 375g
• 3-9 W
Features
• I/O: GigE, Audio in/out, USB 2.0 Host, GPS In
• Micro SD memory card slot
• 10-axis IMU
• 3-axis MEMs Gyro, Accelerometer & Magnetometer
• Barometric Altimeter
• GPS Receiver
USRP E-Series Overview
Applications
• Mobile network research
• Network testbeds
• Small, portable, low cost spectrum
monitor
• Small UAVs
• Handheld universal communicator
Derivatives
• E313 - Waterproof - IP67
• E330 -4 Rx to TDOA/DF Applications
• E310OEM - OEM/Unboxed
• E312 -Battery
30ni.com
E313 IP67 Enclosure
Power Over Ethernet
(POE) DC-DC Lightning Protection
E310 or E312 Thermally Connected to
Enclosure
31ni.com
E312 Battery
• Battery life powered down ~160 hours
• Battery life on idle ~5:30
• Battery life on full load (1x1 TX/RX @5GHz, 1MHz, 100%) ~2:20
• Battery life on full load (2x2 TX/RX @5GHz, 1MHz, 100%) ~1:45
• Battery charge time to full ~2:00
32ni.com
B200Mini
• Small form-factor SDR • 1x1, 56MHz IBW
• USB 3.0 mini-B, bus powered
• Tx/Rx & Rx2 Antennas
• Spartan 6 LX75
• B200 driver
• RefCLK/PPS Input
• 89 × 55 mm (3.5 × 2.17 in)
• Enclosure (Optional)
• Extended Temperature (Optional)
XILINX Spartan6 LX75
USB 3.0
Type B Mini
Connector
USB 3.0
PHY
(FX3)
UHD Transport
Control Time
Sync
TX_DSP_0
TX_DSP_1
Analog
Devices
Integrated
RFIC
AD-9364
System
Clock &
Timing
SMA
EXT_REF
SMA
RFA TX/RX
SMA
RFA RX
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RF Network-on-Chip (RFNoC)
34ni.com
Example: Wideband Spectral Analysis
• Simple in Theory: 200 MHz real-time, Welch's Algorithm
Highly parallelizable operations, basic math
=> Ideal to shift to FPGA
Transport: Overloaded
FPGA:
Underutilized
35ni.com
Goal
• Heterogeneous Processing
• Support composable and modular designs using GPP, FPGA &
beyond
• Maintain ease of use
• Tight integration with popular SDR frameworks
FPGA
Processing
GPP
Processing
36ni.com
FPGA
Processing
GPP
Processing
Goal
• Heterogeneous Processing
• Support composable and modular designs using GPP, FPGA &
beyond
• Maintain ease of use
• Tight integration with popular SDR frameworks
37ni.com
RFNoC Architecture
User Application – GNU Radio
Crossbar
Ingress Egress Interface
USRP Hardware Driver
Radio Core
HO
ST P
CU
SRP
FPGA
Computation
Engine
Computation
Engine
38ni.com
USRP Hardware Driver
Crossbar
Ingress Egress Interface
RFNoC Architecture
User Application – GNU Radio
Radio Core
HO
ST P
CU
SRP
FPGA
FFTComputation
Engine
39ni.com
Computation Engine
Crossbar
FFT
FIFO FIFO
Packetizer
Xilinx FFT IP
Radio Core
Depacketizer
FIFO FIFO
RX DSP
RX Sample Data
To Host PC
TX DSP
DepacketizerPacketizer
AXI-Stream
40ni.com
Many Types of CEs
• Many computation engines
• Not limited to one crossbar, one device• Scales across devices for massive distributed processing
Crossbar
Radio Core FFT FIR Demodulator
Crypto CoreCompression
DecompressionChannelization
To Other RFNoC Capable Device
41ni.com
Summary
• Introduction to Software-Defined Radio (SDR)
• Applications of SDR in Aerospace and Defence
• Passive Radar
• GNSS Record and Playback
• Satellite Communications
• SDR Hardware Options
• From board-only to battery-powered to multi-Rx
• System Design Software Options
• LabVIEW Communications System Design Suite
• RF Network-on-Chip (RFNoC)
ni.com
Questions?
