Agile Hardware Design: Building Chips with Small Teams · 2017-12-19 · •Agile Validation: Did we build the right thing? •On-demand FPGAs (e.g., Amazon F1) will play big role

© 2017 SiFive. All Rights Reserved.

Agile Hardware Design:Building Chipswith Small Teams Yunsup LeeASPIRE Graduate 2016Co-Founder and CTO

2 © 2017SiFive.AllRightsReserved.

World’s FirstSingle-Chip

MicroprocessorThat Communicates Directly Using Light


Mem

ory

cont

rolle

r

PD

50/50 Power SplitterPD

Transmitter

Transmitter

Receiver

Receiver

Inte

rface

RIS

C-V

pro

cess

or

1MB

mem

ory

bank

Chip (Processor mode) Chip (Memory mode)

Processor to memory link

Command + address + write data

Memory to processor link

read data

Opticalamplifier

Opticalamplifier

Laser

Single-mode fiber

1MB memory bank (inactive)

RISC-V processor (inactive)

Control FPGA

Electrical bus


How did we build working microprocessors with

such a small team?








But there werethe unknown unknowns

along the way…


Connects to Pad

Pad Output Drivers

Termination Resistor

“Wait, why

are all outputs floating?

”


ToPad

PadOutputDrivers

Dude, where’s my Termination Resistor??

Output drivers not connected to pad!!!

LVS check doesn’t catch

problems when the

“S” is incorrect


VDDDecouplingCaps

I/O VDDDecouplingCaps

Analog VDDDecoupling

Caps

Decoupling Caps are Too Far Away!



SpecificationDesign

Implementation

C++

FPGA

ASIC flow

Tape-in

Small tape-out

Big tape-out

Agile Hardware Design


!RocketChip

18

10+ Tapeouts at Berkeley

© 2017SiFive.AllRightsReserved.

Raven-1 Raven-2Raven-3

EOS14 EOS16 EOS18 EOS20

2011 2013 2014 20152012May Apr Aug Feb Jul Mar Nov

EOS22

Raven3.5

Mar AprSep

EOS24

SWERVERaven-4


Enabling Small Teams to Build Custom Silicon

20

Custom Silicon For All

• We contribute to the open-source Freedom SoC platform based on RISC-V and open-source infrastructure

• We build customized Freedom SoCs as a service, which is quick, easy, and predictable at low upfront cost

ProductRequirements Fabs

3rd Party IPEDA ToolsPackaging/TestLogistics

SystemDesigner

CustomFreedom SoCs

Chip Design Factory



Freedom Everywhere SoCsLow power, 32-bit microcontrollers

22

Freedom E310

• First RISC-V based SoCbased on the Freedom Everywhere SoC platform

• Target markets: IoT, Wearables, Embedded

• Low-power, low-cost, high-performance

• Open-source software and tools support

23

Freedom E310 Chip Block DiagramFirst RISC-V SoC based on the Freedom Everywhere SoC platform

FE310-G000 Chip GPIO Complex

Always-On Domain

P-Bu

s: T

ileLi

nk B

32 D

32

QSPI0

Real-Time Clock

Platform-Level Interrupt Control

TAPCDebug Module

Debug RAM (28B)

Instruction Fetch

RV32IMAC

Branch Prediction

Inst. DecompressorInstruction Buffer

M

MLoad/Store

dip

eip

lip

Instruction Cache(16KiB, 2-way)

Instruction Cache Refill M

OTP (8KiB)

Data SRAM (16KiB)

UART0

QSPI1

M

JTAG1.8V AON Core

erst_n

QSPI Flash

GPIO

Multiplier/Divider

Watchdog

Coreplex-Local Interrupt Control

Real-Time Clock Ticks

Backup RegistersPMU

Reset Unit

dwakeup_n

1.8V AON Pads

vddpaden

LFROSC

psdaon*

Mask ROM (8KiB)

Clock Generation

HFXOSC

PLL

HFROSC

vddpllvsspllhfxoscinhfxoscout

UART1PWM0 (16-bit)PWM1 (8-bit)

QSPI2

C-Bu

s: T

ileLi

nk B

32 D

32

A-Bu

s: T

ileLi

nk B

4 D3

2

M

hfclkrst

rtccmpip

wdogcmpip

Global Interrupts

1.8V MOFF Core3.3V MOFF Pads

psd*

E31 Coreplex

Core Reset Sync corerst

• 320+ MHz SiFive E31 CPU• 1.61 DMIPS/MHz• 16KB L1 I$• 16KB Data Scratchpad• Hardware Multiply/Divide• Debug Module• Multiple Power Domains• Low Power Standby• Wide Range of Clock

Inputs• TSMC180G• 6mmx6mm 48-Pin QFN


24

Freedom E310 Chip~6mm2 in TSMC 180nm


25

HiFive1: Arduino-Compatible RISC-V Dev KitPowered by the Freedom E310 chip

• Operating Voltage: 3.3 V and 1.8 V

• Input Voltage: 5 V USB or 7-12 VDC Jack

• IO Voltages: Both 3.3 V or 5 V supported

• Digital I/O Pins: 19

• PWM Pins: 9

• SPI Controllers/HW CS Pins: 1/3

• External Interrupt Pins: 19

• External Wakeup Pins: 1

• Flash Memory: 128 Mbit Off-Chip (ISSI SPI Flash)

• Host Interface (microUSB): Program, Debug, and Serial Communication$59, https://www.crowdsupply.com/sifive/hifive1



Freedom Unleashed SoCs64-bit multi-core SoCs for embedded computing

27

Freedom U500 Base Platform Block DiagramTSMC 28nm Chip for Rapid Customization of the Freedom Unleashed Platform

• U54-MC Coreplex• Single- and Double-

precision floating-point support

• Banked L2$ with directory-based cache-coherence

• Modern OS support

• ChipLink• Serialized Chip-to-

Chip TileLinkInterconnect

• GbE• Peripherals• DDR3/4

U54-MC Coreplex

Platform-Level Interrupt ControlBoot ROM

Debug Module

TileLink Switch

DDR3/4 Controller/PHY

ChipLink

GbE

E51 Core 0

RV64IMACL1 I$

SRAM

Tile

Link

Sw

itch

Clock Generation

Quad SPI

TileLink Coherence Manager

M

M

U54 Core

RV64GC16KiB L1 I$

16KiB L1 D$

U54 Core

RV64GC16KiB L1 I$

16KiB L1 D$

U54 Core

RV64GC16KiB L1 I$

16KiB L1 D$

U54 Core 1-4

RV64GCL1 I$

L1 D$

Banked L2$

Tile

Link

Sw

itch

SD Card

Mask ROM

Clock/Reset Control

GPIOUARTI2CSPI

OTP

FPGA

PCIe/USB/MIPI

ChipLink

TileLink

TileLink Switch

YourIP Block

JTAG

FU500 Base Platform


28

Freedom U500 Base Platform Chip

• 250M transistors

• 1.5 GHz+ SiFive E51/U54 CPU• 1x E51: 16KB L1I$ and 8KB DTIM• 4x U54: 32KB L1I$ and 32KB L1D$

• ECC support

• Banked 2MB L2$• ECC support

• TSMC 28HPC

• FCBGA package

• Development board available in Q1 2018

~30mm2 in TSMC 28nm

U54

U54

U54

U54

E51

L2$

DDR

GbE

Ch

ipLi

nk

OTP


29

What’s Next?

• Agile Verification: Did we build the thing right?• What role does Chisel/FIRRTL play?• Formal verification methodology on the horizon

• Agile Validation: Did we build the right thing?• On-demand FPGAs (e.g., Amazon F1) will play big role• High-fidelity emulation will become more important

• Agile Analog Design• How do we write portable Analog design?

• Enabling agile hardware design will spur innovation!

Taking Agile Hardware Design to the Next Level


Documents

Agile Hardware Design: Building Chips with Small Teams · 2017-12-19 · •Agile Validation: Did we build the right thing? •On-demand FPGAs (e.g., Amazon F1) will play big role