AIDA ASIC reviewDavide Braga

Steve Thomas

ASIC Design Group

11 February 2009

11 February 2009 AIDA ASIC review 2

Top level – final version

Analogue inputs left edge

Control/outputs right edge

Power/bias top and bottom

Most bias lines have two pads, with optional capacitors to gnd / Vdd

11 February 2009 AIDA ASIC review 3

Bias voltage generation

Externalcapacitor

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Module wire bonding examples

Staggered, two-rowbonding

Tracks mostly with vertical orientation

Single-line, parallel bonding

Tracks with vertical orientation

Multiple bond wire lengths

Power/bias lines horizontally

Control signals/outputs vertically

11 February 2009 AIDA ASIC review 5

Bond-wire parasitics:Bond-wire capacitance across chip:

C=L/cosh-1(a/d)

a=~7mm,d~25m, L~1mm

which gives C~4fF

Injected charge Q=CV~12fC=75ke for single wire

“Dummy” wires have opposite polarity signals. Electric field drops as r2 for a dipole, giving much lower coupling capacitance

Dummy signals should to be bonded out, but tracks do not necessarily need to be routed any distance on the module.

~7mm

~2mm

Charge injection

11 February 2009 AIDA ASIC review 6

Differential outputs

Digital outputs driven differentially from two pads

Clock signal into pad, inverted signal driven out

Analogue outputs: single-ended drive,reference pad has static voltage. No differentialCancellation.

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Future work:•Updates of documentation (pad definitions, functions, waveforms).•Preparation for testing – adapter board, waveform definitions, IMS chip tester interfacing.•Test report, including defining the optimal waveforms and analogue bias point.•Module floor-planning, capacitor selection, track resistance analysis.

Time-scales:•Delivery of 100 ASICs : 20th April

•Bonding into 40-pin dual-in-line packages: 1 week

•Bonding onto modules: 1 week

•Preliminary testing: 2 weeks

•Waveform optimisation: 2 weeks

•Bias optimisation: 2 weeks