AIM: Design of a Seven-Segment display using IC-7447snmgaya.weebly.com/uploads/2/6/9/4/26948220/digital... · Web viewDesign of a 2 bit binary parallel adder using IC CD4030 and IC

EC 4102 : DIGITAL ELECTRONICS LABORATORY

LIST OF EXPERIMENTS:

COMPULSORY EXPERIMENTS:

1. Design and realization of Parity bit checker using IC 7486

2. Design and realization of 4:2 line encoder using IC 7432

3. Design and realization of 4-bit magnitude comparator using IC 7485

4. Assembling of a seven segment decoder using IC 7447 and IC 7404

5. Design and testing of SR and JK Flip-flop using IC 7400 & IC 7402

6. Design of a 2 bit binary parallel adder using IC CD4030 and IC CD4081

7. Design of an Astable Multivibrator (using IC 555 Timer) and observe the output waveforms

8. Design of an Monostable Multivibrator (using IC 555 Timer) and observe the output waveforms

9. Design and testing of 2 : 1 multiplexer and CMOS switch using IC CD4066

10. Design of a 4 bit serial in serial out shift register using IC CD4027 and 555 timer

11. Design of a Modulo-9 ripple counter using IC CD4029 and IC CD4091

12. Design of a Schmitt Trigger Circuit (using IC 741 OPAMP) & observation of the output waveforms.

OPTIONAL EXPERIMENTS:

13.i. Design and realization of Binary to Gray code converter using IC 7486

ii. Design and realization of Gray to Binary code converter using IC 7486

14. Design of an EX-OR gate using minimum number of 2 input NAND gates IC7400

15. Design and realization of an odd parity generator using IC7486

16. Design of a 1 bit half substractor using IC CD4066

17. Design and realization of 4:16 Decoder using 1:4 De-multiplexer

18. Design of a modulo 256 ripple counter using IC7493

19. Design of a 4 : 16 line decoder using IC CD4514

20. Reading 8 specified address location of a programmed IC Intel 2716

21. Storing a nibble in an IC 2114 RAM and read it.

DEPARTMENTOF

ELECTRONICS AND COMMUNICATION ENGINEERING

DIGITAL ELECTRONICS LABORATORYORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

ON

DESIGN AND REALISATION OF A PARITY BIT CHECKER USING IC 7486

BIRLA INSTITUTE OF TECHNOLOGY

MESRA RANCHI

AIM: Design and realization of Parity bit checker using IC 7486

APPARATUS REQUIRED:

1. Wish Board2. D.C. Power supply

Or Trainer Kit (MicroLABORATORY-II)

CIRCUIT COMPONENTS:

1. IC74862. Connecting Wires3. LED with resistors

PIN DIAGRAM:

G PIN DIAGRAM OF IC 7486

QUAD 2 INPUTS EX-OR GATE

THEORY:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.2. Before switching ON Power Supply, make sure that the connections are

correct.3. Apply the input logic as per Truth Table in terms of +5 volts for state-1 and 0

volts for state-0.4. Observe the output states.5. Verify the result of truth ness.6. Repeat steps from 3 to 5 for all possible combinations.

FUNCTION TABLE:

Sr. No INPUTS PCX Y Z P

1 0 0 0 02 0 0 0 0345678

RESULT:

PRECAUTIONS:

DEPARTMENTOF


DIGITAL ELECTRONICS LABORATORY


ON

DESIGN AND REALISATION OF A 4:2 LINE ENCODER USING IC-7432

BIRLA INSTITUTE OF TECHNOLOGYMESRA RANCHI

AIM: Design and realization of 4:2 line encoder using IC 7432

APPARATUS REQUIRED:

1. Wish board2. D.C. power supply Or

Trainer Kit (MicroLABORATORY-II)

CIRCUIT COMPONENT:

1. IC 74322. Connecting Wires3. LED with resistors

PIN DIAGRAM:


QUAD 2 INPUTS OR GATE

THEORY:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.2. Before switching ON power Supply, make sure that the connections are

correct.

3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0 volts for state-0.

4. Observe the Output state.5. Verify the result of truthness.6. Repeat steps from 3 to 5 for all possible combination.

FUNCTION TABLE:

INPUT OUTPUTD0 D1 D2 D3 X Y1 0 0 00 1 0 00 0 1 00 0 0 1

RESULT:

PRECAUTIONS:

DEPARTMENTOF




ON

DESIGN AND REALISATION OF A 4-BIT MAGNITUDE COMPARATOR USING IC-7485


AIM: Design and realization of 4-bit magnitude comparator using IC 7485

APPARATUS REQUIRED:

1. Wish board2. D.C. power supply Or


CIRCUIT COMPONENT:


PIN DIAGRAM:

THEORY:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.2. Before switching ON power Supply, make sure that the connection are

correct.3. Apply the input logic as per Truth table in terms of +5 volts for state-1 and 0

volts for state-0.4. Observe the Output state.5. Verify the result of truthness.6. Repeat steps from 3 to 5 for all possible combination.

FUNCTION TABLE:

Sl. No.

A B A>B A<B A=BA3 A2 A1 A0 B3 B2 B1 B0

1 0 1 1 1 0 0 1 1 1 0 02 0 1 1 0 0 1 1 0 0 0 13 1 0 0 0 1 1 0 0 0 1 04 1 1 0 0 1 1 0 0 0 0 1567

RESULT:

PRECAUTIONS:

Fig. four bit magnitude comparator using IC 7485

DEPARTMENT

OFELECTRONICS AND COMMUNICATION ENGINEERING



ON

ASSEMBLING OF A SEVEN SEGMENT DECODERUSING IC 7447 AND IC 7404


MESRA RANCHI

AIM: Design of a Seven-Segment display using IC-7447 & 7404

APPARATUS REQUIRED:

1. Wish Board2. D.C. Power Supply

OrTrainer Kit (MicroLABORATORY-II)

CIRCUIT COMPONENT:

1. IC 7447 & IC 74042. Connecting Wires3. Seven Segment display IC-LT543

PIN DIAGRAM:

G PIN DIAGRAM OF IC 7404 HEX NOT GATEQuad 2-in

puts NOR GATE


BCD TO 7 SEGMENT DISPLAY DRIVER

The appropriate outputs a-g become low to display the BCD (binary coded decimal) number supplied on

inputs A-D. The 7447 has open collector outputs a-g which can sink up to 40mA. The 7-segment display

segments must be connected between +Vs and the outputs with a resistor in series (330 with a 5V

supply). A common anode display is required.

Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light (showing number 8).

If the blank input is low the display will be blank when the count input is zero (0000). This can be used to

blank leading zeros when there are several display digits driven by a chain of counters. To achieve this

blank output should be connected to blank input of the next display down the chain (the next most

significant digit).

The 7447 is intended for BCD (binary coded decimal) which is input values 0 to 9 (0000 to 1001 in binary). Inputs from 10 to 15 (1010 to 1111 in binary) will light odd display segments but will do no harm

THEORY:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.2. Before switching ON power supply, make sure that the connection are correct.3. Apply the input logic state code mentioned in observation Table in terms of

+5 volts for state-1 and 0 volts for state-0.4. Observe the output states.5. Verify the displayed digit with decimal equivalent of applied input binary

code.6. Repeat steps from 3 to 5 for all possible combination.

OBSERVATION TABLE:

Note: Show the combined output of seven-segment display in observation.

S. No.

BINARY CODE a b c d e f g Displayed DigitA3 A2 A1 A0

12345

RESULT:

PRECAUTIONS:

DEPARTMENTOF




ON

DESIGN AND TESTING OF SR AND JK FLIP-FLOP USING IC 7400 & IC 7402


AIM: Design and testing of SR and JK Flip-flop using IC 7400 & IC 7402

APPARATUS REQUIRED:

1. Wish board2. D.C. power supply

OrTrainer kit (MicroLABORATORY-II)

CIRCUIT COMPONENT:

1. IC7400, IC74022. Connecting wires3. LED with resistor

PIN-DIAGRAM:

PIN DIAGRAM OF IC 7400

4 2-INPUTS NAND GATE


QUAD 2 INPUTS NOR GATE

7402

THEORY:

PROCEDURE:1. Connect the circuit as shown in the circuit diagram.2. Before switching ON power Supply, make sure that the connection are

correct.3. Apply the input logic state as per Truth table / Function table in terms of +5

volts for state-1 and 0 volts for state-0.4. Observe the output state.5. Verify the result of truth ness.6. Repeat steps from 3 to 5 for all possible combination.

FUNCTION TABLE:

(a) Testing of the Characteristic table of SR Flip-flop

Sr. No. Present stateQn

S R Next State

Qn+1 Q’n+1

1 0 0 02 0 0 13 0 1 04 0 1 15 1 0 06 1 0 17 1 1 08 1 1 1

(b) Testing of the Characteristic table of JK Flip-flop

Sr. No. Present stateQn

J K Next State

Qn+1 Q’n+1

1 0 0 02 0 0 13 0 1 04 0 1 15 1 0 06 1 0 17 1 1 08 1 1 1

RESULT:

PRECAUTIONS:

DEPARTMENTOF




ON

DESIGN OF A 2 BIT BINARY PARALLEL ADDER USING IC CD4030 AND IC CD4081


AIM:- Design of a 2-bit binary parallel full adder using IC CD4030 and IC CD4081.

APPARATUS REQUIRED:

1. IC CD4030 & IC CD40812. MICROLABORATORY KIT3. Connecting wires

PIN DIAGRAM


QUAD 2-INPUT EXOR GATE

I PIN DIAGRAM OF IC 4081

QUAD 2-INPUT AND GATE

THEORY: A Full Adder is a combinational circuit that performs the sum of three input bits Ai, Bi, and Ci. It consists of three inputs and two outputs. Ai, Bi are bits of 2 n bit numbers and C represents the carry from the previous lower significant position. The two output’s are Si (Sum) and Ci+1 (Carry).

A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. It consists of full adders connected in cascade, with the output carry from one full adder connected to the input carry of the next full adder.

PROCEDURE:

1. Connect the circuit a shown in fig.2. Take all possible combination of two 2-bit numbers

OBSERVATION TABLE:

A2 A1 B2 B1 S1 C2 S2 C3

RESULT:

PRECAUTIONS:

B2 A2 B1 A1

C3 C2 C1

S2 S1

BLOCK DIAGRAM OF A 2 BIT BINARY PARALLEL FULL ADDER

F.A.F.A.

DEPARTMENTOF




ON

DESIGN OF AN ASTABLE MULTIVIBRATOR (USING IC 555 TIMER) AND OBSERVE THE OUTPUT

WAVEFORMS


AIM: - Design of an Astable Multivibrator (using IC 555 Timer) and observe the output waveforms.

APPARATUS REQUIRED:

1. Wish board2. D.C. Power Supply Or Trainer Kit.3. C.R.O.

CIRCUIT COMPONENTS:

1. IC 5552. Capacitor (0.01F)3. Resistors4. Connecting wires

PIN DIAGRAM OF THE 555 TIMER

Functions of pins:

1. Ground: All voltages are measured with respect to this terminal.2. Trigger: It is the external input that will be applied to the inverting input of the lower comparator & will be compared with Vcc/3 coming from the potential divider network.3. Output: Complement of the output of the flip-flop acts as the final output of timer as it passes through a power amplifier with inverter. Load can either be connected between pin 3 & ground or pin 3 & Vcc.4. Reset : This is an input to the timing device which provides a mechanism to reset the flip-flop in a manner which overrides the effect of any instruction coming to the FF from lower comparator. This is effective when the reset input is less than 0.4V.When not used it is returned to Vcc.5. Control Voltage input: Generally the fixed voltages of 1/3Vcc & 2/3Vcc also aid in determining the timing interval. The control voltage at 5 can be used when it is required to vary the time & also in such cases when the reference level at V- of the UC is other than 2/3Vcc.Generally when not used a capacitor of 0.01uF should be connected between 5 & ground to bypass noise or ripple from the supply.

Threshold

Control voltage

Discharge

outputIC 555

+ VccGND

Trigger

Reset

6. Threshold: An external voltage by means of a timing capacitor & resistor is applied to this pin. When this voltage is greater than 2/3Vccoutput of UC is 1 which is given to the set input of FF thereby setting the FF making Q=1 & Q=0.7. Discharge: This pin is connected to the collector of the discharge transistor Q1.When Q output of the FF is 1,then Transistor Q1 is on due to sufficient base drive hence driving transistor into saturation.When output of the FF is low Transistor Q1 is off hence acting as a open circuit to any external device connected to it.8. +Vcc (Power Supply): It can work with any supply voltage between 5 & 18V.

THEORY:

PROCEDURE:

1. Connect the circuit diagram as shown in the circuit diagram.2. Before switch ON the power supply, make sure that the connections are

correct.3. Connect the C.R.O. probe at terminals 3 and ground.4. Observe the output waveform for different RB.5. Tabulate the reading of W and T in Observation Table.6. Calculate Dm, Dt and % Error.7. Plot the waveform observed at terminal no. 2 and 3.

OBSERVATION:

At VCC=5V/12V, RA=33 K

SlNo

RB

(K)W(S)

T(S)

Measured Duty CycleDm=W/T X 100%

Theoretical Duty CycleDt=(RA+RB)/ (RA+2RB) X 100

% Error=(Dt-Dm)/Dt X 100

1 302 60

RESULT:

PRECAUTION:

DEPARTMENTOF




ON

DESIGN OF AN MONOSTABLE MULTIVIBRATOR (USING IC 555 TIMER) AND OBSERVE THE OUTPUT

WAVEFORMS


AIM: - To design a Monostable Multivibrator using IC 555 and observe the output waveform.

APPARATUS REQUIRED:

1. Wish board2. D.C. Power supply3. Function generator Or Trainer Kit4. C.R.O

CIRCUIT COMPONENTS:

1. IC5552. Capacitor (1000pF, 10000pF)3. Resistors (10 to 30K variable)4. Connecting wires


Functions of pins:

1. Ground: All voltages are measured with respect to this terminal.2. Trigger: It is the external input that will be applied to the inverting input of the lower comparator & will be compared with Vcc/3 coming from the potential divider network.3. Output: Complement of the output of the flip-flop acts as the final output of timer as it passes through a power amplifier with inverter. Load can either be connected between pin 3 & ground or pin 3 & Vcc.4. Reset : This is an input to the timing device which provides a mechanism to reset the flip-flop in a manner which overrides the effect of any instruction coming to the FF from lower comparator. This is effective when the reset input is less than 0.4V.When not used it is returned to Vcc.5. Control Voltage input: Generally the fixed voltages of 1/3Vcc & 2/3Vcc also aid in determining the timing interval. The control voltage at 5 can be used when it is required to vary the time & also in such cases when the reference level at V- of the UC is other than 2/3Vcc.Generally when not used a capacitor of 0.01uF should be connected between 5 & ground to bypass noise or ripple from the supply.

Threshold

Control voltage

Discharge

outputIC 555

+ VccGND

Trigger

Reset

6. Threshold: An external voltage by means of a timing capacitor & resistor is applied to this pin. When this voltage is greater than 2/3Vccoutput of UC is 1 which is given to the set input of FF thereby setting the FF making Q=1 & Q=0.7. Discharge: This pin is connected to the collector of the discharge transistor Q1.When Q output of the FF is 1,then Transistor Q1 is on due to sufficient base drive hence driving transistor into saturation.When output of the FF is low Transistor Q1 is off hence acting as a open circuit to any external device connected to it.8. +Vcc (Power Supply): It can work with any supply voltage between 5 & 18V.

THEORY:

PROCEDURE:

1. Connect the circuit diagram as shown in the circuit diagram.2. Before switch ON Power Supply, make sure that the connections are correct.3. Connect the C.R.O. probe at terminals 3 and ground.4. Observe the output waveforms for different values of R.5. Tabulate the reading of Pulse Width as Wo in observation table.6. Calculate the Wt and % Error.7. Plot the waveform observed at terminal no. 2, 3 and 6.

OBSERVATIONS:At Vcc=10V, C=8.2nF

SlNo.

R(K)

Wo

(S)Theoretical Pulse WidthWt=1.1 x Rx C

% Error=Wt-Wo X100 Wt

1 302 403 50

RESULT:

PRECAUTION:

DEPARTMENTOF




ON

DESIGN AND TESTING OF 2 : 1 MULTIPLEXER AND CMOS SWITCH USING IC CD4066


AIM: Design and testing of CMOS switch and 2 : 1 multiplexer using IC CD4066

APPARATUS REQUIRED:

1. IC CD4027 & IC 555 timer2. MICROLABORATORY KIT3. Connecting wires


QUAD 2 IN/OUTPUT DIGITAL AND ANALOG BILETERAL CMOS SWITCH

THEORY:

IC CD4066 is bileteral CMOS Switch. It is the new class of logic circuits, which use the TGs as their basic building blocks.The TG consists of one NMOS and one PMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bi-directional switch between the nodes A & B, which is controlled by signal C.

C GND

A B A B A TG

C

If the control signal C is at logic high (=VDD) then the PMOS & NMOS transistors are turned ON and they provide a low resistance current path between A & B A B

C = 1

If the control signal C is low then both are off and there is no conduction path between A & B. A B

C = 0

Using the generalized MUX approach, each Boolean function can be realized with a TG logic circuit.The implementation of CMOS transmission gates in logic circuit design usually results in compact circuit structure, which may even require a smaller number of transistors than their standard CMOS counterparts.

2 * 1 MULTIPLEXER:

2 * 1 multiplexer having 2 input and 1 output. The two inputs of the multiplexer is A and B. The data at a A or B is selected through control signal C, which acts as selection line for it. So output of the 2 * 1 multiplexer is F = AC + BC’

PROCEDURE:1. Connect the circuit as shown in the circuit diagram.2. Before switch ON the power supply, make sure that the connections are

correct.3. Observe the A, C and output F. See Switching action of the CMOS Switch.4. In Second of the fig observe A,B,C and output and verify F = AC + BC’

OBSERVATIONS: (a) For CMOS switch

INPUT Control Signal

OUTPUT

A C F

0 01 01 11 1

2 * 1 multiplexer

A

B

C

(b) For 2 * 1 MULTIPLEXER

RESULT:

PRECAUTIONS:

INPUT Control signal

OUTPUT

A B C F

0 0 00 1 01 0 01 1 00 0 10 1 11 0 11 1 1

DEPARTMENTOF




ON

DESIGN OF A 4 BIT SERIAL IN SERIAL OUT SHIFT REGISTER USING IC CD4027 AND 555 TIMER


MESRA RANCHI

AIM:- Design of a 4-bit serial in serial out shift register using IC CD4027 and 555 timer.

APPARATUS REQUIRED:

1. IC CD4027 & IC 555 timer2. MICROLABORATORY KIT3. Connecting wires

THEORY:Register:- A register is a group of binary storage cells suitable for holding binary information. A group of flip-flop’s constitutes a register, since each flip-flop is a binary cell capable of storing one bit of information so an n-bit register consists of n flip-flop’s and is capable of storing any binary information containing n bits.

Shift Register:- A register capable of shifting its binary information either to the right or to the left is called a Shift Register. Also we can feed data/information in shift register in two manners – 1) Serial Input:- In this at a time only one bit of n bit information is feeded/loaded in

shift register firstly the least significant bit (leftmost bit) of the n-bit information is loaded and at the end most significant bit is loaded. So serial shift register needs n clock period (T) for feeding n bit data into the register.

2) Parallel Input:- In this the whole n bits of a n-bit information is loaded into the register in only one clock period (T). So all bits are loaded parallely.

Output also can be find from shift register in the same manner serially or parallely.So we have 4 kindf of shift registers1. Serial in Serial out2. Serial in Parallel out3. parallel in Serial out4. parallel in parallel out

In serial in serial out, loading in and extracting out the data from shift register both processes takes place in serial manner


Threshold

Control voltage

Discharge

outputIC 555

+ VccGND

Trigger

Reset

Functions of pins:

1. Ground: All voltages are measured with respect to this terminal.2. Trigger: It is the external input that will be applied to the inverting input of the lower comparator & will be compared with Vcc/3 coming from the potential divider network.3. Output: Complement of the output of the flip-flop acts as the final output of timer as it passes through a power amplifier with inverter. Load can either be connected between pin 3 & ground or pin 3 & Vcc.4. Reset : This is an input to the timing device which provides a mechanism to reset the flip-flop in a manner which overrides the effect of any instruction coming to the FF from lower comparator. This is effective when the reset input is less than 0.4V.When not used it is returned to Vcc.5. Control Voltage input: Generally the fixed voltages of 1/3Vcc & 2/3Vcc also aid in determining the timing interval. The control voltage at 5 can be used when it is required to vary the time & also in such cases when the reference level at V- of the UC is other than 2/3Vcc.Generally when not used a capacitor of 0.01uF should be connected between 5 & ground to bypass noise or ripple from the supply.6. Threshold: An external voltage by means of a timing capacitor & resistor is applied to this pin. When this voltage is greater than 2/3Vccoutput of UC is 1 which is given to the set input of FF thereby setting the FF making Q=1 & Q=0.7. Discharge: This pin is connected to the collector of the discharge transistor Q1.When Q output of the FF is 1,then Transistor Q1 is on due to sufficient base drive hence driving transistor into saturation.When output of the FF is low Transistor Q1 is off hence acting as a open circuit to any external device connected to it.8. +Vcc (Power Supply): It can work with any supply voltage between 5 & 18V.


2 adet JK FLIP FLOP

PROCEDURE:

1. Connect the circuit as shown in fig.2. Connect the output of the 555 timer output to clock 1 and clock 2 input of

all IC 4027B.3. See the input and output waveform and observe the output.

RESULT:

PRECAUTIONS:

DEPARTMENTOF




ON

DESIGN OF A MODULO-9 RIPPLE COUNTER USING IC CD4029 AND IC CD4091


AIM: - Design of a Modulo 9-ripple counter using IC CD4029 and IC CD4091.

APPARATUS REQUIRED:


CIRCUIT COMPONENTS:

1. IC CD4029, IC CD40912. Connecting wires

PIN DIAGRAM OF IC 4029 : IC 4029 Decade counter

4029 Ayarlanabilir synchronous yukari / asagi Counter

THEORY:Modulo ‘n’ counter is a counters, which counts from 0000 to binary equivalent of ‘n’ and

then again start counting from 0000

(i.e. 0000 0001 ……. upto binary equivalent of ‘n’ 0000 0001……. )

Modulo 9 ripple counter will start count from 0000 to 1001 than reset to 0000 after which

it again start counting from 0000 to 1001. This process repeated again and again.

To design of a Modulo 9 ripple counter using IC CD4029 (Decade counter) it has to be

reset to 0000 after counting 1001. This resetting after 1001 is done through a two input

AND gate. Input of AND gate is QA [least significant bit (LSB) of decade counter] and

QD [Most significant bit (MSB) of decade counter]. So only when output of the decade

counter IC 4029 will be 1001 then only the output of AND gate will be 1. Output of the

AND gate is connected to PRESET input of decade counter so decade counter will be

reset to 0000 and again start counting from 0000.

PROCEDURE:

5. Connect the circuit as shown in the circuit diagram.6. Before switch ON the power supply, make sure that the connections are

correct.7. Observe the Q1,Q2, Q3, Q48. Complete the observation table.

OBSERVATIONS:

S. No Q3 Q2 Q1 Q0

RESULT:

PRECAUTION:

DEPARTMENTOF




ON

DESIGN OF A SCHMITT TRIGGER (USING IC 741 OPAMP) OBSERVATION OF THE OUTPUT WAVEFORMS


AIM: - Design of a Schmitt Trigger Circuit (using IC 741 OPAMP) & observation of the output waveforms.

APPARATUS REQUIRED:


CIRCUIT COMPONENTS:

3. IC7414. Resistors ( 8.2K, 100)5. Connecting wires

ABOUT IC 741:

The 741 is the godfather of all operational amplifiers (amplifiers on a chip). Although most up-to-date designs beat it for speed, low noise, etc, it still works well as a general purpose device. One of its advantages is that it is compensated (its frequency response is tailored) to ensure that under most curcumstances it won't produce unwanted spurious oscillations. This means it is easy to use, but the down-side of this is the poor speed/gain performance compared to more modern op-amps.

The 741 is usually supplied in an 8-pin ‘DIL’ (Dual In Line) or ‘DIP’ (Dual Inline Package, or sometimes Dual Inline Plastic) package with a pinout shown above. This has proved so popular that many other competing op-amps have adoped the same package/pinout. Hence for many applications the various op-amps are ‘drop in’ replacements or upgrades for one another. These days there is a large family of 741 type devices, made by various manufacturers. Sometimes one manufacturer will make different versions which work better than others in some respect. Each has a slightly different part number, but it generally has “741” in it somewhere!

The values given below are ‘typical’ for an ordinary 741, better versions (more expensive) may give better results...

Typical values of Basic Parameters: Rail voltages : +/- 15V dc (+/- 5V min, +/- 18V max)Input impedance: Around 2MegOhmsLow Frequency voltage gain: approx 200,000Input bias current: 80nASlew rate: 0.5V per microsecondMaximum output current: 20mARecommended output load: not less than 2kilOhms

Note that, due to the frequency compensation, the 741's voltage gain falls rapidly with increasing signal frequency. Typically down to 1000 at 1kHz, 100 at 10kHz, and unity at about 1MHz. To make this easy to remember we can say that the 741 has a gain-bandwidth product of around one million (i.e. 1 MHz

THEORY:

PROCEDURE:

9. Connect the circuit as shown in the circuit diagram.10. Before switch ON the power supply, make sure that the connections are

correct.11. Select the sinusoidal input from function generator.12. Connect the C.R.O. probe at terminal 3 and ground.13. Observe the input waveforms.14. Plot the waveforms observed at terminal no. 2 and 6.15. Repeat the above procedure for triangular input waveform.16. Calculate the loop gain for both observations.

OBSERVATIONS:

R1-=8.2k AND R2= 100Waveforms Vi

(Volts)Vo

(Volts)AV=VO/Vi =R2/(R1+R2) L=- x AV

SinusoidalTriangular

L=Loop gain, = Feed back Factor, AV=Voltage Gain

RESULT:

PRECAUTION:

DEPARTMENTOF




ON

DESIGN AND REALISATION OF A BINARY TO GRAY CODE CONVERTER USING IC 7486


AIM: Design and realization of Binary to Gray code converter using IC 7486

APPARATUS REQUIRED:1. Wish board2. D.C. power supply Or


CIRCUIT COMPONENT:1. IC 74862. Connecting Wires3. LED with resistors

PIN DIAGRAM:



THEORY:




FUNCTION TABLE:

Sr. No

INPUT (BINARY CODE) OUTPUT (GRAY CODE)B4 B3 B2 B1 B0 G4 G3 G2 G1 G0

1 0 0 0 0 0

2 0 0 0 0 1

3 0 0 0 1 0

4 0 0 0 1 1

5 0 0 1 0 0

6

7

RESULT:

PRECAUTIONS:

Fig. BINARY TO GRAY CODE CONVERTER

DEPARTMENTOF




ON

DESIGN AND REALISATION OF A GRAY CODE TO BINARY CODE CONVERTER USING IC 7486


AIM: Design and realization of a Gray code to Binary code converter using IC7486.

APPARATUS REQUIRED:1. Wish board2. D.C. power supply Or


CIRCUIT COMPONENT:1. IC74862. Connecting Wires3. LED with resistors

PIN DIAGRAM:



THEORY:




FUNCTION TABLE:

Sr. No

INPUT (GRAY CODE) OUTPUT (BINARY CODE)G4 G3 G2 G1 G0 B4 B3 B2 B1 B0

1 0 0 0 0 0

2 0 0 0 0 1

3 0 0 0 1 1

4 0 0 0 1 0

5 0 0 1 1 0

6

7

RESULT:

PRECAUTIONS:

Fig. GRAY TO BINARY CONVERTER

DEPARTMENTOF




ON

DESIGN OF AN EX-OR GATE USING MINIMUM NUMBER OF 2 INPUT NAND GATES IC 7400


AIM: Design of an EX-OR gate using minimum number of 2 input NAND gates IC 7400

APPARATUS REQUIRED:

1. Wish board2. D.C. Power supply

or Trainer Kit (MicroLABORATORY-II)

CIRCUIT COMPONENTS:


PIN DIAGRAM:


4 2-INPUTS NAND GATE

THEORY:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.2. Before switching ON Power Supply, make sure that the connections are

correct..3. Apply the input logic states as per Truth Table, in terms of +5 volts for state-1

and 0 volts for state-0.4. Observe the output states.5. Verify the results of truth ness.6. Repeat steps from 3 to 5 for all possible combinations of function table.

OBSERVATION TABLE:

RESULT:

PRECAUTIONS:

:

INPUT OUTPUT

X Y X.Y (X.Y)’.X (X.Y)’.Y X Y

0 00 11 01 1

DEPARTMENTOF




ONDESIGN AND REALISATION OF A PARITY BIT GENERATOR

USING IC 7486


AIM: Design and realization of an Odd Parity generator with IC 7486.

APPARATUS REQUIRED:1. Wish Board1. D.C. Power Supply

OrTrainer Kit (MicroLABORATORY-II)

CIRCUIT COMPONENT:

1. IC74862. Connecting Wires

PIN DIAGRAM:



THEORY:

PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.2. Before switching ON power supply, make sure that the connection are correct.3. Apply the input logic state code mentioned in Observation Table in terms of +5

volts for state-1 and 0 volts for state-0.4. Observe the output states.5. Verify the result of truth ness.6. Repeat steps from 3 to 5 for all possible combination.

OBSERVATION TABLE:

Sr. No INPUT Podd

X Y Z1 0 0 02 0 0 1345678

RESULT:

PRECAUTIONS:

Documents

AIM: Design of a Seven-Segment display using IC-7447snmgaya.weebly.com/uploads/2/6/9/4/26948220/digital... · Web viewDesign of a 2 bit binary parallel adder using IC CD4030 and IC