AK4520_datasheet

ASAHI KASEI [AK4520A]

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AK4520A

100dB 20Bit Stereo ∆Σ ADC & DAC

General DescriptionThe AK4520 is a stereo CMOS A/D & D/A converter for middle-range MD/DAT, Surround System and musicalinstruments. Signal inputs and outputs are single-ended. The DAC outputs are analog filtered to remove out ofband noise. External components are minimized.

Features

∆Σ Stereo ADC- 64x Oversampling- S/(N+D): 90dB at 5V, 86dB at 3V- Dynamic Range: 100dB at 5V, 96dB at 3V- S/N: 100dB at 5V, 96dB at 3V- Digital HPF for offset cancel

∆Σ Stereo DAC- 128x Oversampling- 2nd order SCF + 2nd order CTF- Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling- S/(N+D): 90dB at 5V, 90dB at 3V- Dynamic Range: 100dB at 5V, 96dB at 3V- S/N: 100dB at 5V, 96dB at 3V

High Jitter Tolerance Sample Rate Ranging from 16kHz to 54kHz Master Clock: 256fs or 384fs 2.7 to 3.6V or 4.5 to 5.5V supply Low Power Dissipation: 255mW Small 28pin VSOP Package


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Ordering Guide

AK4520A-VF -10∼+70°C 28pin VSOPAKD4520 AK4520A Evaluation Board

Pin Layout


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PIN/FUNCTION

No. Pin Name I/O Function

1 VREFH I Positive Voltage Reference Input Pin, VA Used as a positive voltage reference by ADC & DAC. VREFH is connected externally to filtered VA.

2 VREFL I Negative Voltage Reference Input Pin, AGND Used as a negative voltage reference by ADC & DAC. VREFL is connected externally to AGND.

3 AINR+ I Rch Analog Positive Input pin

4 AINR- I Rch Analog Negative Input Pin

5 AINL+ I Lch Analog Positive Input pin

6 AINL- I Lch Analog Negative Input Pin

7 VA - Analog Power Supply Pin

8 AGND - Analog Ground pin

9 DIF0 I Audio Data Interface Format Pin

10 DIF1 I Audio Data Interface Format Pin

11 LRCK I Input/Output Channel Clock Pin

12 SCLK I Audio Serial Data Clock Pin

13 SDTI I Audio Serial Data Input Pin

14 SDTO O Audio Serial Data Output Pin

15 MCLK I Master Clock Input Pin

16 DEM0 I De-emphasis Frequency Select Pin

17 DEM1 I De-emphasis Frequency Select Pin

181920

TST3 TST2 TST1

I/O I/O I

Test Pins (Pull down pins) Must be left open or connected to DGND.

21 VD - Digital Power Supply Pin

22 DGND - Digital Ground Pin

23 PWDA I DAC Power-Down Mode Pin

24 PWAD I ADC Power-Down Mode Pin

25 CMODE I Master Clock Select Pin "H": 384fs, "L": 256fs

26 AOUTL O Lch analog output pin

27 AOUTR O Rch analog output pin

28 VCOM O Common Voltage Output Pin, VA/2

Note: All input pins except pull-down pins should not be left floating.


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ABSOLUTE MAXIMUM RATINGS

(AGND,DGND=0V; Note 1 )

Parameter Symbol min max Units

Power Supplies: Analog Digital |AGND-DGND|

VAVD

∆GND

-0.3-0.3

-

6.06.00.3

VVV

Input Current, Any Pin Except Supplies IIN - ±10 mA

Analog Input Voltage VINA -0.3 VA+0.3 V

Digital Input Voltage VIND -0.3 VD+0.3 V

Ambient Temperature (power applied) Ta -10 70 °C

Storage Temperature Tstg -65 150 °C

Note: 1 . All voltages with respect to ground.

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normaloperation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AGND,DGND=0V; Note 1 )

Parameter Symbol min typ max Units

3V operation Analog Digital

VAVD

2.72.7

3.03.0

3.6VA

VV

Power Supplies: (Note 2 )

5V operation Analog Digital

VAVD

4.54.5

5.05.0

5.5VA

VV

Note: 1 . All voltages with respect to ground.2 . The power up sequence between VA and VD is not critical.


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ANALOG CHARACTERISTICS

(Ta=25°C; VA,VD=5.0V; AGND=DGND=0V; VREFH=VA; VREFL=AGND; fs=44.1kHz; SCLK=64fs, Signal Frequency=1kHz; 20bit Data; Measurement frequency=10Hz∼20kHz; unless otherwise specified)

Parameter min typ max Units

ADC Analog Input Characteristics: Differential Inputs; Analog Source Impedance=470Ω Resolution 20 Bits

S/(N+D) (-0.5dB Input) (Note 3 )

VA=3V VA=5V

8084

8690

dBdB

DR (-60dB Input, A-Weighted) (Note 4 )

VA=3V VA=5V

9094

96100

dBdB

S/N (A-Weighted) (Note 4 ,5 )

VA=3V VA=5V

9094

96100

dBdB

Interchannel Isolation 90 110 dB

Interchannel Gain Mismatch 0.1 0.3 dB

Gain Drift 20 ppm/°C

Input Voltage AIN=0.6x(VREFH-VREFL)

VA=3V VA=5V

1.72.85

1.83.0

1.93.15

VppVpp

Input Resistance 20 30 kΩ Power Supply Rejection (Note 6 ) 50 dB

DAC Analog Output Characteristics:

Resolution 20 Bits

S/(N+D) VA=3V VA=5V

8480

9090

dBdB

DR (-60dB Output, A-Weighted) (Note 4 )

VA=3V VA=5V

9296

96100

dBdB

S/N (A-Weighted) (Note 7,5 )

VA=3V VA=5V

9296

96100

dBdB

Interchannel Isolation 90 110 dB

Interchannel Gain Mismatch 0.1 0.3 dB

Gain Drift 20 ppm/°C

Output Voltage AOUT=0.626x(VREFH-VREFL)

VA=3V VA=5V

1.762.94

1.883.13

1.993.32

VppVpp

Load Resistance 10 kΩ Load Capacitance 25 pF

Power Supply Rejection (Note 6 ) 50 dB Note: 3 . In case of single ended input, S/(N+D)=84dB(typ, @VA=5V).

4 . In case of 16bit, DR and S/N of ADC are 98dB. DR of DAC is 98dB.5 . S/N measured by CCIR-ARM is 96dB at each converter and 94dB at ADC to DAC loopback.6 . PSR is applied to VA,VD with 1kHz, 50mVpp. VREFH/VREFL pin is held a constant voltage.7 . As the input data is "0", S/N is 100dB regardless of resolution.


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Parameter min typ max Units

Power supply Current VA=VD=5V

Analog VA

AD+DA AD DA

PWAD="H",PWDA="H" PWAD="H",PWDA="L" PWAD="L",PWDA="H"

411725

622638

mAmAmA

Digital VD (Note 8 )

AD+DA AD DA

PWAD="H",PWDA="H" PWAD="H",PWDA="L" PWAD="L",PWDA="H"

1064

1596

mAmAmA

VA+VD Power down PWAD="L",PWDA="L" 0.2 0.4 mA

Note:8 The typical supply current of VD drops to AD+DA=5.5mA, AD=3.5mA, DA=2mA at 3.0V supplyvoltage.

FILTER CHARACTERISTICS

(Ta=25°C; VA,VD=2.7∼5.5V; fs=44.1kHz; DEM0="1", DEM1="0")


ADC Digital Filter(Decimation LPF):

Passband (Note 9 ) -0.005dB -0.02dB -0.06dB -6.0dB

PB 0000

19.7620.0220.2022.05

kHzkHzkHzkHz

Stopband SB 24.34 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 80 dB

Group Delay (Note 10 ) GD 29.3 1/fs

Group Delay Distortion ∆GD 0 us

ADC Digital Filter(HPF):

Frequency Response (Note 9 ) -3dB -0.5dB -0.1dB

FR 0.92.76.0

HzHzHz

DAC Digital Filter:

Passband (Note 9 ) -0.06dB -6.0dB

PB 00

20.022.05

kHzkHz

Stopband SB 24.1 kHz

Passband Ripple PR ±0.06 dB

Stopband Attenuation SA 43 dB

Group Delay (Note 10 ) GD 14.7 1/fs

DAC Digital Filter+Analog Filter:

Frequency Response 0∼20.0kHz FR ±0.1 dB

Notes: 9. The Passband and stopband frequencies scale with fs. For example, 20.02kHz at -0.02dB is0.454 x fs.

10. The calculating delay time which occurred by digital filtering. This time is from the input of analogsignal to setting the 20bit data of both channels to the output register for ADC.For DAC, this time is from setting the 20bit data of both channels on input register to the output ofanalog signal.


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DIGITAL CHARACTERISTICS

(Ta=25°C; VA,VD=2.7∼5.5V)


High-Level Input Voltage Low-Level Input Voltage

VIHVIL

70%VD-

--

-30%VD

VV

High-Level Output Voltage (Iout=-100uA) Low-Level Output Voltage (Iout=100uA)

VOHVOL

VD-0.5-

- -0.5

VV

Input Leakage Current Iin - - ±10 uA

SWITCHING CHARACTERISTICS

(Ta=25°C; VA,VD=2.7∼5.5V; CL=20pF)

Parameter Symbol min typ max Unit

Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High

fCLK tCLKL tCLKH fCLK tCLKL tCLKH

4.0962727

6.1442020

13.824

20.736

MHznsns

MHznsns

LRCK Frequency VD=2.7-3.6V VD=4.5-5.5V

fs fs

1616

44.144.1

5054

kHz

Duty Cycle (Note 11 ) 45 55 %

Serial Interface Timing SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK "↑" (Note 12 ) SCLK "↑" to LRCK Edge (Note 12 )

LRCK to SDTO(MSB) SCLK "↓" to SDTO

SDTI Hold Time SDTI Setup Time

tSCK tSCKL tSCKH tLRS tSLR tLRM tSSD tSDH tSDS

289.41201203030

4040

100100

nsnsnsnsnsnsnsnsns

Reset Timing PWAD & PWDA Pulse Width PWAD "↑" to SDTO valid (Note 13 )

tPW tPWV

150516

ns1/fs

Notes: 11.If the duty cycle of LRCK changes larger than 5 to 50%, the AK4520A is reset by the internal phase circuit automatically.

12.SCLK rising edge must not occur at the same time as LRCK edge.13.These cycles are the number of LRCK rising from PWAD rising.


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Timing Diagram


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OPERATION OVERVIEW

System Clock Input

The AK4520A with CMODE is used to select either MCLK=256fs or 384fs. The relationship between theexternal clock applied to the MCLK input and the desired sample rate is defined in Table 1 . The LRCK clockinput must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized toLRCK upon power-up or when the internal timing becomes out of phase. All external clocks must be presentunless both PWDA and PWAD ="L", otherwise excessive current may result from abnormal operation ofinternal dynamic logic.

MCLK SCLK

fs 256fs CMODE="L"

384fs CMODE="H"

64fs 32fs

32.0kHz 8.1920MHz 12.2880MHz 2.048MHz 1.0240MHz

44.1kHz 11.2896MHz 16.9344MHz 2.822MHz 1.4112MHz

48.0kHz 12.2880MHz 18.4320MHz 3.072MHz 1.5360MHzTable 1 . System Clock Example

Audio Serial Interface Format

Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes aresupported selected by the DIF0 and DIF1 pins as shown in Table 2 . In all modes the serial data is MSB-first,2's compliment format is clocked on the falling edge of SCLK. For mode 3, if SCLK is 32fs, then the leastsignificant bits will be truncated.

Mode DIF1 DIF0 SDTO(ADC) SDTI(DAC) L/R SCLK

0 0 0 20bit, MSB justified 16bit, LSB justified H/L ≥32fs

1 0 1 20bit, MSB justified 20bit, LSB justified H/L ≥40fs

2 1 0 20bit, MSB justified 20bit, MSB justifie H/L ≥40fs

3 1 1 IIS(I2S) IIS(I2S) L/H 32fs or ≥40fs

Table 2 . Serial Data Modes


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Digital High Pass Filter

The ADC of AK4520A has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is

0.9Hz at fs=44.1kHz and also scales with sampling rate(fs).

De-emphasis filter

The DAC of AK4520A includes the digital de-emphasis filter(tc=50/15us) by IIR filter. This filter corresponds tothree frequencies (32kHz,44.1kHz,48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled forinput audio data. The de-emphasis is also disabled at DEM0="1" and DEM1="0".

DEM 1 DEM0 Mode

0 0 44.1kHz

0 1 OFF

1 0 48kHz

1 1 32kHz

Table 3 . De-emphasis filter control


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Power-Down & Reset

The ADC and DAC of AK4520A are placed in the power-down mode by bringing each power down pin, PWAD

PWDA "L" independently and each digital filter is also reset at the same time. This reset should always be done

after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode.

Therefore, the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle

does not affect the DAC operation.

Figure 5 shows the power-up sequence when the DAC is powered up before the ADC power-up.

1 The analog part of ADC is initialized after exiting the power-down state.2 Digital output corresponding to analog input and analog output corresponding to digital input have

the group delay(GD).3 A/D output is "0" data at the power-down state.4 Click noise occurs at the end of initialization of the analog part. Please mute the digital output

externally if the click noise influences system application. Required muting time depends on theconfiguration of the input buffer circuits.

Figure 6: 1sFigure 9: 200ms

5 Click noise occurs at the edge of PWDA.6 Please mute the analog output externally if the click noise( 5) influences system application.

Figure 5 . Power-up sequence


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SYSTEM DESIGNFigure 6 shows the system connection diagram. This is an example which analog signal is input by singleended circuit. In case of differential input, please refer to Figure 9 . An evaluation board is available whichdemonstrates application circuits, the optimum layout, power supply arrangements and measurement results.


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Figure 8 . Power Supply Arrangement

1. Grounding and Power Supply Decoupling

The AK4520A requires careful attention to power supply and grounding arrangements. VA and VD are usuallysupplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power upsequence is not critical. AGND and DGND of the AK4520A should be connected to analog ground plane.System analog ground and digital ground should be connected together near to where the supplies arebrought onto the printed circuit board. Decoupling capacitors should be as near to the AK4520A as possible,with the small value ceramic capacitor being the nearest.


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2. On-chip voltage reference

The differential Voltage between VREFH and VREFL sets the analog input/output range. VREFH pin isnormally connected to VA with a 0.1uF ceramic capacitor and VREFL pin is connected to AGND. VCOM is asignal ground of this chip. An electrolytic capacitor 10uF parallel with a 0.1uF ceramic capacitor attached toVCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. Allsignals, especially clocks, should be kept away from the VREFH,VREFL and VCOM pins in order to avoidunwanted coupling into the AK4520A.

3. Analog Inputs

The ADC inputs are differential and internally biased to the common voltage(VA/2) with 30kΩ (typ) resistance.Figure 6 is a circuit example which analog signal is input by single end. the signal can be input from eitherpositive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x(VREFH-VREFL) Vpp. In case of single ended input, the distortion around full scale degrades compared withdifferential input. Figure 9 is a circuit example which analog signal is input to both positive and negative inputand the input signal range scales with the supply voltage and nominally 0.3 x (VREFH-VREFL) Vpp. TheAK4520A can accept input voltages from AGND to VA. The ADC output data format is 2's complement Theoutput code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below anegative full scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by theinternal HPF.

The AK4520A samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except formultiples of 64fs. A simple RC filter(fc=150kHz) may be used to attenuate any noise around 64fs and mostaudio signals do not have significant energy at 64fs.

The AK4520A has tone noise with around -110dB on the ADC output. There are two methods of dropping VDto 3V or adding a small DC offset at the ADC input to reduce the noise level. The evaluation board(AKD4520)manual should be referred about the detail.

Figure 9 . Differential Input Buffer Example


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4. Analog Outputs

The analog outputs are also single-ended and centered around the VCOM voltage. The input signal rangescales with the supply voltage and nominally 0.626 x (VREFH-VREFL) Vpp. The DAC input data format is 2'scomplement. The output voltage is a positive full scale for 7FFFFH(@20bit) and a negative full scale for80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). The internal switched-capacitor filterand continuous-time filter removes most of the noise generated by the delta-sigma modulator of DAC beyondthe audio passband.

DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.Figure 10 shows the example of external op-amp circuit with 6dB gain. The output signal is inverted by usingthe circuit in this case.

Figure 10 . External analog circuit example(gain=6dB)


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PACKAGE

zzzz 28pin VSOP (Unit: mm)

Material & Lead finish

Package molding compound: EpoxyLead frame material: CuLead frame surface treatment: Solder plate


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MARKING

XXXBYYYYC date code identifier

XXXB: Lot number(X:Digit number, B:Alpha character)YYYYC: Assembly date(Y:Digit number,C:Alpha character)

IMPORTANT NOTICE

zThese products and their specifications are subject to change without notice. Beforeconsidering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)sales office or authorized distributor concerning their current status.

zAKM assumes no liability for infringement of any patent, intellectual property, or otherright in the application or use of any information contained herein.

zAny export of these products, or devices or systems containing them, may require anexport license or other official approval under the law and regulations of the country ofexport pertaining to customs and tariffs, currency exchange, or strategic materials.

zAKM products are neither intended nor authorized for use as critical components in anysafety, life support, or other hazard related device or system, and AKM assumes noresponsibility relating to any such use, except with the express written consent of theRepresentative Director of AKM. As used here:(a) A hazard related device or system is one designed or intended for life support or

maintenance of safety or for applications in medicine, aerospace, nuclear energy, orother fields, in which its failure to function or perform may reasonably be expected toresult in loss of life or in significant injury or damage to person or property.

(b) A critical component is one whose failure to function or perform may reasonably beexpected to result, whether directly or indirectly, in the loss of the safety oreffectiveness of the device or system containing it, and which must therefore meetvery high standards of performance and reliability.

z It is the responsibility of the buyer or distributor of an AKM product who distributes,disposes of, or otherwise places the product with a third party to notify that party inadvance of the above content and conditions, and the buyer or distributor agrees toassume any and all responsibility and liability for and hold AKM harmless from any andall claims arising from the use of said product in the absence of such notification.

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AK4520_datasheet