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George Mason University
Algorithmic State Machine (ASM) Charts:VHDL Code & Timing Diagrams
ECE 448Lecture 7
2
Required reading
• P. Chu, FPGA Prototyping by VHDL ExamplesChapter 5, FSM
3
Recommended reading
• S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design
Chapter 8, Synchronous Sequential CircuitsSections 8.1-8.5Section 8.10, Algorithmic State Machine (ASM)
Charts
4
Finite State Machinesin VHDL
5
Recommended FSM Coding Style
Based on RTL Hardware Design by P. Chu
Process(clk, reset)
Process(Present State, Input)
Next StatePresent State
6
ASM Chart of Moore Machine S0
reset
input
S1
S2
input
input
0
1
0
1
1 0
output
7
Moore FSM in VHDL (1)
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY FSM_Moore ISPORT ( clk : IN STD_LOGIC ;
reset : IN STD_LOGIC ;input : IN STD_LOGIC ;output : OUT STD_LOGIC) ;
END FSM_Moore ;
8
Moore FSM in VHDL (1)
ARCHITECTURE behavioral of FSM_Moore ISTYPE state IS (S0, S1, S2);SIGNAL Present_State, Next_State: state;
BEGIN
U_Moore: PROCESS (clk, reset)BEGIN
IF(reset = '1') THENPresent_State <= S0;
ELSIF rising_edge(clk) THENPresent_State <= Next_State;
END IF;END PROCESS;
9
Moore FSM in VHDL (2)
Next_State_Output: PROCESS (Present_State, input)BEGIN
Next_State <= Present_State;output <= '0';CASE Present_State IS
WHEN S0 =>IF input = '1' THEN
Next_State <= S1; ELSE
Next_State <= S0;END IF;
10
Moore FSM in VHDL (3)WHEN S1 =>
IF input = '0' THEN Next_State <= S2;
ELSENext_State <= S1;
END IF;WHEN S2 =>
output <= '1' ;IF input = '1' THEN
Next_State <= S1; ELSE
Next_State <= S0; END IF;
END CASE;END PROCESS;
END behavioral;
11
ASM Chart of Mealy Machine
S0
S1
reset
input
input
output
0
1
1 0
12
Mealy FSM in VHDL (1)
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY FSM_Mealy ISPORT ( clk : IN STD_LOGIC ;
reset : IN STD_LOGIC ;input : IN STD_LOGIC ;output : OUT STD_LOGIC) ;
END FSM_Mealy ;
13
Mealy FSM in VHDL (1)
ARCHITECTURE behavioral of FSM_Mealy ISTYPE state IS (S0, S1);SIGNAL Present_State, Next_State: state;
BEGINU_Mealy: PROCESS(clk, reset)BEGIN
IF(reset = '1') THENPresent_State <= S0;
ELSIF rising_edge(clk) THENPresent_State <= Next_State;
END IF;END PROCESS;
14
Mealy FSM in VHDL (2)
Next_State_Output: PROCESS (Present_State, input)BEGIN
Next_State <= Present_State;output <= '0';CASE Present_State IS
WHEN S0 =>IF input = '1' THEN
Next_State <= S1; ELSE
Next_State <= S0;END IF;
15
Mealy FSM in VHDL (3)WHEN S1 =>IF input = '0' THEN
Next_State <= S0; Output <= '1' ;
ELSENext_State <= S1;
END IF;END CASE;
END PROCESS;
END behavioral;
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Control Unit Example: Arbiter (1)
Arbiter
reset
r1
r2
r3
g1
g2
g3
clock
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ASM Chart for Control Unit - Example 4
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
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VHDL code of arbiter
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY arbiter ISPORT ( Clk, Reset : IN STD_LOGIC ;
r : IN STD_LOGIC_VECTOR(1 TO 3) ;g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;
END arbiter ;
ARCHITECTURE Behavior OF arbiter ISTYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;SIGNAL y, y_next : State_type ;
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VHDL code of arbiter – Style 2 (2)BEGIN
PROCESS ( Reset, Clk )BEGIN
IF Reset = '1' THEN y <= Idle ;
ELSIF rising_edge(Clk) THENy <= y_next;
END IF;END PROCESS;
20
VHDL code of arbiterPROCESS ( y, r )BEGIN
y_next <= y;g <= "000";CASE y IS
WHEN Idle =>IF r(1) = '1' THEN y_next <= gnt1 ;ELSIF r(2) = '1' THEN y_next <= gnt2 ;ELSIF r(3) = '1' THEN y_next <= gnt3 ;ELSE y_next <= Idle ;END IF ;
WHEN gnt1 =>g(1) <= '1' ;IF r(1) = '0' THEN y_next <= Idle ;ELSE y_next <= gnt1 ;END IF ;
21
WHEN gnt2 =>g(2) <= '1' ;IF r(2) = '0' THEN y_next <= Idle ;ELSE y_next <= gnt2 ;END IF ;
WHEN gnt3 =>g(2) <= '1' ;IF r(3) = '0' THEN y_next <= Idle ;ELSE y_next <= gnt3 ;END IF ;
END CASE ;END PROCESS ;
END Behavior ;
VHDL code of arbiter
Problem 1
Assuming ASM chart given on the next slide, supplement timing waveforms given in the answer
sheet with the correct values of signals State, g1, g2, g3, in the interval from 0 to 575 ns.
23
ASM Chart
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
r 1
r 3 0 1
1
Idle
Reset
r 2
r 1
r 3
r 2
gnt1
gnt2
gnt3
1
1
1
0
0
0
g 1
g 2
g 3
0
0
1
Clk
r1
r2
State
Reset
r3
g1
g2
g30 ns 100 ns 200 ns 300 ns 400 ns 500 ns
Problem 2
Assuming state diagram given on the next slide, supplement timing waveforms given in the answer sheet
with the correct values of signals State and c, in the interval from 0 to 575 ns.
X
Reset
a
Y
Z
b
1
0
0
1
0 1
c
b
c
c
Clk
a
b
State
c
Reset
0 ns 100 ns 200 ns 300 ns 400 ns 500 ns
28
FSM Coding Style
Process(clk, reset)
Process(Present State,Inputs)
RTL Hardware Design by P. Chu
Chapter 10 29
oe<=1
oe<=1
oe<=1
oe<=1
Memory Controller
30
31
32
