All-Optical Header ProcessingAll-Optical Header Processingin Optical Packet-Switched in Optical Packet-Switched

NetworksNetworks

Hoa Le Minh, Hoa Le Minh, Fary Z GhassemlooyFary Z Ghassemlooy and and

Wai Pang NgWai Pang Ng

Optical Communications Research GroupOptical Communications Research Group

Northumbria Communications Research LabNorthumbria Communications Research Lab

Northumbria UniversityNorthumbria University

U.K.U.K.

July, 2005

ContentsContents

Overview of processing in optical networksOverview of processing in optical networks

New Node ArchitectureNew Node Architecture

Proposed processing schemeProposed processing scheme

ResultsResults

SummarySummary

Optical CommunicationsOptical Communications

1st generation optical networks: packet routing and switching are mainly carried out using high-speed electronic devices.

However, as the transmission rate continues to increase, electronically processing data potentially becomes a bottleneck at an intermediate node along the network.

Solution: All-Optical processing

1P

100T

10T

1T

100G

10G

1G

100M

1995 2000 2005 2010

[bit/s]

Voice

DataTotal

Traffic demand forecast (NEC–2001)

Capacity increase : 2~4 times a year

Bit cost decrease : 1/2 time a year

Future Optical NetworksFuture Optical Networks

Node B

Node D

Node F

Node H

Node A

Transparent domain

Transparent domain

Regionalnetwork

Regionalnetwork

Node G

Regionalnetwork

Regionalnetwork

Optical transport network (OTN)Node E

Node C

Hop 1

Regionalnetwork

Regionalnetwork

Regionalnetwork

Regionalnetwork

Source: NEC-2001

All-Optical Packet-Switched NetworksAll-Optical Packet-Switched Networks(Core network)(Core network)

EdgeRouter

Core Network

EdgeRouter

EdgeRouter

Edge nodeEdge node O/E & E/O interfaceO/E & E/O interface Large routing tableLarge routing table Electronic processingElectronic processing

Core nodeCore node No O/E & E/ONo O/E & E/O Wavelength labelsWavelength labels All-optical processingAll-optical processing

EdgeRouter

EdgeRouter

EdgeRouter

Optical transparent !PL H

All-Optical Packet-Switched NetworksAll-Optical Packet-Switched Networks

22

994545

1313

551010

AddressAddress PortPort

A_1A_1 P3P3

A_2A_2 P2P2

A_3A_3 P1P1

…… ……

A_99A_99 P2P2

…… ……

A_127A_127 P2P2

A_128A_128 P1P1

P1

P2

P3

2323

88

66

All electronic node: O/E & E/O conversions O/E & E/O conversions limit processing speed limit processing speed

All-Optical node: A large routing table – opt. memory issue Complexity

O/E Processing E/O

Routing table for a network with 128 nodes

A_99

H

…

33PL H

Electronic Processing Vs. Optical Electronic Processing Vs. Optical ProcessingProcessing

AdvantagesAdvantages DisadvantagesDisadvantages

ElectronicElectronic

ProcessingProcessing

High processing High processing capacity capacity

High scalability High scalability Low cost Low cost Large memory Large memory

Able to support Able to support

< 40Gbits/s< 40Gbits/s

OpticalOptical

processingprocessing Ultra-fast Ultra-fast (> 40Gbps)(> 40Gbps)

Impractical Impractical complex complex configurationsconfigurations

Unavailable Unavailable optical memoryoptical memory

ExpensiveExpensive

All-Optical Processing -All-Optical Processing -Proposed ApproachProposed Approach

OffersOffers Novel routing table in pulse-position Novel routing table in pulse-position

modulation formatmodulation format– Small and fixed number of routing table entries Small and fixed number of routing table entries

regardless of the number of nodes in network.regardless of the number of nodes in network. High scalabilityHigh scalability

– Using simple optical configuration (SMZI).Using simple optical configuration (SMZI). Ultrahigh speed and high capabilityUltrahigh speed and high capability

– Header address matching is done readily with Header address matching is done readily with reduced size routing table.reduced size routing table.

Proposed Header Processing UnitProposed Header Processing Unit

Matching pulse(Synchronized)

HeaderExtraction

PPMConversion

PPRT

Delay fiber

Data packet

Pattern of port 1

Pattern of port 2

…

Pattern of port M

Optical AND gate 1

Optical AND gate 2

…

Optical AND gate M

All-OpticalSwitch

All-OpticalSwitch

…

Control port 1Control port 2Control port M

…

Port 1

Port 2

Port MH

Control

Synchronization

ClockExtraction

HPL Clk

Clk

OpticalHeader Processor

C[M]

HPL Clk

HPL Clk

Data Packet FormatData Packet Format

Payload Header Sync

AddressOthers

N bits

(N optical pulses)

Controls

Parity

…

Data packet:

-Optical pulses in RZ-format,

- Speed a few hundreds Gbit/s

- Each bit slot spreads from dozens to a few picoseconds

1 0 1 1 0 …

Pulse Position Modulation FormatPulse Position Modulation Format

In PPM M-bit address symbol is converted into 2M-slot symbol

1 0 0 1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Tb

Ts

LSB

Tb – bit duration, Ts – slot duration

a3 a2 a1 a0

RZ Data

PPM

Tsym

0 1 1 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Tsym

PPM Generation Optical CircuitPPM Generation Optical Circuit

PP-format address: y(t) = x(t + ai2iTs)

N-bit address-codeword: A = [ai {0,1}], i = 0, …, N

SW1SW1 SW2SW2 SW3SW3 SW4SW4

20Ts 21Ts 22Ts 23Tsx(t) y(t)

a0a1 a2 a3

HeaderExt. UnitHeaderExt. Unit

PPM Based Routing TablePPM Based Routing Table

AddressAddress

bitsbits

DecimalDecimal

weightweight

Switch to Switch to port…port…

00…0000…00 00 Port 2Port 2

00…0100…01 11 Port 1Port 1

00…1000…10 22 Port 3Port 3

00…1100…11 33 Port 1Port 1

…… …… ……

11…1011…10 22NN-2-2 Port 2Port 2

11…1111…11 22NN-1-1 Port 1Port 1

2N en

tries

Switch Switch

toto

Pulse-Pulse-positionspositions

Actual PP frameActual PP frame

(length 2(length 2NN slots) slots)

Port 1Port 1 ((11,,33,…,,…,22NN-1-1))

Port 2Port 2 ((00,…,,…,22NN-2-2))

Port 3Port 3 ((22,…),…)

0 1 2 3 4 2N-1

… …

0 1 2 3 4 2N-1

… …

0 1 2 3 4 2N-1

… …

2N- entry RT M- entry PPM routing table

M is fixed number of entries is fixed at each node

M = 3 ith

s

b

T

TNR

Processing gain:

PPM Based Routing Table – PPM Based Routing Table – contd.contd.

Is initialized with the clock synchronization Is initialized with the clock synchronization . . MM entries are filled by: entries are filled by:

– Single optical pulse + Array of 2Single optical pulse + Array of 2NN optical optical delay lines; Or,delay lines; Or,

– MM pattern generators + pattern generators + MM optical modulators. optical modulators.

Ultrafast Optical AND GateUltrafast Optical AND Gate

A/BA/B 00 11

00 00 00

11 00 11

Implementation:

- Using optical interferometer configuration

Terahertz Optical Asymmetric Demultiplexer (TOAD)

SOA

AB

A.B

B

AA.B

SOA1

SOA2

Symmetric Mach-Zehnder Interferometer (SMZI)

All-Optical SwitchAll-Optical Switch

1 MSMZI-1

SMZI-2

SMZI-M

…

C[1]

C[2]

C[M]

1

2

M

Using an array of SMZI with controls provided from the processing unit

Simulation ParametersSimulation Parameters

Parameters ValueData bitrate 50Gbits/sData packet length 53 bytes (424 bits)Data packet guard time 3 nsHeader length 4 bitsData power (per pulse) 2mWData pulse width (FWHM) 1 psPPM slot Ts 5 psWavelength 1554 nm

Simulation ResultsSimulation Results

Extracted clocks

Extracted clocksExtracted clocks

Incoming packetIncoming packet

Switched OutputsSwitched Outputs

Packets @ output 1

Packets @ output 2

Packets @ output 3

Node 1

Node 2

Node 3

SummarySummary

A novel node architecture encooprating all A novel node architecture encooprating all optical processing with much reduced optical processing with much reduced routing table entries based om PPM was routing table entries based om PPM was proposed and simulated using VPI proposed and simulated using VPI simulation package.simulation package.

It is possible to significantly increase the It is possible to significantly increase the number of nodes in network as well as number of nodes in network as well as enlarge the size or routing table at each enlarge the size or routing table at each node without introducing large processing node without introducing large processing delay.delay.

AcknowledgementsAcknowledgements

One of the authors One of the authors Hoa Le MinhHoa Le Minh is is sponsored by the Northumbria sponsored by the Northumbria University for his PhD study.University for his PhD study.

Thank you!