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Alpha Holdings Introduction
íìŹ ì°í
2002.11 ăìíìč©ì€ ëČìžì€ëŠœ
2003.01 ìŒì±ì ìă Design Partner ì§ì
2003.04 ìŒì±ëČ€ìČíŹìă í©ìíŹì êłìœ ìČŽêČ°
2003.05 ăìíìč©ì€ êž°ì ë¶ì€ì°ê”Źì ì€ëŠœ
2003.12 ëČ€ìČêž°ì íìž
2004.01 ê”ëŽ ASIC/SoC ìì ê°ì
2004.05 íê”ë°ëìČŽì°ì íí íììŹ ê°ì
2005.05 90nmêłŒì 1st Silicon Pass ëŹì±
2005.09 ARM Peripherals ì€êł ìëŁ
2005.11 íčíì·šë 5걎
2006.04 ARM Platform êž°ë° SoC ì€êł ìëŁ
2007.01 ìŒì±ì ì ă ì°ì íë „ì ìČŽ íŹì
2007.08 65nmêłŒì 1st Silicon Pass ëŹì±
2008.01 T-CON êłŒì ê°ë° ë° ìì° ì§í äž
(ìŒì± LCD ì ì íì íìŹëìŽ ìì° äž)
2009.11 ìžìŹêž°ì ëì ì§êČœë¶ ì„êŽ íì°œ ìì
2010.03 ISP êł”ë ì€êł ìëŁ(ìŒì± S3 Phoneì
íìŹëìŽ 40Mê° ìŽì ìì° ì§í äž)
2010.05 ì€íêž°ì ìĄì±ìŹì ì ì [ì±ëšì]
2010.05 45nm êłŒì 1st Silicon Pass ëŹì±
(45nm 30êłŒì ìŽì ìì° ì§í äž)
2010.07 Network Camera êł”ë ì€êł ìëŁ
(1st PassëìŽ 2013ë ìì° ì§í ì€)
2010.09 íê”ê±°ëì ìœì€ë„ìì„ ìì„
2011.03 45nm Analog IP 4ìą ê°ë° ìëŁ
2011.11 ì ì ë „ All Silicon Oscillator IPê°ë°
2012.09 130nm IP ê°ë°ìëŁ
(Dithered PLL, XPLL, Oscillator AiPi ++)
2012.12 Level-0 ì í 1st Silicon Pass(45nm)
2013.02 Flash Memory Controller ê°ë° ìëŁ
2013.08 28nm êłŒì 1st Silicon Pass ëŹì±
(28nm 20êłŒì ìŽì ìì° ì§í äž)
2014.05 Level-0 ì í 1st Silicon Pass(28nm)
2016.08 ìížëłêČœ_(ìŁŒ)ìííë©ì€
2016.12 ìíì룚ì ìŠ ëŹŒì ë¶í (HDMIìŹì )
2017.10 ISO9001ìžìŠ
âȘ ìŹì êž°ë° ê”Źì¶âȘ ìŒì±ì ìă Design Partner ì ì
âȘ Cutting Edge êž°ì ë „ í볎âȘ ìì ì ìž ìŹì êž°ë° ê”Źì¶
âȘ ì§ìì ìž ìŹì ê”ŹìĄ° í볎âȘ 믞ë ìŹì ì€ëč
(IP/ì€êł ë„ë „ ê”Źì¶/íŽìž)
ìëĄìŽ ëì
(2002ë ~2006ë )
ì±ì„êłŒ íì
(2007ë ~2010ë )
ì±ì„ ê°ìí ë° ëìœêž°
(2011ë ~íìŹ)
2
CEO
âȘ Product DesignâȘ IP DesignâȘ Product PlanâȘ Patent
âȘ SalesâȘ MarketingâȘ Mass Product
âȘ AccountâȘ Management
3
âȘ Yield AnalysisâȘ Board SolutionâȘ Claim ëì
âȘ SynthesisâȘ DFT& STAâȘ Auto P&RâȘ Manual Layout
SoCì룚ì ìŹì ë¶
DesignServiceìŹì ë¶
FieldApp.ì€
ì ë”ë§ìŒí ì€
êČœìì§ìì€
ìŹì ë¶ì„ì€êČœë ž ì돎
ìŽ 18ëȘ
ìŹì ë¶ì„ìĄ°ê·ì ìŽìŹ
ìŽ 58ëȘ
ì€ì„ì ì 돞 ì 돎
ìŽ 5ëȘ
ì€ì„ì ìë ì돎
ìŽ 5ëȘ
ì€ì„êčëêž° ëí(êČžì)
ìŽ 7ëȘ
âȘ IP DevelopmentâȘ Chip PlanningâȘ ARM basedDesign
âȘ HPDFâȘ LP/HS DesignâȘ Power AwareDesign
âȘ 28nm / 45nm
âȘ SEM/FIB/IDSâȘ FAEâȘ Circuit Repair &
Analysis
Business ê°íë„Œ ìí ìŹì ë¶ ìČŽì ê”Źì¶ íšìšì ìž ì§ìì ìí ìČŽì ëłêČœ
ìĄ°ì§ë
High-Level Engineer Man Power 볎ì êČœë „ëł/ì§ê”°ëł ìžë „ íí© (2018ë 4ìë§ êž°ì€)
SoCì룚ì ìŹì ë¶ ê°ë°ìžë „ íí©
Design Service ìŹì ë¶ê°ë°ìžë „ íí©
êČœ ë „ 3ë ìŽí 4ë ~ 7ë 8ë ìŽì
ìž ë „ 3 3 12
êČœ ë „ 3ë ìŽí 4ë ~ 7ë 8ë ìŽì
ìž ë „ 7 26 25
4
ìžë „ê”Źì±
ì§ìì€
17ëȘ
(18%)
ì°ê”Źê°ë°
76ëȘ
(82%)
ê°ë°ì ëŹŽëł ìžë „ê”Źì±
ëììžìëčì€
ìŹì ë¶ 58ëȘ
(76%)
SoC ì룚ì
ìŹì ë¶ 18ëȘ
(24%)
Engineer Man Power
âą ë°ëìČŽ êŽë š ë€ìí ë žíì°ë„Œ ì¶ìČí ì°ìí ì°ê”Źìžë „ í볎
âą êł êČœë „ì ìžë „ì í”í ì”ìì Total Solution ì êł”
ì êł ì”êł ì 돞ê°ë€ëĄ ê”Źì±ë í”ìŹ ìžë „ ë€ì 볎ì
Digital ì€êł
5
Field Application
Design Service(FE/BE) Manual Layout Verification
âą SoC ì룚ì ìŹì ë¶ â 18ëȘ
âą ARM Based Platform 볎ì
âą ê°ìą Digital IP ì ì
(Memory Ctrl., DMA Ctrl., HEVCë±)
âą Full Chip Design(ìì°ì í ë€ì)
âą RTL êČìŠ, FPGA êČìŠ êČœí ë€ì
âą Power, Coverage ì”ì í
볎ì êž°ì ìë
âą Field Applicationì€ â 4ëȘ
âą íì§ êČí ë° êŽëŠŹ
âą Test Set-Up(Test Cost ì”ì í)
âą Yield Management
âą Failure Analysis(SEM/FIB)
âą Circuit Repair & Analysis
âą Design Service ìŹì ë¶ć § â 44ëȘ
âą ê°ìą êł”ì êČœí ë€ì(~28nm)
âą Multiple Application êČœí
(Multimedia, Security, Communication, Displayë±)
âą Large Scale Design êČœí
(Total 270M, Logic 140Mates êž)
âą Proven Track Record 볎ì
(ìë°± ì í ê°ë° êČœí)
âą Design Service ìŹì ë¶ć § â 10ëȘ
âą MCU/Analog IP/Mem./CIS/DDIë±
êłŒì êČœí ë€ì(ìŽ 693ê° êłŒì ìí)
âą Cell Library(Primitive, I/O)êČœí ë€ì
âą ê° ìą êł”ì êČœí ë€ì(~28nm)
âą WPE ë° STI êž°ëČ ìŹì©ê°ë„
âą Power Noise: Mesh, Decoupling Cap.
âą ì ëą°ì± í„ì: Double Guard Ring, P-tapíì©
âą Design Service ìŹì ë¶ć § â 4ëȘ
âą Verification ì ëŽí ìŽì
âą Pre-Verification FlowìŽì
âą Auto P&R/Manual LayoutêłŒ
ꞎë°í Co-workì í”í êČìŠ ì§í
Business Model
ìì€í ë°ëìČŽ ê°ë° ì ëŹžêž°ì
(ì€êł/Chip Implementation)
Foundry ì ìČŽ
ì íì ê°ë°ë¶í° ìì° ë° ìì°êł”êžêčì§ Total Solution ì êł”
Chip Size ì”ìí
ê°ë°êž°ê° ëšì¶
ë¶ëë„ Zero
Level-0 ì€êł ì êł”
ìĄ°ëŠœ/Test ì ìČŽTotal
ì룚ì ì êł”
ì í ê°ë°
ìëą°
ê°êł”
ìëą°
ì í
êł”êž
Mobile
Display
Communication
Security
ë€ìí
ì°ì ê”°
í”ìŹ ê°ì
Fablessì ìČŽ
(SPEC/ì€êł)
6
Alpha Holdings
êł ê° ë§ìĄ± ë° ì±ì„ êž°ë°
No. 1 ê”ëŽ ìì€í ë°ëìČŽ ê°ë° ì ëŹžêž°ì
ì±ì„ ì§ìTotal
Solution ì êł”
âą ìŹëŠŒí ì í
âą ì”ëł”í© ì í
ìì„ Needs ì¶©ìĄ±
ê”ëŽ Tier1êł ê° ëłŽì
Level-0ì€êłë„ë „ëłŽì (1st Pass ëŹì±)
í”ìŹ êž°ì êČœìë „ 볎ì
(28nm/45nm)
Proven Track Record 볎ì (ìë°± ì íê°ë° êČœí)
âą Time to Design
âą Time to Market
âą ìê° êČœìë „
âą ì€êł ìëčì€ ì êł”
êł ê° Needs ì¶©ìĄ±
ìì ì ìžì±ì„
ì§ìì ìžì±ì„
êł ìì±ì„
ìëì§íšêłŒ
7
Alpha Holdings
볎ì êž°ì íí©
ì íì ê°ë°ë¶í° ìì í ìì° ë° ìì° êł”êžêčì§ì í”ìŹ êž°ì 볎ì
8
Back-End Design(Auto ë ìŽìì)
Front-End Design(íëĄí©ì± ë° ë¶ì)
Full Chip Design(ì íêž°í ë° ì€êł)
âą Field Application Analysisâą Board Level Emulationâą ESD/EMI Robust Analysis
âą Test Vector Generationâą Yield Improvementâą Product Reliability Guaranteeâą ESD Robust I/O Design
âą Special Analog IP Designâą High Speed Data Path Design âą Full Chip Floor Plan
âą Hierarchical Physical Layoutâą NMOS/PMOS Power Gatingâą Synthesis & Timing Closure
âą DFT(SCAN/BIST/JTAG)âą STA(Static Timing Analysis)
Field Application(ì€ì„ ë° êł ê°ì§ì)Mass Production
(ìì°)Custom Layout(Manual íëĄë°°ìč)
âą System Architecture Analysisâą Power Management Controlâą Real Emulation with FPGA
8
ìŹëŹŽ íí©
ìŹì ë¶ëŹžëł ë§€ì¶ ëčì€(17ë )
2011 2012
9
ì í©ì ë°ë„ž ëźì ëłëì±ìŒëĄ ìì ì ì±ì„ ì§ì
2013 2014
Mobile Multimedia
67.1%
Security10.2%
Cosumer8.7%
êž°í14.0%
22
30
20 29
222
322
36
34
317
45
45
387
2015
29
24
513
2016 2017
(427)
(83)
566
(57)
(14)
696
맀ì¶ìĄ ìì ìŽì” ëčêž° ììŽì” (ëšì:ì”ì)
Target Application & Customers
ë€ìí Application êČœí íëłŽëĄ ëȘšë ë¶ìŒì êłŒì ì§í ê°ë„
Mobile Multimedia
Display Security
Communication
LTE, WiMAX, Wibro, Wi-Fi ë±
CCTV, IP Camera, DVR, NVR, CAS ë±UD-TV, LCD TV, T-CON, OLED-TV, LCD Monitor ë±
Smart Phone, Tablet-PC, PMP, MP3 ë±
1010
Alpha Holdings
ëŽë¶ 볎ì ìì€í
11
FTP Server
Firewall
볎ììì
ìŹì€ IP ìŹì©
Linux Server
Terminal PC
Internet PC
Internet Phone
Security Server
Internet
ìžë¶ FTP Server
êł”ìž IP ìŹì©
FTP
FTP
FTP
FTP
ëŽë¶ êČ°ìŹë„Œ í”íŽë±ëĄë FTP Server
File Server
FTP
âą ìžë¶ ìží°ë· ë§êłŒ ëŽë¶ ìžížëŒë· ë§ì ìëČœí ë¶ëŠŹ
âą Linux, FTP, Security Serverë íê°ë ìë§ ì¶ì ê°ë„ (ëíìŽìŹ, íì„, 볎ì êŽëŠŹì)
âą CCTVë„Œ í”í 24 ìê° Monitoring, 24 ìê° FTP Server Monitoring
âą ìì Terminal PCë USBë„Œ ëč륯í ëȘšë ì ì¶ë „ ì„ìč ì€ì í”ì
âą ìŒì±ì ìì êł”ìì ìž ìžìŠì ë°ì ìíìŽë©°, RTL Codeë„Œ ëč륯í ëȘšë DB Interface ì€
12
Discussion
Appendix
13
âȘ ìŒì±ì ì LF6 eFlash Foundry
âȘ Level-0 Business ìŹëĄ
âȘ High Speed Interface IPs
âȘ Manual Layout Track-Record
Chip Area
Relative Comparison
Power@same speed
Performance@same leakage
1
1.40
130nm LF6
Relative Comparison
40%â
1
0.43
57%â
130nm LF6
1
0.44
Relative Comparison
56%â
130nm LF6
âȘ Device and SRAM offerings
- Core FET: 1.5V (RVT/LVT/sLVT)
- IO FET: 3.3V/5V
- SPSRAM
âȘ Four to Five metal layers
- Including up to four 1x, one 4x metal levels
âȘ Flash Feature (ESF3)
- Endurance: 100K cycles @RT
- Operation Temp.(Ta): -25â~85ââ -40â~105â
- Data retention: 25yrs (RT)
- Read speed: 30ns/5mA
LF6(8-inch) = 100nm logic gate length + 65nm level eFlash(ESF3 type)â The most competitive embedded flash process among 8-inch process
14
LF6 Technology Overview
eFlash Feature
Item LF6 LF13H
Flash cell size (um2) 0.103 0.397
Memory Density(Bits) *ì êł” ëČì 32Kbit ~ 16Mbit 32Kbit ~ 4Mbit
Supply Voltage 1.5V 1.8V
Endurance 100K cycle @RT 100K cycle @RT
Operation Temp. (Ta) -25â ~ 85â -25â ~ 85â
Data retention 25yrs (RT) 10 yrs (RT)
Read Speed(ns)/Current32bit(mA) 30ns/5mA 50ns/5mA
Program Speed(us)/Current(mA) 30us/4mA 30us/4mA
Erase Speed(ms) / Current (mA) 4ms/4mA 8ms/4mA
15
eFlash Feature
Level0 Project : Security Network Camera Processor
âȘ Cortex-A8 BUS Architecture Design & VerificationâȘ 2013ë ìì° ê°ì
16
Level0 Project : Security Analog Camera Processor
ì ïŒëŹŽì êł ì ì ì¶ë „ìží°íìŽì€ êž°ì
êł ì±ë„ëčëì€ Interface(Analog & Digital)
ì§ë„í ìì ê°ì êž°ì
Multi Layer High Speed System Bus
BU
S
SensorUpto2M
ARM926EJ@300MHz
DDR2-1066256Mb
CIFI/F
DMAC
Pre-proccessor
DisplayCONT
Progressive
DisplayCONT
Interface
IPC
VideoIris
DDR2Controller
Static MemoryController
NOR/NAND
DAC
FR_DIS_MD
M2M
_BLK
SD/MMC
I2S
UART X 2
GPIO
VIC
SPI X 3
I2C X 2ADC
PWM
WDT
Remap&Pause
DAC
SRAM
2ë©ê° 60frame ìí늏í°Analog ìčŽë©ëŒì© SoC ê°ë°Low-cost/Low-power SoC
âȘ ARM926 Single Core BUS Architecture Design & VerificationâȘ 2014ë ìì° ê°ì
Level0 Project : FRC+TCON
âȘ2013/2014ë ìì°
19
High Speed Interface IPs
Smart Interface Engine
World Best Size and Performance
High Speed Data Interface IP Portpolio
âą LVDS / Link&PHY âą AiPi+ / Link&PHY
âą USI-T / Link âą HDMI 2.0 / Link&PHY âą MHL 3.0 / Link&PHY
âą V-by-one / Link&PHYâą AiPi++ / Link&PHY
âą HDMI 1.4 / Link&PHY